Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28217882	1			T1	69		T2	44		T3	17
all_levels[1]	195187	1			T3	2		T4	4		T5	11
all_levels[2]	2634	1			T3	5		T5	1		T6	1
all_levels[3]	1122	1			T2	1		T3	3		T10	8
all_levels[4]	779	1			T3	2		T4	1		T5	2
all_levels[5]	516	1			T8	1		T136	3		T12	2
all_levels[6]	413	1			T4	1		T18	1		T41	1
all_levels[7]	351	1			T4	1		T11	1		T12	1
all_levels[8]	303	1			T4	2		T10	2		T16	1
all_levels[9]	287	1			T10	1		T137	1		T136	1
all_levels[10]	219	1			T6	1		T8	1		T11	1
all_levels[11]	177	1			T136	2		T44	1		T45	1
all_levels[12]	169	1			T137	1		T14	1		T138	2
all_levels[13]	142	1			T11	1		T35	1		T139	1
all_levels[14]	139	1			T3	2		T24	1		T137	1
all_levels[15]	125	1			T44	2		T14	1		T139	1
all_levels[16]	97	1			T136	1		T12	1		T19	1
all_levels[17]	103	1			T12	1		T44	2		T37	1
all_levels[18]	106	1			T2	1		T140	1		T141	1
all_levels[19]	84	1			T12	1		T139	1		T37	1
all_levels[20]	72	1			T44	1		T14	1		T142	1
all_levels[21]	88	1			T136	1		T44	1		T143	1
all_levels[22]	63	1			T6	2		T44	2		T138	1
all_levels[23]	71	1			T6	1		T24	1		T38	2
all_levels[24]	64	1			T24	1		T138	1		T38	1
all_levels[25]	56	1			T12	1		T141	1		T144	3
all_levels[26]	37	1			T11	1		T126	1		T145	2
all_levels[27]	60	1			T35	4		T126	1		T146	1
all_levels[28]	39	1			T136	1		T19	1		T14	1
all_levels[29]	40	1			T19	1		T14	1		T119	2
all_levels[30]	39	1			T139	2		T141	1		T147	1
all_levels[31]	33	1			T126	1		T139	1		T148	2
all_levels[32]	40	1			T2	3		T139	2		T55	1
all_levels[33]	18	1			T60	2		T149	1		T111	1
all_levels[34]	30	1			T19	1		T150	1		T60	1
all_levels[35]	26	1			T6	1		T19	1		T126	1
all_levels[36]	17	1			T151	1		T152	1		T153	1
all_levels[37]	31	1			T16	1		T139	1		T132	2
all_levels[38]	20	1			T19	1		T154	1		T59	1
all_levels[39]	29	1			T136	1		T42	1		T14	1
all_levels[40]	17	1			T19	1		T155	1		T53	1
all_levels[41]	15	1			T36	1		T51	1		T156	1
all_levels[42]	20	1			T11	1		T38	1		T151	2
all_levels[43]	21	1			T157	1		T158	1		T159	1
all_levels[44]	22	1			T136	2		T14	1		T138	1
all_levels[45]	18	1			T155	1		T120	1		T83	1
all_levels[46]	11	1			T160	1		T79	1		T121	1
all_levels[47]	19	1			T155	1		T161	1		T120	1
all_levels[48]	16	1			T162	2		T163	1		T164	1
all_levels[49]	8	1			T165	1		T166	1		T167	1
all_levels[50]	16	1			T6	1		T14	1		T56	1
all_levels[51]	11	1			T140	1		T144	1		T168	1
all_levels[52]	16	1			T6	1		T11	2		T169	2
all_levels[53]	11	1			T147	1		T170	4		T171	1
all_levels[54]	13	1			T19	1		T172	2		T61	1
all_levels[55]	13	1			T11	1		T12	1		T173	1
all_levels[56]	13	1			T24	3		T174	1		T175	1
all_levels[57]	19	1			T38	1		T117	1		T176	5
all_levels[58]	10	1			T14	1		T138	1		T148	1
all_levels[59]	8	1			T177	1		T178	1		T65	3
all_levels[60]	7	1			T83	3		T179	1		T180	1
all_levels[61]	1	1			T158	1		-	-		-	-
all_levels[62]	8	1			T148	1		T181	4		T121	1
all_levels[63]	9	1			T146	1		T182	1		T177	1
all_levels[64]	112	1			T11	4		T119	1		T174	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28417294

1

T1

63

T2

43

T3

26

auto[1]

4848

1

T1

6

T2

6

T3

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[40] , all_levels[41]]	[auto[1]]	--	--	2
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[49]]	[auto[1]]	0	1	1
[all_levels[51]]	[auto[1]]	0	1	1
[all_levels[58]]	[auto[1]]	0	1	1
[all_levels[61]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28213556	1			T1	63		T2	40		T3	15
all_levels[0]	auto[1]	4326	1			T1	6		T2	4		T3	2
all_levels[1]	auto[0]	195104	1			T3	2		T4	3		T5	11
all_levels[1]	auto[1]	83	1			T4	1		T10	1		T38	3
all_levels[2]	auto[0]	2608	1			T3	3		T5	1		T6	1
all_levels[2]	auto[1]	26	1			T3	2		T139	2		T183	1
all_levels[3]	auto[0]	1097	1			T2	1		T3	3		T10	8
all_levels[3]	auto[1]	25	1			T24	1		T184	1		T185	1
all_levels[4]	auto[0]	764	1			T3	2		T4	1		T5	2
all_levels[4]	auto[1]	15	1			T8	2		T143	2		T150	1
all_levels[5]	auto[0]	496	1			T8	1		T136	2		T12	2
all_levels[5]	auto[1]	20	1			T136	1		T157	2		T186	1
all_levels[6]	auto[0]	399	1			T4	1		T18	1		T41	1
all_levels[6]	auto[1]	14	1			T77	1		T184	1		T187	1
all_levels[7]	auto[0]	337	1			T4	1		T11	1		T12	1
all_levels[7]	auto[1]	14	1			T138	1		T188	1		T159	1
all_levels[8]	auto[0]	285	1			T4	1		T10	1		T16	1
all_levels[8]	auto[1]	18	1			T4	1		T10	1		T79	1
all_levels[9]	auto[0]	264	1			T10	1		T137	1		T136	1
all_levels[9]	auto[1]	23	1			T148	2		T189	1		T190	1
all_levels[10]	auto[0]	207	1			T6	1		T8	1		T11	1
all_levels[10]	auto[1]	12	1			T191	1		T192	1		T179	2
all_levels[11]	auto[0]	161	1			T136	1		T44	1		T45	1
all_levels[11]	auto[1]	16	1			T136	1		T143	1		T148	1
all_levels[12]	auto[0]	152	1			T137	1		T14	1		T138	1
all_levels[12]	auto[1]	17	1			T138	1		T193	3		T116	3
all_levels[13]	auto[0]	128	1			T11	1		T35	1		T139	1
all_levels[13]	auto[1]	14	1			T185	2		T163	1		T194	2
all_levels[14]	auto[0]	128	1			T3	1		T24	1		T137	1
all_levels[14]	auto[1]	11	1			T3	1		T19	1		T168	2
all_levels[15]	auto[0]	119	1			T44	2		T14	1		T139	1
all_levels[15]	auto[1]	6	1			T195	1		T196	2		T197	1
all_levels[16]	auto[0]	96	1			T136	1		T12	1		T19	1
all_levels[16]	auto[1]	1	1			T198	1		-	-		-	-
all_levels[17]	auto[0]	95	1			T12	1		T44	1		T37	1
all_levels[17]	auto[1]	8	1			T44	1		T199	1		T128	1
all_levels[18]	auto[0]	85	1			T2	1		T140	1		T141	1
all_levels[18]	auto[1]	21	1			T200	2		T201	3		T202	1
all_levels[19]	auto[0]	76	1			T12	1		T139	1		T37	1
all_levels[19]	auto[1]	8	1			T203	4		T204	1		T205	1
all_levels[20]	auto[0]	63	1			T44	1		T14	1		T142	1
all_levels[20]	auto[1]	9	1			T206	2		T77	1		T128	1
all_levels[21]	auto[0]	74	1			T136	1		T44	1		T143	1
all_levels[21]	auto[1]	14	1			T156	3		T207	1		T208	3
all_levels[22]	auto[0]	54	1			T6	1		T44	2		T138	1
all_levels[22]	auto[1]	9	1			T6	1		T209	2		T210	5
all_levels[23]	auto[0]	63	1			T6	1		T24	1		T38	1
all_levels[23]	auto[1]	8	1			T38	1		T211	3		T212	1
all_levels[24]	auto[0]	61	1			T24	1		T138	1		T38	1
all_levels[24]	auto[1]	3	1			T213	3		-	-		-	-
all_levels[25]	auto[0]	49	1			T12	1		T141	1		T144	1
all_levels[25]	auto[1]	7	1			T144	2		T156	1		T83	1
all_levels[26]	auto[0]	34	1			T11	1		T126	1		T145	1
all_levels[26]	auto[1]	3	1			T145	1		T214	1		T215	1
all_levels[27]	auto[0]	51	1			T35	1		T126	1		T146	1
all_levels[27]	auto[1]	9	1			T35	3		T83	3		T199	1
all_levels[28]	auto[0]	34	1			T136	1		T19	1		T14	1
all_levels[28]	auto[1]	5	1			T216	3		T217	1		T218	1
all_levels[29]	auto[0]	33	1			T19	1		T14	1		T119	2
all_levels[29]	auto[1]	7	1			T84	1		T177	1		T219	1
all_levels[30]	auto[0]	36	1			T139	1		T141	1		T147	1
all_levels[30]	auto[1]	3	1			T139	1		T220	2		-	-
all_levels[31]	auto[0]	30	1			T126	1		T139	1		T148	1
all_levels[31]	auto[1]	3	1			T148	1		T221	1		T222	1
all_levels[32]	auto[0]	37	1			T2	1		T139	2		T55	1
all_levels[32]	auto[1]	3	1			T2	2		T223	1		-	-
all_levels[33]	auto[0]	18	1			T60	2		T149	1		T111	1
all_levels[34]	auto[0]	24	1			T19	1		T150	1		T60	1
all_levels[34]	auto[1]	6	1			T197	2		T224	1		T225	1
all_levels[35]	auto[0]	24	1			T6	1		T19	1		T126	1
all_levels[35]	auto[1]	2	1			T226	2		-	-		-	-
all_levels[36]	auto[0]	17	1			T151	1		T152	1		T153	1
all_levels[37]	auto[0]	27	1			T16	1		T139	1		T132	1
all_levels[37]	auto[1]	4	1			T132	1		T227	2		T228	1
all_levels[38]	auto[0]	18	1			T19	1		T154	1		T59	1
all_levels[38]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[39]	auto[0]	24	1			T136	1		T42	1		T14	1
all_levels[39]	auto[1]	5	1			T231	4		T232	1		-	-
all_levels[40]	auto[0]	17	1			T19	1		T155	1		T53	1
all_levels[41]	auto[0]	15	1			T36	1		T51	1		T156	1
all_levels[42]	auto[0]	17	1			T11	1		T38	1		T151	1
all_levels[42]	auto[1]	3	1			T151	1		T233	2		-	-
all_levels[43]	auto[0]	15	1			T157	1		T158	1		T159	1
all_levels[43]	auto[1]	6	1			T234	4		T235	1		T236	1
all_levels[44]	auto[0]	20	1			T136	1		T14	1		T138	1
all_levels[44]	auto[1]	2	1			T136	1		T237	1		-	-
all_levels[45]	auto[0]	17	1			T155	1		T120	1		T83	1
all_levels[45]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[46]	auto[0]	11	1			T160	1		T79	1		T121	1
all_levels[47]	auto[0]	15	1			T155	1		T161	1		T120	1
all_levels[47]	auto[1]	4	1			T233	1		T229	1		T239	1
all_levels[48]	auto[0]	14	1			T162	1		T163	1		T164	1
all_levels[48]	auto[1]	2	1			T162	1		T240	1		-	-
all_levels[49]	auto[0]	8	1			T165	1		T166	1		T167	1
all_levels[50]	auto[0]	15	1			T6	1		T14	1		T56	1
all_levels[50]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[51]	auto[0]	11	1			T140	1		T144	1		T168	1
all_levels[52]	auto[0]	14	1			T6	1		T11	2		T169	1
all_levels[52]	auto[1]	2	1			T169	1		T215	1		-	-
all_levels[53]	auto[0]	8	1			T147	1		T170	1		T171	1
all_levels[53]	auto[1]	3	1			T170	3		-	-		-	-
all_levels[54]	auto[0]	9	1			T19	1		T172	1		T61	1
all_levels[54]	auto[1]	4	1			T172	1		T157	1		T223	2
all_levels[55]	auto[0]	9	1			T11	1		T12	1		T173	1
all_levels[55]	auto[1]	4	1			T242	3		T243	1		-	-
all_levels[56]	auto[0]	11	1			T24	1		T174	1		T175	1
all_levels[56]	auto[1]	2	1			T24	2		-	-		-	-
all_levels[57]	auto[0]	13	1			T38	1		T117	1		T176	1
all_levels[57]	auto[1]	6	1			T176	4		T244	2		-	-
all_levels[58]	auto[0]	10	1			T14	1		T138	1		T148	1
all_levels[59]	auto[0]	6	1			T177	1		T178	1		T65	1
all_levels[59]	auto[1]	2	1			T65	2		-	-		-	-
all_levels[60]	auto[0]	4	1			T83	1		T179	1		T180	1
all_levels[60]	auto[1]	3	1			T83	2		T245	1		-	-
all_levels[61]	auto[0]	1	1			T158	1		-	-		-	-
all_levels[62]	auto[0]	5	1			T148	1		T181	1		T121	1
all_levels[62]	auto[1]	3	1			T181	3		-	-		-	-
all_levels[63]	auto[0]	8	1			T146	1		T182	1		T177	1
all_levels[63]	auto[1]	1	1			T246	1		-	-		-	-
all_levels[64]	auto[0]	93	1			T11	4		T119	1		T174	1
all_levels[64]	auto[1]	19	1			T112	1		T247	1		T64	2