Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99156	1			T1	35		T2	42		T3	17
all_pins[1]	99156	1			T1	35		T2	42		T3	17
all_pins[2]	99156	1			T1	35		T2	42		T3	17
all_pins[3]	99156	1			T1	35		T2	42		T3	17
all_pins[4]	99156	1			T1	35		T2	42		T3	17
all_pins[5]	99156	1			T1	35		T2	42		T3	17
all_pins[6]	99156	1			T1	35		T2	42		T3	17
all_pins[7]	99156	1			T1	35		T2	42		T3	17
all_pins[8]	99156	1			T1	35		T2	42		T3	17

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	852347	1			T1	305		T2	342		T3	136
values[0x1]	40057	1			T1	10		T2	36		T3	17
transitions[0x0=>0x1]	32734	1			T1	7		T2	36		T3	12
transitions[0x1=>0x0]	32507	1			T1	6		T2	35		T3	13

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78305	1			T1	30		T2	12		T3	7
all_pins[0]	values[0x1]	20851	1			T1	5		T2	30		T3	10
all_pins[0]	transitions[0x0=>0x1]	20296	1			T1	5		T2	30		T3	10
all_pins[0]	transitions[0x1=>0x0]	1132	1			T6	6		T10	10		T24	1
all_pins[1]	values[0x0]	97469	1			T1	35		T2	42		T3	17
all_pins[1]	values[0x1]	1687	1			T6	6		T10	10		T24	1
all_pins[1]	transitions[0x0=>0x1]	1573	1			T6	5		T10	10		T11	1
all_pins[1]	transitions[0x1=>0x0]	2461	1			T1	2		T2	2		T3	1
all_pins[2]	values[0x0]	96581	1			T1	33		T2	40		T3	16
all_pins[2]	values[0x1]	2575	1			T1	2		T2	2		T3	1
all_pins[2]	transitions[0x0=>0x1]	2496	1			T1	1		T2	2		T3	1
all_pins[2]	transitions[0x1=>0x0]	281	1			T11	2		T12	1		T14	4
all_pins[3]	values[0x0]	98796	1			T1	34		T2	42		T3	17
all_pins[3]	values[0x1]	360	1			T1	1		T11	2		T12	1
all_pins[3]	transitions[0x0=>0x1]	323	1			T1	1		T11	1		T12	1
all_pins[3]	transitions[0x1=>0x0]	440	1			T11	1		T12	9		T14	5
all_pins[4]	values[0x0]	98679	1			T1	35		T2	42		T3	17
all_pins[4]	values[0x1]	477	1			T11	2		T12	9		T14	5
all_pins[4]	transitions[0x0=>0x1]	405	1			T11	2		T12	6		T14	3
all_pins[4]	transitions[0x1=>0x0]	169	1			T34	1		T35	1		T20	1
all_pins[5]	values[0x0]	98915	1			T1	35		T2	42		T3	17
all_pins[5]	values[0x1]	241	1			T12	3		T14	2		T34	2
all_pins[5]	transitions[0x0=>0x1]	198	1			T12	3		T14	2		T34	1
all_pins[5]	transitions[0x1=>0x0]	899	1			T2	4		T3	1		T24	1
all_pins[6]	values[0x0]	98214	1			T1	35		T2	38		T3	16
all_pins[6]	values[0x1]	942	1			T2	4		T3	1		T24	1
all_pins[6]	transitions[0x0=>0x1]	880	1			T2	4		T3	1		T24	1
all_pins[6]	transitions[0x1=>0x0]	287	1			T16	1		T11	2		T12	2
all_pins[7]	values[0x0]	98807	1			T1	35		T2	42		T3	17
all_pins[7]	values[0x1]	349	1			T16	1		T11	2		T12	3
all_pins[7]	transitions[0x0=>0x1]	217	1			T16	1		T12	3		T14	3
all_pins[7]	transitions[0x1=>0x0]	12443	1			T1	2		T3	5		T5	2
all_pins[8]	values[0x0]	86581	1			T1	33		T2	42		T3	12
all_pins[8]	values[0x1]	12575	1			T1	2		T3	5		T5	2
all_pins[8]	transitions[0x0=>0x1]	6346	1			T5	1		T6	2		T8	2
all_pins[8]	transitions[0x1=>0x0]	14395	1			T1	2		T2	29		T3	6