Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	5828053	1			T1	4		T2	3		T3	7
all_levels[1]	2407288	1			T1	2		T2	2		T4	10
all_levels[2]	622355	1			T2	2		T5	2		T25	28214
all_levels[3]	258093	1			T2	1		T5	1		T7	2
all_levels[4]	327916	1			T5	2		T6	1		T25	2069
all_levels[5]	213888	1			T7	9		T8	12		T25	2069
all_levels[6]	305036	1			T3	4		T6	1		T7	3
all_levels[7]	258069	1			T2	1		T25	2065		T46	2649
all_levels[8]	222080	1			T4	1		T5	3		T6	1
all_levels[9]	216272	1			T3	4		T6	1		T7	1
all_levels[10]	205127	1			T3	1		T25	2075		T137	1
all_levels[11]	520154	1			T25	2069		T137	37		T46	2646
all_levels[12]	296676	1			T3	1		T8	22		T25	2062
all_levels[13]	269766	1			T10	1		T25	2071		T137	44
all_levels[14]	223275	1			T3	2		T5	50		T8	4
all_levels[15]	207604	1			T1	5		T3	1		T5	2
all_levels[16]	340795	1			T3	5		T8	1		T10	1
all_levels[17]	427962	1			T1	1		T2	4		T5	1
all_levels[18]	554692	1			T1	1		T2	3		T3	1
all_levels[19]	222153	1			T2	1		T25	2062		T137	2
all_levels[20]	236571	1			T1	4		T2	2		T4	2
all_levels[21]	258440	1			T1	5		T8	6		T10	149
all_levels[22]	192507	1			T1	1		T4	16		T25	2073
all_levels[23]	185967	1			T25	2075		T46	2641		T12	24
all_levels[24]	222396	1			T1	2		T2	2		T8	6
all_levels[25]	204199	1			T1	8		T2	2		T5	2
all_levels[26]	221265	1			T1	3		T24	1		T25	2068
all_levels[27]	199204	1			T1	9		T2	1		T10	3
all_levels[28]	221205	1			T1	4		T24	1		T25	31670
all_levels[29]	302057	1			T1	7		T5	125		T10	1
all_levels[30]	448340	1			T1	6		T4	1		T5	1
all_levels[31]	496439	1			T1	4		T5	2		T6	2
all_levels[32]	11305806	1			T1	2		T2	23		T3	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28417294

1

T1

63

T2

43

T3

26

auto[1]

4356

1

T1

5

T2

4

T3

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	5825500	1			T1	3		T2	3		T3	5
all_levels[0]	auto[1]	2553	1			T1	1		T3	2		T6	5
all_levels[1]	auto[0]	2407020	1			T1	1		T2	2		T4	9
all_levels[1]	auto[1]	268	1			T1	1		T4	1		T10	1
all_levels[2]	auto[0]	622310	1			T2	2		T5	2		T25	28214
all_levels[2]	auto[1]	45	1			T44	1		T138	1		T143	1
all_levels[3]	auto[0]	257971	1			T2	1		T5	1		T7	2
all_levels[3]	auto[1]	122	1			T136	1		T14	1		T273	2
all_levels[4]	auto[0]	327884	1			T5	2		T6	1		T25	2069
all_levels[4]	auto[1]	32	1			T136	1		T188	1		T160	1
all_levels[5]	auto[0]	213853	1			T7	9		T8	12		T25	2069
all_levels[5]	auto[1]	35	1			T168	1		T76	3		T242	3
all_levels[6]	auto[0]	305005	1			T3	3		T6	1		T7	3
all_levels[6]	auto[1]	31	1			T3	1		T44	1		T145	1
all_levels[7]	auto[0]	258003	1			T2	1		T25	2065		T46	2649
all_levels[7]	auto[1]	66	1			T12	11		T156	1		T318	2
all_levels[8]	auto[0]	222063	1			T4	1		T5	3		T6	1
all_levels[8]	auto[1]	17	1			T168	1		T318	4		T185	1
all_levels[9]	auto[0]	216245	1			T3	4		T6	1		T7	1
all_levels[9]	auto[1]	27	1			T42	1		T138	1		T247	1
all_levels[10]	auto[0]	205087	1			T3	1		T25	2075		T137	1
all_levels[10]	auto[1]	40	1			T155	1		T59	1		T200	2
all_levels[11]	auto[0]	520130	1			T25	2069		T137	36		T46	2646
all_levels[11]	auto[1]	24	1			T137	1		T252	1		T148	2
all_levels[12]	auto[0]	296647	1			T3	1		T8	22		T25	2062
all_levels[12]	auto[1]	29	1			T117	1		T201	1		T122	1
all_levels[13]	auto[0]	269745	1			T10	1		T25	2071		T137	44
all_levels[13]	auto[1]	21	1			T38	1		T172	2		T319	1
all_levels[14]	auto[0]	223253	1			T3	2		T5	50		T8	4
all_levels[14]	auto[1]	22	1			T132	1		T181	2		T200	1
all_levels[15]	auto[0]	207457	1			T1	2		T3	1		T5	2
all_levels[15]	auto[1]	147	1			T1	3		T47	1		T15	7
all_levels[16]	auto[0]	340763	1			T3	5		T8	1		T10	1
all_levels[16]	auto[1]	32	1			T261	2		T139	1		T206	2
all_levels[17]	auto[0]	427947	1			T1	1		T2	2		T5	1
all_levels[17]	auto[1]	15	1			T2	2		T10	1		T44	1
all_levels[18]	auto[0]	554666	1			T1	1		T2	2		T3	1
all_levels[18]	auto[1]	26	1			T2	1		T148	2		T133	1
all_levels[19]	auto[0]	222135	1			T2	1		T25	2062		T137	2
all_levels[19]	auto[1]	18	1			T132	1		T57	1		T156	1
all_levels[20]	auto[0]	236555	1			T1	4		T2	2		T4	1
all_levels[20]	auto[1]	16	1			T4	1		T10	1		T132	1
all_levels[21]	auto[0]	258417	1			T1	5		T8	6		T10	148
all_levels[21]	auto[1]	23	1			T10	1		T35	2		T294	1
all_levels[22]	auto[0]	192480	1			T1	1		T4	14		T25	2073
all_levels[22]	auto[1]	27	1			T4	2		T81	1		T292	1
all_levels[23]	auto[0]	185939	1			T25	2075		T46	2641		T12	24
all_levels[23]	auto[1]	28	1			T38	1		T188	1		T206	1
all_levels[24]	auto[0]	222374	1			T1	2		T2	2		T8	6
all_levels[24]	auto[1]	22	1			T132	2		T128	1		T320	4
all_levels[25]	auto[0]	204181	1			T1	8		T2	2		T5	2
all_levels[25]	auto[1]	18	1			T10	1		T185	2		T203	4
all_levels[26]	auto[0]	221250	1			T1	3		T24	1		T25	2068
all_levels[26]	auto[1]	15	1			T154	1		T321	1		T322	1
all_levels[27]	auto[0]	199176	1			T1	9		T2	1		T10	2
all_levels[27]	auto[1]	28	1			T10	1		T269	1		T172	1
all_levels[28]	auto[0]	221190	1			T1	4		T24	1		T25	31670
all_levels[28]	auto[1]	15	1			T57	1		T77	2		T323	1
all_levels[29]	auto[0]	302038	1			T1	7		T5	125		T10	1
all_levels[29]	auto[1]	19	1			T138	1		T148	1		T264	1
all_levels[30]	auto[0]	448318	1			T1	6		T4	1		T5	1
all_levels[30]	auto[1]	22	1			T139	1		T51	1		T185	1
all_levels[31]	auto[0]	496423	1			T1	4		T5	2		T6	2
all_levels[31]	auto[1]	16	1			T151	2		T124	1		T203	1
all_levels[32]	auto[0]	11305269	1			T1	2		T2	22		T3	3
all_levels[32]	auto[1]	537	1			T2	1		T3	2		T6	3