Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	844	1			T11	4		T14	11		T34	11
all_values[1]	844	1			T11	4		T14	11		T34	11
all_values[2]	844	1			T11	4		T14	11		T34	11
all_values[3]	844	1			T11	4		T14	11		T34	11
all_values[4]	844	1			T11	4		T14	11		T34	11
all_values[5]	844	1			T11	4		T14	11		T34	11
all_values[6]	844	1			T11	4		T14	11		T34	11
all_values[7]	844	1			T11	4		T14	11		T34	11
all_values[8]	844	1			T11	4		T14	11		T34	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4205

1

T11

20

T14

58

T34

63

auto[1]

3391

1

T11

16

T14

41

T34

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2514

1

T11

14

T14

32

T34

34

auto[1]

5082

1

T11

22

T14

67

T34

65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4465

1

T11

21

T14

56

T34

57

auto[1]

3131

1

T11

15

T14

43

T34

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	285	1			T11	1		T14	4		T34	4
all_values[0]	auto[0]	auto[1]	auto[1]	218	1			T14	2		T34	2		T35	1
all_values[0]	auto[1]	auto[0]	auto[1]	191	1			T11	2		T14	4		T34	4
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T11	1		T14	1		T34	1
all_values[1]	auto[0]	auto[0]	auto[0]	270	1			T14	2		T34	1		T35	4
all_values[1]	auto[0]	auto[1]	auto[0]	227	1			T11	1		T14	5		T34	6
all_values[1]	auto[1]	auto[0]	auto[1]	214	1			T11	2		T14	2		T34	4
all_values[1]	auto[1]	auto[1]	auto[1]	133	1			T11	1		T14	2		T38	1
all_values[2]	auto[0]	auto[0]	auto[0]	211	1			T11	2		T14	5		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	85	1			T34	2		T35	1		T38	2
all_values[2]	auto[0]	auto[1]	auto[0]	129	1			T11	2		T14	2		T34	1
all_values[2]	auto[0]	auto[1]	auto[1]	75	1			T34	1		T35	2		T132	1
all_values[2]	auto[1]	auto[0]	auto[1]	206	1			T14	1		T34	5		T35	3
all_values[2]	auto[1]	auto[1]	auto[1]	138	1			T14	3		T35	1		T37	3
all_values[3]	auto[0]	auto[0]	auto[0]	186	1			T11	1		T14	2		T34	5
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T14	2		T34	1		T38	2
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T14	1		T34	1		T35	2
all_values[3]	auto[0]	auto[1]	auto[1]	101	1			T11	2		T14	1		T37	2
all_values[3]	auto[1]	auto[0]	auto[1]	180	1			T14	3		T34	2		T35	2
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T11	1		T14	2		T34	2
all_values[4]	auto[0]	auto[0]	auto[0]	168	1			T14	1		T34	3		T35	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T14	2		T35	1		T60	2
all_values[4]	auto[0]	auto[1]	auto[0]	143	1			T11	2		T35	4		T37	2
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T14	1		T34	3		T37	1
all_values[4]	auto[1]	auto[0]	auto[1]	212	1			T11	1		T14	3		T34	2
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T11	1		T14	4		T34	3
all_values[5]	auto[0]	auto[0]	auto[0]	198	1			T14	4		T34	2		T35	1
all_values[5]	auto[0]	auto[0]	auto[1]	78	1			T11	2		T14	1		T34	2
all_values[5]	auto[0]	auto[1]	auto[0]	144	1			T14	1		T34	4		T35	3
all_values[5]	auto[0]	auto[1]	auto[1]	89	1			T14	1		T133	3		T120	2
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T11	2		T14	2		T34	2
all_values[5]	auto[1]	auto[1]	auto[1]	161	1			T14	2		T34	1		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	183	1			T11	4		T14	2		T34	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T14	3		T120	2		T61	1
all_values[6]	auto[0]	auto[1]	auto[0]	170	1			T14	3		T34	3		T35	5
all_values[6]	auto[0]	auto[1]	auto[1]	81	1			T14	1		T38	2		T133	2
all_values[6]	auto[1]	auto[0]	auto[1]	199	1			T14	2		T34	5		T35	1
all_values[6]	auto[1]	auto[1]	auto[1]	139	1			T34	1		T35	1		T37	3
all_values[7]	auto[0]	auto[0]	auto[0]	197	1			T34	3		T35	1		T37	2
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T11	1		T14	1		T34	2
all_values[7]	auto[0]	auto[1]	auto[0]	154	1			T11	2		T14	4		T34	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T14	1		T34	1		T37	1
all_values[7]	auto[1]	auto[0]	auto[1]	188	1			T11	1		T14	3		T34	3
all_values[7]	auto[1]	auto[1]	auto[1]	152	1			T14	2		T34	1		T132	2
all_values[8]	auto[0]	auto[0]	auto[1]	270	1			T14	3		T34	3		T37	2
all_values[8]	auto[0]	auto[1]	auto[1]	209	1			T11	1		T14	1		T34	2
all_values[8]	auto[1]	auto[0]	auto[1]	206	1			T11	1		T14	6		T34	4
all_values[8]	auto[1]	auto[1]	auto[1]	159	1			T11	2		T14	1		T34	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal