Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1318
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T1254 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3069149493 Jul 28 07:35:10 PM PDT 24 Jul 28 07:35:11 PM PDT 24 47293923 ps
T1255 /workspace/coverage/cover_reg_top/11.uart_tl_errors.1030369514 Jul 28 07:35:09 PM PDT 24 Jul 28 07:35:10 PM PDT 24 115901190 ps
T103 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1173582005 Jul 28 07:35:08 PM PDT 24 Jul 28 07:35:09 PM PDT 24 70961765 ps
T1256 /workspace/coverage/cover_reg_top/31.uart_intr_test.864448492 Jul 28 07:35:22 PM PDT 24 Jul 28 07:35:23 PM PDT 24 22272361 ps
T1257 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2023023290 Jul 28 07:35:09 PM PDT 24 Jul 28 07:35:10 PM PDT 24 167447543 ps
T1258 /workspace/coverage/cover_reg_top/35.uart_intr_test.3163451598 Jul 28 07:35:24 PM PDT 24 Jul 28 07:35:25 PM PDT 24 12324738 ps
T1259 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1382701622 Jul 28 07:35:18 PM PDT 24 Jul 28 07:35:19 PM PDT 24 31802292 ps
T1260 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.254354235 Jul 28 07:35:06 PM PDT 24 Jul 28 07:35:07 PM PDT 24 817134580 ps
T1261 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1187381568 Jul 28 07:34:55 PM PDT 24 Jul 28 07:34:56 PM PDT 24 26740945 ps
T1262 /workspace/coverage/cover_reg_top/27.uart_intr_test.551130838 Jul 28 07:35:23 PM PDT 24 Jul 28 07:35:23 PM PDT 24 36505681 ps
T1263 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2607483435 Jul 28 07:35:18 PM PDT 24 Jul 28 07:35:19 PM PDT 24 166622454 ps
T1264 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1484903432 Jul 28 07:34:49 PM PDT 24 Jul 28 07:34:50 PM PDT 24 14393902 ps
T1265 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2222087532 Jul 28 07:35:06 PM PDT 24 Jul 28 07:35:07 PM PDT 24 1376709945 ps
T1266 /workspace/coverage/cover_reg_top/23.uart_intr_test.2829084364 Jul 28 07:35:26 PM PDT 24 Jul 28 07:35:26 PM PDT 24 30781977 ps
T1267 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.740858866 Jul 28 07:35:19 PM PDT 24 Jul 28 07:35:20 PM PDT 24 24514093 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3159574028 Jul 28 07:35:09 PM PDT 24 Jul 28 07:35:09 PM PDT 24 44938149 ps
T1269 /workspace/coverage/cover_reg_top/19.uart_tl_errors.1369391034 Jul 28 07:35:18 PM PDT 24 Jul 28 07:35:21 PM PDT 24 272080365 ps
T1270 /workspace/coverage/cover_reg_top/9.uart_csr_rw.3188179077 Jul 28 07:35:09 PM PDT 24 Jul 28 07:35:10 PM PDT 24 13404223 ps
T1271 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.471618920 Jul 28 07:35:20 PM PDT 24 Jul 28 07:35:20 PM PDT 24 54439448 ps
T1272 /workspace/coverage/cover_reg_top/11.uart_intr_test.936444018 Jul 28 07:35:05 PM PDT 24 Jul 28 07:35:06 PM PDT 24 43662049 ps
T1273 /workspace/coverage/cover_reg_top/42.uart_intr_test.3317002720 Jul 28 07:35:26 PM PDT 24 Jul 28 07:35:27 PM PDT 24 46426822 ps
T1274 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2961128242 Jul 28 07:35:04 PM PDT 24 Jul 28 07:35:04 PM PDT 24 106087342 ps
T1275 /workspace/coverage/cover_reg_top/39.uart_intr_test.3894349955 Jul 28 07:35:28 PM PDT 24 Jul 28 07:35:29 PM PDT 24 10613446 ps
T1276 /workspace/coverage/cover_reg_top/12.uart_csr_rw.210421348 Jul 28 07:35:12 PM PDT 24 Jul 28 07:35:13 PM PDT 24 41668937 ps
T1277 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3992377358 Jul 28 07:35:21 PM PDT 24 Jul 28 07:35:22 PM PDT 24 71450098 ps
T1278 /workspace/coverage/cover_reg_top/17.uart_intr_test.3743961893 Jul 28 07:35:19 PM PDT 24 Jul 28 07:35:20 PM PDT 24 20362966 ps
T1279 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1383574408 Jul 28 07:35:07 PM PDT 24 Jul 28 07:35:08 PM PDT 24 71060871 ps
T1280 /workspace/coverage/cover_reg_top/20.uart_intr_test.2825967858 Jul 28 07:35:16 PM PDT 24 Jul 28 07:35:16 PM PDT 24 35058168 ps
T1281 /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.371599113 Jul 28 07:35:19 PM PDT 24 Jul 28 07:35:19 PM PDT 24 63845308 ps
T1282 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1088221928 Jul 28 07:35:05 PM PDT 24 Jul 28 07:35:06 PM PDT 24 23351867 ps
T1283 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2496758208 Jul 28 07:34:46 PM PDT 24 Jul 28 07:34:48 PM PDT 24 339585291 ps
T1284 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3364379375 Jul 28 07:35:00 PM PDT 24 Jul 28 07:35:01 PM PDT 24 30324802 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_intr_test.3463000670 Jul 28 07:34:50 PM PDT 24 Jul 28 07:34:51 PM PDT 24 12175437 ps
T1286 /workspace/coverage/cover_reg_top/8.uart_intr_test.2689949846 Jul 28 07:35:11 PM PDT 24 Jul 28 07:35:12 PM PDT 24 12110986 ps
T1287 /workspace/coverage/cover_reg_top/28.uart_intr_test.365234129 Jul 28 07:35:24 PM PDT 24 Jul 28 07:35:25 PM PDT 24 14410972 ps
T1288 /workspace/coverage/cover_reg_top/38.uart_intr_test.3986036115 Jul 28 07:35:25 PM PDT 24 Jul 28 07:35:26 PM PDT 24 11064288 ps
T1289 /workspace/coverage/cover_reg_top/19.uart_intr_test.1674254432 Jul 28 07:35:21 PM PDT 24 Jul 28 07:35:22 PM PDT 24 76131861 ps
T1290 /workspace/coverage/cover_reg_top/13.uart_tl_errors.297212195 Jul 28 07:35:12 PM PDT 24 Jul 28 07:35:15 PM PDT 24 123092469 ps
T1291 /workspace/coverage/cover_reg_top/41.uart_intr_test.75484548 Jul 28 07:35:25 PM PDT 24 Jul 28 07:35:26 PM PDT 24 62117807 ps
T1292 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1928477661 Jul 28 07:34:53 PM PDT 24 Jul 28 07:34:55 PM PDT 24 347978003 ps
T1293 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3177318439 Jul 28 07:34:55 PM PDT 24 Jul 28 07:34:57 PM PDT 24 63258161 ps
T1294 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3579842673 Jul 28 07:35:11 PM PDT 24 Jul 28 07:35:12 PM PDT 24 31132745 ps
T1295 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2048952402 Jul 28 07:35:06 PM PDT 24 Jul 28 07:35:07 PM PDT 24 39246534 ps
T1296 /workspace/coverage/cover_reg_top/16.uart_intr_test.2690444675 Jul 28 07:35:18 PM PDT 24 Jul 28 07:35:19 PM PDT 24 54926305 ps
T1297 /workspace/coverage/cover_reg_top/33.uart_intr_test.3893204997 Jul 28 07:35:25 PM PDT 24 Jul 28 07:35:25 PM PDT 24 23063975 ps
T1298 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4128537451 Jul 28 07:35:20 PM PDT 24 Jul 28 07:35:21 PM PDT 24 29335234 ps
T1299 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.641870822 Jul 28 07:35:05 PM PDT 24 Jul 28 07:35:06 PM PDT 24 26391110 ps
T1300 /workspace/coverage/cover_reg_top/2.uart_intr_test.2978018727 Jul 28 07:34:52 PM PDT 24 Jul 28 07:34:53 PM PDT 24 19917199 ps
T1301 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3709567011 Jul 28 07:35:17 PM PDT 24 Jul 28 07:35:18 PM PDT 24 252110830 ps
T1302 /workspace/coverage/cover_reg_top/36.uart_intr_test.2960056630 Jul 28 07:35:29 PM PDT 24 Jul 28 07:35:29 PM PDT 24 41744441 ps
T1303 /workspace/coverage/cover_reg_top/4.uart_intr_test.704845265 Jul 28 07:35:04 PM PDT 24 Jul 28 07:35:05 PM PDT 24 32013800 ps
T1304 /workspace/coverage/cover_reg_top/3.uart_intr_test.1566543711 Jul 28 07:34:56 PM PDT 24 Jul 28 07:34:57 PM PDT 24 41547382 ps
T1305 /workspace/coverage/cover_reg_top/4.uart_csr_rw.302897575 Jul 28 07:34:59 PM PDT 24 Jul 28 07:35:00 PM PDT 24 53001485 ps
T1306 /workspace/coverage/cover_reg_top/30.uart_intr_test.3323451212 Jul 28 07:35:25 PM PDT 24 Jul 28 07:35:26 PM PDT 24 46461740 ps
T1307 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.710684173 Jul 28 07:35:06 PM PDT 24 Jul 28 07:35:07 PM PDT 24 85540095 ps
T1308 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2738932557 Jul 28 07:35:12 PM PDT 24 Jul 28 07:35:14 PM PDT 24 505398348 ps
T73 /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1754714737 Jul 28 07:34:50 PM PDT 24 Jul 28 07:34:51 PM PDT 24 31633761 ps
T74 /workspace/coverage/cover_reg_top/7.uart_csr_rw.236614473 Jul 28 07:35:07 PM PDT 24 Jul 28 07:35:08 PM PDT 24 40928833 ps
T1309 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.967121429 Jul 28 07:34:58 PM PDT 24 Jul 28 07:34:59 PM PDT 24 14110422 ps
T1310 /workspace/coverage/cover_reg_top/13.uart_intr_test.566830101 Jul 28 07:35:12 PM PDT 24 Jul 28 07:35:12 PM PDT 24 14899571 ps
T1311 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1384783258 Jul 28 07:34:51 PM PDT 24 Jul 28 07:34:52 PM PDT 24 18112406 ps
T1312 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2897729698 Jul 28 07:34:59 PM PDT 24 Jul 28 07:34:59 PM PDT 24 21185161 ps
T1313 /workspace/coverage/cover_reg_top/40.uart_intr_test.4091808479 Jul 28 07:35:24 PM PDT 24 Jul 28 07:35:25 PM PDT 24 12791198 ps
T1314 /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2508796576 Jul 28 07:35:20 PM PDT 24 Jul 28 07:35:21 PM PDT 24 22326555 ps
T1315 /workspace/coverage/cover_reg_top/16.uart_tl_errors.778170991 Jul 28 07:35:21 PM PDT 24 Jul 28 07:35:23 PM PDT 24 834775891 ps
T1316 /workspace/coverage/cover_reg_top/47.uart_intr_test.2785882257 Jul 28 07:35:26 PM PDT 24 Jul 28 07:35:27 PM PDT 24 37812001 ps
T1317 /workspace/coverage/cover_reg_top/44.uart_intr_test.3079747969 Jul 28 07:35:26 PM PDT 24 Jul 28 07:35:27 PM PDT 24 26397809 ps
T1318 /workspace/coverage/cover_reg_top/14.uart_intr_test.3435110427 Jul 28 07:35:11 PM PDT 24 Jul 28 07:35:12 PM PDT 24 54100492 ps

Test location /workspace/coverage/default/196.uart_fifo_reset.1739429722
Short name T1
Test name
Test status
Simulation time 145785224890 ps
CPU time 58.78 seconds
Started Jul 28 07:12:50 PM PDT 24
Finished Jul 28 07:13:48 PM PDT 24
Peak memory 200072 kb
Host smart-72f682b4-e1b7-49bf-8cba-03dabff9d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739429722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1739429722
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.540796800
Short name T14
Test name
Test status
Simulation time 256703125233 ps
CPU time 919.03 seconds
Started Jul 28 07:11:30 PM PDT 24
Finished Jul 28 07:26:49 PM PDT 24
Peak memory 225008 kb
Host smart-f19cd4f9-16a3-4908-a043-1a063b866400
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540796800 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.540796800
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.659802557
Short name T19
Test name
Test status
Simulation time 228505133518 ps
CPU time 291.93 seconds
Started Jul 28 07:08:57 PM PDT 24
Finished Jul 28 07:13:49 PM PDT 24
Peak memory 200372 kb
Host smart-35aacdd9-2c9c-4d5a-a733-6998a0e17ebb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659802557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.659802557
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3153366149
Short name T12
Test name
Test status
Simulation time 253953721419 ps
CPU time 688.24 seconds
Started Jul 28 07:09:50 PM PDT 24
Finished Jul 28 07:21:19 PM PDT 24
Peak memory 216664 kb
Host smart-b02c63e2-15e3-4c8c-8b3b-4ea2ce55f64c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153366149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3153366149
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2347415449
Short name T59
Test name
Test status
Simulation time 302901161553 ps
CPU time 1083.42 seconds
Started Jul 28 07:09:18 PM PDT 24
Finished Jul 28 07:27:22 PM PDT 24
Peak memory 227756 kb
Host smart-1897b2e1-e707-4051-860a-0444a3e98ffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347415449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2347415449
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2480943332
Short name T2
Test name
Test status
Simulation time 439833606410 ps
CPU time 153.8 seconds
Started Jul 28 07:09:08 PM PDT 24
Finished Jul 28 07:11:41 PM PDT 24
Peak memory 200184 kb
Host smart-8f66bc47-5f66-4e9b-9504-63740e8b63c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480943332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2480943332
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.425877731
Short name T38
Test name
Test status
Simulation time 278623595632 ps
CPU time 740.86 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:20:25 PM PDT 24
Peak memory 215724 kb
Host smart-63b26278-aa41-4a27-9231-956d3fed4473
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425877731 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.425877731
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.3286940008
Short name T254
Test name
Test status
Simulation time 64897572203 ps
CPU time 145.73 seconds
Started Jul 28 07:10:48 PM PDT 24
Finished Jul 28 07:13:14 PM PDT 24
Peak memory 200192 kb
Host smart-d9db42dc-d2f6-414e-bb0b-e54625147413
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286940008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.3286940008
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2598459887
Short name T120
Test name
Test status
Simulation time 678587521361 ps
CPU time 464.61 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:11:58 PM PDT 24
Peak memory 216696 kb
Host smart-9c62687e-a3eb-468d-a134-8f7713cd9d53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598459887 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2598459887
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all.1174883536
Short name T148
Test name
Test status
Simulation time 307575665448 ps
CPU time 215.29 seconds
Started Jul 28 07:07:54 PM PDT 24
Finished Jul 28 07:11:30 PM PDT 24
Peak memory 216216 kb
Host smart-bee6eaa3-a72f-40bd-98c2-900895d369ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174883536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1174883536
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.3645584095
Short name T160
Test name
Test status
Simulation time 154064408810 ps
CPU time 219.05 seconds
Started Jul 28 07:04:26 PM PDT 24
Finished Jul 28 07:08:05 PM PDT 24
Peak memory 200100 kb
Host smart-b0be418b-412b-4f8f-80e1-5def025576f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645584095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.3645584095
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_sec_cm.511456043
Short name T108
Test name
Test status
Simulation time 212440158 ps
CPU time 0.84 seconds
Started Jul 28 07:04:19 PM PDT 24
Finished Jul 28 07:04:20 PM PDT 24
Peak memory 218316 kb
Host smart-f9160d0e-12bc-4fe0-a05b-0b6bcfacb513
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511456043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.511456043
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.32732851
Short name T37
Test name
Test status
Simulation time 308222169662 ps
CPU time 649.61 seconds
Started Jul 28 07:11:27 PM PDT 24
Finished Jul 28 07:22:16 PM PDT 24
Peak memory 216792 kb
Host smart-82ff27c3-3e7a-44c5-bead-00cb681ae1d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32732851 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.32732851
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_alert_test.3695678988
Short name T340
Test name
Test status
Simulation time 22358189 ps
CPU time 0.55 seconds
Started Jul 28 07:04:30 PM PDT 24
Finished Jul 28 07:04:30 PM PDT 24
Peak memory 195568 kb
Host smart-4d8f32e6-9989-480a-aeb8-2a516304edf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695678988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3695678988
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.1709433570
Short name T6
Test name
Test status
Simulation time 106611090792 ps
CPU time 137.5 seconds
Started Jul 28 07:13:14 PM PDT 24
Finished Jul 28 07:15:32 PM PDT 24
Peak memory 200160 kb
Host smart-fefa0e02-a46e-4625-a314-94981fb45f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709433570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.1709433570
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_perf.402605330
Short name T265
Test name
Test status
Simulation time 27101534908 ps
CPU time 602.86 seconds
Started Jul 28 07:06:17 PM PDT 24
Finished Jul 28 07:16:20 PM PDT 24
Peak memory 200152 kb
Host smart-d7861cbf-88be-422b-b491-af880fb33c0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=402605330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.402605330
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1541399237
Short name T60
Test name
Test status
Simulation time 62721599433 ps
CPU time 1245.03 seconds
Started Jul 28 07:09:28 PM PDT 24
Finished Jul 28 07:30:13 PM PDT 24
Peak memory 216584 kb
Host smart-5ca0f714-d648-40e5-bb7d-b2c77e32a907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541399237 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1541399237
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.985047783
Short name T64
Test name
Test status
Simulation time 1068492037218 ps
CPU time 1215.39 seconds
Started Jul 28 07:05:20 PM PDT 24
Finished Jul 28 07:25:35 PM PDT 24
Peak memory 225072 kb
Host smart-d1ed63c0-b8d1-4664-9165-ad3acbfb3c3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985047783 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.985047783
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.2265221221
Short name T99
Test name
Test status
Simulation time 49677156 ps
CPU time 0.92 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 200056 kb
Host smart-d9c2ede0-9c8d-4a75-9f5a-36d01ec2204b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265221221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.2265221221
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.737816864
Short name T280
Test name
Test status
Simulation time 30783902727 ps
CPU time 475.19 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:16:22 PM PDT 24
Peak memory 215948 kb
Host smart-94c7fdd1-7f65-46b0-85ae-2cfffcf305c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737816864 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.737816864
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4230479833
Short name T147
Test name
Test status
Simulation time 358401754483 ps
CPU time 69.39 seconds
Started Jul 28 07:05:46 PM PDT 24
Finished Jul 28 07:06:56 PM PDT 24
Peak memory 200116 kb
Host smart-f68fdf4c-0905-4128-b9c4-2ab763bacd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230479833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4230479833
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_stress_all.1436130589
Short name T138
Test name
Test status
Simulation time 174512790003 ps
CPU time 142.3 seconds
Started Jul 28 07:07:42 PM PDT 24
Finished Jul 28 07:10:04 PM PDT 24
Peak memory 200108 kb
Host smart-6bc6c793-8e38-444f-b416-0ba1bba8cba8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436130589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1436130589
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.2637931641
Short name T11
Test name
Test status
Simulation time 144835170694 ps
CPU time 280.85 seconds
Started Jul 28 07:11:17 PM PDT 24
Finished Jul 28 07:15:58 PM PDT 24
Peak memory 216812 kb
Host smart-43aeda53-6e3c-487f-b5a3-7a979f2d1a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637931641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.2637931641
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.1388958352
Short name T68
Test name
Test status
Simulation time 49663946 ps
CPU time 0.79 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 197768 kb
Host smart-00b989f1-b9a1-49e8-8f13-f181f4bb3757
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388958352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.1388958352
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3893225005
Short name T91
Test name
Test status
Simulation time 50527551 ps
CPU time 0.59 seconds
Started Jul 28 07:34:54 PM PDT 24
Finished Jul 28 07:34:55 PM PDT 24
Peak memory 196008 kb
Host smart-a1f15189-09c4-4b67-a955-0e94a9f20532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893225005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3893225005
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/default/20.uart_stress_all.4236869933
Short name T155
Test name
Test status
Simulation time 591292715325 ps
CPU time 243.56 seconds
Started Jul 28 07:06:56 PM PDT 24
Finished Jul 28 07:11:00 PM PDT 24
Peak memory 200384 kb
Host smart-fd1a8789-6f01-42d0-8a77-fb959663860b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236869933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.4236869933
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1400917880
Short name T102
Test name
Test status
Simulation time 172224031 ps
CPU time 0.93 seconds
Started Jul 28 07:34:51 PM PDT 24
Finished Jul 28 07:34:52 PM PDT 24
Peak memory 199644 kb
Host smart-cb559a95-4f7f-446d-b311-db97a82965c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400917880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1400917880
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/29.uart_stress_all.2783304138
Short name T132
Test name
Test status
Simulation time 251687790361 ps
CPU time 177.33 seconds
Started Jul 28 07:08:08 PM PDT 24
Finished Jul 28 07:11:05 PM PDT 24
Peak memory 208648 kb
Host smart-62f5def7-d9c8-48f8-98c2-212e838526b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783304138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2783304138
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_perf.914892460
Short name T276
Test name
Test status
Simulation time 21869379311 ps
CPU time 1283.04 seconds
Started Jul 28 07:05:39 PM PDT 24
Finished Jul 28 07:27:03 PM PDT 24
Peak memory 200180 kb
Host smart-c0990581-4247-4ffe-910b-a2503beaab2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=914892460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.914892460
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2174418156
Short name T156
Test name
Test status
Simulation time 93965529485 ps
CPU time 100.34 seconds
Started Jul 28 07:06:06 PM PDT 24
Finished Jul 28 07:07:47 PM PDT 24
Peak memory 200120 kb
Host smart-3c9dba58-fc4d-4373-80a0-625233defe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174418156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2174418156
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2797278349
Short name T177
Test name
Test status
Simulation time 18299329183 ps
CPU time 32.97 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:04:46 PM PDT 24
Peak memory 200184 kb
Host smart-2aeb952e-6df5-4cf1-93a7-fcdcbd9a6d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797278349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2797278349
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1541667808
Short name T24
Test name
Test status
Simulation time 115251948294 ps
CPU time 239.64 seconds
Started Jul 28 07:08:00 PM PDT 24
Finished Jul 28 07:12:00 PM PDT 24
Peak memory 200212 kb
Host smart-a750223d-51bc-4729-94a8-1f4ab301cd7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541667808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1541667808
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all.573728461
Short name T165
Test name
Test status
Simulation time 505770472924 ps
CPU time 381.03 seconds
Started Jul 28 07:10:47 PM PDT 24
Finished Jul 28 07:17:08 PM PDT 24
Peak memory 200096 kb
Host smart-53562fa2-f758-4bbe-9db6-3bbb0393c776
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573728461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.573728461
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1240901833
Short name T79
Test name
Test status
Simulation time 46597571728 ps
CPU time 91.64 seconds
Started Jul 28 07:12:17 PM PDT 24
Finished Jul 28 07:13:49 PM PDT 24
Peak memory 200100 kb
Host smart-0d839bfe-c026-411f-ac3f-7ccc9a26fbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240901833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1240901833
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_fifo_full.605140842
Short name T266
Test name
Test status
Simulation time 95760697592 ps
CPU time 68.44 seconds
Started Jul 28 07:06:32 PM PDT 24
Finished Jul 28 07:07:41 PM PDT 24
Peak memory 200176 kb
Host smart-667a682f-4401-4590-bada-c5c95af197c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605140842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.605140842
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.2691621705
Short name T168
Test name
Test status
Simulation time 172029280658 ps
CPU time 70.59 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:14:29 PM PDT 24
Peak memory 200132 kb
Host smart-d8217c12-42d3-43d2-91f6-19372d54ed28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691621705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.2691621705
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1965688797
Short name T83
Test name
Test status
Simulation time 35027773795 ps
CPU time 17.28 seconds
Started Jul 28 07:12:17 PM PDT 24
Finished Jul 28 07:12:35 PM PDT 24
Peak memory 200168 kb
Host smart-69dde388-1bb9-412e-9a27-aed2a7bcd44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965688797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1965688797
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1067172260
Short name T203
Test name
Test status
Simulation time 116099608763 ps
CPU time 264.09 seconds
Started Jul 28 07:12:56 PM PDT 24
Finished Jul 28 07:17:20 PM PDT 24
Peak memory 200164 kb
Host smart-1a34e22e-6f88-4004-b890-f0501c3fb0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067172260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1067172260
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2266342551
Short name T157
Test name
Test status
Simulation time 13480726239 ps
CPU time 10.58 seconds
Started Jul 28 07:13:09 PM PDT 24
Finished Jul 28 07:13:19 PM PDT 24
Peak memory 199968 kb
Host smart-7a8e3f3d-3aed-49ce-a7be-6cdac2b21e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266342551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2266342551
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3998021323
Short name T293
Test name
Test status
Simulation time 100230023041 ps
CPU time 159.98 seconds
Started Jul 28 07:13:23 PM PDT 24
Finished Jul 28 07:16:03 PM PDT 24
Peak memory 200352 kb
Host smart-32c6351e-ce4c-41be-9a8d-95e0d9383604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998021323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3998021323
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1121001275
Short name T77
Test name
Test status
Simulation time 113866477210 ps
CPU time 24.63 seconds
Started Jul 28 07:05:44 PM PDT 24
Finished Jul 28 07:06:09 PM PDT 24
Peak memory 200084 kb
Host smart-2833e3dc-6527-42e8-bebb-20dc6cce955e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121001275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1121001275
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.423113163
Short name T3
Test name
Test status
Simulation time 82054885512 ps
CPU time 100.07 seconds
Started Jul 28 07:12:30 PM PDT 24
Finished Jul 28 07:14:10 PM PDT 24
Peak memory 199992 kb
Host smart-b70bb2f4-fbb7-4510-83d0-fe10cada9e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423113163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.423113163
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2067300401
Short name T139
Test name
Test status
Simulation time 163306982181 ps
CPU time 250.82 seconds
Started Jul 28 07:12:45 PM PDT 24
Finished Jul 28 07:16:56 PM PDT 24
Peak memory 200080 kb
Host smart-16fe3617-0a67-4cd8-982b-072b971486a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067300401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2067300401
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.328543891
Short name T107
Test name
Test status
Simulation time 341171694 ps
CPU time 1.34 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:13 PM PDT 24
Peak memory 200136 kb
Host smart-5c0516fd-9df3-4e95-89f1-f340dd81d610
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328543891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.328543891
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.3542669538
Short name T215
Test name
Test status
Simulation time 17141689812 ps
CPU time 13.4 seconds
Started Jul 28 07:12:28 PM PDT 24
Finished Jul 28 07:12:42 PM PDT 24
Peak memory 200120 kb
Host smart-599b6a6b-5698-4b58-8051-7409bebf465c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542669538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.3542669538
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.574831747
Short name T238
Test name
Test status
Simulation time 50229265635 ps
CPU time 87.58 seconds
Started Jul 28 07:07:00 PM PDT 24
Finished Jul 28 07:08:27 PM PDT 24
Peak memory 200052 kb
Host smart-1eb38439-5e5f-4b16-8954-79eb082b1914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574831747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.574831747
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.1021051576
Short name T10
Test name
Test status
Simulation time 204567483588 ps
CPU time 153.35 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:15:49 PM PDT 24
Peak memory 200212 kb
Host smart-5a140c15-9ba9-4af1-ac99-a3bf9b88baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021051576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.1021051576
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1685676765
Short name T233
Test name
Test status
Simulation time 133408606834 ps
CPU time 119.36 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:15:17 PM PDT 24
Peak memory 200180 kb
Host smart-5b7ec795-46c6-45e0-b380-f98f159fad67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685676765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1685676765
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1732119799
Short name T312
Test name
Test status
Simulation time 55503563837 ps
CPU time 635.21 seconds
Started Jul 28 07:07:54 PM PDT 24
Finished Jul 28 07:18:30 PM PDT 24
Peak memory 216696 kb
Host smart-341c323a-ba6e-4f63-a551-66cc86fb8cbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732119799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1732119799
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1916210899
Short name T158
Test name
Test status
Simulation time 61050562093 ps
CPU time 985.16 seconds
Started Jul 28 07:11:22 PM PDT 24
Finished Jul 28 07:27:47 PM PDT 24
Peak memory 216664 kb
Host smart-03d586ed-dff6-414f-99a6-b16241adc459
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916210899 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1916210899
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.748203208
Short name T197
Test name
Test status
Simulation time 48013693403 ps
CPU time 17.55 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:11:54 PM PDT 24
Peak memory 199956 kb
Host smart-f3c60c95-d795-44eb-9f90-b9222795b8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748203208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.748203208
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2986886179
Short name T246
Test name
Test status
Simulation time 22489307006 ps
CPU time 33.6 seconds
Started Jul 28 07:11:48 PM PDT 24
Finished Jul 28 07:12:22 PM PDT 24
Peak memory 200124 kb
Host smart-0b12baef-87ff-4640-b92b-da6e68421ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986886179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2986886179
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_stress_all.2387975305
Short name T1086
Test name
Test status
Simulation time 456088895346 ps
CPU time 781.42 seconds
Started Jul 28 07:04:18 PM PDT 24
Finished Jul 28 07:17:19 PM PDT 24
Peak memory 215676 kb
Host smart-f25c32c8-872d-4dc1-9f9f-ef8772af3d62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387975305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.2387975305
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2276533925
Short name T830
Test name
Test status
Simulation time 59472326323 ps
CPU time 119.53 seconds
Started Jul 28 07:11:55 PM PDT 24
Finished Jul 28 07:13:55 PM PDT 24
Peak memory 200156 kb
Host smart-6d60bf6c-b2a6-4c75-b783-c0766ec7db7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276533925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2276533925
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2706334751
Short name T199
Test name
Test status
Simulation time 12893354661 ps
CPU time 17.48 seconds
Started Jul 28 07:11:55 PM PDT 24
Finished Jul 28 07:12:13 PM PDT 24
Peak memory 200176 kb
Host smart-69f2b67b-8524-452c-b7b4-0dee50f6a305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706334751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2706334751
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3067594122
Short name T153
Test name
Test status
Simulation time 147296453282 ps
CPU time 32.98 seconds
Started Jul 28 07:05:35 PM PDT 24
Finished Jul 28 07:06:08 PM PDT 24
Peak memory 200100 kb
Host smart-409e9ee2-00f4-4eca-881e-95da1e7820af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067594122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3067594122
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.1273234117
Short name T216
Test name
Test status
Simulation time 173942754516 ps
CPU time 21.94 seconds
Started Jul 28 07:05:35 PM PDT 24
Finished Jul 28 07:05:57 PM PDT 24
Peak memory 200184 kb
Host smart-c5bc9803-b9cf-4e49-95d0-6729ac7b323c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273234117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.1273234117
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.288058913
Short name T181
Test name
Test status
Simulation time 99104343125 ps
CPU time 35.39 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:12:33 PM PDT 24
Peak memory 200156 kb
Host smart-7388a93a-645c-46bc-a1d8-b8ae77c48972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288058913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.288058913
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.469003530
Short name T235
Test name
Test status
Simulation time 63742255366 ps
CPU time 12.29 seconds
Started Jul 28 07:11:59 PM PDT 24
Finished Jul 28 07:12:11 PM PDT 24
Peak memory 200116 kb
Host smart-41e35e9a-9493-4615-8c42-6ded2bb23cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469003530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.469003530
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.1552933602
Short name T232
Test name
Test status
Simulation time 17011922641 ps
CPU time 29.11 seconds
Started Jul 28 07:12:03 PM PDT 24
Finished Jul 28 07:12:33 PM PDT 24
Peak memory 200176 kb
Host smart-9f984324-1834-44cc-b427-e4c266db927f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552933602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.1552933602
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.224602452
Short name T170
Test name
Test status
Simulation time 14331231373 ps
CPU time 12.34 seconds
Started Jul 28 07:12:28 PM PDT 24
Finished Jul 28 07:12:41 PM PDT 24
Peak memory 200188 kb
Host smart-4853a4bb-2d2a-4b6f-996f-570fd3133e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224602452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.224602452
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.3620029078
Short name T237
Test name
Test status
Simulation time 74956328385 ps
CPU time 57.17 seconds
Started Jul 28 07:12:36 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200008 kb
Host smart-1edf2c59-57d0-4540-b804-393e5c7b732f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620029078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.3620029078
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2424215454
Short name T244
Test name
Test status
Simulation time 172227987969 ps
CPU time 79.03 seconds
Started Jul 28 07:12:43 PM PDT 24
Finished Jul 28 07:14:02 PM PDT 24
Peak memory 200148 kb
Host smart-bbf8007d-7cf1-41df-9913-25cbffea1058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424215454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2424215454
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2283067190
Short name T226
Test name
Test status
Simulation time 15894238719 ps
CPU time 25.08 seconds
Started Jul 28 07:12:50 PM PDT 24
Finished Jul 28 07:13:15 PM PDT 24
Peak memory 200196 kb
Host smart-cf47ce6d-6a11-4a39-b286-f813a27dd003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283067190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2283067190
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2647610370
Short name T242
Test name
Test status
Simulation time 15612546043 ps
CPU time 30.28 seconds
Started Jul 28 07:12:57 PM PDT 24
Finished Jul 28 07:13:28 PM PDT 24
Peak memory 200176 kb
Host smart-fc638ae9-65a3-4400-ac21-fce7c5b9d06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647610370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2647610370
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.4085535094
Short name T240
Test name
Test status
Simulation time 56061613253 ps
CPU time 67.71 seconds
Started Jul 28 07:13:07 PM PDT 24
Finished Jul 28 07:14:15 PM PDT 24
Peak memory 200108 kb
Host smart-233117e7-0db0-4d17-a3bc-5eb6ea59325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085535094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.4085535094
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_stress_all.1538634405
Short name T241
Test name
Test status
Simulation time 209316620437 ps
CPU time 263.05 seconds
Started Jul 28 07:09:10 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200204 kb
Host smart-49665c77-8b23-4550-81be-0437257b3dd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538634405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1538634405
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3228535336
Short name T230
Test name
Test status
Simulation time 205553853983 ps
CPU time 103.33 seconds
Started Jul 28 07:09:40 PM PDT 24
Finished Jul 28 07:11:24 PM PDT 24
Peak memory 200072 kb
Host smart-f5e83321-6472-4690-badc-bb1554d676b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228535336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3228535336
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1530163129
Short name T65
Test name
Test status
Simulation time 77416382813 ps
CPU time 210.16 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 215932 kb
Host smart-f5af9133-110d-4236-8857-488276b58c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530163129 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1530163129
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.337686798
Short name T213
Test name
Test status
Simulation time 56387731010 ps
CPU time 495.33 seconds
Started Jul 28 07:11:13 PM PDT 24
Finished Jul 28 07:19:28 PM PDT 24
Peak memory 227380 kb
Host smart-09220d2d-b812-4520-b303-e000c83735af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337686798 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.337686798
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.1497677414
Short name T198
Test name
Test status
Simulation time 37629918021 ps
CPU time 62.61 seconds
Started Jul 28 07:11:47 PM PDT 24
Finished Jul 28 07:12:50 PM PDT 24
Peak memory 200184 kb
Host smart-2df9c9e5-d1e1-49a0-a6bf-a9c47707e001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497677414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.1497677414
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3767109978
Short name T1212
Test name
Test status
Simulation time 330096580 ps
CPU time 1.51 seconds
Started Jul 28 07:34:52 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 198620 kb
Host smart-d54259e3-6062-464e-81cf-1a5a2df3b230
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767109978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3767109978
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1384783258
Short name T1311
Test name
Test status
Simulation time 18112406 ps
CPU time 0.59 seconds
Started Jul 28 07:34:51 PM PDT 24
Finished Jul 28 07:34:52 PM PDT 24
Peak memory 196320 kb
Host smart-81f30cdd-0168-417b-83ff-abcff48ae27e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384783258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1384783258
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2971550815
Short name T1200
Test name
Test status
Simulation time 172784635 ps
CPU time 0.75 seconds
Started Jul 28 07:34:50 PM PDT 24
Finished Jul 28 07:34:51 PM PDT 24
Peak memory 199904 kb
Host smart-d4525479-0d27-4067-ad5e-853014190a06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971550815 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2971550815
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.3562566523
Short name T1196
Test name
Test status
Simulation time 49878786 ps
CPU time 0.6 seconds
Started Jul 28 07:34:54 PM PDT 24
Finished Jul 28 07:34:55 PM PDT 24
Peak memory 196012 kb
Host smart-3f58f60f-4b8c-4c16-94da-dbe434056e81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562566523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.3562566523
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.1723120328
Short name T1195
Test name
Test status
Simulation time 46355756 ps
CPU time 0.57 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:53 PM PDT 24
Peak memory 195284 kb
Host smart-f6e996df-73b9-45e9-be6a-a97dcb62125d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723120328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.1723120328
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1484903432
Short name T1264
Test name
Test status
Simulation time 14393902 ps
CPU time 0.7 seconds
Started Jul 28 07:34:49 PM PDT 24
Finished Jul 28 07:34:50 PM PDT 24
Peak memory 197580 kb
Host smart-f9593806-0e0a-4598-a3ce-611a1a125c73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484903432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1484903432
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1485064703
Short name T1235
Test name
Test status
Simulation time 81323713 ps
CPU time 1.74 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 200900 kb
Host smart-e522e588-697f-43d0-a1cb-d87a26e1a99a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485064703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1485064703
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2496758208
Short name T1283
Test name
Test status
Simulation time 339585291 ps
CPU time 1.3 seconds
Started Jul 28 07:34:46 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 200380 kb
Host smart-e8828b4b-1006-4468-bc36-5942c6134bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496758208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2496758208
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2466287503
Short name T85
Test name
Test status
Simulation time 159965011 ps
CPU time 0.65 seconds
Started Jul 28 07:34:47 PM PDT 24
Finished Jul 28 07:34:48 PM PDT 24
Peak memory 195972 kb
Host smart-d7a564c5-f0db-4d05-95a9-d48e7a049172
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466287503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2466287503
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2172410674
Short name T1226
Test name
Test status
Simulation time 36401227 ps
CPU time 1.36 seconds
Started Jul 28 07:34:50 PM PDT 24
Finished Jul 28 07:34:51 PM PDT 24
Peak memory 198192 kb
Host smart-0131e944-2f76-426f-867a-895e76c11aba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172410674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2172410674
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1754714737
Short name T73
Test name
Test status
Simulation time 31633761 ps
CPU time 0.59 seconds
Started Jul 28 07:34:50 PM PDT 24
Finished Jul 28 07:34:51 PM PDT 24
Peak memory 196292 kb
Host smart-fdae18bb-b172-46b0-ae28-b97645e89cd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754714737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1754714737
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2504315666
Short name T1238
Test name
Test status
Simulation time 22640478 ps
CPU time 1.07 seconds
Started Jul 28 07:34:54 PM PDT 24
Finished Jul 28 07:34:55 PM PDT 24
Peak memory 200760 kb
Host smart-c4833247-37a0-4499-900d-389834ec4992
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504315666 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2504315666
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3463000670
Short name T1285
Test name
Test status
Simulation time 12175437 ps
CPU time 0.53 seconds
Started Jul 28 07:34:50 PM PDT 24
Finished Jul 28 07:34:51 PM PDT 24
Peak memory 195232 kb
Host smart-10517256-ff83-452c-a930-05d91974482d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463000670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3463000670
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3430914273
Short name T89
Test name
Test status
Simulation time 111158457 ps
CPU time 0.73 seconds
Started Jul 28 07:34:52 PM PDT 24
Finished Jul 28 07:34:53 PM PDT 24
Peak memory 197916 kb
Host smart-9e3bfeff-d766-40a2-b1df-0c5c4daff943
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430914273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3430914273
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.369631444
Short name T1205
Test name
Test status
Simulation time 359740481 ps
CPU time 1.95 seconds
Started Jul 28 07:34:52 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 201004 kb
Host smart-9fe5da71-37e4-4dfd-9672-6189d4a434d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369631444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.369631444
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.2961128242
Short name T1274
Test name
Test status
Simulation time 106087342 ps
CPU time 0.71 seconds
Started Jul 28 07:35:04 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 199052 kb
Host smart-28670598-b405-480b-92d7-c3ed568d7aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961128242 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.2961128242
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.478926647
Short name T1234
Test name
Test status
Simulation time 15769145 ps
CPU time 0.6 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 196340 kb
Host smart-e2d759e3-e7e7-474a-a636-7f88c37c11a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478926647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.478926647
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.83365267
Short name T1217
Test name
Test status
Simulation time 86669484 ps
CPU time 0.57 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 195324 kb
Host smart-73048609-3aec-461f-9508-57e6120a9e24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83365267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.83365267
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.684789619
Short name T1240
Test name
Test status
Simulation time 30974656 ps
CPU time 0.73 seconds
Started Jul 28 07:35:08 PM PDT 24
Finished Jul 28 07:35:09 PM PDT 24
Peak memory 197744 kb
Host smart-b5d10d5b-5322-4ba4-b19a-0eb9c8cff6b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684789619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.684789619
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.173501803
Short name T1239
Test name
Test status
Simulation time 43401259 ps
CPU time 1.05 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:15 PM PDT 24
Peak memory 200880 kb
Host smart-3c2676f0-39d0-4388-be80-e682ee089677
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173501803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.173501803
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2023023290
Short name T1257
Test name
Test status
Simulation time 167447543 ps
CPU time 0.91 seconds
Started Jul 28 07:35:09 PM PDT 24
Finished Jul 28 07:35:10 PM PDT 24
Peak memory 199780 kb
Host smart-109b27a1-6b70-431a-a25d-5b21f247618c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023023290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2023023290
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.3069149493
Short name T1254
Test name
Test status
Simulation time 47293923 ps
CPU time 0.74 seconds
Started Jul 28 07:35:10 PM PDT 24
Finished Jul 28 07:35:11 PM PDT 24
Peak memory 200364 kb
Host smart-fdae28a3-6e67-4e00-a12c-776f7ef04e5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069149493 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.3069149493
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3059521045
Short name T95
Test name
Test status
Simulation time 12167001 ps
CPU time 0.66 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 196648 kb
Host smart-3e1594ca-d18c-4ace-9030-d7174688a505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059521045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3059521045
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.936444018
Short name T1272
Test name
Test status
Simulation time 43662049 ps
CPU time 0.53 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 195232 kb
Host smart-b06b9678-d1ec-4684-8f78-f9cbc015607d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936444018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.936444018
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3994784301
Short name T90
Test name
Test status
Simulation time 67202081 ps
CPU time 0.64 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:13 PM PDT 24
Peak memory 196736 kb
Host smart-7f7f92ed-d143-4021-a0c9-9f51438cf69c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994784301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.3994784301
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.1030369514
Short name T1255
Test name
Test status
Simulation time 115901190 ps
CPU time 1.06 seconds
Started Jul 28 07:35:09 PM PDT 24
Finished Jul 28 07:35:10 PM PDT 24
Peak memory 200668 kb
Host smart-7bed89f5-bdee-470a-8df7-cd0b8b1d492b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030369514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.1030369514
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.2222087532
Short name T1265
Test name
Test status
Simulation time 1376709945 ps
CPU time 1.28 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 200268 kb
Host smart-4f83fb9a-33f1-4e6c-91bb-ea471f339d40
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222087532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.2222087532
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.7444285
Short name T1191
Test name
Test status
Simulation time 52524415 ps
CPU time 0.7 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 199240 kb
Host smart-627dc64b-8f6c-4f2b-98fb-842f39b6fe63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7444285 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.7444285
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.210421348
Short name T1276
Test name
Test status
Simulation time 41668937 ps
CPU time 0.58 seconds
Started Jul 28 07:35:12 PM PDT 24
Finished Jul 28 07:35:13 PM PDT 24
Peak memory 196328 kb
Host smart-9e662c0c-7f17-4ed3-961b-830ad5ee0844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210421348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.210421348
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.931981632
Short name T1204
Test name
Test status
Simulation time 101633665 ps
CPU time 0.56 seconds
Started Jul 28 07:35:15 PM PDT 24
Finished Jul 28 07:35:16 PM PDT 24
Peak memory 195252 kb
Host smart-21cb2ed1-839f-4f98-8652-a1e1673a6be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931981632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.931981632
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3000741974
Short name T94
Test name
Test status
Simulation time 20303945 ps
CPU time 0.76 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 198448 kb
Host smart-7d331f1c-7360-4f99-965d-21cc62932117
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000741974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3000741974
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1439467113
Short name T1201
Test name
Test status
Simulation time 151566451 ps
CPU time 1.39 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:13 PM PDT 24
Peak memory 200964 kb
Host smart-0450af28-b0f2-410a-9ebd-06f160d0074c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439467113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1439467113
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3904584024
Short name T98
Test name
Test status
Simulation time 331750131 ps
CPU time 1.38 seconds
Started Jul 28 07:35:12 PM PDT 24
Finished Jul 28 07:35:13 PM PDT 24
Peak memory 200248 kb
Host smart-b3d67263-7d83-4c3e-996b-0952b46c3b36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904584024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3904584024
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.3203665258
Short name T1214
Test name
Test status
Simulation time 86557462 ps
CPU time 0.82 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 200884 kb
Host smart-11c42d2f-250c-4833-94fd-eefe74c13346
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203665258 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.3203665258
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.3440145935
Short name T71
Test name
Test status
Simulation time 14702211 ps
CPU time 0.57 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 196324 kb
Host smart-eddb9d02-7259-4883-b237-562d2c51b348
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440145935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.3440145935
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.566830101
Short name T1310
Test name
Test status
Simulation time 14899571 ps
CPU time 0.57 seconds
Started Jul 28 07:35:12 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 195316 kb
Host smart-9520cb1f-f808-458a-9074-5629bb1b5ae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566830101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.566830101
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.2217517598
Short name T1236
Test name
Test status
Simulation time 19682502 ps
CPU time 0.66 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 196540 kb
Host smart-33dfbf35-2331-4015-a585-d1524746f516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217517598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.2217517598
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.297212195
Short name T1290
Test name
Test status
Simulation time 123092469 ps
CPU time 2.2 seconds
Started Jul 28 07:35:12 PM PDT 24
Finished Jul 28 07:35:15 PM PDT 24
Peak memory 200932 kb
Host smart-2539c3af-456a-4adf-a656-7eecadcf995f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297212195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.297212195
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.4270326576
Short name T100
Test name
Test status
Simulation time 997930320 ps
CPU time 1.25 seconds
Started Jul 28 07:35:17 PM PDT 24
Finished Jul 28 07:35:18 PM PDT 24
Peak memory 199964 kb
Host smart-14ad9cba-17f0-4cce-bf6e-88f9333aff98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270326576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.4270326576
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.4035502288
Short name T1252
Test name
Test status
Simulation time 47152278 ps
CPU time 0.77 seconds
Started Jul 28 07:35:10 PM PDT 24
Finished Jul 28 07:35:11 PM PDT 24
Peak memory 199524 kb
Host smart-e493733f-97d3-4f15-bd62-c4c1e495b20f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035502288 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.4035502288
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.19534599
Short name T1225
Test name
Test status
Simulation time 57864642 ps
CPU time 0.6 seconds
Started Jul 28 07:35:13 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 196252 kb
Host smart-6c9fdab6-4ea7-473a-8a36-a33bfe11108a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19534599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.19534599
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3435110427
Short name T1318
Test name
Test status
Simulation time 54100492 ps
CPU time 0.57 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 195428 kb
Host smart-364df96c-26f6-41b1-b106-cb91daa1e83c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435110427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3435110427
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3579842673
Short name T1294
Test name
Test status
Simulation time 31132745 ps
CPU time 0.65 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 196444 kb
Host smart-8fb7d463-92ae-423f-aed7-41210a5e97d6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579842673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3579842673
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2244781859
Short name T1208
Test name
Test status
Simulation time 193510508 ps
CPU time 2.55 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 200932 kb
Host smart-c4623214-2bc3-4657-a79f-72ff5ca3d6ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244781859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2244781859
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.3574578926
Short name T1197
Test name
Test status
Simulation time 38920690 ps
CPU time 0.77 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 200480 kb
Host smart-b21498fd-9842-47b5-ad84-71265a2fd76d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574578926 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.3574578926
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2291312634
Short name T1194
Test name
Test status
Simulation time 36663982 ps
CPU time 0.59 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:21 PM PDT 24
Peak memory 196252 kb
Host smart-3034d0f6-0998-4b45-bfae-cec4175666cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291312634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2291312634
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2610904661
Short name T1230
Test name
Test status
Simulation time 52346543 ps
CPU time 0.56 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 195256 kb
Host smart-296d7a28-c601-447c-b9dc-e913fde2abef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610904661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2610904661
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.2508796576
Short name T1314
Test name
Test status
Simulation time 22326555 ps
CPU time 0.66 seconds
Started Jul 28 07:35:20 PM PDT 24
Finished Jul 28 07:35:21 PM PDT 24
Peak memory 196908 kb
Host smart-e2de32d6-1dde-4cc5-8fdb-1110f406ae1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508796576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.2508796576
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2738932557
Short name T1308
Test name
Test status
Simulation time 505398348 ps
CPU time 1.92 seconds
Started Jul 28 07:35:12 PM PDT 24
Finished Jul 28 07:35:14 PM PDT 24
Peak memory 200852 kb
Host smart-624402c7-2310-4804-9b63-e524ec57363f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738932557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2738932557
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3792201466
Short name T106
Test name
Test status
Simulation time 290622115 ps
CPU time 0.94 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:22 PM PDT 24
Peak memory 199792 kb
Host smart-1d9613fe-acd9-4476-90d2-da772f77f4ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792201466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3792201466
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.3992377358
Short name T1277
Test name
Test status
Simulation time 71450098 ps
CPU time 0.91 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:22 PM PDT 24
Peak memory 200760 kb
Host smart-45eaaac1-49fc-4019-a4bf-ae189cb3be30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992377358 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.3992377358
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1696055736
Short name T92
Test name
Test status
Simulation time 25095075 ps
CPU time 0.6 seconds
Started Jul 28 07:35:15 PM PDT 24
Finished Jul 28 07:35:15 PM PDT 24
Peak memory 196496 kb
Host smart-764f649e-3240-443c-b768-f6f0b56782e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696055736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1696055736
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2690444675
Short name T1296
Test name
Test status
Simulation time 54926305 ps
CPU time 0.57 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 195312 kb
Host smart-9d82d804-b2c3-4c85-92fc-090a059e8e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690444675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2690444675
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.4265622049
Short name T1244
Test name
Test status
Simulation time 17419408 ps
CPU time 0.73 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 197824 kb
Host smart-0f86d2f7-ea68-40b4-9687-8b3c559eafdb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265622049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.4265622049
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.778170991
Short name T1315
Test name
Test status
Simulation time 834775891 ps
CPU time 1.36 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:23 PM PDT 24
Peak memory 200924 kb
Host smart-aa5dffc3-ef26-44ae-84bd-97709d34de09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778170991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.778170991
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2279324846
Short name T134
Test name
Test status
Simulation time 74372661 ps
CPU time 1.27 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:22 PM PDT 24
Peak memory 200112 kb
Host smart-b5a576de-f0f9-45a5-950d-e5192d9668eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279324846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2279324846
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.341474504
Short name T1206
Test name
Test status
Simulation time 56553832 ps
CPU time 0.86 seconds
Started Jul 28 07:35:17 PM PDT 24
Finished Jul 28 07:35:18 PM PDT 24
Peak memory 200748 kb
Host smart-90fdb763-08ed-4790-9563-0a8def74e167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341474504 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.341474504
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1382701622
Short name T1259
Test name
Test status
Simulation time 31802292 ps
CPU time 0.58 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 196292 kb
Host smart-09fd257f-e759-49f8-afeb-70d6fd8a2dfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382701622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1382701622
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3743961893
Short name T1278
Test name
Test status
Simulation time 20362966 ps
CPU time 0.56 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 195304 kb
Host smart-86d3fa8b-db6b-4a33-97c5-201864e1dd1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743961893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3743961893
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.740858866
Short name T1267
Test name
Test status
Simulation time 24514093 ps
CPU time 0.74 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 196924 kb
Host smart-f0363d67-ee66-431c-b554-e703eba8cc28
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740858866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.740858866
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2809195733
Short name T1203
Test name
Test status
Simulation time 423105188 ps
CPU time 2.25 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 200920 kb
Host smart-9c849a36-c049-43c8-97f6-6da45ec47484
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809195733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2809195733
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3785280786
Short name T101
Test name
Test status
Simulation time 44764512 ps
CPU time 0.91 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 199640 kb
Host smart-b915b6fb-5bf8-46d9-8573-40742ad1a1f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785280786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3785280786
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.471618920
Short name T1271
Test name
Test status
Simulation time 54439448 ps
CPU time 0.62 seconds
Started Jul 28 07:35:20 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 198328 kb
Host smart-0c91d964-adcf-46c3-980d-7ec7cdc1654e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471618920 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.471618920
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.1914808687
Short name T69
Test name
Test status
Simulation time 41504724 ps
CPU time 0.59 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 196320 kb
Host smart-50763e46-8137-4f90-adf0-990cf94a31c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914808687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1914808687
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3296089426
Short name T1207
Test name
Test status
Simulation time 44215177 ps
CPU time 0.58 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 195200 kb
Host smart-f2a7dfbb-10d2-4969-9e59-a585e2a4cbd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296089426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3296089426
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2607483435
Short name T1263
Test name
Test status
Simulation time 166622454 ps
CPU time 0.65 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 196412 kb
Host smart-c9d1cbad-d3be-429d-b80e-1316182555ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607483435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2607483435
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.218453517
Short name T1245
Test name
Test status
Simulation time 83040176 ps
CPU time 1.25 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 200984 kb
Host smart-74c014b6-b87e-4dbe-b0ee-8cfcea8fb640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218453517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.218453517
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.3709567011
Short name T1301
Test name
Test status
Simulation time 252110830 ps
CPU time 1.27 seconds
Started Jul 28 07:35:17 PM PDT 24
Finished Jul 28 07:35:18 PM PDT 24
Peak memory 200304 kb
Host smart-85d27f88-0b4c-44c9-ab99-a91414fad2fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709567011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.3709567011
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.4128537451
Short name T1298
Test name
Test status
Simulation time 29335234 ps
CPU time 0.9 seconds
Started Jul 28 07:35:20 PM PDT 24
Finished Jul 28 07:35:21 PM PDT 24
Peak memory 200764 kb
Host smart-be80ee85-8581-424c-b4ce-80ce8a010a80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128537451 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.4128537451
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3968855235
Short name T1253
Test name
Test status
Simulation time 29942940 ps
CPU time 0.62 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 196360 kb
Host smart-a2d55cee-3ea2-4d14-896a-d844a887b44b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968855235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3968855235
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1674254432
Short name T1289
Test name
Test status
Simulation time 76131861 ps
CPU time 0.59 seconds
Started Jul 28 07:35:21 PM PDT 24
Finished Jul 28 07:35:22 PM PDT 24
Peak memory 195268 kb
Host smart-dc42a84f-c6c7-4a0c-89a3-217158e484ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674254432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1674254432
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.371599113
Short name T1281
Test name
Test status
Simulation time 63845308 ps
CPU time 0.76 seconds
Started Jul 28 07:35:19 PM PDT 24
Finished Jul 28 07:35:19 PM PDT 24
Peak memory 196944 kb
Host smart-76f6725e-f970-45b9-8db9-a64eef4b6203
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371599113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.371599113
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.1369391034
Short name T1269
Test name
Test status
Simulation time 272080365 ps
CPU time 2.32 seconds
Started Jul 28 07:35:18 PM PDT 24
Finished Jul 28 07:35:21 PM PDT 24
Peak memory 200952 kb
Host smart-1ece6fa0-9621-4f3d-ba02-74b0c3dccd20
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369391034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.1369391034
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2897729698
Short name T1312
Test name
Test status
Simulation time 21185161 ps
CPU time 0.72 seconds
Started Jul 28 07:34:59 PM PDT 24
Finished Jul 28 07:34:59 PM PDT 24
Peak memory 196288 kb
Host smart-563887a9-86ba-4c7d-b909-cc463a1898a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897729698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2897729698
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1316742833
Short name T1220
Test name
Test status
Simulation time 231074280 ps
CPU time 1.62 seconds
Started Jul 28 07:34:58 PM PDT 24
Finished Jul 28 07:35:00 PM PDT 24
Peak memory 198736 kb
Host smart-69813267-a7e4-4616-8956-42f257f8bce2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316742833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1316742833
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.167040546
Short name T86
Test name
Test status
Simulation time 21806524 ps
CPU time 0.6 seconds
Started Jul 28 07:35:00 PM PDT 24
Finished Jul 28 07:35:00 PM PDT 24
Peak memory 196292 kb
Host smart-fc492202-d092-4647-b9da-d3c417f68490
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167040546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.167040546
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3177318439
Short name T1293
Test name
Test status
Simulation time 63258161 ps
CPU time 0.86 seconds
Started Jul 28 07:34:55 PM PDT 24
Finished Jul 28 07:34:57 PM PDT 24
Peak memory 200756 kb
Host smart-29144324-481d-4d38-82e9-08f606cfc219
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177318439 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3177318439
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.262647030
Short name T72
Test name
Test status
Simulation time 11752892 ps
CPU time 0.6 seconds
Started Jul 28 07:34:58 PM PDT 24
Finished Jul 28 07:34:59 PM PDT 24
Peak memory 196376 kb
Host smart-0753c14e-b6f0-4380-a446-24abbd3c9633
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262647030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.262647030
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2978018727
Short name T1300
Test name
Test status
Simulation time 19917199 ps
CPU time 0.55 seconds
Started Jul 28 07:34:52 PM PDT 24
Finished Jul 28 07:34:53 PM PDT 24
Peak memory 195232 kb
Host smart-8220772d-62f7-48ae-89ae-27082a5b024e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978018727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2978018727
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3383363973
Short name T93
Test name
Test status
Simulation time 107622533 ps
CPU time 0.76 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 198248 kb
Host smart-4516ffd0-e455-41c0-a384-f381e2696842
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383363973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3383363973
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.2657049069
Short name T1237
Test name
Test status
Simulation time 108195302 ps
CPU time 1.32 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 200904 kb
Host smart-a64883e8-7e03-4a51-bc88-44918a8e03a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657049069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.2657049069
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3809974356
Short name T97
Test name
Test status
Simulation time 241941136 ps
CPU time 0.97 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:54 PM PDT 24
Peak memory 199768 kb
Host smart-bc7c4a1f-f487-4eb0-8fdb-ebe7f678badc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809974356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3809974356
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2825967858
Short name T1280
Test name
Test status
Simulation time 35058168 ps
CPU time 0.57 seconds
Started Jul 28 07:35:16 PM PDT 24
Finished Jul 28 07:35:16 PM PDT 24
Peak memory 195232 kb
Host smart-29f59e67-1278-429c-9b73-fa65924415e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825967858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2825967858
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.3738002741
Short name T1190
Test name
Test status
Simulation time 31886717 ps
CPU time 0.55 seconds
Started Jul 28 07:35:20 PM PDT 24
Finished Jul 28 07:35:20 PM PDT 24
Peak memory 195304 kb
Host smart-2af75572-5e39-406b-8a32-df091436df6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738002741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.3738002741
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1249045691
Short name T1243
Test name
Test status
Simulation time 22856794 ps
CPU time 0.57 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:32 PM PDT 24
Peak memory 195172 kb
Host smart-9f8a0ef4-d2c3-44c3-ba6d-20ea8ad3c571
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249045691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1249045691
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2829084364
Short name T1266
Test name
Test status
Simulation time 30781977 ps
CPU time 0.58 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195272 kb
Host smart-de13c39b-5020-4e55-af30-44958cc9d609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829084364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2829084364
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.547327962
Short name T1210
Test name
Test status
Simulation time 37115521 ps
CPU time 0.57 seconds
Started Jul 28 07:35:31 PM PDT 24
Finished Jul 28 07:35:31 PM PDT 24
Peak memory 195240 kb
Host smart-1810f9b1-5c7a-4444-80fc-a3d81867c21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547327962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.547327962
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3235314198
Short name T1193
Test name
Test status
Simulation time 30339185 ps
CPU time 0.58 seconds
Started Jul 28 07:35:32 PM PDT 24
Finished Jul 28 07:35:33 PM PDT 24
Peak memory 195188 kb
Host smart-a8073bca-38ea-4169-82a9-1622458c1949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235314198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3235314198
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.618759133
Short name T1227
Test name
Test status
Simulation time 12023294 ps
CPU time 0.54 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 195280 kb
Host smart-8b6623b4-f6cc-449b-89d6-877165e6832d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618759133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.618759133
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.551130838
Short name T1262
Test name
Test status
Simulation time 36505681 ps
CPU time 0.63 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:23 PM PDT 24
Peak memory 195332 kb
Host smart-b52ffcc7-744e-4651-8901-cdb0815c6b2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551130838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.551130838
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.365234129
Short name T1287
Test name
Test status
Simulation time 14410972 ps
CPU time 0.57 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:25 PM PDT 24
Peak memory 195304 kb
Host smart-b8c33882-641b-4d2d-9709-297dd9aae70b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365234129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.365234129
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2872391607
Short name T1233
Test name
Test status
Simulation time 36576195 ps
CPU time 0.59 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:23 PM PDT 24
Peak memory 195256 kb
Host smart-e397454f-cb1a-441e-a296-79198f9baab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872391607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2872391607
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.967121429
Short name T1309
Test name
Test status
Simulation time 14110422 ps
CPU time 0.65 seconds
Started Jul 28 07:34:58 PM PDT 24
Finished Jul 28 07:34:59 PM PDT 24
Peak memory 195756 kb
Host smart-5234804f-3a9d-474d-9e5f-73764a52160f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967121429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.967121429
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1928477661
Short name T1292
Test name
Test status
Simulation time 347978003 ps
CPU time 2.49 seconds
Started Jul 28 07:34:53 PM PDT 24
Finished Jul 28 07:34:55 PM PDT 24
Peak memory 198712 kb
Host smart-83de2e22-f9a6-4d1a-8996-c13298b4c7ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928477661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1928477661
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1187381568
Short name T1261
Test name
Test status
Simulation time 26740945 ps
CPU time 0.63 seconds
Started Jul 28 07:34:55 PM PDT 24
Finished Jul 28 07:34:56 PM PDT 24
Peak memory 196304 kb
Host smart-391ba896-dbbd-4fab-8330-e79dac87c17d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187381568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1187381568
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.4053235198
Short name T1231
Test name
Test status
Simulation time 70874997 ps
CPU time 0.76 seconds
Started Jul 28 07:34:57 PM PDT 24
Finished Jul 28 07:34:58 PM PDT 24
Peak memory 199964 kb
Host smart-55dc402f-54a9-4b7d-950d-011828732551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053235198 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.4053235198
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2826836999
Short name T1198
Test name
Test status
Simulation time 44291646 ps
CPU time 0.58 seconds
Started Jul 28 07:35:00 PM PDT 24
Finished Jul 28 07:35:00 PM PDT 24
Peak memory 196276 kb
Host smart-2cf5bc3c-0dc1-4a0c-a2e8-5051eed6e500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826836999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2826836999
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1566543711
Short name T1304
Test name
Test status
Simulation time 41547382 ps
CPU time 0.58 seconds
Started Jul 28 07:34:56 PM PDT 24
Finished Jul 28 07:34:57 PM PDT 24
Peak memory 195320 kb
Host smart-df7fb03d-0784-4b3f-9c4f-62c5b344a4ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566543711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1566543711
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.2751072459
Short name T1251
Test name
Test status
Simulation time 28312875 ps
CPU time 0.72 seconds
Started Jul 28 07:34:57 PM PDT 24
Finished Jul 28 07:34:58 PM PDT 24
Peak memory 197828 kb
Host smart-d8548e3d-4845-44af-9d82-35df1fb2a537
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751072459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.2751072459
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1539392808
Short name T1186
Test name
Test status
Simulation time 72481935 ps
CPU time 1.52 seconds
Started Jul 28 07:34:54 PM PDT 24
Finished Jul 28 07:34:56 PM PDT 24
Peak memory 200976 kb
Host smart-569bfadc-0ab9-4cb0-a622-4ca3a2f85e67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539392808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1539392808
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2080037724
Short name T104
Test name
Test status
Simulation time 144060045 ps
CPU time 0.96 seconds
Started Jul 28 07:34:56 PM PDT 24
Finished Jul 28 07:34:57 PM PDT 24
Peak memory 200040 kb
Host smart-d881dfa4-2852-4076-a311-25889e9f2ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080037724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2080037724
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.3323451212
Short name T1306
Test name
Test status
Simulation time 46461740 ps
CPU time 0.58 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195344 kb
Host smart-0ade9b48-03d4-49c7-a408-ad3b513e6acf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323451212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.3323451212
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.864448492
Short name T1256
Test name
Test status
Simulation time 22272361 ps
CPU time 0.56 seconds
Started Jul 28 07:35:22 PM PDT 24
Finished Jul 28 07:35:23 PM PDT 24
Peak memory 195348 kb
Host smart-a9aca906-6abe-4faf-a125-5a5abae31d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864448492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.864448492
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.3282539318
Short name T1248
Test name
Test status
Simulation time 22239612 ps
CPU time 0.66 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195300 kb
Host smart-90206f4a-acf1-41cf-99af-17e011b83828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282539318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.3282539318
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.3893204997
Short name T1297
Test name
Test status
Simulation time 23063975 ps
CPU time 0.57 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:25 PM PDT 24
Peak memory 195308 kb
Host smart-748bdcae-a649-480b-b036-5913d3f1f953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893204997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.3893204997
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.4170892312
Short name T1223
Test name
Test status
Simulation time 13371455 ps
CPU time 0.57 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:27 PM PDT 24
Peak memory 195324 kb
Host smart-03633b45-c441-4599-aa9e-c35f3ef6a4ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170892312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.4170892312
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3163451598
Short name T1258
Test name
Test status
Simulation time 12324738 ps
CPU time 0.62 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:25 PM PDT 24
Peak memory 195312 kb
Host smart-ec33cc7a-1841-48a4-bc52-2ea205ad30a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163451598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3163451598
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2960056630
Short name T1302
Test name
Test status
Simulation time 41744441 ps
CPU time 0.54 seconds
Started Jul 28 07:35:29 PM PDT 24
Finished Jul 28 07:35:29 PM PDT 24
Peak memory 195356 kb
Host smart-39026d5d-20da-4c52-84bc-e2d950128953
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960056630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2960056630
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2384373294
Short name T1192
Test name
Test status
Simulation time 31997579 ps
CPU time 0.55 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 195304 kb
Host smart-adb06c2b-35f6-4303-9197-7984ac00068a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384373294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2384373294
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3986036115
Short name T1288
Test name
Test status
Simulation time 11064288 ps
CPU time 0.58 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195300 kb
Host smart-836d1202-2a2c-4502-82bc-f1cc321a650b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986036115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3986036115
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3894349955
Short name T1275
Test name
Test status
Simulation time 10613446 ps
CPU time 0.55 seconds
Started Jul 28 07:35:28 PM PDT 24
Finished Jul 28 07:35:29 PM PDT 24
Peak memory 195284 kb
Host smart-2f65c924-c0e6-4034-938a-8734bf4e7556
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894349955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3894349955
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3364379375
Short name T1284
Test name
Test status
Simulation time 30324802 ps
CPU time 0.78 seconds
Started Jul 28 07:35:00 PM PDT 24
Finished Jul 28 07:35:01 PM PDT 24
Peak memory 197200 kb
Host smart-36a748ff-7dc3-4001-b734-ad36a7a8626b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364379375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3364379375
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.1265908604
Short name T1213
Test name
Test status
Simulation time 720580763 ps
CPU time 2.5 seconds
Started Jul 28 07:35:01 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 198936 kb
Host smart-33420fca-378f-43db-aaf6-91f28e44c106
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265908604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.1265908604
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.865064795
Short name T1216
Test name
Test status
Simulation time 14133135 ps
CPU time 0.57 seconds
Started Jul 28 07:35:01 PM PDT 24
Finished Jul 28 07:35:02 PM PDT 24
Peak memory 196280 kb
Host smart-d1045cf3-ce15-42ca-b5d7-999e77f0627a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865064795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.865064795
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1020521900
Short name T1247
Test name
Test status
Simulation time 75024785 ps
CPU time 0.76 seconds
Started Jul 28 07:35:01 PM PDT 24
Finished Jul 28 07:35:02 PM PDT 24
Peak memory 199212 kb
Host smart-e9ce024a-a3de-4876-9ab2-6bcdf1433f3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020521900 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1020521900
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.302897575
Short name T1305
Test name
Test status
Simulation time 53001485 ps
CPU time 0.59 seconds
Started Jul 28 07:34:59 PM PDT 24
Finished Jul 28 07:35:00 PM PDT 24
Peak memory 196384 kb
Host smart-81e378a9-7ec3-4dd8-ac34-f2f00615988d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302897575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.302897575
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.704845265
Short name T1303
Test name
Test status
Simulation time 32013800 ps
CPU time 0.57 seconds
Started Jul 28 07:35:04 PM PDT 24
Finished Jul 28 07:35:05 PM PDT 24
Peak memory 195304 kb
Host smart-77119118-9b79-4474-96ae-f856e6b15bdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704845265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.704845265
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.2149769410
Short name T1246
Test name
Test status
Simulation time 33778678 ps
CPU time 0.63 seconds
Started Jul 28 07:35:00 PM PDT 24
Finished Jul 28 07:35:01 PM PDT 24
Peak memory 195764 kb
Host smart-90f60239-d7ba-494c-8d75-0d521e676b99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149769410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.2149769410
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.4007036965
Short name T1218
Test name
Test status
Simulation time 69206396 ps
CPU time 1.42 seconds
Started Jul 28 07:35:03 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 200868 kb
Host smart-78dd7031-803a-4fa4-8da3-aa4f0de84477
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007036965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.4007036965
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.313300623
Short name T1228
Test name
Test status
Simulation time 318832712 ps
CPU time 1.25 seconds
Started Jul 28 07:35:03 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 200296 kb
Host smart-1f357350-ac6a-4080-8691-7fa790a2d7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313300623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.313300623
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.4091808479
Short name T1313
Test name
Test status
Simulation time 12791198 ps
CPU time 0.58 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:25 PM PDT 24
Peak memory 195244 kb
Host smart-4486cf0a-97b3-4c1a-973f-244fa5b3f169
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091808479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.4091808479
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.75484548
Short name T1291
Test name
Test status
Simulation time 62117807 ps
CPU time 0.6 seconds
Started Jul 28 07:35:25 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195264 kb
Host smart-e827ffc0-d0c2-4419-b5b0-494cc20c92a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75484548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.75484548
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3317002720
Short name T1273
Test name
Test status
Simulation time 46426822 ps
CPU time 0.57 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:27 PM PDT 24
Peak memory 195260 kb
Host smart-7b469b68-cfa3-41fd-b4bf-fe46f4584c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317002720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3317002720
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.820571386
Short name T1188
Test name
Test status
Simulation time 29312417 ps
CPU time 0.6 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 195280 kb
Host smart-b446b757-5b75-480e-970f-230304558ecc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820571386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.820571386
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3079747969
Short name T1317
Test name
Test status
Simulation time 26397809 ps
CPU time 0.6 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:27 PM PDT 24
Peak memory 195268 kb
Host smart-a22d7437-18eb-4e71-b56a-a88258bc1081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079747969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3079747969
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.683133268
Short name T1215
Test name
Test status
Simulation time 21680936 ps
CPU time 0.59 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195288 kb
Host smart-43902700-396b-40ff-a681-54a6256854f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683133268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.683133268
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.826259794
Short name T1224
Test name
Test status
Simulation time 41982311 ps
CPU time 0.62 seconds
Started Jul 28 07:35:23 PM PDT 24
Finished Jul 28 07:35:24 PM PDT 24
Peak memory 195324 kb
Host smart-7346ef45-0f35-4100-970a-1a01556c628d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826259794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.826259794
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2785882257
Short name T1316
Test name
Test status
Simulation time 37812001 ps
CPU time 0.55 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:27 PM PDT 24
Peak memory 195172 kb
Host smart-ae434937-0b8d-47f1-8638-f6c51360c458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785882257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2785882257
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.1831590816
Short name T1250
Test name
Test status
Simulation time 14268481 ps
CPU time 0.61 seconds
Started Jul 28 07:35:26 PM PDT 24
Finished Jul 28 07:35:26 PM PDT 24
Peak memory 195200 kb
Host smart-929cf963-5e30-49db-8b47-02f95847557b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831590816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.1831590816
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2153628328
Short name T1209
Test name
Test status
Simulation time 14335468 ps
CPU time 0.59 seconds
Started Jul 28 07:35:24 PM PDT 24
Finished Jul 28 07:35:25 PM PDT 24
Peak memory 195284 kb
Host smart-c6e3468a-e197-4e7a-8ecd-14038524adaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153628328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2153628328
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.2098198224
Short name T1242
Test name
Test status
Simulation time 40065270 ps
CPU time 0.73 seconds
Started Jul 28 07:35:10 PM PDT 24
Finished Jul 28 07:35:11 PM PDT 24
Peak memory 198904 kb
Host smart-43c6ce6e-2b80-4890-804e-33fd53584f49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098198224 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.2098198224
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.586129381
Short name T1249
Test name
Test status
Simulation time 30892917 ps
CPU time 0.59 seconds
Started Jul 28 07:35:03 PM PDT 24
Finished Jul 28 07:35:03 PM PDT 24
Peak memory 196308 kb
Host smart-89a7c3a4-1cfa-4a93-b361-1c7baab4cb53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586129381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.586129381
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.266212545
Short name T1219
Test name
Test status
Simulation time 33525476 ps
CPU time 0.55 seconds
Started Jul 28 07:35:01 PM PDT 24
Finished Jul 28 07:35:01 PM PDT 24
Peak memory 195244 kb
Host smart-85e4c8b6-4270-41df-aec2-d3486f72a087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266212545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.266212545
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3159574028
Short name T1268
Test name
Test status
Simulation time 44938149 ps
CPU time 0.75 seconds
Started Jul 28 07:35:09 PM PDT 24
Finished Jul 28 07:35:09 PM PDT 24
Peak memory 197820 kb
Host smart-dcea6122-1341-49c1-96dd-11d946e77369
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159574028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3159574028
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3018391000
Short name T1211
Test name
Test status
Simulation time 388160863 ps
CPU time 1.81 seconds
Started Jul 28 07:35:02 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 200960 kb
Host smart-2c562554-055d-44d2-95ad-9629b870e5c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018391000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3018391000
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1197242394
Short name T135
Test name
Test status
Simulation time 53297860 ps
CPU time 0.99 seconds
Started Jul 28 07:35:03 PM PDT 24
Finished Jul 28 07:35:05 PM PDT 24
Peak memory 199892 kb
Host smart-75f3fd3a-4a38-4251-b0ec-6abdabddf639
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197242394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1197242394
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.710684173
Short name T1307
Test name
Test status
Simulation time 85540095 ps
CPU time 1.1 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 200964 kb
Host smart-4f576d3e-2b31-4c0e-ac4e-d581c032afc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710684173 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.710684173
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1111980507
Short name T1232
Test name
Test status
Simulation time 14251862 ps
CPU time 0.57 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 196372 kb
Host smart-9ba76f8b-20e7-4a72-8fa6-a63f20c4aa70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111980507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1111980507
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.4147972195
Short name T1241
Test name
Test status
Simulation time 115904637 ps
CPU time 0.54 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 195260 kb
Host smart-4525e9b7-f881-4283-89c6-4d642f3ae3f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147972195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.4147972195
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.613256209
Short name T88
Test name
Test status
Simulation time 63400611 ps
CPU time 0.78 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 197940 kb
Host smart-c1df068c-75f4-4aab-a358-c2c21f14d8f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613256209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_
outstanding.613256209
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1632602880
Short name T1222
Test name
Test status
Simulation time 49629253 ps
CPU time 1.13 seconds
Started Jul 28 07:35:08 PM PDT 24
Finished Jul 28 07:35:10 PM PDT 24
Peak memory 200984 kb
Host smart-9e45171a-583f-49d8-a44a-f7fab3cd9b76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632602880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1632602880
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.254354235
Short name T1260
Test name
Test status
Simulation time 817134580 ps
CPU time 0.88 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 199764 kb
Host smart-baefb0af-5a9a-4c84-b710-dc3f415c4b7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254354235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.254354235
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.1088221928
Short name T1282
Test name
Test status
Simulation time 23351867 ps
CPU time 0.7 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 199320 kb
Host smart-e29ac365-0d55-4b24-9605-20bde87d1a7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088221928 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.1088221928
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.236614473
Short name T74
Test name
Test status
Simulation time 40928833 ps
CPU time 0.58 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 196300 kb
Host smart-bcc394a1-c000-48a7-9107-46384d58e253
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236614473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.236614473
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.290502439
Short name T1202
Test name
Test status
Simulation time 11085094 ps
CPU time 0.59 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 195320 kb
Host smart-ffe11d9a-43f6-451a-be8b-cac0ad98ced2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290502439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.290502439
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2149642629
Short name T87
Test name
Test status
Simulation time 32445714 ps
CPU time 0.77 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 196728 kb
Host smart-654f54a9-0353-4ad6-9186-3869193fe6c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149642629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2149642629
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.656496877
Short name T1199
Test name
Test status
Simulation time 354017724 ps
CPU time 1.94 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 200896 kb
Host smart-7f859328-063a-4671-8dab-9a16f3b95124
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656496877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.656496877
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1347499409
Short name T105
Test name
Test status
Simulation time 95591283 ps
CPU time 1.46 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 200332 kb
Host smart-6eda9406-22f9-41d5-9d00-87a846617444
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347499409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1347499409
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3793947133
Short name T1187
Test name
Test status
Simulation time 35551486 ps
CPU time 0.84 seconds
Started Jul 28 07:35:10 PM PDT 24
Finished Jul 28 07:35:11 PM PDT 24
Peak memory 200756 kb
Host smart-08f02fc3-eddc-4358-9a30-b3a9cb1b003b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793947133 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3793947133
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.3990096454
Short name T70
Test name
Test status
Simulation time 17592050 ps
CPU time 0.6 seconds
Started Jul 28 07:35:08 PM PDT 24
Finished Jul 28 07:35:09 PM PDT 24
Peak memory 196336 kb
Host smart-a50d12a0-89cb-4c98-a3c1-d388f5182626
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990096454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.3990096454
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2689949846
Short name T1286
Test name
Test status
Simulation time 12110986 ps
CPU time 0.59 seconds
Started Jul 28 07:35:11 PM PDT 24
Finished Jul 28 07:35:12 PM PDT 24
Peak memory 195204 kb
Host smart-82fc55b8-417d-4168-856c-d8439d31b9f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689949846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2689949846
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2048952402
Short name T1295
Test name
Test status
Simulation time 39246534 ps
CPU time 0.69 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:07 PM PDT 24
Peak memory 196608 kb
Host smart-03e4cd77-2f5d-46c3-a9cc-68ce317b8a5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048952402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2048952402
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2990656215
Short name T1229
Test name
Test status
Simulation time 159622615 ps
CPU time 2.51 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:10 PM PDT 24
Peak memory 200948 kb
Host smart-8cdb791a-e709-4ca4-9fbd-51ac342cbeaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990656215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2990656215
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1173582005
Short name T103
Test name
Test status
Simulation time 70961765 ps
CPU time 1.31 seconds
Started Jul 28 07:35:08 PM PDT 24
Finished Jul 28 07:35:09 PM PDT 24
Peak memory 200196 kb
Host smart-18b2c20b-d557-4c55-8113-37747d818500
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173582005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1173582005
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.641870822
Short name T1299
Test name
Test status
Simulation time 26391110 ps
CPU time 0.8 seconds
Started Jul 28 07:35:05 PM PDT 24
Finished Jul 28 07:35:06 PM PDT 24
Peak memory 200696 kb
Host smart-52d9b79c-2955-4efd-b8f8-c3a19ae10950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641870822 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.641870822
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.3188179077
Short name T1270
Test name
Test status
Simulation time 13404223 ps
CPU time 0.59 seconds
Started Jul 28 07:35:09 PM PDT 24
Finished Jul 28 07:35:10 PM PDT 24
Peak memory 196252 kb
Host smart-56ea6324-2d7b-4965-889c-4e8b631cc09c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188179077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3188179077
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3973403562
Short name T1221
Test name
Test status
Simulation time 24132755 ps
CPU time 0.56 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 195300 kb
Host smart-5d6ddf9a-9858-48f3-a6a4-afd451fbe3bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973403562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3973403562
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3856205693
Short name T96
Test name
Test status
Simulation time 34831706 ps
CPU time 0.76 seconds
Started Jul 28 07:35:03 PM PDT 24
Finished Jul 28 07:35:04 PM PDT 24
Peak memory 199004 kb
Host smart-f9ba8767-fd53-4af3-bb9f-3b377184c092
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856205693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3856205693
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1561838504
Short name T1189
Test name
Test status
Simulation time 36355064 ps
CPU time 1.88 seconds
Started Jul 28 07:35:06 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 200884 kb
Host smart-01ffffda-8213-42ca-a9a8-265e4948dc9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561838504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1561838504
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1383574408
Short name T1279
Test name
Test status
Simulation time 71060871 ps
CPU time 1.32 seconds
Started Jul 28 07:35:07 PM PDT 24
Finished Jul 28 07:35:08 PM PDT 24
Peak memory 200244 kb
Host smart-f909f257-fb0e-4495-922e-5fcff6239598
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383574408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1383574408
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.3365037858
Short name T1005
Test name
Test status
Simulation time 14107237 ps
CPU time 0.58 seconds
Started Jul 28 07:04:17 PM PDT 24
Finished Jul 28 07:04:18 PM PDT 24
Peak memory 194532 kb
Host smart-3dc55cde-5b20-4136-82cd-5be7103f1d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365037858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.3365037858
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1223739614
Short name T408
Test name
Test status
Simulation time 52797798373 ps
CPU time 40.16 seconds
Started Jul 28 07:04:09 PM PDT 24
Finished Jul 28 07:04:49 PM PDT 24
Peak memory 200164 kb
Host smart-cb11075d-78bd-4848-8cb1-6d0d2d8e8e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223739614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1223739614
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.546167108
Short name T174
Test name
Test status
Simulation time 14096031405 ps
CPU time 11.97 seconds
Started Jul 28 07:04:10 PM PDT 24
Finished Jul 28 07:04:22 PM PDT 24
Peak memory 200132 kb
Host smart-0e168d31-6620-4668-ab1e-f8aba58e6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546167108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.546167108
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.581326093
Short name T471
Test name
Test status
Simulation time 64394653313 ps
CPU time 64.69 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:05:17 PM PDT 24
Peak memory 200140 kb
Host smart-433aa8c0-94c9-478e-99dd-180b653e8a1c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581326093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.581326093
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.474863048
Short name T894
Test name
Test status
Simulation time 71543884121 ps
CPU time 402.33 seconds
Started Jul 28 07:04:14 PM PDT 24
Finished Jul 28 07:10:57 PM PDT 24
Peak memory 200184 kb
Host smart-168b8e93-69a7-4489-9efb-74974cd31af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=474863048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.474863048
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2672506716
Short name T446
Test name
Test status
Simulation time 6302320433 ps
CPU time 11.73 seconds
Started Jul 28 07:04:15 PM PDT 24
Finished Jul 28 07:04:27 PM PDT 24
Peak memory 199152 kb
Host smart-d72b03d8-a251-4715-bb76-417e576e76ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672506716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2672506716
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1166378593
Short name T613
Test name
Test status
Simulation time 172840314363 ps
CPU time 52.2 seconds
Started Jul 28 07:04:15 PM PDT 24
Finished Jul 28 07:05:07 PM PDT 24
Peak memory 200316 kb
Host smart-5bf61558-2864-40a1-ae2b-401e4557b806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166378593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1166378593
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.3345293187
Short name T796
Test name
Test status
Simulation time 7717164430 ps
CPU time 406.09 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:10:59 PM PDT 24
Peak memory 200152 kb
Host smart-5e00eaae-f07d-4e9f-b65b-08b55e1dc33c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345293187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.3345293187
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2133255170
Short name T594
Test name
Test status
Simulation time 1899738089 ps
CPU time 4.92 seconds
Started Jul 28 07:04:15 PM PDT 24
Finished Jul 28 07:04:20 PM PDT 24
Peak memory 198176 kb
Host smart-e8f75485-65d3-4d2c-86c9-e9c40f7c0d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2133255170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2133255170
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2868994024
Short name T315
Test name
Test status
Simulation time 119025612210 ps
CPU time 84.01 seconds
Started Jul 28 07:04:14 PM PDT 24
Finished Jul 28 07:05:38 PM PDT 24
Peak memory 199996 kb
Host smart-d25a7432-0e7f-4bc3-a591-2e25b68fcfb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868994024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2868994024
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1313230236
Short name T344
Test name
Test status
Simulation time 3746978250 ps
CPU time 6.38 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:04:19 PM PDT 24
Peak memory 196688 kb
Host smart-fd22f35c-ba8d-4ec8-9de1-2c80a9e03a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313230236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1313230236
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.232156018
Short name T771
Test name
Test status
Simulation time 306006345 ps
CPU time 1.01 seconds
Started Jul 28 07:04:07 PM PDT 24
Finished Jul 28 07:04:08 PM PDT 24
Peak memory 198676 kb
Host smart-3e435d31-1098-4289-8384-cecb01900dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232156018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.232156018
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.894729300
Short name T17
Test name
Test status
Simulation time 444604122 ps
CPU time 1.41 seconds
Started Jul 28 07:04:13 PM PDT 24
Finished Jul 28 07:04:15 PM PDT 24
Peak memory 198060 kb
Host smart-9d1867c6-0449-4b71-b3ac-c5351ddfbe15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894729300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.894729300
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3910832137
Short name T557
Test name
Test status
Simulation time 15346297301 ps
CPU time 13.43 seconds
Started Jul 28 07:04:07 PM PDT 24
Finished Jul 28 07:04:20 PM PDT 24
Peak memory 200200 kb
Host smart-a402abcf-6b64-4ecb-bbae-d60f26435eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910832137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3910832137
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1039787264
Short name T556
Test name
Test status
Simulation time 47284065695 ps
CPU time 72.28 seconds
Started Jul 28 07:04:19 PM PDT 24
Finished Jul 28 07:05:31 PM PDT 24
Peak memory 200184 kb
Host smart-f54da2d7-2886-4ad9-97d4-d3eeba0a3d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039787264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1039787264
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1694951505
Short name T783
Test name
Test status
Simulation time 47494030637 ps
CPU time 32.77 seconds
Started Jul 28 07:04:18 PM PDT 24
Finished Jul 28 07:04:51 PM PDT 24
Peak memory 200140 kb
Host smart-ef374e54-68da-461b-9488-1925b0cc931c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694951505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1694951505
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3081907926
Short name T358
Test name
Test status
Simulation time 85364155144 ps
CPU time 130.31 seconds
Started Jul 28 07:04:18 PM PDT 24
Finished Jul 28 07:06:29 PM PDT 24
Peak memory 200172 kb
Host smart-2ceca979-7a5d-404f-a7ac-304bd466a203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081907926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3081907926
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1501914346
Short name T607
Test name
Test status
Simulation time 12748205281 ps
CPU time 20.5 seconds
Started Jul 28 07:04:20 PM PDT 24
Finished Jul 28 07:04:40 PM PDT 24
Peak memory 196272 kb
Host smart-39e2d658-1546-464f-b48b-d1fd613a9498
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501914346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1501914346
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2092964093
Short name T838
Test name
Test status
Simulation time 252820929416 ps
CPU time 183.3 seconds
Started Jul 28 07:04:29 PM PDT 24
Finished Jul 28 07:07:32 PM PDT 24
Peak memory 200180 kb
Host smart-36b7db20-94db-495d-a0d4-752712852c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092964093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2092964093
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2351785263
Short name T466
Test name
Test status
Simulation time 3901148536 ps
CPU time 7.25 seconds
Started Jul 28 07:04:25 PM PDT 24
Finished Jul 28 07:04:32 PM PDT 24
Peak memory 199060 kb
Host smart-3644ea67-fef4-43ff-bf6f-0afd4598e769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351785263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2351785263
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.4236156211
Short name T1109
Test name
Test status
Simulation time 8080859130 ps
CPU time 11.67 seconds
Started Jul 28 07:04:26 PM PDT 24
Finished Jul 28 07:04:38 PM PDT 24
Peak memory 198048 kb
Host smart-32597207-9afe-4218-8438-ba85c03335bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236156211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.4236156211
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.931792137
Short name T754
Test name
Test status
Simulation time 30116971307 ps
CPU time 349.49 seconds
Started Jul 28 07:04:27 PM PDT 24
Finished Jul 28 07:10:16 PM PDT 24
Peak memory 200184 kb
Host smart-2501db4b-d47a-44e9-a6ca-36d7daf5081f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931792137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.931792137
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.745591954
Short name T524
Test name
Test status
Simulation time 4127782511 ps
CPU time 15.36 seconds
Started Jul 28 07:04:19 PM PDT 24
Finished Jul 28 07:04:34 PM PDT 24
Peak memory 199120 kb
Host smart-7ba71ee8-583a-4543-9011-a4f4252071bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745591954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.745591954
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.101596426
Short name T954
Test name
Test status
Simulation time 3277486597 ps
CPU time 5.45 seconds
Started Jul 28 07:04:28 PM PDT 24
Finished Jul 28 07:04:34 PM PDT 24
Peak memory 196484 kb
Host smart-0dbfb4c9-582b-43d1-a07f-60450b6d1f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101596426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.101596426
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3251242931
Short name T33
Test name
Test status
Simulation time 269631272 ps
CPU time 0.79 seconds
Started Jul 28 07:04:29 PM PDT 24
Finished Jul 28 07:04:30 PM PDT 24
Peak memory 218320 kb
Host smart-01af5db1-5bd5-4ce0-8c56-146156d88ed6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251242931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3251242931
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.110845789
Short name T1113
Test name
Test status
Simulation time 6202491145 ps
CPU time 16.97 seconds
Started Jul 28 07:04:20 PM PDT 24
Finished Jul 28 07:04:37 PM PDT 24
Peak memory 200168 kb
Host smart-b87836f5-41d9-43b9-86c2-33e40cff4be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110845789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.110845789
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.2328881461
Short name T1167
Test name
Test status
Simulation time 268436866887 ps
CPU time 1482.61 seconds
Started Jul 28 07:04:30 PM PDT 24
Finished Jul 28 07:29:13 PM PDT 24
Peak memory 200088 kb
Host smart-bd425614-8a86-438b-aac2-1640efc51df4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328881461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.2328881461
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.109132381
Short name T873
Test name
Test status
Simulation time 862242985868 ps
CPU time 1708.63 seconds
Started Jul 28 07:04:26 PM PDT 24
Finished Jul 28 07:32:55 PM PDT 24
Peak memory 231176 kb
Host smart-4670c4ed-59a2-4508-bed4-3a11fe3e0cfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109132381 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.109132381
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3921390941
Short name T277
Test name
Test status
Simulation time 1106807732 ps
CPU time 2.66 seconds
Started Jul 28 07:04:26 PM PDT 24
Finished Jul 28 07:04:28 PM PDT 24
Peak memory 198432 kb
Host smart-b1edc894-e12e-49a6-8691-fa110f8d3492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921390941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3921390941
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.2650769822
Short name T486
Test name
Test status
Simulation time 54310144458 ps
CPU time 91.11 seconds
Started Jul 28 07:04:19 PM PDT 24
Finished Jul 28 07:05:51 PM PDT 24
Peak memory 200148 kb
Host smart-8d21cce5-83f6-4537-8995-b7f8f10f7d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650769822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.2650769822
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.455875459
Short name T455
Test name
Test status
Simulation time 33349719 ps
CPU time 0.56 seconds
Started Jul 28 07:05:29 PM PDT 24
Finished Jul 28 07:05:30 PM PDT 24
Peak memory 195824 kb
Host smart-5b7dcdb3-0f54-4f12-ba2e-b7a228f5c875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455875459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.455875459
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1893601716
Short name T619
Test name
Test status
Simulation time 151074126108 ps
CPU time 304.6 seconds
Started Jul 28 07:05:22 PM PDT 24
Finished Jul 28 07:10:27 PM PDT 24
Peak memory 200156 kb
Host smart-8a50d3bc-b630-4b9d-ad6d-3c4e1635e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893601716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1893601716
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.1469000853
Short name T867
Test name
Test status
Simulation time 31555124021 ps
CPU time 14.64 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:38 PM PDT 24
Peak memory 200076 kb
Host smart-81f3e888-ecc9-498d-acd4-6b101e0fbebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469000853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.1469000853
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.2950164478
Short name T836
Test name
Test status
Simulation time 111931465442 ps
CPU time 160.61 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:08:06 PM PDT 24
Peak memory 200072 kb
Host smart-85cacda4-9dec-4fe3-91ab-e41a62fdd37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950164478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.2950164478
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3300963354
Short name T127
Test name
Test status
Simulation time 10485886663 ps
CPU time 26.77 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:05:52 PM PDT 24
Peak memory 200068 kb
Host smart-1de15041-7336-44ba-a40c-a3d5fbf577e4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300963354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3300963354
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1647770517
Short name T642
Test name
Test status
Simulation time 67356898198 ps
CPU time 55.87 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:06:21 PM PDT 24
Peak memory 200112 kb
Host smart-88ee9bc5-6746-4231-9c2c-e05f92d79b9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1647770517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1647770517
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.411447953
Short name T399
Test name
Test status
Simulation time 2584381204 ps
CPU time 5.35 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:28 PM PDT 24
Peak memory 198396 kb
Host smart-5cf5e4b7-7fb7-4e4e-948a-b5f4e173c1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411447953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.411447953
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.426340735
Short name T824
Test name
Test status
Simulation time 37623622264 ps
CPU time 7.49 seconds
Started Jul 28 07:05:24 PM PDT 24
Finished Jul 28 07:05:31 PM PDT 24
Peak memory 200004 kb
Host smart-728dbb84-f63d-4db9-b43e-bd8ed4ab7895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426340735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.426340735
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.3269183617
Short name T25
Test name
Test status
Simulation time 18032883756 ps
CPU time 989.98 seconds
Started Jul 28 07:05:28 PM PDT 24
Finished Jul 28 07:21:58 PM PDT 24
Peak memory 200092 kb
Host smart-5c505284-7d83-4c6a-9013-f5377ae8dd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3269183617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.3269183617
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1350640816
Short name T333
Test name
Test status
Simulation time 6517100653 ps
CPU time 29.33 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:53 PM PDT 24
Peak memory 199308 kb
Host smart-93e43b4a-e753-46f1-86a7-a705472093c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350640816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1350640816
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.612269453
Short name T467
Test name
Test status
Simulation time 82087980923 ps
CPU time 221.5 seconds
Started Jul 28 07:05:24 PM PDT 24
Finished Jul 28 07:09:06 PM PDT 24
Peak memory 200084 kb
Host smart-f302135e-22c0-4017-abf3-5e4a1cee25ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612269453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.612269453
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3009086495
Short name T888
Test name
Test status
Simulation time 1405802943 ps
CPU time 2.77 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:26 PM PDT 24
Peak memory 195860 kb
Host smart-c6abfd85-1ae8-402d-9a6e-4e6c9c205898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009086495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3009086495
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2398330130
Short name T9
Test name
Test status
Simulation time 526282760 ps
CPU time 1.29 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:24 PM PDT 24
Peak memory 198720 kb
Host smart-2f051ff7-78ce-4a69-afee-33a28f11abe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398330130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2398330130
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2412755255
Short name T1160
Test name
Test status
Simulation time 158955294472 ps
CPU time 332.19 seconds
Started Jul 28 07:05:28 PM PDT 24
Finished Jul 28 07:11:01 PM PDT 24
Peak memory 216600 kb
Host smart-955af150-477b-4b49-bb28-7aa91bc3317f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412755255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2412755255
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3022771252
Short name T468
Test name
Test status
Simulation time 35659308404 ps
CPU time 230.31 seconds
Started Jul 28 07:05:28 PM PDT 24
Finished Jul 28 07:09:18 PM PDT 24
Peak memory 213964 kb
Host smart-65fafbd5-3df9-46fa-9c2c-98d56a7c423c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022771252 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3022771252
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.362972928
Short name T270
Test name
Test status
Simulation time 448253691 ps
CPU time 1.35 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:05:24 PM PDT 24
Peak memory 198056 kb
Host smart-18efdc21-8a77-43d9-9767-c2025d3e6a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362972928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.362972928
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2428433499
Short name T562
Test name
Test status
Simulation time 30107179356 ps
CPU time 46.78 seconds
Started Jul 28 07:05:23 PM PDT 24
Finished Jul 28 07:06:10 PM PDT 24
Peak memory 200172 kb
Host smart-a3ca66ed-6f26-4447-bbeb-67ec1daa632c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428433499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2428433499
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.4063347940
Short name T1067
Test name
Test status
Simulation time 128684429210 ps
CPU time 103.85 seconds
Started Jul 28 07:11:47 PM PDT 24
Finished Jul 28 07:13:31 PM PDT 24
Peak memory 200200 kb
Host smart-208b5393-16bb-430f-bb22-f2a13578e5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063347940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.4063347940
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.2999481511
Short name T722
Test name
Test status
Simulation time 69253513710 ps
CPU time 26.71 seconds
Started Jul 28 07:11:53 PM PDT 24
Finished Jul 28 07:12:20 PM PDT 24
Peak memory 200180 kb
Host smart-5b24aeee-fcee-4ce3-bc58-60e498ee036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999481511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.2999481511
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.451999267
Short name T1154
Test name
Test status
Simulation time 176177643980 ps
CPU time 64.57 seconds
Started Jul 28 07:11:54 PM PDT 24
Finished Jul 28 07:12:59 PM PDT 24
Peak memory 200100 kb
Host smart-a382510d-bd7d-48c7-b560-9dbc7d795c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451999267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.451999267
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3040576138
Short name T1101
Test name
Test status
Simulation time 11174284477 ps
CPU time 10.91 seconds
Started Jul 28 07:11:52 PM PDT 24
Finished Jul 28 07:12:04 PM PDT 24
Peak memory 199776 kb
Host smart-72af942c-fd5b-4fc3-a7ce-8e11042ae5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040576138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3040576138
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.561347884
Short name T154
Test name
Test status
Simulation time 34612596517 ps
CPU time 37.52 seconds
Started Jul 28 07:11:52 PM PDT 24
Finished Jul 28 07:12:30 PM PDT 24
Peak memory 200084 kb
Host smart-8b34a93e-3af0-42fe-ab76-ecd2822c89e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561347884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.561347884
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3287750967
Short name T395
Test name
Test status
Simulation time 109300744757 ps
CPU time 26.9 seconds
Started Jul 28 07:11:53 PM PDT 24
Finished Jul 28 07:12:20 PM PDT 24
Peak memory 200108 kb
Host smart-d0de94d7-d275-4cfe-8fcd-6e28c8ce1089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287750967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3287750967
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2962548589
Short name T523
Test name
Test status
Simulation time 114011678533 ps
CPU time 179.64 seconds
Started Jul 28 07:11:54 PM PDT 24
Finished Jul 28 07:14:54 PM PDT 24
Peak memory 200196 kb
Host smart-1aa47066-9c27-49ba-84f4-da8da7695656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962548589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2962548589
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1443451342
Short name T209
Test name
Test status
Simulation time 55833689998 ps
CPU time 14.6 seconds
Started Jul 28 07:11:53 PM PDT 24
Finished Jul 28 07:12:07 PM PDT 24
Peak memory 200092 kb
Host smart-9a992db1-ab63-450a-939d-0ed1bcad1e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443451342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1443451342
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4025664873
Short name T1015
Test name
Test status
Simulation time 14523456 ps
CPU time 0.53 seconds
Started Jul 28 07:05:41 PM PDT 24
Finished Jul 28 07:05:42 PM PDT 24
Peak memory 195600 kb
Host smart-43d6d0e5-094f-4132-aa27-2e22c1270dd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025664873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4025664873
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2972351004
Short name T1182
Test name
Test status
Simulation time 251085836806 ps
CPU time 790.35 seconds
Started Jul 28 07:05:27 PM PDT 24
Finished Jul 28 07:18:38 PM PDT 24
Peak memory 200184 kb
Host smart-aea05d1c-ffd1-4369-ac65-4cfbc536cf49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972351004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2972351004
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_intr.1172741511
Short name T1145
Test name
Test status
Simulation time 14036637273 ps
CPU time 12.22 seconds
Started Jul 28 07:05:36 PM PDT 24
Finished Jul 28 07:05:48 PM PDT 24
Peak memory 199848 kb
Host smart-276693dc-b094-4885-942e-66ee86516e72
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172741511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1172741511
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2910361649
Short name T837
Test name
Test status
Simulation time 289856164024 ps
CPU time 332.7 seconds
Started Jul 28 07:05:47 PM PDT 24
Finished Jul 28 07:11:20 PM PDT 24
Peak memory 200036 kb
Host smart-9da2e0b8-336a-4da7-bf7a-78e36d370788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2910361649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2910361649
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.1238563104
Short name T1066
Test name
Test status
Simulation time 1658692627 ps
CPU time 3.49 seconds
Started Jul 28 07:05:35 PM PDT 24
Finished Jul 28 07:05:39 PM PDT 24
Peak memory 197604 kb
Host smart-c283d659-80dd-417b-a03e-a2ca11cef0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238563104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.1238563104
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3649262849
Short name T884
Test name
Test status
Simulation time 173365682076 ps
CPU time 34.4 seconds
Started Jul 28 07:05:35 PM PDT 24
Finished Jul 28 07:06:10 PM PDT 24
Peak memory 199556 kb
Host smart-2fe9c7ea-de4f-4eaf-ae68-80fcec05ed42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649262849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3649262849
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2667349855
Short name T772
Test name
Test status
Simulation time 3186321701 ps
CPU time 6.13 seconds
Started Jul 28 07:05:36 PM PDT 24
Finished Jul 28 07:05:43 PM PDT 24
Peak memory 198328 kb
Host smart-8b58e8df-696a-41dd-a42a-463488dd18eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667349855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2667349855
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.880860769
Short name T1037
Test name
Test status
Simulation time 212101744735 ps
CPU time 141.17 seconds
Started Jul 28 07:05:36 PM PDT 24
Finished Jul 28 07:07:57 PM PDT 24
Peak memory 200096 kb
Host smart-32738ec2-da3d-4d28-a7e7-fc7644d24fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880860769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.880860769
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.839232790
Short name T398
Test name
Test status
Simulation time 37184837558 ps
CPU time 5.55 seconds
Started Jul 28 07:05:36 PM PDT 24
Finished Jul 28 07:05:42 PM PDT 24
Peak memory 196680 kb
Host smart-f59c8b1b-9b7f-4805-816a-bf893ba460e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839232790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.839232790
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3117340676
Short name T564
Test name
Test status
Simulation time 520264723 ps
CPU time 1.24 seconds
Started Jul 28 07:05:30 PM PDT 24
Finished Jul 28 07:05:31 PM PDT 24
Peak memory 198712 kb
Host smart-7754b9ca-18f9-4849-bc49-338b5e46f3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117340676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3117340676
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1021602588
Short name T720
Test name
Test status
Simulation time 86084243176 ps
CPU time 79.04 seconds
Started Jul 28 07:05:42 PM PDT 24
Finished Jul 28 07:07:01 PM PDT 24
Peak memory 200180 kb
Host smart-d6d52d66-7629-4c4b-a571-fc29dae63a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021602588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1021602588
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2779773056
Short name T1054
Test name
Test status
Simulation time 55099792743 ps
CPU time 1361.93 seconds
Started Jul 28 07:05:40 PM PDT 24
Finished Jul 28 07:28:22 PM PDT 24
Peak memory 216708 kb
Host smart-0787ca08-3cfe-446c-9933-26aa1f5c4ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779773056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2779773056
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.716678435
Short name T407
Test name
Test status
Simulation time 1815842059 ps
CPU time 2.03 seconds
Started Jul 28 07:05:36 PM PDT 24
Finished Jul 28 07:05:38 PM PDT 24
Peak memory 198604 kb
Host smart-d274d44e-5c51-4b64-aa39-fe8977e634ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716678435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.716678435
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.4041529238
Short name T394
Test name
Test status
Simulation time 164706579481 ps
CPU time 29.74 seconds
Started Jul 28 07:05:28 PM PDT 24
Finished Jul 28 07:05:58 PM PDT 24
Peak memory 200232 kb
Host smart-6d016f86-dcbf-4eb0-b9ac-35e0d7651c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041529238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.4041529238
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.1707763972
Short name T1053
Test name
Test status
Simulation time 8308051092 ps
CPU time 12.94 seconds
Started Jul 28 07:11:54 PM PDT 24
Finished Jul 28 07:12:07 PM PDT 24
Peak memory 198628 kb
Host smart-5a0c540d-fc1e-4251-b593-141fd6645011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707763972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1707763972
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2716160476
Short name T1023
Test name
Test status
Simulation time 330674450397 ps
CPU time 610.55 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:22:09 PM PDT 24
Peak memory 200076 kb
Host smart-3ffbba3a-c75d-42ce-b493-7710245e765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716160476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2716160476
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3539504269
Short name T116
Test name
Test status
Simulation time 65237449862 ps
CPU time 39.19 seconds
Started Jul 28 07:11:57 PM PDT 24
Finished Jul 28 07:12:36 PM PDT 24
Peak memory 200184 kb
Host smart-02a34983-cf19-4f0c-859c-0fcd8de60e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539504269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3539504269
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.318354234
Short name T1183
Test name
Test status
Simulation time 30305942150 ps
CPU time 36.14 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:12:34 PM PDT 24
Peak memory 200172 kb
Host smart-bcf2cb14-c08d-4221-a7b4-56505ecd0c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318354234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.318354234
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.1170153548
Short name T617
Test name
Test status
Simulation time 25105322695 ps
CPU time 27.06 seconds
Started Jul 28 07:11:57 PM PDT 24
Finished Jul 28 07:12:24 PM PDT 24
Peak memory 200012 kb
Host smart-129cae31-f283-4138-a44c-7e5fcb1e7300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170153548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.1170153548
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2037215370
Short name T554
Test name
Test status
Simulation time 9825880259 ps
CPU time 14.72 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:12:13 PM PDT 24
Peak memory 200196 kb
Host smart-1ec7e7a7-85ca-40d1-8ea8-410243a1cb34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037215370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2037215370
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.91932986
Short name T941
Test name
Test status
Simulation time 59217684715 ps
CPU time 89.18 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:13:27 PM PDT 24
Peak memory 200192 kb
Host smart-1961d658-244c-4d9e-a8e7-8b9a402faf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91932986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.91932986
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.388936396
Short name T1098
Test name
Test status
Simulation time 105882091783 ps
CPU time 41.37 seconds
Started Jul 28 07:11:55 PM PDT 24
Finished Jul 28 07:12:36 PM PDT 24
Peak memory 200148 kb
Host smart-11e24c3f-a19a-48ca-9214-12ff046c8b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388936396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.388936396
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4042843510
Short name T416
Test name
Test status
Simulation time 12612319435 ps
CPU time 11.3 seconds
Started Jul 28 07:12:00 PM PDT 24
Finished Jul 28 07:12:11 PM PDT 24
Peak memory 199824 kb
Host smart-6151a3af-1314-40b8-badf-4b8ea4a32841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042843510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4042843510
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.609150640
Short name T973
Test name
Test status
Simulation time 13036175 ps
CPU time 0.58 seconds
Started Jul 28 07:05:51 PM PDT 24
Finished Jul 28 07:05:51 PM PDT 24
Peak memory 195576 kb
Host smart-7cae96c2-ce38-4d29-afa6-77f3963e1087
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609150640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.609150640
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.844861538
Short name T696
Test name
Test status
Simulation time 176702628513 ps
CPU time 76.56 seconds
Started Jul 28 07:05:47 PM PDT 24
Finished Jul 28 07:07:04 PM PDT 24
Peak memory 200220 kb
Host smart-a93684a2-64e2-4877-a897-3cab8e028f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844861538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.844861538
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.990055469
Short name T856
Test name
Test status
Simulation time 75961844300 ps
CPU time 30.91 seconds
Started Jul 28 07:05:47 PM PDT 24
Finished Jul 28 07:06:18 PM PDT 24
Peak memory 200152 kb
Host smart-46478e3f-801c-40b4-aca2-1fc3f8dc2bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990055469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.990055469
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1842298291
Short name T576
Test name
Test status
Simulation time 22123423029 ps
CPU time 20.25 seconds
Started Jul 28 07:05:44 PM PDT 24
Finished Jul 28 07:06:05 PM PDT 24
Peak memory 200152 kb
Host smart-7f12acc2-5a74-4685-9bed-605fc34d1b26
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842298291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1842298291
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2885301073
Short name T823
Test name
Test status
Simulation time 72782413093 ps
CPU time 155.47 seconds
Started Jul 28 07:05:45 PM PDT 24
Finished Jul 28 07:08:20 PM PDT 24
Peak memory 200152 kb
Host smart-1c2223f2-9053-41ce-82c7-b7af1c1fb3a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2885301073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2885301073
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1638420947
Short name T871
Test name
Test status
Simulation time 4555371138 ps
CPU time 9.11 seconds
Started Jul 28 07:05:46 PM PDT 24
Finished Jul 28 07:05:55 PM PDT 24
Peak memory 198400 kb
Host smart-13c1869c-e058-4126-9164-fc04cb3093df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638420947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1638420947
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.548889486
Short name T700
Test name
Test status
Simulation time 87435148178 ps
CPU time 131.71 seconds
Started Jul 28 07:05:46 PM PDT 24
Finished Jul 28 07:07:57 PM PDT 24
Peak memory 200364 kb
Host smart-65085c67-b002-48f8-924e-cef057285eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548889486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.548889486
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1780539017
Short name T969
Test name
Test status
Simulation time 6235718342 ps
CPU time 242.68 seconds
Started Jul 28 07:05:47 PM PDT 24
Finished Jul 28 07:09:50 PM PDT 24
Peak memory 200176 kb
Host smart-d74f5b40-cf9d-4b5f-a34e-d9c9f88262f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1780539017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1780539017
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.4050376214
Short name T621
Test name
Test status
Simulation time 6770176831 ps
CPU time 60.87 seconds
Started Jul 28 07:05:46 PM PDT 24
Finished Jul 28 07:06:47 PM PDT 24
Peak memory 199632 kb
Host smart-e97ef903-b74b-4d58-980c-315aa235c15f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4050376214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.4050376214
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1199481737
Short name T552
Test name
Test status
Simulation time 5027466109 ps
CPU time 7.44 seconds
Started Jul 28 07:05:45 PM PDT 24
Finished Jul 28 07:05:53 PM PDT 24
Peak memory 196696 kb
Host smart-e94a753b-a612-4a88-93c0-64bbdffc11b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199481737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1199481737
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1686305125
Short name T288
Test name
Test status
Simulation time 5683480838 ps
CPU time 13.09 seconds
Started Jul 28 07:05:40 PM PDT 24
Finished Jul 28 07:05:54 PM PDT 24
Peak memory 200120 kb
Host smart-bac99a15-3a9d-44a1-a735-d1c58935b291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686305125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1686305125
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.898196492
Short name T171
Test name
Test status
Simulation time 246089644339 ps
CPU time 283.23 seconds
Started Jul 28 07:05:55 PM PDT 24
Finished Jul 28 07:10:39 PM PDT 24
Peak memory 200184 kb
Host smart-90df82d3-dabd-4095-a21d-c8ea9752bf8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898196492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.898196492
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1008928762
Short name T712
Test name
Test status
Simulation time 93833213683 ps
CPU time 236.92 seconds
Started Jul 28 07:05:46 PM PDT 24
Finished Jul 28 07:09:43 PM PDT 24
Peak memory 216772 kb
Host smart-d933c0ca-b82c-469f-9f3a-a33b2680ea7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008928762 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1008928762
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4240166536
Short name T808
Test name
Test status
Simulation time 519402040 ps
CPU time 1.56 seconds
Started Jul 28 07:05:44 PM PDT 24
Finished Jul 28 07:05:46 PM PDT 24
Peak memory 197532 kb
Host smart-2f863e2f-55ef-43a1-b065-edf6e8d5d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240166536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4240166536
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3561049564
Short name T996
Test name
Test status
Simulation time 8939520411 ps
CPU time 12.72 seconds
Started Jul 28 07:05:47 PM PDT 24
Finished Jul 28 07:06:00 PM PDT 24
Peak memory 199984 kb
Host smart-9e2825cf-cbdf-429b-b74b-e31cf93a19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561049564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3561049564
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.827404913
Short name T849
Test name
Test status
Simulation time 102917346806 ps
CPU time 77.84 seconds
Started Jul 28 07:11:59 PM PDT 24
Finished Jul 28 07:13:17 PM PDT 24
Peak memory 200064 kb
Host smart-7cb55c8e-bcc4-402c-a5cd-a132929423c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827404913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.827404913
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.585379629
Short name T1040
Test name
Test status
Simulation time 8173072071 ps
CPU time 13.08 seconds
Started Jul 28 07:11:58 PM PDT 24
Finished Jul 28 07:12:11 PM PDT 24
Peak memory 200124 kb
Host smart-d9294d59-5c01-4ac8-9ece-09e4149177f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585379629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.585379629
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.3439884337
Short name T1184
Test name
Test status
Simulation time 131585429332 ps
CPU time 237.92 seconds
Started Jul 28 07:12:04 PM PDT 24
Finished Jul 28 07:16:02 PM PDT 24
Peak memory 199972 kb
Host smart-5f5927d3-0343-42c5-9f12-8b01b6108902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439884337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.3439884337
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1311818048
Short name T190
Test name
Test status
Simulation time 22081897717 ps
CPU time 26.72 seconds
Started Jul 28 07:12:08 PM PDT 24
Finished Jul 28 07:12:35 PM PDT 24
Peak memory 200208 kb
Host smart-d71db996-32bd-4c78-8c08-a69ad0f8db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311818048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1311818048
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1621991368
Short name T675
Test name
Test status
Simulation time 112591016807 ps
CPU time 120.2 seconds
Started Jul 28 07:12:05 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 200096 kb
Host smart-32b1a793-fa54-4946-9b33-571e72707a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621991368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1621991368
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1949534573
Short name T727
Test name
Test status
Simulation time 99062519116 ps
CPU time 147.97 seconds
Started Jul 28 07:12:04 PM PDT 24
Finished Jul 28 07:14:32 PM PDT 24
Peak memory 200012 kb
Host smart-3aa8945e-3eb3-42e8-9a40-ebf8dde8be85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949534573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1949534573
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.317941691
Short name T1128
Test name
Test status
Simulation time 147664876804 ps
CPU time 15.9 seconds
Started Jul 28 07:12:08 PM PDT 24
Finished Jul 28 07:12:24 PM PDT 24
Peak memory 200140 kb
Host smart-ff0c7617-f453-453f-a49f-a5e28a6b0f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317941691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.317941691
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2761289564
Short name T231
Test name
Test status
Simulation time 86900016993 ps
CPU time 144.12 seconds
Started Jul 28 07:12:04 PM PDT 24
Finished Jul 28 07:14:29 PM PDT 24
Peak memory 200128 kb
Host smart-53aabf8c-1d28-44fc-899e-50761ec28c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761289564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2761289564
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.615957457
Short name T1024
Test name
Test status
Simulation time 21413145 ps
CPU time 0.58 seconds
Started Jul 28 07:06:03 PM PDT 24
Finished Jul 28 07:06:03 PM PDT 24
Peak memory 195572 kb
Host smart-09a1b977-3b0c-4f38-abc4-466b370a1a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615957457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.615957457
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.135868275
Short name T781
Test name
Test status
Simulation time 17783160618 ps
CPU time 27.47 seconds
Started Jul 28 07:05:55 PM PDT 24
Finished Jul 28 07:06:22 PM PDT 24
Peak memory 200200 kb
Host smart-7d7c933f-455f-4765-abb2-333b7fda9276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135868275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.135868275
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2591685847
Short name T934
Test name
Test status
Simulation time 67488783582 ps
CPU time 92.37 seconds
Started Jul 28 07:05:56 PM PDT 24
Finished Jul 28 07:07:28 PM PDT 24
Peak memory 200116 kb
Host smart-12c79e59-c2b2-4cde-9bbf-611e20099fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591685847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2591685847
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1774673102
Short name T112
Test name
Test status
Simulation time 164547459877 ps
CPU time 16.63 seconds
Started Jul 28 07:05:53 PM PDT 24
Finished Jul 28 07:06:10 PM PDT 24
Peak memory 199624 kb
Host smart-f6177500-b627-43e9-ad23-da2260f8681b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774673102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1774673102
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.2802809944
Short name T780
Test name
Test status
Simulation time 28180860150 ps
CPU time 39.75 seconds
Started Jul 28 07:05:54 PM PDT 24
Finished Jul 28 07:06:34 PM PDT 24
Peak memory 197332 kb
Host smart-e999337a-8f65-4c30-883f-56c4ba26d55e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802809944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.2802809944
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.2669135871
Short name T255
Test name
Test status
Simulation time 185285535483 ps
CPU time 650.82 seconds
Started Jul 28 07:05:54 PM PDT 24
Finished Jul 28 07:16:45 PM PDT 24
Peak memory 200164 kb
Host smart-3822cbc3-1f46-47a9-b7b5-283c4d278d52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2669135871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.2669135871
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1927543698
Short name T1050
Test name
Test status
Simulation time 8594648718 ps
CPU time 15.05 seconds
Started Jul 28 07:05:54 PM PDT 24
Finished Jul 28 07:06:09 PM PDT 24
Peak memory 199024 kb
Host smart-03abd5f7-1e09-445a-af91-32f783181fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927543698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1927543698
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.2460664002
Short name T5
Test name
Test status
Simulation time 14490451208 ps
CPU time 29.11 seconds
Started Jul 28 07:05:58 PM PDT 24
Finished Jul 28 07:06:27 PM PDT 24
Peak memory 198940 kb
Host smart-a36c7a6a-efe2-4ed6-97a8-b1e31f6a682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460664002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2460664002
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3049233219
Short name T1031
Test name
Test status
Simulation time 7022982092 ps
CPU time 88.39 seconds
Started Jul 28 07:05:52 PM PDT 24
Finished Jul 28 07:07:20 PM PDT 24
Peak memory 200144 kb
Host smart-8f797fcd-84da-4d4d-b93b-8d0201bd3361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049233219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3049233219
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1362655079
Short name T625
Test name
Test status
Simulation time 4846975139 ps
CPU time 19.72 seconds
Started Jul 28 07:05:55 PM PDT 24
Finished Jul 28 07:06:14 PM PDT 24
Peak memory 199540 kb
Host smart-f30a155a-d699-4c8d-82c6-b1757a19f706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362655079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1362655079
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.801635940
Short name T886
Test name
Test status
Simulation time 219247144884 ps
CPU time 27.2 seconds
Started Jul 28 07:05:56 PM PDT 24
Finished Jul 28 07:06:23 PM PDT 24
Peak memory 200156 kb
Host smart-2ecf00e1-c830-4c94-aad8-0fa08f401438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801635940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.801635940
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.3958763385
Short name T773
Test name
Test status
Simulation time 3163339760 ps
CPU time 5.22 seconds
Started Jul 28 07:05:55 PM PDT 24
Finished Jul 28 07:06:01 PM PDT 24
Peak memory 196404 kb
Host smart-2585535e-61c7-42b8-82d0-0172486fb652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958763385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.3958763385
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.1542968715
Short name T297
Test name
Test status
Simulation time 6090057668 ps
CPU time 6.83 seconds
Started Jul 28 07:05:53 PM PDT 24
Finished Jul 28 07:06:00 PM PDT 24
Peak memory 199400 kb
Host smart-f8a9cb0c-d201-491f-8dcc-4258c1fb473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542968715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.1542968715
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3126520653
Short name T832
Test name
Test status
Simulation time 152193857175 ps
CPU time 589.37 seconds
Started Jul 28 07:06:01 PM PDT 24
Finished Jul 28 07:15:51 PM PDT 24
Peak memory 200172 kb
Host smart-4dec860f-7544-44d9-8c09-1a9afacf58fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126520653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3126520653
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2571043056
Short name T870
Test name
Test status
Simulation time 26851115259 ps
CPU time 270.9 seconds
Started Jul 28 07:06:07 PM PDT 24
Finished Jul 28 07:10:38 PM PDT 24
Peak memory 216732 kb
Host smart-2a8b0593-39d9-46a6-bec9-76a86bf766eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571043056 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2571043056
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.323751089
Short name T959
Test name
Test status
Simulation time 6836218781 ps
CPU time 27.55 seconds
Started Jul 28 07:05:55 PM PDT 24
Finished Jul 28 07:06:23 PM PDT 24
Peak memory 200080 kb
Host smart-61fea307-162a-4d8c-a47e-5125911862ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323751089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.323751089
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.3780485554
Short name T1148
Test name
Test status
Simulation time 41228496962 ps
CPU time 56.92 seconds
Started Jul 28 07:05:54 PM PDT 24
Finished Jul 28 07:06:51 PM PDT 24
Peak memory 200136 kb
Host smart-ca6667e1-9755-4b66-8143-e85270a8f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780485554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.3780485554
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1431656527
Short name T413
Test name
Test status
Simulation time 35527791887 ps
CPU time 15.86 seconds
Started Jul 28 07:12:08 PM PDT 24
Finished Jul 28 07:12:24 PM PDT 24
Peak memory 200216 kb
Host smart-d87d64bf-e0ba-47a4-869f-70610c9e4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431656527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1431656527
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1423778759
Short name T191
Test name
Test status
Simulation time 411742498626 ps
CPU time 44.65 seconds
Started Jul 28 07:12:11 PM PDT 24
Finished Jul 28 07:12:56 PM PDT 24
Peak memory 200156 kb
Host smart-e0dcb5df-e043-45cb-97df-04d7f5175d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423778759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1423778759
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.2626417377
Short name T779
Test name
Test status
Simulation time 53227887282 ps
CPU time 57.58 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:13:08 PM PDT 24
Peak memory 200184 kb
Host smart-a5ce77f0-a7f8-4ab5-83d0-5029c3661b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626417377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.2626417377
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3755193779
Short name T193
Test name
Test status
Simulation time 29859167403 ps
CPU time 19.37 seconds
Started Jul 28 07:12:08 PM PDT 24
Finished Jul 28 07:12:28 PM PDT 24
Peak memory 200108 kb
Host smart-e5689e1c-a493-4e0d-85b5-10434e8f89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755193779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3755193779
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1705747845
Short name T1121
Test name
Test status
Simulation time 26821484765 ps
CPU time 43.71 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:12:54 PM PDT 24
Peak memory 200192 kb
Host smart-73b9f767-a768-42d7-b3f6-5dad27e2cbf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705747845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1705747845
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.4277867878
Short name T499
Test name
Test status
Simulation time 57399974638 ps
CPU time 92.02 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 200140 kb
Host smart-b597f28b-9f60-4f06-b41d-8f22b389c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277867878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.4277867878
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4097667321
Short name T985
Test name
Test status
Simulation time 12004898861 ps
CPU time 13.11 seconds
Started Jul 28 07:12:09 PM PDT 24
Finished Jul 28 07:12:22 PM PDT 24
Peak memory 200116 kb
Host smart-383a1ded-b2b8-4003-981c-4d91f2bd8df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097667321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4097667321
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4003707200
Short name T800
Test name
Test status
Simulation time 358884807373 ps
CPU time 76.73 seconds
Started Jul 28 07:12:08 PM PDT 24
Finished Jul 28 07:13:25 PM PDT 24
Peak memory 200184 kb
Host smart-1ce9ba35-c868-4a03-9fc1-a027c0a9c4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003707200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4003707200
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1048794587
Short name T1123
Test name
Test status
Simulation time 94149725503 ps
CPU time 29.77 seconds
Started Jul 28 07:12:12 PM PDT 24
Finished Jul 28 07:12:41 PM PDT 24
Peak memory 200208 kb
Host smart-a824122b-ba10-4f54-8404-a76e1cbed056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048794587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1048794587
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.3954465304
Short name T218
Test name
Test status
Simulation time 22255252748 ps
CPU time 17.44 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:12:28 PM PDT 24
Peak memory 200068 kb
Host smart-16e49314-4f4e-4fcf-ac5d-0c05dc3156a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954465304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.3954465304
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.650527090
Short name T644
Test name
Test status
Simulation time 14015490 ps
CPU time 0.56 seconds
Started Jul 28 07:06:07 PM PDT 24
Finished Jul 28 07:06:07 PM PDT 24
Peak memory 195780 kb
Host smart-7dee2902-adca-40c0-a5ae-b9734db3d07b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650527090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.650527090
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.525140789
Short name T764
Test name
Test status
Simulation time 97787589266 ps
CPU time 74.93 seconds
Started Jul 28 07:06:02 PM PDT 24
Finished Jul 28 07:07:17 PM PDT 24
Peak memory 200064 kb
Host smart-28ce7d93-ba84-45ad-8769-f550c49a34a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525140789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.525140789
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.326308063
Short name T1071
Test name
Test status
Simulation time 39988138129 ps
CPU time 23.93 seconds
Started Jul 28 07:06:00 PM PDT 24
Finished Jul 28 07:06:24 PM PDT 24
Peak memory 200116 kb
Host smart-63714ea5-7480-40d4-8daf-baae0f006b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326308063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.326308063
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.2559867723
Short name T689
Test name
Test status
Simulation time 208401313266 ps
CPU time 61.96 seconds
Started Jul 28 07:06:02 PM PDT 24
Finished Jul 28 07:07:04 PM PDT 24
Peak memory 200184 kb
Host smart-7f3f5ad4-7c19-41b4-91ff-e44ce5646535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559867723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2559867723
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.4078782452
Short name T599
Test name
Test status
Simulation time 21787910183 ps
CPU time 32.12 seconds
Started Jul 28 07:05:59 PM PDT 24
Finished Jul 28 07:06:32 PM PDT 24
Peak memory 196156 kb
Host smart-88323e14-ef9c-4dfb-92c7-f0fb6b454c41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078782452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.4078782452
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.1461984148
Short name T663
Test name
Test status
Simulation time 27595782144 ps
CPU time 85.72 seconds
Started Jul 28 07:06:01 PM PDT 24
Finished Jul 28 07:07:26 PM PDT 24
Peak memory 200096 kb
Host smart-940042a2-1b9c-4951-87b9-ec87031121e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461984148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.1461984148
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.4072071592
Short name T23
Test name
Test status
Simulation time 12976402436 ps
CPU time 16.75 seconds
Started Jul 28 07:06:00 PM PDT 24
Finished Jul 28 07:06:17 PM PDT 24
Peak memory 199672 kb
Host smart-0913c250-004d-47d7-a28f-21f2689028dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072071592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.4072071592
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.1867112660
Short name T1093
Test name
Test status
Simulation time 50039081360 ps
CPU time 82.99 seconds
Started Jul 28 07:06:01 PM PDT 24
Finished Jul 28 07:07:24 PM PDT 24
Peak memory 200296 kb
Host smart-3dd31d53-3b01-497f-b2fb-08bc72222e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867112660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.1867112660
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.810454534
Short name T474
Test name
Test status
Simulation time 1655340936 ps
CPU time 83.73 seconds
Started Jul 28 07:06:02 PM PDT 24
Finished Jul 28 07:07:25 PM PDT 24
Peak memory 199996 kb
Host smart-2747eb0c-ed9f-453e-929e-ab3bd106a63a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810454534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.810454534
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.700545632
Short name T749
Test name
Test status
Simulation time 5807198571 ps
CPU time 5.15 seconds
Started Jul 28 07:06:00 PM PDT 24
Finished Jul 28 07:06:05 PM PDT 24
Peak memory 198340 kb
Host smart-1c66b3d2-00cf-4a92-afe9-62e4e856aef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700545632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.700545632
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.888990689
Short name T531
Test name
Test status
Simulation time 41961733901 ps
CPU time 15.83 seconds
Started Jul 28 07:06:02 PM PDT 24
Finished Jul 28 07:06:18 PM PDT 24
Peak memory 200224 kb
Host smart-5334f3dd-5ce2-41e1-b59f-ebe4feca7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888990689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.888990689
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1737074279
Short name T536
Test name
Test status
Simulation time 3853917664 ps
CPU time 3.29 seconds
Started Jul 28 07:06:03 PM PDT 24
Finished Jul 28 07:06:06 PM PDT 24
Peak memory 196720 kb
Host smart-554730b8-4b09-4b8a-9dda-852ae0fab31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737074279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1737074279
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.4236730611
Short name T1061
Test name
Test status
Simulation time 5758373225 ps
CPU time 10.39 seconds
Started Jul 28 07:06:05 PM PDT 24
Finished Jul 28 07:06:16 PM PDT 24
Peak memory 200056 kb
Host smart-04ffe278-2392-45a4-90e7-50ecff38b265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236730611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.4236730611
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.226039219
Short name T131
Test name
Test status
Simulation time 397561386110 ps
CPU time 1326.38 seconds
Started Jul 28 07:06:05 PM PDT 24
Finished Jul 28 07:28:12 PM PDT 24
Peak memory 200140 kb
Host smart-a9de7034-c55e-44a6-a39b-c6e281039c6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226039219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.226039219
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3349018647
Short name T533
Test name
Test status
Simulation time 157771302977 ps
CPU time 499.8 seconds
Started Jul 28 07:06:00 PM PDT 24
Finished Jul 28 07:14:20 PM PDT 24
Peak memory 213052 kb
Host smart-f1c63ced-1586-4e44-93b0-49d94ca91aa0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349018647 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3349018647
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3549983132
Short name T1152
Test name
Test status
Simulation time 1409472971 ps
CPU time 1.96 seconds
Started Jul 28 07:06:02 PM PDT 24
Finished Jul 28 07:06:04 PM PDT 24
Peak memory 198360 kb
Host smart-83c8e49a-3ee0-480b-9e0c-188043173893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549983132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3549983132
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.2772159305
Short name T673
Test name
Test status
Simulation time 3389322538 ps
CPU time 5.76 seconds
Started Jul 28 07:06:01 PM PDT 24
Finished Jul 28 07:06:07 PM PDT 24
Peak memory 198576 kb
Host smart-1604b760-4ff9-49f6-b0f8-9af6199132c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772159305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.2772159305
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.2649817706
Short name T840
Test name
Test status
Simulation time 18287187946 ps
CPU time 29.91 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:12:40 PM PDT 24
Peak memory 200108 kb
Host smart-ef1f10e9-1dd3-4bd7-95c0-d8c451115127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649817706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.2649817706
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.54724871
Short name T217
Test name
Test status
Simulation time 61684957587 ps
CPU time 23.2 seconds
Started Jul 28 07:12:10 PM PDT 24
Finished Jul 28 07:12:33 PM PDT 24
Peak memory 200068 kb
Host smart-1a6f6893-009c-4c93-acdb-db8b2f0f2333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54724871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.54724871
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2143047855
Short name T1181
Test name
Test status
Simulation time 254323140791 ps
CPU time 43.02 seconds
Started Jul 28 07:12:19 PM PDT 24
Finished Jul 28 07:13:02 PM PDT 24
Peak memory 200140 kb
Host smart-88977e45-c63b-499d-9002-af700eeeae18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143047855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2143047855
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2407727847
Short name T1105
Test name
Test status
Simulation time 10319255006 ps
CPU time 19.31 seconds
Started Jul 28 07:12:16 PM PDT 24
Finished Jul 28 07:12:35 PM PDT 24
Peak memory 200156 kb
Host smart-b7762097-ee22-450c-b624-3adeda3b7b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407727847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2407727847
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.57714136
Short name T984
Test name
Test status
Simulation time 66139162812 ps
CPU time 28.66 seconds
Started Jul 28 07:12:19 PM PDT 24
Finished Jul 28 07:12:48 PM PDT 24
Peak memory 200140 kb
Host smart-54da55ad-38f6-4b74-a938-90c6f1f348d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57714136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.57714136
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3433754659
Short name T463
Test name
Test status
Simulation time 87578889543 ps
CPU time 206.68 seconds
Started Jul 28 07:12:17 PM PDT 24
Finished Jul 28 07:15:43 PM PDT 24
Peak memory 200104 kb
Host smart-f9c948ca-6886-4706-800a-6356cb214b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433754659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3433754659
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.986607467
Short name T252
Test name
Test status
Simulation time 35513209811 ps
CPU time 32.26 seconds
Started Jul 28 07:12:16 PM PDT 24
Finished Jul 28 07:12:48 PM PDT 24
Peak memory 200316 kb
Host smart-441a7e29-7044-4843-8958-b0bdfefc368f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986607467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.986607467
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.479273396
Short name T186
Test name
Test status
Simulation time 43153678131 ps
CPU time 25.95 seconds
Started Jul 28 07:12:16 PM PDT 24
Finished Jul 28 07:12:43 PM PDT 24
Peak memory 200168 kb
Host smart-3f8e1ff3-f93b-4af1-8367-5d4d9b2453f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479273396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.479273396
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.3971788460
Short name T318
Test name
Test status
Simulation time 112910032096 ps
CPU time 24.02 seconds
Started Jul 28 07:12:17 PM PDT 24
Finished Jul 28 07:12:41 PM PDT 24
Peak memory 200184 kb
Host smart-436c0735-d23c-4aab-a524-34b48d73ecc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971788460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.3971788460
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.3529041295
Short name T991
Test name
Test status
Simulation time 33463631 ps
CPU time 0.55 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:06:10 PM PDT 24
Peak memory 195768 kb
Host smart-999aa95c-578a-4fde-a8a3-bd05ee41c11b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529041295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.3529041295
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2718300143
Short name T298
Test name
Test status
Simulation time 134967245881 ps
CPU time 138.3 seconds
Started Jul 28 07:06:06 PM PDT 24
Finished Jul 28 07:08:24 PM PDT 24
Peak memory 200192 kb
Host smart-3730cb42-fad9-4ca2-a592-c5127f157a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718300143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2718300143
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2192209492
Short name T1134
Test name
Test status
Simulation time 50329563323 ps
CPU time 93.17 seconds
Started Jul 28 07:06:06 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200124 kb
Host smart-d9995f0c-6fb4-4c65-b2b4-1a30c713a57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192209492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2192209492
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.3914749068
Short name T436
Test name
Test status
Simulation time 46105281364 ps
CPU time 76.22 seconds
Started Jul 28 07:06:05 PM PDT 24
Finished Jul 28 07:07:21 PM PDT 24
Peak memory 199324 kb
Host smart-4ffc964f-278f-4b58-a0ac-e634be98107c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914749068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3914749068
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1861258748
Short name T507
Test name
Test status
Simulation time 105295553376 ps
CPU time 623.86 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:16:33 PM PDT 24
Peak memory 200184 kb
Host smart-68347bde-4fbb-4bd9-8910-ab2e45f86f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861258748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1861258748
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1575645675
Short name T1132
Test name
Test status
Simulation time 3883499712 ps
CPU time 1.84 seconds
Started Jul 28 07:06:10 PM PDT 24
Finished Jul 28 07:06:12 PM PDT 24
Peak memory 200072 kb
Host smart-9fbd3e4f-dff8-4f0d-ab4b-d1dd1d4382cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575645675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1575645675
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1954439530
Short name T269
Test name
Test status
Simulation time 30762794774 ps
CPU time 37.41 seconds
Started Jul 28 07:06:05 PM PDT 24
Finished Jul 28 07:06:42 PM PDT 24
Peak memory 199752 kb
Host smart-4eeec54f-8ea0-4249-82f4-4a204d12dbf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954439530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1954439530
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1763518486
Short name T516
Test name
Test status
Simulation time 7852372600 ps
CPU time 427.38 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:13:17 PM PDT 24
Peak memory 200172 kb
Host smart-d7989ce8-5fbf-4837-9d9f-20d0eac9ffbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763518486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1763518486
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.4010052571
Short name T426
Test name
Test status
Simulation time 2320864116 ps
CPU time 14.87 seconds
Started Jul 28 07:06:06 PM PDT 24
Finished Jul 28 07:06:21 PM PDT 24
Peak memory 198416 kb
Host smart-fadd22c1-2964-4631-b798-9e999fb21e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010052571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.4010052571
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.4270189638
Short name T711
Test name
Test status
Simulation time 61530927697 ps
CPU time 22.1 seconds
Started Jul 28 07:06:06 PM PDT 24
Finished Jul 28 07:06:28 PM PDT 24
Peak memory 200116 kb
Host smart-eca1c00a-2e1f-43e0-b378-def292c95820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270189638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.4270189638
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3654777819
Short name T1004
Test name
Test status
Simulation time 4776770502 ps
CPU time 1.87 seconds
Started Jul 28 07:06:07 PM PDT 24
Finished Jul 28 07:06:09 PM PDT 24
Peak memory 196488 kb
Host smart-00482bf0-89c6-4f0c-8938-2d6f02050ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654777819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3654777819
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.3958316586
Short name T670
Test name
Test status
Simulation time 6207874172 ps
CPU time 8.88 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:06:18 PM PDT 24
Peak memory 200196 kb
Host smart-70444343-a424-494f-a2da-11da50e1587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958316586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3958316586
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.3982852714
Short name T208
Test name
Test status
Simulation time 79866491764 ps
CPU time 73.05 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:07:22 PM PDT 24
Peak memory 200156 kb
Host smart-eadb3fd3-aa72-4896-9c95-53660c973357
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982852714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.3982852714
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2134738983
Short name T974
Test name
Test status
Simulation time 123195296239 ps
CPU time 449.02 seconds
Started Jul 28 07:06:11 PM PDT 24
Finished Jul 28 07:13:40 PM PDT 24
Peak memory 216624 kb
Host smart-614bd610-9106-4b32-b3dd-fe9a043b308c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134738983 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2134738983
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.45352886
Short name T517
Test name
Test status
Simulation time 1045937737 ps
CPU time 1.53 seconds
Started Jul 28 07:06:09 PM PDT 24
Finished Jul 28 07:06:11 PM PDT 24
Peak memory 198548 kb
Host smart-ab759f58-09fa-43bc-8ae7-b666647e0dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45352886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.45352886
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.993746081
Short name T1171
Test name
Test status
Simulation time 32642336642 ps
CPU time 51.12 seconds
Started Jul 28 07:06:07 PM PDT 24
Finished Jul 28 07:06:59 PM PDT 24
Peak memory 200204 kb
Host smart-c2cccd26-103b-4ecb-8388-360e879d9371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993746081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.993746081
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.3495625802
Short name T357
Test name
Test status
Simulation time 21162232727 ps
CPU time 34.38 seconds
Started Jul 28 07:12:18 PM PDT 24
Finished Jul 28 07:12:52 PM PDT 24
Peak memory 200160 kb
Host smart-bcf7490c-bf8b-43fc-aa1c-df9976fe819f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495625802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3495625802
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.4177587026
Short name T222
Test name
Test status
Simulation time 64531787339 ps
CPU time 25.51 seconds
Started Jul 28 07:12:18 PM PDT 24
Finished Jul 28 07:12:43 PM PDT 24
Peak memory 200152 kb
Host smart-c6693b99-a5bc-4fd2-b000-1656c0001241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177587026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.4177587026
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.4204960068
Short name T1058
Test name
Test status
Simulation time 104135274264 ps
CPU time 46.96 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:13:10 PM PDT 24
Peak memory 199936 kb
Host smart-e6ed78b2-a390-4ab6-be52-33fcd50e4448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204960068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.4204960068
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1185086279
Short name T1142
Test name
Test status
Simulation time 23900395933 ps
CPU time 41.29 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:13:05 PM PDT 24
Peak memory 200072 kb
Host smart-a0913bb3-6d10-4143-befb-6b23afff9b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185086279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1185086279
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2043754810
Short name T929
Test name
Test status
Simulation time 111783537587 ps
CPU time 137.07 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:14:40 PM PDT 24
Peak memory 200188 kb
Host smart-2c636922-39a0-4fed-b178-0749cf0a0756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043754810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2043754810
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.2332764692
Short name T50
Test name
Test status
Simulation time 10954943116 ps
CPU time 20.48 seconds
Started Jul 28 07:12:22 PM PDT 24
Finished Jul 28 07:12:43 PM PDT 24
Peak memory 200060 kb
Host smart-513799d0-9ed1-4fa0-b3a1-b1394448e9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332764692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.2332764692
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3009901052
Short name T786
Test name
Test status
Simulation time 27812320404 ps
CPU time 37.8 seconds
Started Jul 28 07:12:24 PM PDT 24
Finished Jul 28 07:13:02 PM PDT 24
Peak memory 200148 kb
Host smart-5d2501fc-56c7-49ef-883a-bf9e0903d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009901052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3009901052
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1359968116
Short name T182
Test name
Test status
Simulation time 120816652915 ps
CPU time 31.73 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:12:55 PM PDT 24
Peak memory 200096 kb
Host smart-5e4c9f0b-c1d4-4aaf-87e8-5394baad94e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359968116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1359968116
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2907620230
Short name T692
Test name
Test status
Simulation time 31330180200 ps
CPU time 24.49 seconds
Started Jul 28 07:12:22 PM PDT 24
Finished Jul 28 07:12:47 PM PDT 24
Peak memory 200184 kb
Host smart-fabd5a62-9681-4ebd-b9b6-01cef1fcd483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907620230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2907620230
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.486943344
Short name T441
Test name
Test status
Simulation time 42781157 ps
CPU time 0.56 seconds
Started Jul 28 07:06:21 PM PDT 24
Finished Jul 28 07:06:22 PM PDT 24
Peak memory 195568 kb
Host smart-f4d1653f-b6c9-48fe-8096-94895b6abe33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486943344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.486943344
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1522805332
Short name T431
Test name
Test status
Simulation time 36679802077 ps
CPU time 15.67 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:06:32 PM PDT 24
Peak memory 200112 kb
Host smart-49967ade-9780-4cc1-9911-ffa2d7c32021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522805332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1522805332
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.132541122
Short name T1095
Test name
Test status
Simulation time 83527913666 ps
CPU time 18.93 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:06:35 PM PDT 24
Peak memory 200048 kb
Host smart-b2e60768-dd6d-4384-872b-b43ce72767d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132541122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.132541122
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.548050218
Short name T997
Test name
Test status
Simulation time 80887396506 ps
CPU time 11.75 seconds
Started Jul 28 07:06:19 PM PDT 24
Finished Jul 28 07:06:30 PM PDT 24
Peak memory 200100 kb
Host smart-c5b9d6e4-7dc7-4ca2-ae24-0cbf298afd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548050218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.548050218
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.2768672907
Short name T1135
Test name
Test status
Simulation time 21522199667 ps
CPU time 11.35 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:06:27 PM PDT 24
Peak memory 200192 kb
Host smart-648209e6-813b-4303-b1b2-e86c99eb5338
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768672907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.2768672907
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2992692316
Short name T250
Test name
Test status
Simulation time 109873780838 ps
CPU time 783.11 seconds
Started Jul 28 07:06:23 PM PDT 24
Finished Jul 28 07:19:26 PM PDT 24
Peak memory 200160 kb
Host smart-28a15ef0-8673-45e0-b8d6-ff9a538ba04a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992692316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2992692316
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2462903360
Short name T1180
Test name
Test status
Simulation time 11592725109 ps
CPU time 4.36 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:06:21 PM PDT 24
Peak memory 199780 kb
Host smart-f0932b2a-8e94-4efd-beae-1d3ede2a770c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462903360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2462903360
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.4246072447
Short name T304
Test name
Test status
Simulation time 69502131363 ps
CPU time 123.71 seconds
Started Jul 28 07:06:17 PM PDT 24
Finished Jul 28 07:08:21 PM PDT 24
Peak memory 198444 kb
Host smart-da938f8f-9b81-423a-bea6-f23471ce4060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246072447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.4246072447
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.3440980324
Short name T448
Test name
Test status
Simulation time 2631932442 ps
CPU time 16.24 seconds
Started Jul 28 07:06:18 PM PDT 24
Finished Jul 28 07:06:35 PM PDT 24
Peak memory 199216 kb
Host smart-4ad63057-b1e2-4571-8c1c-bb8d6ce571b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440980324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.3440980324
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2943311871
Short name T975
Test name
Test status
Simulation time 27734091428 ps
CPU time 44.59 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:07:01 PM PDT 24
Peak memory 200116 kb
Host smart-35d409df-fb6c-4f08-a72a-1ff324edea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943311871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2943311871
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.4108165280
Short name T615
Test name
Test status
Simulation time 6004145203 ps
CPU time 4.73 seconds
Started Jul 28 07:06:17 PM PDT 24
Finished Jul 28 07:06:21 PM PDT 24
Peak memory 196236 kb
Host smart-4e0436b6-298e-4956-9bfe-c9d9e95d2dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108165280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.4108165280
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2772045565
Short name T54
Test name
Test status
Simulation time 673248990 ps
CPU time 1.96 seconds
Started Jul 28 07:06:10 PM PDT 24
Finished Jul 28 07:06:12 PM PDT 24
Peak memory 199916 kb
Host smart-12c0ae36-a726-4678-bf7b-1820e6b582ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772045565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2772045565
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3951485789
Short name T1062
Test name
Test status
Simulation time 150210862070 ps
CPU time 277.9 seconds
Started Jul 28 07:06:22 PM PDT 24
Finished Jul 28 07:11:00 PM PDT 24
Peak memory 200168 kb
Host smart-89f77111-800b-482e-b644-70f1af9efb1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951485789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3951485789
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1197638662
Short name T1034
Test name
Test status
Simulation time 26763027819 ps
CPU time 407.83 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:13:04 PM PDT 24
Peak memory 214580 kb
Host smart-c7eda94a-95f5-49c9-a06e-3ee04baaae57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197638662 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1197638662
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.4012480692
Short name T981
Test name
Test status
Simulation time 2300102868 ps
CPU time 2.69 seconds
Started Jul 28 07:06:16 PM PDT 24
Finished Jul 28 07:06:19 PM PDT 24
Peak memory 200076 kb
Host smart-6184eac0-8ad5-4709-8599-d6cba046e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012480692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.4012480692
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.2278520584
Short name T417
Test name
Test status
Simulation time 47977849876 ps
CPU time 27.25 seconds
Started Jul 28 07:06:10 PM PDT 24
Finished Jul 28 07:06:37 PM PDT 24
Peak memory 200220 kb
Host smart-c93e0bde-9726-4f01-92ad-f378bcbc60ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278520584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2278520584
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.2740384442
Short name T1016
Test name
Test status
Simulation time 315832573809 ps
CPU time 77.57 seconds
Started Jul 28 07:12:24 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 200044 kb
Host smart-061c4c2c-fb3f-4854-a284-5f89b7d826a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740384442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.2740384442
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1821535506
Short name T950
Test name
Test status
Simulation time 84864672021 ps
CPU time 38.8 seconds
Started Jul 28 07:12:24 PM PDT 24
Finished Jul 28 07:13:03 PM PDT 24
Peak memory 200108 kb
Host smart-95c93628-6294-43e1-80dd-2678fa6b61a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821535506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1821535506
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.616890597
Short name T204
Test name
Test status
Simulation time 94275463983 ps
CPU time 104.7 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:14:08 PM PDT 24
Peak memory 200052 kb
Host smart-537e70fe-e6f1-4ea7-a3cf-4869fc85ca03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616890597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.616890597
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1509153240
Short name T600
Test name
Test status
Simulation time 109569925547 ps
CPU time 80.15 seconds
Started Jul 28 07:12:22 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 200284 kb
Host smart-f94bedc9-a385-40cf-a5b4-330022bea91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509153240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1509153240
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.4258916134
Short name T1143
Test name
Test status
Simulation time 28289455495 ps
CPU time 25.02 seconds
Started Jul 28 07:12:23 PM PDT 24
Finished Jul 28 07:12:49 PM PDT 24
Peak memory 200100 kb
Host smart-5b43dbdd-3caa-4f43-b394-db3a7bc503e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258916134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.4258916134
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1329678946
Short name T889
Test name
Test status
Simulation time 81806128251 ps
CPU time 42.5 seconds
Started Jul 28 07:12:24 PM PDT 24
Finished Jul 28 07:13:06 PM PDT 24
Peak memory 200164 kb
Host smart-e040c251-7dab-4c11-b3da-99c215cf4a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329678946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1329678946
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.2039065372
Short name T924
Test name
Test status
Simulation time 7680228589 ps
CPU time 14.1 seconds
Started Jul 28 07:12:27 PM PDT 24
Finished Jul 28 07:12:41 PM PDT 24
Peak memory 200128 kb
Host smart-cbf24274-39a2-452a-a6b0-8a6c4fe9d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039065372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.2039065372
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2114433323
Short name T601
Test name
Test status
Simulation time 87041860139 ps
CPU time 57.21 seconds
Started Jul 28 07:12:29 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 200128 kb
Host smart-14b68ed2-c1ba-4d1d-8eb9-6ff1dc195f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114433323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2114433323
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.50752863
Short name T848
Test name
Test status
Simulation time 23124264388 ps
CPU time 52.67 seconds
Started Jul 28 07:12:30 PM PDT 24
Finished Jul 28 07:13:22 PM PDT 24
Peak memory 200116 kb
Host smart-8c5531bb-1ec9-40d5-b722-041fa473e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50752863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.50752863
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2500528497
Short name T525
Test name
Test status
Simulation time 100800155014 ps
CPU time 418.58 seconds
Started Jul 28 07:12:26 PM PDT 24
Finished Jul 28 07:19:25 PM PDT 24
Peak memory 200208 kb
Host smart-2fd892ee-df7a-459b-a268-b844cf90454f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500528497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2500528497
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3731227604
Short name T1149
Test name
Test status
Simulation time 147021417 ps
CPU time 0.55 seconds
Started Jul 28 07:06:33 PM PDT 24
Finished Jul 28 07:06:34 PM PDT 24
Peak memory 195600 kb
Host smart-f087db27-2154-4641-bfef-3f13cba4b22b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731227604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3731227604
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3058768909
Short name T839
Test name
Test status
Simulation time 28275151354 ps
CPU time 11.58 seconds
Started Jul 28 07:06:21 PM PDT 24
Finished Jul 28 07:06:32 PM PDT 24
Peak memory 200120 kb
Host smart-859735b5-c756-42d1-8f54-b0664a9af6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058768909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3058768909
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.754085987
Short name T698
Test name
Test status
Simulation time 217892065917 ps
CPU time 51.69 seconds
Started Jul 28 07:06:22 PM PDT 24
Finished Jul 28 07:07:14 PM PDT 24
Peak memory 200232 kb
Host smart-f9a29896-27ba-43e8-bf22-91b1c55091a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754085987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.754085987
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1157930330
Short name T1045
Test name
Test status
Simulation time 37860381678 ps
CPU time 64.97 seconds
Started Jul 28 07:06:29 PM PDT 24
Finished Jul 28 07:07:34 PM PDT 24
Peak memory 200120 kb
Host smart-c445e545-0089-40aa-a602-72b0a0e4d1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157930330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1157930330
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.431628788
Short name T356
Test name
Test status
Simulation time 11320833268 ps
CPU time 7.35 seconds
Started Jul 28 07:06:27 PM PDT 24
Finished Jul 28 07:06:35 PM PDT 24
Peak memory 200140 kb
Host smart-e0d45b5c-f228-4954-8fba-6df1ccdf94cf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431628788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.431628788
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1771699878
Short name T458
Test name
Test status
Simulation time 156066238046 ps
CPU time 383.57 seconds
Started Jul 28 07:06:27 PM PDT 24
Finished Jul 28 07:12:50 PM PDT 24
Peak memory 200124 kb
Host smart-de83e787-0b16-4766-8a74-0fc8c8d79769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1771699878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1771699878
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.208222439
Short name T365
Test name
Test status
Simulation time 9951592041 ps
CPU time 5.78 seconds
Started Jul 28 07:06:26 PM PDT 24
Finished Jul 28 07:06:32 PM PDT 24
Peak memory 200084 kb
Host smart-e120a259-815b-4d91-83bd-2eb299ac5a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208222439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.208222439
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2808848260
Short name T302
Test name
Test status
Simulation time 128038485964 ps
CPU time 199.48 seconds
Started Jul 28 07:06:29 PM PDT 24
Finished Jul 28 07:09:48 PM PDT 24
Peak memory 200316 kb
Host smart-f8632d8e-c648-4ee1-92d2-2836754bc7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808848260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2808848260
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2229041139
Short name T1120
Test name
Test status
Simulation time 23682800474 ps
CPU time 168.09 seconds
Started Jul 28 07:06:27 PM PDT 24
Finished Jul 28 07:09:15 PM PDT 24
Peak memory 200124 kb
Host smart-8d9b3638-c7b5-450a-9583-82136f7969dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229041139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2229041139
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3403080
Short name T546
Test name
Test status
Simulation time 1699464550 ps
CPU time 9.27 seconds
Started Jul 28 07:06:29 PM PDT 24
Finished Jul 28 07:06:39 PM PDT 24
Peak memory 198252 kb
Host smart-f559e170-6dfa-4cb0-9e3d-008d0bbe98d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3403080
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.133060408
Short name T505
Test name
Test status
Simulation time 23689487434 ps
CPU time 39.7 seconds
Started Jul 28 07:06:29 PM PDT 24
Finished Jul 28 07:07:09 PM PDT 24
Peak memory 200024 kb
Host smart-0637f379-1046-4d56-8c9d-e50978af8cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133060408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.133060408
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1484106850
Short name T503
Test name
Test status
Simulation time 5370233683 ps
CPU time 1.38 seconds
Started Jul 28 07:06:24 PM PDT 24
Finished Jul 28 07:06:25 PM PDT 24
Peak memory 196324 kb
Host smart-7caf9c49-3428-4bb1-861c-64a130296fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484106850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1484106850
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.1266033067
Short name T447
Test name
Test status
Simulation time 5893302822 ps
CPU time 13.92 seconds
Started Jul 28 07:06:21 PM PDT 24
Finished Jul 28 07:06:35 PM PDT 24
Peak memory 200012 kb
Host smart-8f99b884-9c2a-4074-a08b-8426be3331b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266033067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.1266033067
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2644980054
Short name T608
Test name
Test status
Simulation time 375885663700 ps
CPU time 625.46 seconds
Started Jul 28 07:06:33 PM PDT 24
Finished Jul 28 07:16:58 PM PDT 24
Peak memory 200128 kb
Host smart-bed8562d-aa6e-42b5-bf6d-a72ca226e84c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644980054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2644980054
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1667980638
Short name T367
Test name
Test status
Simulation time 65318754275 ps
CPU time 900.09 seconds
Started Jul 28 07:06:26 PM PDT 24
Finished Jul 28 07:21:26 PM PDT 24
Peak memory 216624 kb
Host smart-036ca866-8a0f-4aac-88f5-ad45d4c50d7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667980638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1667980638
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.523079251
Short name T1133
Test name
Test status
Simulation time 12877274939 ps
CPU time 47.19 seconds
Started Jul 28 07:06:26 PM PDT 24
Finished Jul 28 07:07:14 PM PDT 24
Peak memory 200156 kb
Host smart-a53d450f-1c42-45c9-af6a-dcc79b5c3a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523079251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.523079251
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1697000349
Short name T267
Test name
Test status
Simulation time 29165982042 ps
CPU time 12.22 seconds
Started Jul 28 07:06:22 PM PDT 24
Finished Jul 28 07:06:35 PM PDT 24
Peak memory 199224 kb
Host smart-6d0c6705-5e40-4911-9ae3-f7d8e9956b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697000349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1697000349
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.2541538925
Short name T223
Test name
Test status
Simulation time 137705022724 ps
CPU time 112.51 seconds
Started Jul 28 07:12:30 PM PDT 24
Finished Jul 28 07:14:23 PM PDT 24
Peak memory 200180 kb
Host smart-37f43755-bb58-4fb3-89d7-2890bffc0b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541538925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.2541538925
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.1742674134
Short name T1059
Test name
Test status
Simulation time 33251214073 ps
CPU time 46.89 seconds
Started Jul 28 07:12:29 PM PDT 24
Finished Jul 28 07:13:16 PM PDT 24
Peak memory 200160 kb
Host smart-f316d329-80d7-4a71-aa77-e19daca8354c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742674134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.1742674134
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1232327774
Short name T386
Test name
Test status
Simulation time 20745705155 ps
CPU time 5.26 seconds
Started Jul 28 07:12:30 PM PDT 24
Finished Jul 28 07:12:36 PM PDT 24
Peak memory 200092 kb
Host smart-274c1570-9d46-48e1-a54e-612e85ddd924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232327774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1232327774
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.566691881
Short name T272
Test name
Test status
Simulation time 164026022053 ps
CPU time 59.61 seconds
Started Jul 28 07:12:30 PM PDT 24
Finished Jul 28 07:13:30 PM PDT 24
Peak memory 200028 kb
Host smart-084c6feb-faa8-41ce-84d9-dc0381be5b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566691881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.566691881
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2003770143
Short name T478
Test name
Test status
Simulation time 174616342510 ps
CPU time 300.29 seconds
Started Jul 28 07:12:37 PM PDT 24
Finished Jul 28 07:17:38 PM PDT 24
Peak memory 200104 kb
Host smart-73849719-4499-413c-85dd-73262672c1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003770143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2003770143
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.1779099135
Short name T1081
Test name
Test status
Simulation time 94667132329 ps
CPU time 31.12 seconds
Started Jul 28 07:12:36 PM PDT 24
Finished Jul 28 07:13:07 PM PDT 24
Peak memory 200168 kb
Host smart-2f06913b-5b8b-4ded-8586-2e4987d74d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779099135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.1779099135
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3599805445
Short name T428
Test name
Test status
Simulation time 106647875473 ps
CPU time 64.5 seconds
Started Jul 28 07:12:36 PM PDT 24
Finished Jul 28 07:13:40 PM PDT 24
Peak memory 200156 kb
Host smart-372fa417-c6b4-4fbb-aca2-04b0947a21f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599805445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3599805445
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3576419503
Short name T459
Test name
Test status
Simulation time 12191717 ps
CPU time 0.52 seconds
Started Jul 28 07:06:37 PM PDT 24
Finished Jul 28 07:06:38 PM PDT 24
Peak memory 195012 kb
Host smart-61291a6f-3e43-4347-9210-a4cd519ce4eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576419503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3576419503
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.3501401939
Short name T300
Test name
Test status
Simulation time 67123664442 ps
CPU time 78.72 seconds
Started Jul 28 07:06:32 PM PDT 24
Finished Jul 28 07:07:51 PM PDT 24
Peak memory 200200 kb
Host smart-29cb6b61-0cdd-49d7-870d-3c2f3ebde36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501401939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.3501401939
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1834930235
Short name T1110
Test name
Test status
Simulation time 8926486095 ps
CPU time 9.15 seconds
Started Jul 28 07:06:33 PM PDT 24
Finished Jul 28 07:06:42 PM PDT 24
Peak memory 200088 kb
Host smart-fec9bbc9-39d3-43ea-9898-fbb038ed5951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834930235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1834930235
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.4047659179
Short name T283
Test name
Test status
Simulation time 92961949920 ps
CPU time 135.08 seconds
Started Jul 28 07:06:39 PM PDT 24
Finished Jul 28 07:08:54 PM PDT 24
Peak memory 200204 kb
Host smart-b30a35d6-23e3-48c4-9bc2-d92efde6cb68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047659179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.4047659179
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1481453427
Short name T901
Test name
Test status
Simulation time 125222464633 ps
CPU time 362.64 seconds
Started Jul 28 07:06:37 PM PDT 24
Finished Jul 28 07:12:39 PM PDT 24
Peak memory 200124 kb
Host smart-a442ed36-45fd-4a09-8227-b97b3f676f98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1481453427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1481453427
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2693639026
Short name T1146
Test name
Test status
Simulation time 11599736457 ps
CPU time 7.99 seconds
Started Jul 28 07:06:36 PM PDT 24
Finished Jul 28 07:06:44 PM PDT 24
Peak memory 199544 kb
Host smart-5c8c6214-55ef-48f9-85c7-3e8af682b6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693639026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2693639026
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.392077309
Short name T731
Test name
Test status
Simulation time 103857019540 ps
CPU time 67.29 seconds
Started Jul 28 07:06:37 PM PDT 24
Finished Jul 28 07:07:45 PM PDT 24
Peak memory 199652 kb
Host smart-78d589ec-1ada-47c4-83f4-bab832bd15b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392077309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.392077309
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2663619801
Short name T976
Test name
Test status
Simulation time 23345953315 ps
CPU time 271.87 seconds
Started Jul 28 07:06:40 PM PDT 24
Finished Jul 28 07:11:12 PM PDT 24
Peak memory 200108 kb
Host smart-4c137a83-8458-49ae-a8dc-b22cc3e9f811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2663619801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2663619801
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2550497261
Short name T329
Test name
Test status
Simulation time 4258216020 ps
CPU time 7.4 seconds
Started Jul 28 07:06:33 PM PDT 24
Finished Jul 28 07:06:41 PM PDT 24
Peak memory 197968 kb
Host smart-dfb5a0bf-dd07-4a41-bbf8-f7195da84936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550497261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2550497261
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1815687826
Short name T684
Test name
Test status
Simulation time 50953194941 ps
CPU time 67.72 seconds
Started Jul 28 07:06:37 PM PDT 24
Finished Jul 28 07:07:45 PM PDT 24
Peak memory 200188 kb
Host smart-ddd1774b-7878-4edd-aa8d-c07eed7c0d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815687826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1815687826
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.3227990042
Short name T27
Test name
Test status
Simulation time 5087532679 ps
CPU time 7.87 seconds
Started Jul 28 07:06:38 PM PDT 24
Finished Jul 28 07:06:47 PM PDT 24
Peak memory 196192 kb
Host smart-46210df1-670a-4bda-8077-93d08e4557c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227990042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.3227990042
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.203885103
Short name T440
Test name
Test status
Simulation time 91929629 ps
CPU time 0.82 seconds
Started Jul 28 07:06:32 PM PDT 24
Finished Jul 28 07:06:32 PM PDT 24
Peak memory 197168 kb
Host smart-f182cd86-58fe-4633-aa7d-f543e6b9a00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203885103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.203885103
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1925784535
Short name T726
Test name
Test status
Simulation time 49859665823 ps
CPU time 96.7 seconds
Started Jul 28 07:06:40 PM PDT 24
Finished Jul 28 07:08:17 PM PDT 24
Peak memory 200044 kb
Host smart-46e4bb72-d81e-44ff-92b5-7ccf114bd75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925784535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1925784535
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2914021761
Short name T66
Test name
Test status
Simulation time 161023546891 ps
CPU time 478.75 seconds
Started Jul 28 07:06:40 PM PDT 24
Finished Jul 28 07:14:39 PM PDT 24
Peak memory 216616 kb
Host smart-c4bb1e07-1a6e-4413-8eda-e74c946cd6d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914021761 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2914021761
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2620170075
Short name T411
Test name
Test status
Simulation time 1644451849 ps
CPU time 2.05 seconds
Started Jul 28 07:06:38 PM PDT 24
Finished Jul 28 07:06:40 PM PDT 24
Peak memory 198496 kb
Host smart-bff9ad43-e2ae-4202-8ac9-ccfc89ba23a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620170075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2620170075
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2885048332
Short name T299
Test name
Test status
Simulation time 131715438094 ps
CPU time 56.49 seconds
Started Jul 28 07:06:33 PM PDT 24
Finished Jul 28 07:07:29 PM PDT 24
Peak memory 200080 kb
Host smart-96dcfd66-89b2-4c2c-a604-4fbf45967f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885048332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2885048332
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3981141899
Short name T970
Test name
Test status
Simulation time 28782361231 ps
CPU time 11.58 seconds
Started Jul 28 07:12:37 PM PDT 24
Finished Jul 28 07:12:49 PM PDT 24
Peak memory 199048 kb
Host smart-5c831ad2-58c2-4f29-9736-eaf242683638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981141899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3981141899
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.2714039984
Short name T623
Test name
Test status
Simulation time 146895103698 ps
CPU time 60.01 seconds
Started Jul 28 07:12:44 PM PDT 24
Finished Jul 28 07:13:44 PM PDT 24
Peak memory 200120 kb
Host smart-a42034e8-02f7-46a4-be42-9f2396724260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714039984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.2714039984
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.3374644733
Short name T903
Test name
Test status
Simulation time 97711971741 ps
CPU time 155.65 seconds
Started Jul 28 07:12:43 PM PDT 24
Finished Jul 28 07:15:18 PM PDT 24
Peak memory 200152 kb
Host smart-e91dd3a4-58af-4f66-9692-5c834270210c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374644733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.3374644733
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.2747143048
Short name T200
Test name
Test status
Simulation time 89610948916 ps
CPU time 40.73 seconds
Started Jul 28 07:12:41 PM PDT 24
Finished Jul 28 07:13:22 PM PDT 24
Peak memory 200104 kb
Host smart-fd32e802-e2b2-4bcb-b18d-eaa002a959be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747143048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.2747143048
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2311031309
Short name T1018
Test name
Test status
Simulation time 65667844612 ps
CPU time 26.92 seconds
Started Jul 28 07:12:44 PM PDT 24
Finished Jul 28 07:13:11 PM PDT 24
Peak memory 200188 kb
Host smart-ac58b35a-450d-49dd-ad88-9e468623f52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311031309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2311031309
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.604458550
Short name T195
Test name
Test status
Simulation time 19411363815 ps
CPU time 36.35 seconds
Started Jul 28 07:12:45 PM PDT 24
Finished Jul 28 07:13:22 PM PDT 24
Peak memory 200116 kb
Host smart-cd640525-cf16-4fc4-a5fc-adbea25d80d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604458550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.604458550
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3842498760
Short name T936
Test name
Test status
Simulation time 107511842108 ps
CPU time 31.23 seconds
Started Jul 28 07:12:43 PM PDT 24
Finished Jul 28 07:13:14 PM PDT 24
Peak memory 200124 kb
Host smart-898e6d13-4a21-484f-a92d-b07b3eb06631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842498760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3842498760
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2896789529
Short name T339
Test name
Test status
Simulation time 10671123 ps
CPU time 0.54 seconds
Started Jul 28 07:06:47 PM PDT 24
Finished Jul 28 07:06:48 PM PDT 24
Peak memory 194940 kb
Host smart-c6df7846-81bf-4cbd-bdf9-a0570980cef1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896789529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2896789529
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3541358912
Short name T990
Test name
Test status
Simulation time 72273062538 ps
CPU time 54.38 seconds
Started Jul 28 07:06:43 PM PDT 24
Finished Jul 28 07:07:38 PM PDT 24
Peak memory 200176 kb
Host smart-e3609a52-63ed-417d-810b-689c5ecfb36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541358912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3541358912
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.179352432
Short name T850
Test name
Test status
Simulation time 47934453802 ps
CPU time 20 seconds
Started Jul 28 07:06:43 PM PDT 24
Finished Jul 28 07:07:04 PM PDT 24
Peak memory 199984 kb
Host smart-0217b2c3-e8e0-45e4-a162-9df80ef8a590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179352432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.179352432
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2956596321
Short name T578
Test name
Test status
Simulation time 16059061421 ps
CPU time 25.64 seconds
Started Jul 28 07:06:49 PM PDT 24
Finished Jul 28 07:07:14 PM PDT 24
Peak memory 200188 kb
Host smart-a5b6a33c-7309-4e11-aac0-1ccc2290c0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956596321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2956596321
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2552257632
Short name T825
Test name
Test status
Simulation time 10466854795 ps
CPU time 17.49 seconds
Started Jul 28 07:06:42 PM PDT 24
Finished Jul 28 07:06:59 PM PDT 24
Peak memory 200092 kb
Host smart-59c21f84-ce3e-4807-adc6-d8691e24506f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552257632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2552257632
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.1553312395
Short name T508
Test name
Test status
Simulation time 108667057468 ps
CPU time 731.56 seconds
Started Jul 28 07:06:45 PM PDT 24
Finished Jul 28 07:18:57 PM PDT 24
Peak memory 200156 kb
Host smart-70ef2a34-8e69-4859-8e13-00ee03c224cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1553312395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.1553312395
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2915775889
Short name T801
Test name
Test status
Simulation time 8251039427 ps
CPU time 11.8 seconds
Started Jul 28 07:06:48 PM PDT 24
Finished Jul 28 07:07:00 PM PDT 24
Peak memory 198600 kb
Host smart-f031a1dd-2eb8-4cf2-9064-39518a518143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915775889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2915775889
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.4020086139
Short name T352
Test name
Test status
Simulation time 68198142545 ps
CPU time 10.09 seconds
Started Jul 28 07:06:43 PM PDT 24
Finished Jul 28 07:06:53 PM PDT 24
Peak memory 200020 kb
Host smart-902ab830-4872-48cb-9596-9cbffc3a468b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020086139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.4020086139
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.228409119
Short name T259
Test name
Test status
Simulation time 23652448298 ps
CPU time 306.54 seconds
Started Jul 28 07:06:48 PM PDT 24
Finished Jul 28 07:11:55 PM PDT 24
Peak memory 200156 kb
Host smart-daec2fce-d4f5-4f20-a50b-050893c72ab4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228409119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.228409119
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1911345638
Short name T21
Test name
Test status
Simulation time 5277227046 ps
CPU time 7.93 seconds
Started Jul 28 07:06:49 PM PDT 24
Finished Jul 28 07:06:57 PM PDT 24
Peak memory 199380 kb
Host smart-91e1d9ce-186b-4d32-ad54-e62f3b46d8a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1911345638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1911345638
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2755238696
Short name T321
Test name
Test status
Simulation time 97703347104 ps
CPU time 31.75 seconds
Started Jul 28 07:06:43 PM PDT 24
Finished Jul 28 07:07:15 PM PDT 24
Peak memory 200108 kb
Host smart-021543d5-e09c-4b66-8b39-31920320b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755238696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2755238696
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.2624890161
Short name T609
Test name
Test status
Simulation time 4952424632 ps
CPU time 4.36 seconds
Started Jul 28 07:06:49 PM PDT 24
Finished Jul 28 07:06:53 PM PDT 24
Peak memory 196320 kb
Host smart-24087963-9de4-41d1-b35d-0f6fec84e67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624890161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.2624890161
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.220993869
Short name T725
Test name
Test status
Simulation time 6077145067 ps
CPU time 17.84 seconds
Started Jul 28 07:06:49 PM PDT 24
Finished Jul 28 07:07:07 PM PDT 24
Peak memory 200176 kb
Host smart-67051600-bc98-47e9-be56-212cb8742bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220993869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.220993869
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1124370469
Short name T317
Test name
Test status
Simulation time 127492870222 ps
CPU time 349.96 seconds
Started Jul 28 07:06:47 PM PDT 24
Finished Jul 28 07:12:37 PM PDT 24
Peak memory 200104 kb
Host smart-147c6a55-6446-4634-bb00-f7b4c1b856c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124370469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1124370469
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3620938720
Short name T797
Test name
Test status
Simulation time 11423117085 ps
CPU time 129.92 seconds
Started Jul 28 07:06:51 PM PDT 24
Finished Jul 28 07:09:01 PM PDT 24
Peak memory 216892 kb
Host smart-2066a716-355f-4bcd-9d6f-b6df8975eff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620938720 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3620938720
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2734595134
Short name T509
Test name
Test status
Simulation time 14709898159 ps
CPU time 16.77 seconds
Started Jul 28 07:06:48 PM PDT 24
Finished Jul 28 07:07:04 PM PDT 24
Peak memory 200196 kb
Host smart-dc85ed72-cf66-492c-b1f6-643a430c9645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734595134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2734595134
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.3152345663
Short name T1038
Test name
Test status
Simulation time 61509330178 ps
CPU time 94.79 seconds
Started Jul 28 07:06:49 PM PDT 24
Finished Jul 28 07:08:24 PM PDT 24
Peak memory 200208 kb
Host smart-eab421e1-5684-43ae-a048-4004a1dea9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152345663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3152345663
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1443328460
Short name T923
Test name
Test status
Simulation time 137766127288 ps
CPU time 245.45 seconds
Started Jul 28 07:12:42 PM PDT 24
Finished Jul 28 07:16:48 PM PDT 24
Peak memory 200196 kb
Host smart-ca3cec02-ab01-45cf-8604-578fde8dbf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443328460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1443328460
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2478527226
Short name T359
Test name
Test status
Simulation time 232361716167 ps
CPU time 83.6 seconds
Started Jul 28 07:12:43 PM PDT 24
Finished Jul 28 07:14:06 PM PDT 24
Peak memory 200100 kb
Host smart-58f57b1c-d1e2-41f8-af2c-c618701ea1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478527226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2478527226
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3646507930
Short name T640
Test name
Test status
Simulation time 112691654010 ps
CPU time 159.8 seconds
Started Jul 28 07:12:40 PM PDT 24
Finished Jul 28 07:15:20 PM PDT 24
Peak memory 200360 kb
Host smart-490c3dc4-9625-4a7d-836e-7c248557c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646507930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3646507930
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3324215951
Short name T219
Test name
Test status
Simulation time 127470407834 ps
CPU time 54.38 seconds
Started Jul 28 07:12:46 PM PDT 24
Finished Jul 28 07:13:40 PM PDT 24
Peak memory 199868 kb
Host smart-be5511d3-4764-43ec-8206-9a9a55e55018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324215951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3324215951
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.465295298
Short name T220
Test name
Test status
Simulation time 165768472277 ps
CPU time 16.9 seconds
Started Jul 28 07:12:44 PM PDT 24
Finished Jul 28 07:13:01 PM PDT 24
Peak memory 200052 kb
Host smart-8b4e2ea8-83e1-4957-bf10-69e99c65bc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465295298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.465295298
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.910341115
Short name T183
Test name
Test status
Simulation time 107915993409 ps
CPU time 59.33 seconds
Started Jul 28 07:12:43 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 200176 kb
Host smart-b1627861-22e5-415b-b9a1-dca185158232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910341115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.910341115
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.534396490
Short name T881
Test name
Test status
Simulation time 48777554191 ps
CPU time 68.14 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:14:00 PM PDT 24
Peak memory 200152 kb
Host smart-dc57789d-f881-4e0a-b7eb-27304882c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534396490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.534396490
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.404220625
Short name T926
Test name
Test status
Simulation time 59397416221 ps
CPU time 79.29 seconds
Started Jul 28 07:12:53 PM PDT 24
Finished Jul 28 07:14:13 PM PDT 24
Peak memory 200164 kb
Host smart-29c63a3f-6ad7-49f9-be3a-d88510ff91dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404220625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.404220625
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1346647953
Short name T1177
Test name
Test status
Simulation time 33266031226 ps
CPU time 15.8 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:13:08 PM PDT 24
Peak memory 200128 kb
Host smart-1c03eebc-5ef3-4dfa-a1bf-7f22a3d54bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346647953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1346647953
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2585287480
Short name T690
Test name
Test status
Simulation time 33553293 ps
CPU time 0.54 seconds
Started Jul 28 07:04:39 PM PDT 24
Finished Jul 28 07:04:40 PM PDT 24
Peak memory 195608 kb
Host smart-761ccab7-cd6f-4e36-bc7b-6d6789f8d935
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585287480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2585287480
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.557888244
Short name T55
Test name
Test status
Simulation time 75745514857 ps
CPU time 33.3 seconds
Started Jul 28 07:04:31 PM PDT 24
Finished Jul 28 07:05:05 PM PDT 24
Peak memory 200192 kb
Host smart-46723d5f-5868-4f01-a460-cf3b140c99f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557888244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.557888244
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3377832528
Short name T695
Test name
Test status
Simulation time 22947030203 ps
CPU time 9.72 seconds
Started Jul 28 07:04:35 PM PDT 24
Finished Jul 28 07:04:44 PM PDT 24
Peak memory 199428 kb
Host smart-42f1038d-584d-4ea3-922c-677d590280ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377832528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3377832528
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4063895430
Short name T142
Test name
Test status
Simulation time 14488859039 ps
CPU time 22.93 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:04:57 PM PDT 24
Peak memory 200060 kb
Host smart-0055a2ef-1815-4105-8463-5f4035d67d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063895430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4063895430
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.4154785325
Short name T632
Test name
Test status
Simulation time 50469265980 ps
CPU time 10.4 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:04:44 PM PDT 24
Peak memory 200344 kb
Host smart-02818dc3-e6cf-4a3e-b24b-a7e10e986c9e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154785325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.4154785325
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.513755523
Short name T714
Test name
Test status
Simulation time 70994685317 ps
CPU time 278.55 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:09:15 PM PDT 24
Peak memory 200192 kb
Host smart-1e197c66-607b-4d33-ab56-1af44db2dc80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513755523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.513755523
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.342778368
Short name T327
Test name
Test status
Simulation time 9713013635 ps
CPU time 21.19 seconds
Started Jul 28 07:04:35 PM PDT 24
Finished Jul 28 07:04:57 PM PDT 24
Peak memory 200060 kb
Host smart-30baf8e9-dbb9-498b-9ab7-a339e5acdc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342778368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.342778368
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3149742693
Short name T693
Test name
Test status
Simulation time 45958745218 ps
CPU time 38.44 seconds
Started Jul 28 07:04:32 PM PDT 24
Finished Jul 28 07:05:10 PM PDT 24
Peak memory 198368 kb
Host smart-85badcdb-c7f5-4267-808b-2b59b6708ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149742693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3149742693
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.3216105387
Short name T316
Test name
Test status
Simulation time 11971081746 ps
CPU time 364.31 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:10:40 PM PDT 24
Peak memory 200184 kb
Host smart-69dd762e-e25e-48a7-9167-80f8ce46b2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216105387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3216105387
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.4112377012
Short name T382
Test name
Test status
Simulation time 3164419685 ps
CPU time 26.03 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:05:00 PM PDT 24
Peak memory 198200 kb
Host smart-a7565c30-e0cc-4fd9-a397-f6245adb557c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4112377012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.4112377012
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4120169359
Short name T301
Test name
Test status
Simulation time 73198613650 ps
CPU time 73.68 seconds
Started Jul 28 07:04:33 PM PDT 24
Finished Jul 28 07:05:47 PM PDT 24
Peak memory 200164 kb
Host smart-54603256-8e19-498f-a99d-d9408fe30d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120169359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4120169359
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1214899162
Short name T402
Test name
Test status
Simulation time 37549424689 ps
CPU time 13.71 seconds
Started Jul 28 07:04:31 PM PDT 24
Finished Jul 28 07:04:45 PM PDT 24
Peak memory 196048 kb
Host smart-28a7ab1d-8528-403d-93e8-b7a15e2ad1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214899162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1214899162
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3164294735
Short name T32
Test name
Test status
Simulation time 37422031 ps
CPU time 0.75 seconds
Started Jul 28 07:04:38 PM PDT 24
Finished Jul 28 07:04:39 PM PDT 24
Peak memory 218396 kb
Host smart-1d8f2abe-095e-41c4-99a8-1944fd90295f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164294735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3164294735
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.1752415012
Short name T812
Test name
Test status
Simulation time 468223818 ps
CPU time 1.53 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:04:35 PM PDT 24
Peak memory 199452 kb
Host smart-2423815a-9e54-4664-a20e-8f2ef0c27dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752415012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1752415012
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.2890795373
Short name T130
Test name
Test status
Simulation time 353503697811 ps
CPU time 334.37 seconds
Started Jul 28 07:04:38 PM PDT 24
Finished Jul 28 07:10:13 PM PDT 24
Peak memory 216128 kb
Host smart-fbe69448-6c14-46e1-b880-1b4abb652562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890795373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.2890795373
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.652153062
Short name T176
Test name
Test status
Simulation time 96534967575 ps
CPU time 581.45 seconds
Started Jul 28 07:04:39 PM PDT 24
Finished Jul 28 07:14:21 PM PDT 24
Peak memory 225868 kb
Host smart-83ebb3f4-47ce-42a9-98dc-fba670a3269e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652153062 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.652153062
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.983206804
Short name T336
Test name
Test status
Simulation time 376714595 ps
CPU time 1.34 seconds
Started Jul 28 07:04:31 PM PDT 24
Finished Jul 28 07:04:33 PM PDT 24
Peak memory 197264 kb
Host smart-cb3d9e32-9fb4-4921-adc3-88df93b665a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983206804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.983206804
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.2481235119
Short name T717
Test name
Test status
Simulation time 22866184262 ps
CPU time 16.9 seconds
Started Jul 28 07:04:29 PM PDT 24
Finished Jul 28 07:04:46 PM PDT 24
Peak memory 199996 kb
Host smart-f97b8d76-3070-4578-9f89-a84e01910d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481235119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.2481235119
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2944437371
Short name T785
Test name
Test status
Simulation time 41142064 ps
CPU time 0.55 seconds
Started Jul 28 07:06:57 PM PDT 24
Finished Jul 28 07:06:57 PM PDT 24
Peak memory 195572 kb
Host smart-fff2a237-528e-42b2-8482-2d9224857846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944437371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2944437371
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.498960100
Short name T393
Test name
Test status
Simulation time 107401112081 ps
CPU time 23.72 seconds
Started Jul 28 07:06:47 PM PDT 24
Finished Jul 28 07:07:11 PM PDT 24
Peak memory 200124 kb
Host smart-36678583-4f82-406b-9535-7afa31c522b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498960100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.498960100
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1070671998
Short name T657
Test name
Test status
Simulation time 35937886366 ps
CPU time 9.39 seconds
Started Jul 28 07:06:52 PM PDT 24
Finished Jul 28 07:07:01 PM PDT 24
Peak memory 200140 kb
Host smart-03574c59-658b-48e3-bf96-0c2c41cc7edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070671998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1070671998
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2946275818
Short name T925
Test name
Test status
Simulation time 23098656850 ps
CPU time 34.99 seconds
Started Jul 28 07:06:52 PM PDT 24
Finished Jul 28 07:07:27 PM PDT 24
Peak memory 200068 kb
Host smart-4aa18fcc-e14a-4b4f-bcb6-0fa4b7992d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946275818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2946275818
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.52779556
Short name T1000
Test name
Test status
Simulation time 21400570736 ps
CPU time 4.31 seconds
Started Jul 28 07:06:55 PM PDT 24
Finished Jul 28 07:07:00 PM PDT 24
Peak memory 200316 kb
Host smart-341388f6-2348-4454-ac46-8cb56df26eb8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52779556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.52779556
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.4031634604
Short name T811
Test name
Test status
Simulation time 140067921985 ps
CPU time 677.18 seconds
Started Jul 28 07:06:58 PM PDT 24
Finished Jul 28 07:18:16 PM PDT 24
Peak memory 200184 kb
Host smart-7a92f1ae-8cea-4499-99d9-de937a51ac2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031634604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.4031634604
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.3840687379
Short name T530
Test name
Test status
Simulation time 5084260773 ps
CPU time 3.18 seconds
Started Jul 28 07:06:53 PM PDT 24
Finished Jul 28 07:06:56 PM PDT 24
Peak memory 199856 kb
Host smart-7ef0189c-3bbe-459d-9819-a1c8f71693b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840687379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.3840687379
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2747668642
Short name T281
Test name
Test status
Simulation time 87599282792 ps
CPU time 72.53 seconds
Started Jul 28 07:06:53 PM PDT 24
Finished Jul 28 07:08:05 PM PDT 24
Peak memory 199948 kb
Host smart-cd28b5d4-4122-42db-8d94-3d9d8c831872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747668642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2747668642
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3361218190
Short name T861
Test name
Test status
Simulation time 10858957952 ps
CPU time 379.26 seconds
Started Jul 28 07:06:55 PM PDT 24
Finished Jul 28 07:13:15 PM PDT 24
Peak memory 200308 kb
Host smart-4280279c-032c-4e20-becf-30ee0f81f23f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361218190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3361218190
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2768522381
Short name T501
Test name
Test status
Simulation time 1581675651 ps
CPU time 8.99 seconds
Started Jul 28 07:06:52 PM PDT 24
Finished Jul 28 07:07:01 PM PDT 24
Peak memory 198204 kb
Host smart-fabf5978-183e-43ef-b33c-33e82815afa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2768522381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2768522381
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2764823943
Short name T351
Test name
Test status
Simulation time 24141571518 ps
CPU time 36.95 seconds
Started Jul 28 07:06:55 PM PDT 24
Finished Jul 28 07:07:32 PM PDT 24
Peak memory 200376 kb
Host smart-0c8ca5a2-85e7-460b-aea7-df0ed0ab1fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764823943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2764823943
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.655727292
Short name T26
Test name
Test status
Simulation time 2635315506 ps
CPU time 1.77 seconds
Started Jul 28 07:06:52 PM PDT 24
Finished Jul 28 07:06:54 PM PDT 24
Peak memory 196736 kb
Host smart-12772ba4-2d50-40db-a98e-d46dc336e6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655727292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.655727292
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.933699130
Short name T844
Test name
Test status
Simulation time 5914094862 ps
CPU time 25.13 seconds
Started Jul 28 07:06:48 PM PDT 24
Finished Jul 28 07:07:13 PM PDT 24
Peak memory 199360 kb
Host smart-24763d3f-56d7-48fd-b036-b45296176781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933699130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.933699130
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2224203710
Short name T125
Test name
Test status
Simulation time 24679496594 ps
CPU time 245.37 seconds
Started Jul 28 07:06:55 PM PDT 24
Finished Jul 28 07:11:01 PM PDT 24
Peak memory 212216 kb
Host smart-a6cfa380-4593-43a4-b7cb-e0a9d4a4244e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224203710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2224203710
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2830463309
Short name T337
Test name
Test status
Simulation time 1167856486 ps
CPU time 2.17 seconds
Started Jul 28 07:06:53 PM PDT 24
Finished Jul 28 07:06:55 PM PDT 24
Peak memory 199288 kb
Host smart-0478b1c1-ab50-4463-bfb9-02f19bef9652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830463309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2830463309
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1863069147
Short name T1179
Test name
Test status
Simulation time 35777611770 ps
CPU time 47.69 seconds
Started Jul 28 07:06:52 PM PDT 24
Finished Jul 28 07:07:40 PM PDT 24
Peak memory 200292 kb
Host smart-f2f2901a-0b2f-491b-ad2a-4d1ff6724ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863069147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1863069147
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2581811127
Short name T1172
Test name
Test status
Simulation time 143515439671 ps
CPU time 174.85 seconds
Started Jul 28 07:12:50 PM PDT 24
Finished Jul 28 07:15:45 PM PDT 24
Peak memory 200228 kb
Host smart-652abeb8-ef5d-444c-9698-c97183834f4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581811127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2581811127
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2600830474
Short name T292
Test name
Test status
Simulation time 110728013336 ps
CPU time 404.61 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:19:37 PM PDT 24
Peak memory 200184 kb
Host smart-f0c6c8bd-0347-4c00-a194-e4373b438a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600830474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2600830474
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.2373579070
Short name T756
Test name
Test status
Simulation time 45082232692 ps
CPU time 32.92 seconds
Started Jul 28 07:12:50 PM PDT 24
Finished Jul 28 07:13:23 PM PDT 24
Peak memory 199804 kb
Host smart-c4af60bd-925a-4f21-8894-fd1dcce48b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373579070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.2373579070
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.1543576046
Short name T572
Test name
Test status
Simulation time 95545960893 ps
CPU time 145.43 seconds
Started Jul 28 07:12:49 PM PDT 24
Finished Jul 28 07:15:14 PM PDT 24
Peak memory 199996 kb
Host smart-b44c0291-a82d-414c-b5b2-6cbfd146f450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543576046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.1543576046
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.2757180685
Short name T723
Test name
Test status
Simulation time 208598840800 ps
CPU time 17.66 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:13:10 PM PDT 24
Peak memory 200080 kb
Host smart-f207ccab-60de-4982-ade9-0519e7723e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757180685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.2757180685
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3921201560
Short name T887
Test name
Test status
Simulation time 321627356825 ps
CPU time 35.88 seconds
Started Jul 28 07:12:51 PM PDT 24
Finished Jul 28 07:13:27 PM PDT 24
Peak memory 199724 kb
Host smart-66c08532-21e6-4ea5-bbfe-abeec36f2f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921201560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3921201560
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.1884433178
Short name T922
Test name
Test status
Simulation time 15420626727 ps
CPU time 22.83 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:13:15 PM PDT 24
Peak memory 199940 kb
Host smart-655eef48-9163-498d-8a25-86d19354f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884433178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1884433178
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.171344785
Short name T1077
Test name
Test status
Simulation time 29137082752 ps
CPU time 34.36 seconds
Started Jul 28 07:12:50 PM PDT 24
Finished Jul 28 07:13:24 PM PDT 24
Peak memory 200188 kb
Host smart-b7eb7e91-5726-45e5-985a-ff0fd29609b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171344785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.171344785
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2924233496
Short name T42
Test name
Test status
Simulation time 9307663911 ps
CPU time 14.3 seconds
Started Jul 28 07:12:51 PM PDT 24
Finished Jul 28 07:13:05 PM PDT 24
Peak memory 200160 kb
Host smart-b0bd89e3-1430-45ae-8cb5-d5a27d79f13d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924233496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2924233496
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2954299894
Short name T665
Test name
Test status
Simulation time 43396890 ps
CPU time 0.59 seconds
Started Jul 28 07:07:02 PM PDT 24
Finished Jul 28 07:07:03 PM PDT 24
Peak memory 194836 kb
Host smart-057da4aa-ee53-4b4e-aad8-9ce4d92526b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954299894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2954299894
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.830980315
Short name T520
Test name
Test status
Simulation time 36616295037 ps
CPU time 14.14 seconds
Started Jul 28 07:06:57 PM PDT 24
Finished Jul 28 07:07:11 PM PDT 24
Peak memory 200300 kb
Host smart-f7e410e7-7cac-443b-ab7f-4e0ab402fe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830980315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.830980315
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.834627990
Short name T999
Test name
Test status
Simulation time 97266701298 ps
CPU time 63.72 seconds
Started Jul 28 07:06:56 PM PDT 24
Finished Jul 28 07:08:00 PM PDT 24
Peak memory 199728 kb
Host smart-087b31d6-72bc-4ef4-9db3-d56ec2e8dafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834627990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.834627990
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.957102704
Short name T1041
Test name
Test status
Simulation time 26676293088 ps
CPU time 32.8 seconds
Started Jul 28 07:06:57 PM PDT 24
Finished Jul 28 07:07:30 PM PDT 24
Peak memory 199164 kb
Host smart-b217df55-97f1-49cc-b285-bd4cc59f4453
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957102704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.957102704
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1079121345
Short name T1144
Test name
Test status
Simulation time 268932497837 ps
CPU time 370.03 seconds
Started Jul 28 07:07:04 PM PDT 24
Finished Jul 28 07:13:14 PM PDT 24
Peak memory 200136 kb
Host smart-d4bdcdaf-b989-498f-a172-fb8e9060247a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1079121345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1079121345
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2087072238
Short name T369
Test name
Test status
Simulation time 11060552192 ps
CPU time 19.79 seconds
Started Jul 28 07:07:03 PM PDT 24
Finished Jul 28 07:07:23 PM PDT 24
Peak memory 199908 kb
Host smart-43f2f920-5fd4-4ebd-ab06-072571c7da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087072238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2087072238
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1370706504
Short name T374
Test name
Test status
Simulation time 131660721956 ps
CPU time 53.3 seconds
Started Jul 28 07:06:57 PM PDT 24
Finished Jul 28 07:07:50 PM PDT 24
Peak memory 200252 kb
Host smart-9b4fd7db-c60b-4f50-a174-4db42978e8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370706504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1370706504
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1656332581
Short name T489
Test name
Test status
Simulation time 6926250231 ps
CPU time 392.62 seconds
Started Jul 28 07:07:04 PM PDT 24
Finished Jul 28 07:13:37 PM PDT 24
Peak memory 200160 kb
Host smart-97c80b53-f1c7-4309-89e6-f1a8c03e8c7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656332581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1656332581
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1029931563
Short name T456
Test name
Test status
Simulation time 1946725766 ps
CPU time 1.93 seconds
Started Jul 28 07:07:00 PM PDT 24
Finished Jul 28 07:07:02 PM PDT 24
Peak memory 198156 kb
Host smart-5a839780-8e0e-4d55-861a-4443573ab7db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1029931563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1029931563
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3448095335
Short name T1042
Test name
Test status
Simulation time 202442729335 ps
CPU time 325.16 seconds
Started Jul 28 07:06:56 PM PDT 24
Finished Jul 28 07:12:22 PM PDT 24
Peak memory 200132 kb
Host smart-7f5c8ca8-874f-4d04-b2f1-4cfadba0fbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448095335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3448095335
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.286638568
Short name T434
Test name
Test status
Simulation time 3811835237 ps
CPU time 6.33 seconds
Started Jul 28 07:06:57 PM PDT 24
Finished Jul 28 07:07:03 PM PDT 24
Peak memory 197012 kb
Host smart-fd763657-3e75-4b04-bd35-244367470714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286638568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.286638568
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3497979003
Short name T732
Test name
Test status
Simulation time 561849822 ps
CPU time 1.7 seconds
Started Jul 28 07:06:56 PM PDT 24
Finished Jul 28 07:06:58 PM PDT 24
Peak memory 198740 kb
Host smart-6bb16bcb-ed7b-4e3a-9d3a-c6f70f9a440c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497979003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3497979003
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2721193618
Short name T1083
Test name
Test status
Simulation time 302059844405 ps
CPU time 472.58 seconds
Started Jul 28 07:07:02 PM PDT 24
Finished Jul 28 07:14:55 PM PDT 24
Peak memory 208840 kb
Host smart-0745c240-f842-4747-bfe3-afa36088c6bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721193618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2721193618
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.151969952
Short name T1091
Test name
Test status
Simulation time 1843478286 ps
CPU time 2.27 seconds
Started Jul 28 07:07:02 PM PDT 24
Finished Jul 28 07:07:04 PM PDT 24
Peak memory 199860 kb
Host smart-eb40bb69-0c61-432a-8213-56834a23f9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151969952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.151969952
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2780873907
Short name T495
Test name
Test status
Simulation time 11393894035 ps
CPU time 21.15 seconds
Started Jul 28 07:06:58 PM PDT 24
Finished Jul 28 07:07:20 PM PDT 24
Peak memory 200204 kb
Host smart-50568ee5-1527-4357-ab67-83ad31420241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780873907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2780873907
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3048778796
Short name T1011
Test name
Test status
Simulation time 130235907682 ps
CPU time 71.83 seconds
Started Jul 28 07:12:48 PM PDT 24
Finished Jul 28 07:14:00 PM PDT 24
Peak memory 200108 kb
Host smart-df247d18-ffa6-4eb3-97e0-c24de275e68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048778796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3048778796
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1625912839
Short name T584
Test name
Test status
Simulation time 109063328176 ps
CPU time 139.15 seconds
Started Jul 28 07:12:49 PM PDT 24
Finished Jul 28 07:15:09 PM PDT 24
Peak memory 200188 kb
Host smart-56b06a07-e81e-4eef-9502-04391142463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625912839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1625912839
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.615789909
Short name T713
Test name
Test status
Simulation time 268619325710 ps
CPU time 49.2 seconds
Started Jul 28 07:12:52 PM PDT 24
Finished Jul 28 07:13:41 PM PDT 24
Peak memory 200108 kb
Host smart-5dec98bd-5532-40b5-86ec-96f2be94d66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615789909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.615789909
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.3662050315
Short name T57
Test name
Test status
Simulation time 55419687809 ps
CPU time 34.8 seconds
Started Jul 28 07:12:53 PM PDT 24
Finished Jul 28 07:13:28 PM PDT 24
Peak memory 200184 kb
Host smart-f47ced76-dae4-4f59-8ea2-e1f1f6e4c5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662050315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.3662050315
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3786596649
Short name T892
Test name
Test status
Simulation time 165910058845 ps
CPU time 217.45 seconds
Started Jul 28 07:12:59 PM PDT 24
Finished Jul 28 07:16:37 PM PDT 24
Peak memory 200136 kb
Host smart-51316c69-1c0a-4cf7-9329-3f05910872ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786596649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3786596649
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2641830176
Short name T1094
Test name
Test status
Simulation time 68091303577 ps
CPU time 25.75 seconds
Started Jul 28 07:12:55 PM PDT 24
Finished Jul 28 07:13:21 PM PDT 24
Peak memory 200176 kb
Host smart-32559f59-ab9c-4678-bc06-44cdc4737053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641830176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2641830176
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2153220547
Short name T225
Test name
Test status
Simulation time 64969944908 ps
CPU time 26 seconds
Started Jul 28 07:12:55 PM PDT 24
Finished Jul 28 07:13:21 PM PDT 24
Peak memory 200180 kb
Host smart-086bad4d-0146-4a9d-8509-ac890fd65b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153220547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2153220547
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2338050849
Short name T1088
Test name
Test status
Simulation time 25402434063 ps
CPU time 37.13 seconds
Started Jul 28 07:12:57 PM PDT 24
Finished Jul 28 07:13:34 PM PDT 24
Peak memory 200108 kb
Host smart-7d1bef3e-5326-4807-84e8-5fb1ec8e3fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338050849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2338050849
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.623823614
Short name T993
Test name
Test status
Simulation time 35687303154 ps
CPU time 26.33 seconds
Started Jul 28 07:13:00 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 200136 kb
Host smart-1e260fde-930f-4aaa-ba0e-3ced780120fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623823614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.623823614
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2885728215
Short name T799
Test name
Test status
Simulation time 56872849 ps
CPU time 0.55 seconds
Started Jul 28 07:07:15 PM PDT 24
Finished Jul 28 07:07:16 PM PDT 24
Peak memory 194576 kb
Host smart-c60708db-16ad-4ccb-a49b-00ee5ed9619e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885728215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2885728215
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.3228677504
Short name T141
Test name
Test status
Simulation time 47348923129 ps
CPU time 74.68 seconds
Started Jul 28 07:07:09 PM PDT 24
Finished Jul 28 07:08:23 PM PDT 24
Peak memory 200176 kb
Host smart-66950c42-c554-4a48-b5fe-49a55577ec43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228677504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.3228677504
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.531414767
Short name T755
Test name
Test status
Simulation time 4600019272 ps
CPU time 9.03 seconds
Started Jul 28 07:07:08 PM PDT 24
Finished Jul 28 07:07:17 PM PDT 24
Peak memory 200188 kb
Host smart-036e3c6e-6ff8-49d8-bf28-ba66294c7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531414767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.531414767
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.98967819
Short name T187
Test name
Test status
Simulation time 114946756453 ps
CPU time 180.26 seconds
Started Jul 28 07:07:09 PM PDT 24
Finished Jul 28 07:10:09 PM PDT 24
Peak memory 200092 kb
Host smart-83588dd6-1dbb-4b4b-bd23-7b56983029a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98967819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.98967819
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.1653931302
Short name T742
Test name
Test status
Simulation time 3140027217 ps
CPU time 5.56 seconds
Started Jul 28 07:07:08 PM PDT 24
Finished Jul 28 07:07:14 PM PDT 24
Peak memory 197032 kb
Host smart-9fcbb5e6-2b0a-44a8-a1e9-122e64a6ff81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653931302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.1653931302
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1924965365
Short name T1085
Test name
Test status
Simulation time 112065506537 ps
CPU time 1070.4 seconds
Started Jul 28 07:07:10 PM PDT 24
Finished Jul 28 07:25:01 PM PDT 24
Peak memory 200224 kb
Host smart-1f5b361c-383f-4523-ac36-d4980c0d02ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1924965365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1924965365
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.189816132
Short name T793
Test name
Test status
Simulation time 5105180401 ps
CPU time 5.8 seconds
Started Jul 28 07:07:13 PM PDT 24
Finished Jul 28 07:07:19 PM PDT 24
Peak memory 199032 kb
Host smart-3a51ae47-0e4c-4954-92cd-3bc17c610839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189816132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.189816132
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3748709606
Short name T911
Test name
Test status
Simulation time 351082451902 ps
CPU time 127.93 seconds
Started Jul 28 07:07:07 PM PDT 24
Finished Jul 28 07:09:15 PM PDT 24
Peak memory 200496 kb
Host smart-d650f980-f320-4f4e-bc7c-6fe9febf70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748709606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3748709606
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.2177409042
Short name T872
Test name
Test status
Simulation time 21482328944 ps
CPU time 195.01 seconds
Started Jul 28 07:07:13 PM PDT 24
Finished Jul 28 07:10:28 PM PDT 24
Peak memory 200124 kb
Host smart-78733236-2ea7-431a-a5ac-59fbddc25942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2177409042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2177409042
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3007260141
Short name T733
Test name
Test status
Simulation time 1385576508 ps
CPU time 5.46 seconds
Started Jul 28 07:07:09 PM PDT 24
Finished Jul 28 07:07:15 PM PDT 24
Peak memory 198736 kb
Host smart-387506c3-4a3b-4cdb-b0a4-8b1db0e3b6fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3007260141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3007260141
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1888355967
Short name T1159
Test name
Test status
Simulation time 24545022998 ps
CPU time 41.09 seconds
Started Jul 28 07:07:10 PM PDT 24
Finished Jul 28 07:07:51 PM PDT 24
Peak memory 200080 kb
Host smart-8a3720c8-ba37-4cdd-a634-febe83ac0aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888355967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1888355967
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.4265163951
Short name T370
Test name
Test status
Simulation time 741165106 ps
CPU time 1.69 seconds
Started Jul 28 07:07:13 PM PDT 24
Finished Jul 28 07:07:15 PM PDT 24
Peak memory 195524 kb
Host smart-7de323b9-905f-446a-a7dc-02fa38d5f1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265163951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.4265163951
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3010063391
Short name T1076
Test name
Test status
Simulation time 5904972904 ps
CPU time 7.87 seconds
Started Jul 28 07:07:09 PM PDT 24
Finished Jul 28 07:07:17 PM PDT 24
Peak memory 200184 kb
Host smart-78f8cd4e-8d7f-4948-bab9-070b3d9a89e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010063391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3010063391
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.194456801
Short name T579
Test name
Test status
Simulation time 269865160328 ps
CPU time 612.18 seconds
Started Jul 28 07:07:06 PM PDT 24
Finished Jul 28 07:17:19 PM PDT 24
Peak memory 208504 kb
Host smart-139ca89c-51ca-46f6-9914-f43459bb8d99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194456801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.194456801
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3265557893
Short name T606
Test name
Test status
Simulation time 105525510140 ps
CPU time 1173.77 seconds
Started Jul 28 07:07:09 PM PDT 24
Finished Jul 28 07:26:43 PM PDT 24
Peak memory 233200 kb
Host smart-d4fbb6d9-6619-43e4-99d8-3c4b20199881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265557893 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3265557893
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3761970166
Short name T899
Test name
Test status
Simulation time 1754561736 ps
CPU time 1.8 seconds
Started Jul 28 07:07:15 PM PDT 24
Finished Jul 28 07:07:17 PM PDT 24
Peak memory 198496 kb
Host smart-ad1b2ead-d6fa-4398-a56e-f5535349d111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761970166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3761970166
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3287289309
Short name T893
Test name
Test status
Simulation time 130951511678 ps
CPU time 60.67 seconds
Started Jul 28 07:07:08 PM PDT 24
Finished Jul 28 07:08:09 PM PDT 24
Peak memory 200176 kb
Host smart-77cb373d-8f61-4443-966d-957b3b76aaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287289309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3287289309
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1233593449
Short name T721
Test name
Test status
Simulation time 125691394846 ps
CPU time 90.88 seconds
Started Jul 28 07:12:59 PM PDT 24
Finished Jul 28 07:14:30 PM PDT 24
Peak memory 200176 kb
Host smart-29644753-f6f8-457d-872b-158b1cfce911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233593449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1233593449
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.759358662
Short name T716
Test name
Test status
Simulation time 36767904677 ps
CPU time 18.02 seconds
Started Jul 28 07:13:02 PM PDT 24
Finished Jul 28 07:13:20 PM PDT 24
Peak memory 200096 kb
Host smart-ff5ca1a1-303b-4fd2-8cf6-bad6d15eb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759358662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.759358662
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.707435967
Short name T858
Test name
Test status
Simulation time 95132156931 ps
CPU time 147.74 seconds
Started Jul 28 07:13:00 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 200160 kb
Host smart-b206dd96-5f45-4ad5-a569-51ed3aa5cd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707435967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.707435967
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.3368313976
Short name T656
Test name
Test status
Simulation time 120169198510 ps
CPU time 46.98 seconds
Started Jul 28 07:13:04 PM PDT 24
Finished Jul 28 07:13:51 PM PDT 24
Peak memory 200188 kb
Host smart-3de3034d-3817-4dd6-ac0f-85792d779386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368313976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.3368313976
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3406484338
Short name T595
Test name
Test status
Simulation time 15148662012 ps
CPU time 16.33 seconds
Started Jul 28 07:13:02 PM PDT 24
Finished Jul 28 07:13:19 PM PDT 24
Peak memory 200148 kb
Host smart-d70e03a0-fb8f-48b1-b0b8-efc8a0410b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406484338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3406484338
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3252050193
Short name T263
Test name
Test status
Simulation time 29388883727 ps
CPU time 12.94 seconds
Started Jul 28 07:13:04 PM PDT 24
Finished Jul 28 07:13:17 PM PDT 24
Peak memory 200204 kb
Host smart-cf5085fd-7986-413b-bab1-30071bc68564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252050193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3252050193
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1819143618
Short name T1020
Test name
Test status
Simulation time 131468473122 ps
CPU time 49.25 seconds
Started Jul 28 07:13:01 PM PDT 24
Finished Jul 28 07:13:50 PM PDT 24
Peak memory 200160 kb
Host smart-1187991e-4768-4905-84ab-eb894213e0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819143618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1819143618
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1398078426
Short name T1125
Test name
Test status
Simulation time 40837623781 ps
CPU time 16.67 seconds
Started Jul 28 07:13:00 PM PDT 24
Finished Jul 28 07:13:17 PM PDT 24
Peak memory 200100 kb
Host smart-c111c375-b8d5-41d6-ae5d-d823935dac1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398078426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1398078426
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3560006580
Short name T1025
Test name
Test status
Simulation time 30446016975 ps
CPU time 11.66 seconds
Started Jul 28 07:13:02 PM PDT 24
Finished Jul 28 07:13:14 PM PDT 24
Peak memory 199908 kb
Host smart-dda93f01-90d0-4a16-b675-ccced75fb77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560006580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3560006580
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3941127413
Short name T29
Test name
Test status
Simulation time 14575351 ps
CPU time 0.58 seconds
Started Jul 28 07:07:25 PM PDT 24
Finished Jul 28 07:07:26 PM PDT 24
Peak memory 195604 kb
Host smart-94186b8e-1691-4712-b8fd-445d8fc404b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941127413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3941127413
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1871658194
Short name T439
Test name
Test status
Simulation time 25785805015 ps
CPU time 39.39 seconds
Started Jul 28 07:07:12 PM PDT 24
Finished Jul 28 07:07:52 PM PDT 24
Peak memory 200200 kb
Host smart-5b7e8891-bbb4-4ed2-87ab-7f9f9614f200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871658194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1871658194
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2558138562
Short name T423
Test name
Test status
Simulation time 91797546868 ps
CPU time 41.3 seconds
Started Jul 28 07:07:18 PM PDT 24
Finished Jul 28 07:07:59 PM PDT 24
Peak memory 200104 kb
Host smart-3eb78eaf-a9b3-452d-892a-146909fb91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558138562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2558138562
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3534727167
Short name T44
Test name
Test status
Simulation time 60232743006 ps
CPU time 142.5 seconds
Started Jul 28 07:07:12 PM PDT 24
Finished Jul 28 07:09:34 PM PDT 24
Peak memory 200136 kb
Host smart-d471e308-edd1-4b03-b509-1ece13bf8837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534727167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3534727167
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1176427589
Short name T678
Test name
Test status
Simulation time 30785271494 ps
CPU time 37.47 seconds
Started Jul 28 07:07:18 PM PDT 24
Finished Jul 28 07:07:56 PM PDT 24
Peak memory 200188 kb
Host smart-22c8ad8d-196f-435d-acc4-6a644fd4f5ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176427589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1176427589
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1644616979
Short name T253
Test name
Test status
Simulation time 166990114759 ps
CPU time 1318.6 seconds
Started Jul 28 07:07:24 PM PDT 24
Finished Jul 28 07:29:23 PM PDT 24
Peak memory 200180 kb
Host smart-74692077-c8bf-4285-af88-2240444f9352
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1644616979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1644616979
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3424167229
Short name T819
Test name
Test status
Simulation time 5496100421 ps
CPU time 22.48 seconds
Started Jul 28 07:07:21 PM PDT 24
Finished Jul 28 07:07:44 PM PDT 24
Peak memory 200024 kb
Host smart-57e2704f-795d-4041-b94c-17d89565d4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424167229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3424167229
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1386965539
Short name T1010
Test name
Test status
Simulation time 114430568054 ps
CPU time 211.89 seconds
Started Jul 28 07:07:19 PM PDT 24
Finished Jul 28 07:10:51 PM PDT 24
Peak memory 200288 kb
Host smart-6719fffb-b1a9-4dca-ac83-23b7e42d1275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386965539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1386965539
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.3074317945
Short name T1157
Test name
Test status
Simulation time 20063721079 ps
CPU time 971.75 seconds
Started Jul 28 07:07:18 PM PDT 24
Finished Jul 28 07:23:29 PM PDT 24
Peak memory 200128 kb
Host smart-260e2b11-1f68-4f17-b920-a8f20b04147f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074317945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3074317945
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1187684730
Short name T931
Test name
Test status
Simulation time 5170786487 ps
CPU time 43.46 seconds
Started Jul 28 07:07:19 PM PDT 24
Finished Jul 28 07:08:02 PM PDT 24
Peak memory 198396 kb
Host smart-630357cc-680b-4493-acd8-4581f206abb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1187684730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1187684730
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1550934184
Short name T547
Test name
Test status
Simulation time 113126236394 ps
CPU time 20.35 seconds
Started Jul 28 07:07:18 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200168 kb
Host smart-788df5af-0990-4334-98b0-ada602af2336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550934184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1550934184
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.140865196
Short name T465
Test name
Test status
Simulation time 72792736865 ps
CPU time 111.22 seconds
Started Jul 28 07:07:21 PM PDT 24
Finished Jul 28 07:09:12 PM PDT 24
Peak memory 197060 kb
Host smart-f76570be-638a-485c-bd17-c1995283c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140865196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.140865196
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.565785073
Short name T916
Test name
Test status
Simulation time 121971360 ps
CPU time 1 seconds
Started Jul 28 07:07:16 PM PDT 24
Finished Jul 28 07:07:17 PM PDT 24
Peak memory 197432 kb
Host smart-fda23554-1b0d-4123-ad48-80e80a3e2364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565785073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.565785073
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.3402636537
Short name T818
Test name
Test status
Simulation time 363947603159 ps
CPU time 340.49 seconds
Started Jul 28 07:07:24 PM PDT 24
Finished Jul 28 07:13:05 PM PDT 24
Peak memory 216140 kb
Host smart-835b2c79-f452-420d-b887-fc28ec91ec91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402636537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.3402636537
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3332430911
Short name T854
Test name
Test status
Simulation time 64421017799 ps
CPU time 549.04 seconds
Started Jul 28 07:07:25 PM PDT 24
Finished Jul 28 07:16:34 PM PDT 24
Peak memory 216000 kb
Host smart-c5283c00-7b47-4c02-a053-080db8ada700
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332430911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3332430911
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4287512565
Short name T427
Test name
Test status
Simulation time 859201763 ps
CPU time 2.52 seconds
Started Jul 28 07:07:17 PM PDT 24
Finished Jul 28 07:07:20 PM PDT 24
Peak memory 199072 kb
Host smart-83f666f1-a463-45f2-9e0c-c2c0b104a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287512565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4287512565
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.3548927465
Short name T674
Test name
Test status
Simulation time 63205661807 ps
CPU time 23.66 seconds
Started Jul 28 07:07:17 PM PDT 24
Finished Jul 28 07:07:41 PM PDT 24
Peak memory 200196 kb
Host smart-6f794384-66d8-4614-baa1-6062429ba832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548927465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3548927465
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.18925693
Short name T1119
Test name
Test status
Simulation time 14292171574 ps
CPU time 23.06 seconds
Started Jul 28 07:13:01 PM PDT 24
Finished Jul 28 07:13:24 PM PDT 24
Peak memory 200176 kb
Host smart-592ba05f-6c0d-483e-83b7-b79741236474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18925693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.18925693
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2053604016
Short name T1107
Test name
Test status
Simulation time 18747029426 ps
CPU time 31.6 seconds
Started Jul 28 07:13:02 PM PDT 24
Finished Jul 28 07:13:34 PM PDT 24
Peak memory 200208 kb
Host smart-7dda8af4-b371-4e2d-927e-a587c678f07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053604016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2053604016
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.2172523876
Short name T647
Test name
Test status
Simulation time 87494793982 ps
CPU time 320.35 seconds
Started Jul 28 07:13:02 PM PDT 24
Finished Jul 28 07:18:23 PM PDT 24
Peak memory 200100 kb
Host smart-c5bff77d-8423-4ea3-8f80-3b00f9a6ccd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172523876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2172523876
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2202646370
Short name T84
Test name
Test status
Simulation time 179138000693 ps
CPU time 64.9 seconds
Started Jul 28 07:13:00 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 200100 kb
Host smart-b0156653-e691-4347-af08-8ea351efa5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202646370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2202646370
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1978947876
Short name T598
Test name
Test status
Simulation time 11871908479 ps
CPU time 18.72 seconds
Started Jul 28 07:13:07 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 199988 kb
Host smart-58da3326-289c-46da-9f98-0fd05e44b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978947876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1978947876
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.480810452
Short name T1168
Test name
Test status
Simulation time 75444691218 ps
CPU time 120.82 seconds
Started Jul 28 07:13:05 PM PDT 24
Finished Jul 28 07:15:06 PM PDT 24
Peak memory 200316 kb
Host smart-bf84fc8e-c35d-4e29-a7f8-53254ec264c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480810452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.480810452
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3291482036
Short name T450
Test name
Test status
Simulation time 24801682984 ps
CPU time 38.07 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:13:53 PM PDT 24
Peak memory 200200 kb
Host smart-a556c2b8-03be-4e36-aa9f-c15c48b7d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291482036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3291482036
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1337268020
Short name T192
Test name
Test status
Simulation time 140927218841 ps
CPU time 50.61 seconds
Started Jul 28 07:13:09 PM PDT 24
Finished Jul 28 07:14:00 PM PDT 24
Peak memory 200164 kb
Host smart-7cf89bda-d77a-4328-a01d-5f78bacbe7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337268020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1337268020
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2202273754
Short name T1046
Test name
Test status
Simulation time 118401589656 ps
CPU time 42.55 seconds
Started Jul 28 07:13:07 PM PDT 24
Finished Jul 28 07:13:49 PM PDT 24
Peak memory 200216 kb
Host smart-0036c20f-d3d9-43f2-bef2-abd15e0b1a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202273754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2202273754
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2347692937
Short name T618
Test name
Test status
Simulation time 20039000 ps
CPU time 0.54 seconds
Started Jul 28 07:07:33 PM PDT 24
Finished Jul 28 07:07:34 PM PDT 24
Peak memory 195012 kb
Host smart-48ac8497-f173-4d5c-a461-005114bfacee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347692937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2347692937
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.904198129
Short name T770
Test name
Test status
Simulation time 78995978829 ps
CPU time 26.99 seconds
Started Jul 28 07:07:23 PM PDT 24
Finished Jul 28 07:07:50 PM PDT 24
Peak memory 200004 kb
Host smart-f98e75fd-a48c-4c9f-afbf-dedd5b217805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904198129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.904198129
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.20677604
Short name T789
Test name
Test status
Simulation time 154540244485 ps
CPU time 58.57 seconds
Started Jul 28 07:07:22 PM PDT 24
Finished Jul 28 07:08:21 PM PDT 24
Peak memory 200088 kb
Host smart-7225d4cd-febe-4e32-9612-238c7af05f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20677604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.20677604
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.2427083667
Short name T634
Test name
Test status
Simulation time 17186866558 ps
CPU time 37.27 seconds
Started Jul 28 07:07:24 PM PDT 24
Finished Jul 28 07:08:02 PM PDT 24
Peak memory 200140 kb
Host smart-62f557f0-c6dc-4381-9e14-40ed002c208e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427083667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.2427083667
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.1091855350
Short name T798
Test name
Test status
Simulation time 37060473346 ps
CPU time 8.69 seconds
Started Jul 28 07:07:30 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200020 kb
Host smart-955001c8-73e6-45f3-8bec-4bab0971d53d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091855350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1091855350
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2717086904
Short name T769
Test name
Test status
Simulation time 99903513175 ps
CPU time 238.7 seconds
Started Jul 28 07:07:28 PM PDT 24
Finished Jul 28 07:11:27 PM PDT 24
Peak memory 200104 kb
Host smart-29eaa592-c607-43b3-b218-0b80b670f515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717086904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2717086904
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1262411016
Short name T672
Test name
Test status
Simulation time 5879472864 ps
CPU time 11.08 seconds
Started Jul 28 07:07:28 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200132 kb
Host smart-f65d15fa-3281-4166-9804-52222dee8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262411016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1262411016
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1606167165
Short name T1141
Test name
Test status
Simulation time 112327962602 ps
CPU time 57.96 seconds
Started Jul 28 07:07:29 PM PDT 24
Finished Jul 28 07:08:27 PM PDT 24
Peak memory 208520 kb
Host smart-9acd4bd1-c7a1-4614-9d22-75a169cc50c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606167165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1606167165
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3072896212
Short name T862
Test name
Test status
Simulation time 4200344680 ps
CPU time 173.23 seconds
Started Jul 28 07:07:30 PM PDT 24
Finished Jul 28 07:10:24 PM PDT 24
Peak memory 200116 kb
Host smart-7f6a59d6-cb82-41f1-9952-3f9127b9dd39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3072896212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3072896212
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1351209349
Short name T510
Test name
Test status
Simulation time 4406223311 ps
CPU time 36.19 seconds
Started Jul 28 07:07:26 PM PDT 24
Finished Jul 28 07:08:03 PM PDT 24
Peak memory 198592 kb
Host smart-7536499e-dcc8-4917-8a9b-8fbdb8f6151e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1351209349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1351209349
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.1941010823
Short name T932
Test name
Test status
Simulation time 11606055847 ps
CPU time 9.92 seconds
Started Jul 28 07:07:30 PM PDT 24
Finished Jul 28 07:07:40 PM PDT 24
Peak memory 200024 kb
Host smart-3c3c0b28-031c-46d9-8782-dd4807b4705a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941010823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.1941010823
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2630056549
Short name T569
Test name
Test status
Simulation time 5495108615 ps
CPU time 2.94 seconds
Started Jul 28 07:07:28 PM PDT 24
Finished Jul 28 07:07:31 PM PDT 24
Peak memory 196708 kb
Host smart-0a14650a-6d59-4032-b295-0d2fb25bf74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630056549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2630056549
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3247580316
Short name T1150
Test name
Test status
Simulation time 121607558 ps
CPU time 1.05 seconds
Started Jul 28 07:07:24 PM PDT 24
Finished Jul 28 07:07:25 PM PDT 24
Peak memory 198456 kb
Host smart-5e40b463-a566-401a-afef-248c0835265e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247580316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3247580316
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.1632591710
Short name T822
Test name
Test status
Simulation time 99012650363 ps
CPU time 69.93 seconds
Started Jul 28 07:07:35 PM PDT 24
Finished Jul 28 07:08:45 PM PDT 24
Peak memory 200064 kb
Host smart-82c79d02-600f-4827-a250-23d57147c047
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632591710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.1632591710
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.2448967201
Short name T121
Test name
Test status
Simulation time 145446567009 ps
CPU time 436.2 seconds
Started Jul 28 07:07:30 PM PDT 24
Finished Jul 28 07:14:46 PM PDT 24
Peak memory 216600 kb
Host smart-2ff41761-c88d-48bd-bef6-35c127c474d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448967201 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.2448967201
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.523469441
Short name T643
Test name
Test status
Simulation time 6584997434 ps
CPU time 12.63 seconds
Started Jul 28 07:07:29 PM PDT 24
Finished Jul 28 07:07:42 PM PDT 24
Peak memory 200232 kb
Host smart-91eccfd9-14db-459a-a6a2-4ad0c49efd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523469441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.523469441
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3444584781
Short name T605
Test name
Test status
Simulation time 60634056721 ps
CPU time 37.08 seconds
Started Jul 28 07:07:25 PM PDT 24
Finished Jul 28 07:08:03 PM PDT 24
Peak memory 200120 kb
Host smart-071a8a15-83d4-4440-b071-3aa9e27264e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444584781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3444584781
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.3856307655
Short name T951
Test name
Test status
Simulation time 81806082776 ps
CPU time 18.36 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200200 kb
Host smart-8d58b173-5616-49d3-9fab-885b0dae29e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856307655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.3856307655
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3237782215
Short name T539
Test name
Test status
Simulation time 65474989477 ps
CPU time 28.32 seconds
Started Jul 28 07:13:07 PM PDT 24
Finished Jul 28 07:13:36 PM PDT 24
Peak memory 200188 kb
Host smart-bb05d197-6c12-4210-91ae-0e0841bd04d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237782215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3237782215
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.126592501
Short name T761
Test name
Test status
Simulation time 49189342640 ps
CPU time 20.64 seconds
Started Jul 28 07:13:09 PM PDT 24
Finished Jul 28 07:13:30 PM PDT 24
Peak memory 200116 kb
Host smart-a226397e-6d73-4562-9ad9-d7b9a960f589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126592501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.126592501
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3496480617
Short name T245
Test name
Test status
Simulation time 35344755084 ps
CPU time 30.93 seconds
Started Jul 28 07:13:14 PM PDT 24
Finished Jul 28 07:13:45 PM PDT 24
Peak memory 200192 kb
Host smart-6655f670-dd54-4187-a5fb-4e8357a3fb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496480617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3496480617
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3618399865
Short name T702
Test name
Test status
Simulation time 80491254696 ps
CPU time 134.32 seconds
Started Jul 28 07:13:08 PM PDT 24
Finished Jul 28 07:15:22 PM PDT 24
Peak memory 200140 kb
Host smart-03398250-c48b-4ccd-9134-8dfb886d266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618399865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3618399865
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2996182816
Short name T143
Test name
Test status
Simulation time 65941821740 ps
CPU time 68.77 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:14:24 PM PDT 24
Peak memory 200152 kb
Host smart-f1891f01-8c97-4188-a73f-c8bc9fa0b436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996182816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2996182816
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.2175398526
Short name T869
Test name
Test status
Simulation time 13564569178 ps
CPU time 18.29 seconds
Started Jul 28 07:13:16 PM PDT 24
Finished Jul 28 07:13:34 PM PDT 24
Peak memory 200068 kb
Host smart-3277bcaf-6bd2-440f-9b60-ef2b382e067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175398526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.2175398526
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2882414433
Short name T661
Test name
Test status
Simulation time 92102658449 ps
CPU time 59.03 seconds
Started Jul 28 07:13:11 PM PDT 24
Finished Jul 28 07:14:11 PM PDT 24
Peak memory 200220 kb
Host smart-5f74962f-f114-4e2d-8106-a30360e3f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882414433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2882414433
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1993967580
Short name T846
Test name
Test status
Simulation time 12519786 ps
CPU time 0.55 seconds
Started Jul 28 07:07:39 PM PDT 24
Finished Jul 28 07:07:40 PM PDT 24
Peak memory 194496 kb
Host smart-0dff29fb-f3a7-42ca-ac26-1a6ea27df263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993967580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1993967580
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1689281543
Short name T855
Test name
Test status
Simulation time 47094572174 ps
CPU time 69 seconds
Started Jul 28 07:07:34 PM PDT 24
Finished Jul 28 07:08:43 PM PDT 24
Peak memory 200128 kb
Host smart-3f4eb7db-20c4-4396-839b-90e0ce714df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689281543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1689281543
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.1527519187
Short name T676
Test name
Test status
Simulation time 35528124458 ps
CPU time 86.23 seconds
Started Jul 28 07:07:35 PM PDT 24
Finished Jul 28 07:09:01 PM PDT 24
Peak memory 200220 kb
Host smart-542acf65-2687-4680-96af-a7064adb086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527519187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.1527519187
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3254466270
Short name T631
Test name
Test status
Simulation time 90267115012 ps
CPU time 146.49 seconds
Started Jul 28 07:07:35 PM PDT 24
Finished Jul 28 07:10:02 PM PDT 24
Peak memory 200108 kb
Host smart-b8cb7d82-3c97-4afd-830b-f43026d1a4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254466270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3254466270
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3972637239
Short name T683
Test name
Test status
Simulation time 26295554955 ps
CPU time 13.86 seconds
Started Jul 28 07:07:33 PM PDT 24
Finished Jul 28 07:07:47 PM PDT 24
Peak memory 200044 kb
Host smart-1fe3aaa6-a06d-451f-b0a3-367e942b8c85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972637239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3972637239
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1072638100
Short name T669
Test name
Test status
Simulation time 71030237036 ps
CPU time 351.67 seconds
Started Jul 28 07:07:41 PM PDT 24
Finished Jul 28 07:13:32 PM PDT 24
Peak memory 200164 kb
Host smart-54deb991-0068-4c83-9882-e2533d266bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1072638100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1072638100
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.205387048
Short name T938
Test name
Test status
Simulation time 1483560830 ps
CPU time 1.39 seconds
Started Jul 28 07:07:37 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 197264 kb
Host smart-e1b4ca75-3f09-42ad-af74-81a67015bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205387048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.205387048
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1573399677
Short name T481
Test name
Test status
Simulation time 157076472300 ps
CPU time 136.79 seconds
Started Jul 28 07:07:39 PM PDT 24
Finished Jul 28 07:09:56 PM PDT 24
Peak memory 200228 kb
Host smart-708b2c0f-c912-437f-ba45-1c101dbd8a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573399677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1573399677
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.439489180
Short name T1043
Test name
Test status
Simulation time 16454190306 ps
CPU time 872.33 seconds
Started Jul 28 07:07:41 PM PDT 24
Finished Jul 28 07:22:13 PM PDT 24
Peak memory 200104 kb
Host smart-91631990-7f5a-4687-bc41-52e82995fe52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=439489180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.439489180
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2662184262
Short name T928
Test name
Test status
Simulation time 4601664370 ps
CPU time 17.84 seconds
Started Jul 28 07:07:32 PM PDT 24
Finished Jul 28 07:07:50 PM PDT 24
Peak memory 200384 kb
Host smart-4ce67da3-5d9c-4800-90ff-15a6abcd0511
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662184262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2662184262
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.580712452
Short name T1002
Test name
Test status
Simulation time 151216008747 ps
CPU time 121.53 seconds
Started Jul 28 07:07:41 PM PDT 24
Finished Jul 28 07:09:43 PM PDT 24
Peak memory 199760 kb
Host smart-cc2ad67d-25b8-4a45-87a4-704b4a632cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580712452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.580712452
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.2646866712
Short name T1155
Test name
Test status
Simulation time 4292517087 ps
CPU time 6.32 seconds
Started Jul 28 07:07:42 PM PDT 24
Finished Jul 28 07:07:48 PM PDT 24
Peak memory 196508 kb
Host smart-a2f39286-ef70-4a96-8c67-d6ed25d93bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646866712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.2646866712
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.564211904
Short name T745
Test name
Test status
Simulation time 964661569 ps
CPU time 1.81 seconds
Started Jul 28 07:07:35 PM PDT 24
Finished Jul 28 07:07:37 PM PDT 24
Peak memory 198580 kb
Host smart-37235f5a-3dc4-4add-997e-6eef55e6ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564211904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.564211904
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1746913650
Short name T710
Test name
Test status
Simulation time 51459445848 ps
CPU time 292.38 seconds
Started Jul 28 07:07:40 PM PDT 24
Finished Jul 28 07:12:33 PM PDT 24
Peak memory 208764 kb
Host smart-0f9e6c9a-d1a8-4f45-a540-af121f05ca2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746913650 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1746913650
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.678809385
Short name T681
Test name
Test status
Simulation time 731648017 ps
CPU time 1.87 seconds
Started Jul 28 07:07:37 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200096 kb
Host smart-53c7e258-0928-4656-a673-3de14e03709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678809385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.678809385
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.3040954950
Short name T403
Test name
Test status
Simulation time 40524804805 ps
CPU time 54 seconds
Started Jul 28 07:07:34 PM PDT 24
Finished Jul 28 07:08:28 PM PDT 24
Peak memory 200112 kb
Host smart-a1f7cfa5-2bd6-44fd-bf88-0b0c91d090c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040954950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3040954950
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3967254781
Short name T841
Test name
Test status
Simulation time 250216719031 ps
CPU time 44.69 seconds
Started Jul 28 07:13:13 PM PDT 24
Finished Jul 28 07:13:58 PM PDT 24
Peak memory 200164 kb
Host smart-2e32f2f8-f267-4be7-94d6-ecd2deb196b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967254781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3967254781
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1213035666
Short name T691
Test name
Test status
Simulation time 102075383310 ps
CPU time 17.87 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200136 kb
Host smart-8f9a1860-c80b-4b69-8fc4-fe7460b44e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213035666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1213035666
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4057021043
Short name T163
Test name
Test status
Simulation time 174170725336 ps
CPU time 144.77 seconds
Started Jul 28 07:13:12 PM PDT 24
Finished Jul 28 07:15:37 PM PDT 24
Peak memory 200136 kb
Host smart-5d6a5f28-4691-42d5-9972-cff38597198d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057021043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4057021043
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.917609056
Short name T247
Test name
Test status
Simulation time 198799511650 ps
CPU time 338.33 seconds
Started Jul 28 07:13:12 PM PDT 24
Finished Jul 28 07:18:51 PM PDT 24
Peak memory 200184 kb
Host smart-d74e3c6b-0b63-4e96-b02e-e65bc8146f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917609056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.917609056
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.798688311
Short name T624
Test name
Test status
Simulation time 175560778401 ps
CPU time 82.66 seconds
Started Jul 28 07:13:12 PM PDT 24
Finished Jul 28 07:14:35 PM PDT 24
Peak memory 200152 kb
Host smart-64bb35fa-e86d-4b9a-a674-c56f380f99ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798688311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.798688311
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.393346737
Short name T863
Test name
Test status
Simulation time 50779210319 ps
CPU time 77.97 seconds
Started Jul 28 07:13:10 PM PDT 24
Finished Jul 28 07:14:28 PM PDT 24
Peak memory 200188 kb
Host smart-ac80378c-6fcd-42d6-ba31-172b2ce10933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393346737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.393346737
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.508483051
Short name T145
Test name
Test status
Simulation time 39307595640 ps
CPU time 22.51 seconds
Started Jul 28 07:13:13 PM PDT 24
Finished Jul 28 07:13:36 PM PDT 24
Peak memory 200140 kb
Host smart-7d128155-58ed-485c-bc1d-51442d9e458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508483051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.508483051
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.3138638833
Short name T221
Test name
Test status
Simulation time 49243895404 ps
CPU time 13.31 seconds
Started Jul 28 07:13:12 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 198952 kb
Host smart-2fdfedbd-20ea-40f5-8d12-7c93dcce19e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138638833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.3138638833
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1552846504
Short name T612
Test name
Test status
Simulation time 12499939929 ps
CPU time 16.41 seconds
Started Jul 28 07:13:13 PM PDT 24
Finished Jul 28 07:13:29 PM PDT 24
Peak memory 200120 kb
Host smart-4ae88982-dc7f-49e4-a493-a89a46d7e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552846504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1552846504
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.1444592157
Short name T334
Test name
Test status
Simulation time 26679703 ps
CPU time 0.55 seconds
Started Jul 28 07:07:53 PM PDT 24
Finished Jul 28 07:07:53 PM PDT 24
Peak memory 194824 kb
Host smart-39a9df42-2ef8-4b34-9bfe-b49fca66efe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444592157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1444592157
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4226104638
Short name T807
Test name
Test status
Simulation time 40964622443 ps
CPU time 24.15 seconds
Started Jul 28 07:07:44 PM PDT 24
Finished Jul 28 07:08:08 PM PDT 24
Peak memory 200168 kb
Host smart-efde9b4b-0ff0-48a1-8e15-18bf45a439e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226104638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4226104638
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1485757699
Short name T994
Test name
Test status
Simulation time 119364531126 ps
CPU time 49.7 seconds
Started Jul 28 07:07:39 PM PDT 24
Finished Jul 28 07:08:28 PM PDT 24
Peak memory 200176 kb
Host smart-d13f8fc1-a32a-45a0-ae62-63a691dfafe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485757699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1485757699
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.2917341518
Short name T159
Test name
Test status
Simulation time 212931443374 ps
CPU time 329.23 seconds
Started Jul 28 07:07:42 PM PDT 24
Finished Jul 28 07:13:11 PM PDT 24
Peak memory 200172 kb
Host smart-6171bad2-9bf1-4209-98e6-33173624504c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917341518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.2917341518
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3441256509
Short name T1063
Test name
Test status
Simulation time 18314220392 ps
CPU time 25.42 seconds
Started Jul 28 07:07:43 PM PDT 24
Finished Jul 28 07:08:09 PM PDT 24
Peak memory 200104 kb
Host smart-04cd864b-3c15-4acc-9788-1c2cde5fc84a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441256509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3441256509
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2590572939
Short name T816
Test name
Test status
Simulation time 66049018575 ps
CPU time 200.67 seconds
Started Jul 28 07:07:44 PM PDT 24
Finished Jul 28 07:11:04 PM PDT 24
Peak memory 200384 kb
Host smart-52bb693a-0ddb-4d82-8c14-37f041a55bab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2590572939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2590572939
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1833901661
Short name T1079
Test name
Test status
Simulation time 1751111098 ps
CPU time 2.96 seconds
Started Jul 28 07:07:45 PM PDT 24
Finished Jul 28 07:07:48 PM PDT 24
Peak memory 199244 kb
Host smart-bf8577db-da72-49fa-88f4-2052e20e82a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833901661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1833901661
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3038729263
Short name T433
Test name
Test status
Simulation time 170266806636 ps
CPU time 68.51 seconds
Started Jul 28 07:07:41 PM PDT 24
Finished Jul 28 07:08:50 PM PDT 24
Peak memory 208216 kb
Host smart-719cc84c-7d1d-47f8-96dd-1d0f54240dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038729263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3038729263
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3941242226
Short name T294
Test name
Test status
Simulation time 19338658371 ps
CPU time 202.01 seconds
Started Jul 28 07:07:45 PM PDT 24
Finished Jul 28 07:11:07 PM PDT 24
Peak memory 200224 kb
Host smart-1ae1fe5d-1a45-473d-8626-875b207e81fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3941242226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3941242226
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4254262928
Short name T335
Test name
Test status
Simulation time 1375308730 ps
CPU time 5.53 seconds
Started Jul 28 07:07:39 PM PDT 24
Finished Jul 28 07:07:45 PM PDT 24
Peak memory 198544 kb
Host smart-8092ec02-b873-48b2-b020-c38a15efc1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254262928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4254262928
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.754015506
Short name T285
Test name
Test status
Simulation time 49651093857 ps
CPU time 84.46 seconds
Started Jul 28 07:07:46 PM PDT 24
Finished Jul 28 07:09:10 PM PDT 24
Peak memory 200160 kb
Host smart-48344107-d3ef-415b-9e93-5d552c163333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754015506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.754015506
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.3527165085
Short name T1092
Test name
Test status
Simulation time 3054536956 ps
CPU time 2.89 seconds
Started Jul 28 07:07:45 PM PDT 24
Finished Jul 28 07:07:48 PM PDT 24
Peak memory 196036 kb
Host smart-1af577fe-39e0-4c52-93a6-8e17cd2b89d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527165085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3527165085
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1082482622
Short name T412
Test name
Test status
Simulation time 11034293372 ps
CPU time 36.83 seconds
Started Jul 28 07:07:40 PM PDT 24
Finished Jul 28 07:08:17 PM PDT 24
Peak memory 199888 kb
Host smart-1e46e980-f63e-4316-b3c7-a4c438b273b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082482622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1082482622
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.689831363
Short name T945
Test name
Test status
Simulation time 31166680777 ps
CPU time 22.32 seconds
Started Jul 28 07:07:49 PM PDT 24
Finished Jul 28 07:08:11 PM PDT 24
Peak memory 200156 kb
Host smart-75fe69bf-f400-4549-baef-00370ba0429b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689831363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.689831363
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3075561080
Short name T744
Test name
Test status
Simulation time 15186328339 ps
CPU time 168.6 seconds
Started Jul 28 07:07:51 PM PDT 24
Finished Jul 28 07:10:39 PM PDT 24
Peak memory 216688 kb
Host smart-185f7203-c096-4c97-93a1-3d48dbedeec6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075561080 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3075561080
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3807866401
Short name T1028
Test name
Test status
Simulation time 2643716002 ps
CPU time 2.12 seconds
Started Jul 28 07:07:44 PM PDT 24
Finished Jul 28 07:07:47 PM PDT 24
Peak memory 198656 kb
Host smart-1810e541-641b-416c-b7f4-a518494733f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807866401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3807866401
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3846548508
Short name T1126
Test name
Test status
Simulation time 10125607206 ps
CPU time 16.5 seconds
Started Jul 28 07:07:39 PM PDT 24
Finished Jul 28 07:07:56 PM PDT 24
Peak memory 198832 kb
Host smart-bdf4e1dc-beb5-4c0d-ac07-ebdbf451e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846548508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3846548508
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2316872188
Short name T542
Test name
Test status
Simulation time 167667020624 ps
CPU time 175.78 seconds
Started Jul 28 07:13:13 PM PDT 24
Finished Jul 28 07:16:09 PM PDT 24
Peak memory 200180 kb
Host smart-e65f0b8a-d14f-4706-9dba-c3c9a4478301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316872188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2316872188
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4132425204
Short name T694
Test name
Test status
Simulation time 68538009585 ps
CPU time 9.88 seconds
Started Jul 28 07:13:14 PM PDT 24
Finished Jul 28 07:13:24 PM PDT 24
Peak memory 200032 kb
Host smart-fe891287-c0fc-4d10-9c96-0810cf8ae611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132425204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4132425204
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.2501758689
Short name T144
Test name
Test status
Simulation time 10749222125 ps
CPU time 9.23 seconds
Started Jul 28 07:13:17 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 199952 kb
Host smart-09d6f2b4-2089-4fab-80e5-7f1002fa74e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501758689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.2501758689
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.371164092
Short name T995
Test name
Test status
Simulation time 72807286697 ps
CPU time 52.25 seconds
Started Jul 28 07:13:15 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 200144 kb
Host smart-a9e528b7-2b8e-4e17-883e-ca2fdeec238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371164092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.371164092
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1160107048
Short name T243
Test name
Test status
Simulation time 39190950921 ps
CPU time 50.9 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:14:09 PM PDT 24
Peak memory 200120 kb
Host smart-67099f36-b4b6-4b18-b8df-23905ffc917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160107048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1160107048
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3591444962
Short name T115
Test name
Test status
Simulation time 210062609910 ps
CPU time 44.59 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:14:02 PM PDT 24
Peak memory 199864 kb
Host smart-5adc81f5-9b57-4975-ae9c-fc5aea9b147d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591444962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3591444962
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3825552984
Short name T491
Test name
Test status
Simulation time 101492460190 ps
CPU time 15.95 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:13:34 PM PDT 24
Peak memory 199892 kb
Host smart-1c2d4200-1725-4837-afc3-3cc9f9b67897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825552984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3825552984
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3387914576
Short name T930
Test name
Test status
Simulation time 9858512121 ps
CPU time 14.76 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 199948 kb
Host smart-b6fa33b5-2154-43cc-ac42-014510a2ff3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387914576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3387914576
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1235762002
Short name T751
Test name
Test status
Simulation time 76528257 ps
CPU time 0.56 seconds
Started Jul 28 07:07:56 PM PDT 24
Finished Jul 28 07:07:57 PM PDT 24
Peak memory 195536 kb
Host smart-1148c89c-32df-4079-a127-17dc87a80050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235762002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1235762002
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.564215608
Short name T260
Test name
Test status
Simulation time 27838411022 ps
CPU time 48.79 seconds
Started Jul 28 07:07:48 PM PDT 24
Finished Jul 28 07:08:37 PM PDT 24
Peak memory 200156 kb
Host smart-fd178136-32d3-4383-9eda-e5a926217a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564215608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.564215608
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.450335729
Short name T1129
Test name
Test status
Simulation time 106462289795 ps
CPU time 147.63 seconds
Started Jul 28 07:07:51 PM PDT 24
Finished Jul 28 07:10:19 PM PDT 24
Peak memory 200196 kb
Host smart-40b980af-e2b6-4d81-850c-4d755ddaa0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450335729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.450335729
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.237509287
Short name T492
Test name
Test status
Simulation time 9836069981 ps
CPU time 16.03 seconds
Started Jul 28 07:07:49 PM PDT 24
Finished Jul 28 07:08:05 PM PDT 24
Peak memory 199604 kb
Host smart-1922ff13-47f1-49e7-9dee-fd4a858d538c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237509287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.237509287
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.484290675
Short name T506
Test name
Test status
Simulation time 82496270931 ps
CPU time 126.6 seconds
Started Jul 28 07:07:49 PM PDT 24
Finished Jul 28 07:09:55 PM PDT 24
Peak memory 200124 kb
Host smart-bb35c03a-1df1-4df7-bba2-03f0ad922fef
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484290675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.484290675
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2205976787
Short name T541
Test name
Test status
Simulation time 105249745293 ps
CPU time 317.22 seconds
Started Jul 28 07:07:54 PM PDT 24
Finished Jul 28 07:13:11 PM PDT 24
Peak memory 200116 kb
Host smart-5f4336fb-5ea2-4ed8-af20-bf2c6934ef9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2205976787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2205976787
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.3342939624
Short name T324
Test name
Test status
Simulation time 1614273064 ps
CPU time 2.66 seconds
Started Jul 28 07:07:55 PM PDT 24
Finished Jul 28 07:07:58 PM PDT 24
Peak memory 196396 kb
Host smart-dae410a2-9bc5-4c66-aa31-7b7ac2ea2a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342939624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.3342939624
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.4046927214
Short name T319
Test name
Test status
Simulation time 4309756911 ps
CPU time 6.47 seconds
Started Jul 28 07:07:53 PM PDT 24
Finished Jul 28 07:07:59 PM PDT 24
Peak memory 194752 kb
Host smart-aee8c1fd-7f73-4050-a174-99173e1c7cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046927214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.4046927214
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3834033225
Short name T645
Test name
Test status
Simulation time 29037613630 ps
CPU time 640.54 seconds
Started Jul 28 07:07:55 PM PDT 24
Finished Jul 28 07:18:35 PM PDT 24
Peak memory 200172 kb
Host smart-0d123497-7313-4cc6-aafc-b9075e69e8a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834033225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3834033225
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.4072273238
Short name T544
Test name
Test status
Simulation time 6067997985 ps
CPU time 10.66 seconds
Started Jul 28 07:07:51 PM PDT 24
Finished Jul 28 07:08:02 PM PDT 24
Peak memory 198604 kb
Host smart-9e6a4033-7716-47af-8942-8fe8a44241dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072273238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.4072273238
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.3085775919
Short name T1074
Test name
Test status
Simulation time 83599084504 ps
CPU time 38.05 seconds
Started Jul 28 07:07:56 PM PDT 24
Finished Jul 28 07:08:34 PM PDT 24
Peak memory 200128 kb
Host smart-e3e34a80-1dcf-4880-8a4f-b0f22d6b35e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085775919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.3085775919
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.722445962
Short name T1082
Test name
Test status
Simulation time 42244221675 ps
CPU time 15.14 seconds
Started Jul 28 07:07:50 PM PDT 24
Finished Jul 28 07:08:06 PM PDT 24
Peak memory 195976 kb
Host smart-0b0a7709-589c-49dc-b2e7-b1b7b0c2a398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722445962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.722445962
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.451546287
Short name T496
Test name
Test status
Simulation time 102911267 ps
CPU time 0.88 seconds
Started Jul 28 07:07:49 PM PDT 24
Finished Jul 28 07:07:50 PM PDT 24
Peak memory 197292 kb
Host smart-e89c8bd3-6450-4223-82a9-dd0d160814c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451546287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.451546287
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.4018235438
Short name T262
Test name
Test status
Simulation time 6910953216 ps
CPU time 19.88 seconds
Started Jul 28 07:07:58 PM PDT 24
Finished Jul 28 07:08:18 PM PDT 24
Peak memory 199208 kb
Host smart-6cd9a5c4-8f37-4f8c-b314-abd406d0dca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018235438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.4018235438
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1682093799
Short name T704
Test name
Test status
Simulation time 85175666475 ps
CPU time 34.97 seconds
Started Jul 28 07:07:50 PM PDT 24
Finished Jul 28 07:08:25 PM PDT 24
Peak memory 200236 kb
Host smart-a526a220-5899-4e7f-a8a0-b3db8a5f3f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682093799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1682093799
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2900039484
Short name T622
Test name
Test status
Simulation time 70736236672 ps
CPU time 44.48 seconds
Started Jul 28 07:13:17 PM PDT 24
Finished Jul 28 07:14:02 PM PDT 24
Peak memory 200100 kb
Host smart-23816b41-0b40-4514-b634-c8497e07b91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900039484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2900039484
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.2920049801
Short name T535
Test name
Test status
Simulation time 9925473677 ps
CPU time 6.83 seconds
Started Jul 28 07:13:17 PM PDT 24
Finished Jul 28 07:13:24 PM PDT 24
Peak memory 199724 kb
Host smart-3c4e7535-05ec-422b-a210-7a55b9f9d6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920049801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.2920049801
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2234671683
Short name T470
Test name
Test status
Simulation time 112800443261 ps
CPU time 38.08 seconds
Started Jul 28 07:13:19 PM PDT 24
Finished Jul 28 07:13:57 PM PDT 24
Peak memory 200144 kb
Host smart-16a391f6-4054-448c-8c51-074a22c9c13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234671683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2234671683
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1252258170
Short name T490
Test name
Test status
Simulation time 89804774088 ps
CPU time 64.66 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:14:22 PM PDT 24
Peak memory 200108 kb
Host smart-81f22293-a4f7-4fb6-ab3d-bebe9bd755a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252258170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1252258170
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.638960144
Short name T227
Test name
Test status
Simulation time 118638957919 ps
CPU time 73.8 seconds
Started Jul 28 07:13:17 PM PDT 24
Finished Jul 28 07:14:31 PM PDT 24
Peak memory 200100 kb
Host smart-d4ee6641-aeeb-4826-b10e-de1caa0661f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638960144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.638960144
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1237100360
Short name T8
Test name
Test status
Simulation time 49304660874 ps
CPU time 72.05 seconds
Started Jul 28 07:13:18 PM PDT 24
Finished Jul 28 07:14:30 PM PDT 24
Peak memory 200020 kb
Host smart-eec28dee-4ef0-4850-9738-cf170c43b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237100360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1237100360
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.810762164
Short name T261
Test name
Test status
Simulation time 104951485689 ps
CPU time 14.43 seconds
Started Jul 28 07:13:25 PM PDT 24
Finished Jul 28 07:13:39 PM PDT 24
Peak memory 200104 kb
Host smart-4940947e-4d4f-4f56-b9a5-8ed5ed882c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810762164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.810762164
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3155657183
Short name T522
Test name
Test status
Simulation time 40823696173 ps
CPU time 121.77 seconds
Started Jul 28 07:13:24 PM PDT 24
Finished Jul 28 07:15:26 PM PDT 24
Peak memory 200180 kb
Host smart-de4ea5a2-ec08-4336-ace6-a7aaf0e1fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155657183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3155657183
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3710677457
Short name T196
Test name
Test status
Simulation time 58847102470 ps
CPU time 31.61 seconds
Started Jul 28 07:13:25 PM PDT 24
Finished Jul 28 07:13:57 PM PDT 24
Peak memory 200184 kb
Host smart-4a0faac9-c69d-4998-845c-4ed344821cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710677457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3710677457
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1071160887
Short name T1044
Test name
Test status
Simulation time 21179434654 ps
CPU time 8.89 seconds
Started Jul 28 07:13:25 PM PDT 24
Finished Jul 28 07:13:34 PM PDT 24
Peak memory 200044 kb
Host smart-c3433e4b-9265-402a-ad81-a887c5b78835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071160887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1071160887
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1832550458
Short name T1139
Test name
Test status
Simulation time 42986823 ps
CPU time 0.56 seconds
Started Jul 28 07:08:05 PM PDT 24
Finished Jul 28 07:08:06 PM PDT 24
Peak memory 195024 kb
Host smart-33714ffd-caa0-4221-9003-7093420390d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832550458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1832550458
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3941052366
Short name T910
Test name
Test status
Simulation time 32346994308 ps
CPU time 45.87 seconds
Started Jul 28 07:07:58 PM PDT 24
Finished Jul 28 07:08:44 PM PDT 24
Peak memory 200192 kb
Host smart-a43a3e9e-1f50-4212-8a68-f8c90964dad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941052366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3941052366
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2979558133
Short name T1111
Test name
Test status
Simulation time 104830575385 ps
CPU time 43.69 seconds
Started Jul 28 07:07:55 PM PDT 24
Finished Jul 28 07:08:39 PM PDT 24
Peak memory 200212 kb
Host smart-aff4ef8e-3788-457f-9692-1c8e28cd9582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979558133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2979558133
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_intr.911516485
Short name T741
Test name
Test status
Simulation time 54109859752 ps
CPU time 93.37 seconds
Started Jul 28 07:08:00 PM PDT 24
Finished Jul 28 07:09:33 PM PDT 24
Peak memory 200112 kb
Host smart-b67fc47c-5201-439b-8efd-a444a7891b86
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911516485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.911516485
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2079430074
Short name T748
Test name
Test status
Simulation time 218349771025 ps
CPU time 177.38 seconds
Started Jul 28 07:08:01 PM PDT 24
Finished Jul 28 07:10:58 PM PDT 24
Peak memory 200156 kb
Host smart-7255aca5-89b9-4927-bf99-66edb88362fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2079430074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2079430074
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.1246099960
Short name T814
Test name
Test status
Simulation time 3379715534 ps
CPU time 3.52 seconds
Started Jul 28 07:07:57 PM PDT 24
Finished Jul 28 07:08:01 PM PDT 24
Peak memory 198984 kb
Host smart-86fd87a2-7bb9-45d8-965d-5d9eb7716fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246099960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.1246099960
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.1592253957
Short name T1124
Test name
Test status
Simulation time 106584859023 ps
CPU time 314.91 seconds
Started Jul 28 07:08:01 PM PDT 24
Finished Jul 28 07:13:16 PM PDT 24
Peak memory 208600 kb
Host smart-20f3eaff-7e3c-4655-a561-b9dc4990bc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592253957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.1592253957
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.804281015
Short name T1090
Test name
Test status
Simulation time 12328004595 ps
CPU time 634.2 seconds
Started Jul 28 07:08:01 PM PDT 24
Finished Jul 28 07:18:35 PM PDT 24
Peak memory 200184 kb
Host smart-db66222c-4e9a-4b69-ad5c-5ae0d62d3231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=804281015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.804281015
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.2966559608
Short name T500
Test name
Test status
Simulation time 2635383111 ps
CPU time 4.24 seconds
Started Jul 28 07:07:56 PM PDT 24
Finished Jul 28 07:08:00 PM PDT 24
Peak memory 198504 kb
Host smart-3502bc8d-e089-4754-80d2-c4968846cbf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2966559608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2966559608
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.559462347
Short name T385
Test name
Test status
Simulation time 260166053440 ps
CPU time 268.67 seconds
Started Jul 28 07:08:00 PM PDT 24
Finished Jul 28 07:12:29 PM PDT 24
Peak memory 200188 kb
Host smart-33d019e0-3474-4260-bf17-4f86075385d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559462347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.559462347
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3768310996
Short name T372
Test name
Test status
Simulation time 5403896640 ps
CPU time 2.51 seconds
Started Jul 28 07:07:59 PM PDT 24
Finished Jul 28 07:08:02 PM PDT 24
Peak memory 196496 kb
Host smart-2ac6e54c-e823-44c8-b202-11a3498d5fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768310996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3768310996
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.1692209444
Short name T939
Test name
Test status
Simulation time 6198991140 ps
CPU time 16.52 seconds
Started Jul 28 07:07:54 PM PDT 24
Finished Jul 28 07:08:11 PM PDT 24
Peak memory 200160 kb
Host smart-0f5ee02c-ebd2-45b2-b6ba-816d05af62cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692209444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.1692209444
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3404531912
Short name T1014
Test name
Test status
Simulation time 841999649812 ps
CPU time 679.28 seconds
Started Jul 28 07:08:05 PM PDT 24
Finished Jul 28 07:19:24 PM PDT 24
Peak memory 200072 kb
Host smart-2b35f29b-5c78-4d46-87a3-94f70b7dd687
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404531912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3404531912
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.3925912372
Short name T610
Test name
Test status
Simulation time 2303709707 ps
CPU time 2.39 seconds
Started Jul 28 07:08:02 PM PDT 24
Finished Jul 28 07:08:04 PM PDT 24
Peak memory 199948 kb
Host smart-12aba2dd-e1ca-4fa8-ac80-7e4601afa742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925912372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.3925912372
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3698232980
Short name T47
Test name
Test status
Simulation time 81347086240 ps
CPU time 183.26 seconds
Started Jul 28 07:07:54 PM PDT 24
Finished Jul 28 07:10:57 PM PDT 24
Peak memory 200028 kb
Host smart-52d5acf2-acb6-4772-a857-e7a636c012e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698232980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3698232980
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.934066086
Short name T421
Test name
Test status
Simulation time 17203174079 ps
CPU time 15.8 seconds
Started Jul 28 07:13:24 PM PDT 24
Finished Jul 28 07:13:39 PM PDT 24
Peak memory 200088 kb
Host smart-0c3f8b74-d3cc-48db-920f-b83d4a7c16ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934066086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.934066086
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.3210371245
Short name T185
Test name
Test status
Simulation time 246750295479 ps
CPU time 85.83 seconds
Started Jul 28 07:13:24 PM PDT 24
Finished Jul 28 07:14:50 PM PDT 24
Peak memory 200124 kb
Host smart-aa165ede-ddf6-4e1d-923d-85e1834a8c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210371245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.3210371245
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3353768826
Short name T212
Test name
Test status
Simulation time 102023095450 ps
CPU time 94.01 seconds
Started Jul 28 07:13:27 PM PDT 24
Finished Jul 28 07:15:01 PM PDT 24
Peak memory 200156 kb
Host smart-77e911b0-dae5-421a-a0ad-206c341055b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353768826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3353768826
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2547243680
Short name T667
Test name
Test status
Simulation time 11133921102 ps
CPU time 15.14 seconds
Started Jul 28 07:13:28 PM PDT 24
Finished Jul 28 07:13:44 PM PDT 24
Peak memory 200100 kb
Host smart-70c280ff-128c-4242-b2cc-f68f69eb219b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547243680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2547243680
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.4085586301
Short name T900
Test name
Test status
Simulation time 29958552788 ps
CPU time 48.53 seconds
Started Jul 28 07:13:30 PM PDT 24
Finished Jul 28 07:14:19 PM PDT 24
Peak memory 200084 kb
Host smart-234d03d4-a77f-4b7a-b235-ea804bea1bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085586301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.4085586301
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.2074197837
Short name T1165
Test name
Test status
Simulation time 91484565961 ps
CPU time 35.7 seconds
Started Jul 28 07:13:29 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 200124 kb
Host smart-0a9d770c-f82d-4630-95f0-2c0c62c8d8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074197837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.2074197837
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2032151526
Short name T392
Test name
Test status
Simulation time 10260616890 ps
CPU time 19.58 seconds
Started Jul 28 07:13:29 PM PDT 24
Finished Jul 28 07:13:49 PM PDT 24
Peak memory 200196 kb
Host smart-e8731df3-0b23-4b76-bcb3-d7014852c6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032151526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2032151526
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.293235940
Short name T809
Test name
Test status
Simulation time 10208196949 ps
CPU time 10.09 seconds
Started Jul 28 07:13:28 PM PDT 24
Finished Jul 28 07:13:39 PM PDT 24
Peak memory 200092 kb
Host smart-8866b2ea-c08f-4197-9c70-a3abf86f8a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293235940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.293235940
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4100725279
Short name T677
Test name
Test status
Simulation time 33953595805 ps
CPU time 12.33 seconds
Started Jul 28 07:13:30 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 199744 kb
Host smart-0f1f0cec-d1fb-4fc3-b796-85c3e8085f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100725279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4100725279
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2680113497
Short name T874
Test name
Test status
Simulation time 41856170 ps
CPU time 0.54 seconds
Started Jul 28 07:08:13 PM PDT 24
Finished Jul 28 07:08:14 PM PDT 24
Peak memory 195572 kb
Host smart-a4193f90-8cc1-4da6-9c86-338828fd2bff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680113497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2680113497
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3822682813
Short name T551
Test name
Test status
Simulation time 30392099587 ps
CPU time 51.35 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:08:55 PM PDT 24
Peak memory 200140 kb
Host smart-fbf3315c-b5ec-4eef-a2ca-29c4cfe32c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822682813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3822682813
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.2251005140
Short name T1096
Test name
Test status
Simulation time 118815651504 ps
CPU time 230.31 seconds
Started Jul 28 07:08:03 PM PDT 24
Finished Jul 28 07:11:53 PM PDT 24
Peak memory 200060 kb
Host smart-c5a663dc-1ca0-4306-bce7-59e65b1d741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251005140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.2251005140
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1006426427
Short name T774
Test name
Test status
Simulation time 137512001309 ps
CPU time 81.78 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:09:26 PM PDT 24
Peak memory 200184 kb
Host smart-888e25c2-7667-4e94-8e4c-3dcf6be5b1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006426427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1006426427
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1724450364
Short name T630
Test name
Test status
Simulation time 302792754720 ps
CPU time 436.74 seconds
Started Jul 28 07:08:08 PM PDT 24
Finished Jul 28 07:15:25 PM PDT 24
Peak memory 200180 kb
Host smart-b75009b3-b6f9-4b81-9ffa-ce4d0d13151d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724450364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1724450364
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.1204137003
Short name T1006
Test name
Test status
Simulation time 119694644957 ps
CPU time 724.09 seconds
Started Jul 28 07:08:10 PM PDT 24
Finished Jul 28 07:20:14 PM PDT 24
Peak memory 200128 kb
Host smart-07e2e479-4555-4f0f-afb0-4e38628c3fee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204137003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.1204137003
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1078494502
Short name T860
Test name
Test status
Simulation time 1168505330 ps
CPU time 0.79 seconds
Started Jul 28 07:08:10 PM PDT 24
Finished Jul 28 07:08:11 PM PDT 24
Peak memory 196120 kb
Host smart-b230c08a-aca7-4dc0-9728-d9c0afcbd13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078494502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1078494502
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.787930689
Short name T1055
Test name
Test status
Simulation time 167271960105 ps
CPU time 144.23 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:10:29 PM PDT 24
Peak memory 199988 kb
Host smart-ec206be5-4d90-4c6d-af54-5572dfa07e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787930689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.787930689
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.3492834924
Short name T1035
Test name
Test status
Simulation time 11677428592 ps
CPU time 157.79 seconds
Started Jul 28 07:08:11 PM PDT 24
Finished Jul 28 07:10:49 PM PDT 24
Peak memory 200076 kb
Host smart-50aab56f-6b1b-4417-9fac-dddcebff6d45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3492834924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.3492834924
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1116611183
Short name T330
Test name
Test status
Simulation time 2960941691 ps
CPU time 21.52 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:08:25 PM PDT 24
Peak memory 198628 kb
Host smart-f84108d1-f964-4311-9720-a636fcb5dc37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1116611183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1116611183
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.2919485907
Short name T637
Test name
Test status
Simulation time 95717278973 ps
CPU time 269.94 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:12:34 PM PDT 24
Peak memory 200116 kb
Host smart-f6791d54-6747-40d7-9949-4b8a98110ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919485907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2919485907
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2049881428
Short name T739
Test name
Test status
Simulation time 5854876482 ps
CPU time 5.75 seconds
Started Jul 28 07:08:05 PM PDT 24
Finished Jul 28 07:08:11 PM PDT 24
Peak memory 196340 kb
Host smart-e5616022-ea17-440b-924d-e36db68f791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049881428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2049881428
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1703748065
Short name T955
Test name
Test status
Simulation time 283009802 ps
CPU time 1.44 seconds
Started Jul 28 07:08:08 PM PDT 24
Finished Jul 28 07:08:09 PM PDT 24
Peak memory 199300 kb
Host smart-65d5c653-c784-405c-a0eb-c9f8a563c1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703748065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1703748065
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2526984212
Short name T75
Test name
Test status
Simulation time 168529275295 ps
CPU time 2549.12 seconds
Started Jul 28 07:08:10 PM PDT 24
Finished Jul 28 07:50:39 PM PDT 24
Peak memory 228176 kb
Host smart-bbb519ed-182c-47c5-b314-eba8ddf42203
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526984212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2526984212
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.3474532623
Short name T1087
Test name
Test status
Simulation time 1516309002 ps
CPU time 2.48 seconds
Started Jul 28 07:08:03 PM PDT 24
Finished Jul 28 07:08:06 PM PDT 24
Peak memory 199816 kb
Host smart-e7e23a88-5a5c-4dd8-8588-68ac0bf01464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474532623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3474532623
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2347415758
Short name T368
Test name
Test status
Simulation time 8478689041 ps
CPU time 12.5 seconds
Started Jul 28 07:08:04 PM PDT 24
Finished Jul 28 07:08:17 PM PDT 24
Peak memory 197780 kb
Host smart-2279f71b-93de-4933-b236-a275b24ed932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347415758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2347415758
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3384472930
Short name T201
Test name
Test status
Simulation time 69660671923 ps
CPU time 33.05 seconds
Started Jul 28 07:13:34 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 200108 kb
Host smart-170ac27f-180b-47ec-b92d-549f7207f1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384472930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3384472930
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2539635235
Short name T409
Test name
Test status
Simulation time 17829877521 ps
CPU time 29.71 seconds
Started Jul 28 07:13:34 PM PDT 24
Finished Jul 28 07:14:04 PM PDT 24
Peak memory 199936 kb
Host smart-3237cb28-8fe6-467c-970a-0180d32fbff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539635235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2539635235
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.44331273
Short name T568
Test name
Test status
Simulation time 21555210502 ps
CPU time 17.49 seconds
Started Jul 28 07:13:35 PM PDT 24
Finished Jul 28 07:13:53 PM PDT 24
Peak memory 199928 kb
Host smart-d1903b70-31f1-42f2-a56d-46575c0a3003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44331273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.44331273
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2426614799
Short name T236
Test name
Test status
Simulation time 13597478272 ps
CPU time 24.57 seconds
Started Jul 28 07:13:34 PM PDT 24
Finished Jul 28 07:13:59 PM PDT 24
Peak memory 200116 kb
Host smart-d23310f3-c263-4a66-a8c1-93bc2561ec4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426614799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2426614799
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2710538859
Short name T750
Test name
Test status
Simulation time 15517744566 ps
CPU time 21.05 seconds
Started Jul 28 07:13:34 PM PDT 24
Finished Jul 28 07:13:55 PM PDT 24
Peak memory 200040 kb
Host smart-8cbc20f3-23f3-4dac-b899-ecdfc652e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710538859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2710538859
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.2048544801
Short name T175
Test name
Test status
Simulation time 21780494165 ps
CPU time 37.45 seconds
Started Jul 28 07:13:35 PM PDT 24
Finished Jul 28 07:14:13 PM PDT 24
Peak memory 200128 kb
Host smart-3a2e0ffc-df08-4892-bc2f-eeb08d01b884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048544801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2048544801
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.27149826
Short name T907
Test name
Test status
Simulation time 23240250516 ps
CPU time 21.41 seconds
Started Jul 28 07:13:43 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 200176 kb
Host smart-2be866b7-a0f1-4ec9-852a-9c5755bef5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27149826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.27149826
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2130417174
Short name T194
Test name
Test status
Simulation time 55775478807 ps
CPU time 16.05 seconds
Started Jul 28 07:13:39 PM PDT 24
Finished Jul 28 07:13:55 PM PDT 24
Peak memory 200120 kb
Host smart-1f4862fb-85ca-4351-a0f5-a885295d5ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130417174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2130417174
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1759613069
Short name T803
Test name
Test status
Simulation time 33376774667 ps
CPU time 53.22 seconds
Started Jul 28 07:13:37 PM PDT 24
Finished Jul 28 07:14:31 PM PDT 24
Peak memory 200068 kb
Host smart-7c9ca0b7-d21d-48e0-ad30-e7e96133075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759613069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1759613069
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.684397974
Short name T414
Test name
Test status
Simulation time 107340784875 ps
CPU time 199.57 seconds
Started Jul 28 07:13:37 PM PDT 24
Finished Jul 28 07:16:57 PM PDT 24
Peak memory 200100 kb
Host smart-617a78ab-58b1-4fd0-a096-e1b1965c3b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684397974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.684397974
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.158694610
Short name T588
Test name
Test status
Simulation time 25667470 ps
CPU time 0.57 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:04:44 PM PDT 24
Peak memory 195536 kb
Host smart-f154e74d-502a-4ac2-9065-e60b81c78698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158694610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.158694610
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2492678169
Short name T376
Test name
Test status
Simulation time 71485350487 ps
CPU time 119.55 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:06:33 PM PDT 24
Peak memory 200228 kb
Host smart-4423d645-00c3-487d-863d-52967566eb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492678169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2492678169
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3362993861
Short name T1176
Test name
Test status
Simulation time 45484629449 ps
CPU time 39.8 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:05:16 PM PDT 24
Peak memory 200040 kb
Host smart-30f25f6d-0e7c-4e86-ba54-dc5957dd70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362993861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3362993861
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2215222903
Short name T343
Test name
Test status
Simulation time 129267408196 ps
CPU time 15.12 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:04:51 PM PDT 24
Peak memory 200156 kb
Host smart-bd4825c9-ff52-4a14-8943-41bdd2ebf6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215222903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2215222903
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3695109532
Short name T273
Test name
Test status
Simulation time 60076620294 ps
CPU time 107.11 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:06:23 PM PDT 24
Peak memory 200140 kb
Host smart-e8d134cc-ff7e-4731-96cd-47385f4af5b9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695109532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3695109532
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1077705555
Short name T444
Test name
Test status
Simulation time 164476082076 ps
CPU time 371.78 seconds
Started Jul 28 07:04:46 PM PDT 24
Finished Jul 28 07:10:58 PM PDT 24
Peak memory 200180 kb
Host smart-e0f0a8eb-62ac-43e4-9b7a-40cb0b7806c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077705555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1077705555
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3407835305
Short name T587
Test name
Test status
Simulation time 3593385908 ps
CPU time 1.98 seconds
Started Jul 28 07:04:41 PM PDT 24
Finished Jul 28 07:04:44 PM PDT 24
Peak memory 199956 kb
Host smart-6a061fdd-6e39-4112-ba90-0c6975d238a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407835305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3407835305
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1672526249
Short name T567
Test name
Test status
Simulation time 75840652024 ps
CPU time 35.18 seconds
Started Jul 28 07:04:35 PM PDT 24
Finished Jul 28 07:05:10 PM PDT 24
Peak memory 208484 kb
Host smart-562a43ed-23d7-439b-81d5-6aa58c18dba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672526249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1672526249
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.166611909
Short name T462
Test name
Test status
Simulation time 5767626145 ps
CPU time 44.01 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:05:26 PM PDT 24
Peak memory 200112 kb
Host smart-a20995fb-6816-4145-bb5d-f9d8e89510cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166611909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.166611909
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.1602859686
Short name T875
Test name
Test status
Simulation time 4527982258 ps
CPU time 8.44 seconds
Started Jul 28 07:04:37 PM PDT 24
Finished Jul 28 07:04:46 PM PDT 24
Peak memory 199424 kb
Host smart-9d6cf7b4-5e55-49e0-b4ad-f69c2d6b9bbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1602859686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.1602859686
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1142827428
Short name T56
Test name
Test status
Simulation time 9987712717 ps
CPU time 16.53 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:05:01 PM PDT 24
Peak memory 199988 kb
Host smart-4d4101ba-5e79-4d63-95fa-996caab0875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142827428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1142827428
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.938820065
Short name T909
Test name
Test status
Simulation time 4987963166 ps
CPU time 1.22 seconds
Started Jul 28 07:04:45 PM PDT 24
Finished Jul 28 07:04:46 PM PDT 24
Peak memory 196952 kb
Host smart-8319bc2f-acfa-4d08-99d4-ad620be3b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938820065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.938820065
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1140323655
Short name T109
Test name
Test status
Simulation time 238994273 ps
CPU time 0.88 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:04:43 PM PDT 24
Peak memory 218348 kb
Host smart-2190b828-7680-41b3-864b-cab66d2ec799
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140323655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1140323655
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.365348140
Short name T380
Test name
Test status
Simulation time 537079342 ps
CPU time 2.12 seconds
Started Jul 28 07:04:36 PM PDT 24
Finished Jul 28 07:04:38 PM PDT 24
Peak memory 200104 kb
Host smart-c98141d7-e865-438a-9136-2d0245c8a83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365348140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.365348140
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2053733443
Short name T320
Test name
Test status
Simulation time 384049316927 ps
CPU time 156.15 seconds
Started Jul 28 07:04:43 PM PDT 24
Finished Jul 28 07:07:19 PM PDT 24
Peak memory 200196 kb
Host smart-da179858-ba7b-471c-8d11-8c2485a2295c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053733443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2053733443
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2518621340
Short name T947
Test name
Test status
Simulation time 53015385953 ps
CPU time 562.39 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 216700 kb
Host smart-1514679d-73b9-441a-af02-a36906ac1f36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518621340 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2518621340
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1624807127
Short name T912
Test name
Test status
Simulation time 8083147712 ps
CPU time 6.99 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:04:49 PM PDT 24
Peak memory 199536 kb
Host smart-bc910d15-2095-4b76-90db-23d2a84a281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624807127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1624807127
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3045063725
Short name T914
Test name
Test status
Simulation time 31423120414 ps
CPU time 46.47 seconds
Started Jul 28 07:04:34 PM PDT 24
Finished Jul 28 07:05:20 PM PDT 24
Peak memory 200188 kb
Host smart-a27e6ead-792a-4599-b8d0-e8e693e834be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045063725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3045063725
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.2976481487
Short name T543
Test name
Test status
Simulation time 32040548 ps
CPU time 0.55 seconds
Started Jul 28 07:08:18 PM PDT 24
Finished Jul 28 07:08:18 PM PDT 24
Peak memory 195576 kb
Host smart-21840d4f-2565-4958-9e45-692baae44d6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976481487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.2976481487
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3583327741
Short name T1170
Test name
Test status
Simulation time 20245947355 ps
CPU time 33.13 seconds
Started Jul 28 07:08:15 PM PDT 24
Finished Jul 28 07:08:48 PM PDT 24
Peak memory 200192 kb
Host smart-78779b07-d19e-4ea7-a158-22ed9a9b85be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583327741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3583327741
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.4060824699
Short name T362
Test name
Test status
Simulation time 127091761582 ps
CPU time 167.7 seconds
Started Jul 28 07:08:15 PM PDT 24
Finished Jul 28 07:11:03 PM PDT 24
Peak memory 200232 kb
Host smart-dcf7bae1-2054-4704-9451-f927de63f446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060824699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.4060824699
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.686206614
Short name T548
Test name
Test status
Simulation time 153425507110 ps
CPU time 207.34 seconds
Started Jul 28 07:08:11 PM PDT 24
Finished Jul 28 07:11:38 PM PDT 24
Peak memory 200392 kb
Host smart-05892bb0-0ac5-47b1-82d8-6361178c7d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686206614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.686206614
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3156975
Short name T20
Test name
Test status
Simulation time 49824003285 ps
CPU time 72.75 seconds
Started Jul 28 07:08:16 PM PDT 24
Finished Jul 28 07:09:29 PM PDT 24
Peak memory 200036 kb
Host smart-87e25956-849d-44f7-9564-251cb89e5579
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3156975
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.1685535791
Short name T1047
Test name
Test status
Simulation time 220098406430 ps
CPU time 384.69 seconds
Started Jul 28 07:08:18 PM PDT 24
Finished Jul 28 07:14:43 PM PDT 24
Peak memory 200176 kb
Host smart-8cc75991-1ade-48e7-b6ec-0be19ef73714
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1685535791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.1685535791
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.482017414
Short name T782
Test name
Test status
Simulation time 138236833 ps
CPU time 0.81 seconds
Started Jul 28 07:08:16 PM PDT 24
Finished Jul 28 07:08:17 PM PDT 24
Peak memory 197716 kb
Host smart-c8f0f1d2-67f8-4774-924d-3a16c5e40e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482017414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.482017414
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2145189150
Short name T791
Test name
Test status
Simulation time 267642976225 ps
CPU time 93.79 seconds
Started Jul 28 07:08:15 PM PDT 24
Finished Jul 28 07:09:49 PM PDT 24
Peak memory 208460 kb
Host smart-01dc35f0-0544-453b-a4ff-9485212b220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145189150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2145189150
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.4037193850
Short name T404
Test name
Test status
Simulation time 11269483938 ps
CPU time 591.97 seconds
Started Jul 28 07:08:15 PM PDT 24
Finished Jul 28 07:18:07 PM PDT 24
Peak memory 200212 kb
Host smart-a46c4106-583a-4a34-9353-b1c6f65dc491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037193850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.4037193850
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3486214225
Short name T591
Test name
Test status
Simulation time 3577483013 ps
CPU time 2.1 seconds
Started Jul 28 07:08:14 PM PDT 24
Finished Jul 28 07:08:16 PM PDT 24
Peak memory 199532 kb
Host smart-c249956d-8d90-4444-b1fa-31d8b5d24136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486214225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3486214225
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1983829347
Short name T146
Test name
Test status
Simulation time 110636771538 ps
CPU time 78.3 seconds
Started Jul 28 07:08:16 PM PDT 24
Finished Jul 28 07:09:34 PM PDT 24
Peak memory 200160 kb
Host smart-bbd02667-fc00-4ada-bc42-cb5d969cb1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983829347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1983829347
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1867181426
Short name T345
Test name
Test status
Simulation time 2791681938 ps
CPU time 5.05 seconds
Started Jul 28 07:08:16 PM PDT 24
Finished Jul 28 07:08:21 PM PDT 24
Peak memory 196032 kb
Host smart-a0b1f002-c1f1-4574-bef0-b1324bd396ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867181426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1867181426
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.596150737
Short name T565
Test name
Test status
Simulation time 529909986 ps
CPU time 2 seconds
Started Jul 28 07:08:14 PM PDT 24
Finished Jul 28 07:08:16 PM PDT 24
Peak memory 198948 kb
Host smart-c69ce113-f827-4104-898b-fbf88c37fccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596150737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.596150737
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.18318023
Short name T129
Test name
Test status
Simulation time 437456390168 ps
CPU time 163.45 seconds
Started Jul 28 07:08:18 PM PDT 24
Finished Jul 28 07:11:01 PM PDT 24
Peak memory 200220 kb
Host smart-885249a8-d851-46d5-8b76-b4d15e503b52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18318023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.18318023
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3264111193
Short name T36
Test name
Test status
Simulation time 36375490254 ps
CPU time 433.26 seconds
Started Jul 28 07:08:14 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 216852 kb
Host smart-52ebcb0b-14c4-49bf-8b49-fa0a2e744dcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264111193 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3264111193
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2485222144
Short name T303
Test name
Test status
Simulation time 9541539943 ps
CPU time 13.35 seconds
Started Jul 28 07:08:18 PM PDT 24
Finished Jul 28 07:08:31 PM PDT 24
Peak memory 199776 kb
Host smart-2528a029-931e-4f94-ac55-fa45a867d764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485222144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2485222144
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2697182586
Short name T290
Test name
Test status
Simulation time 72979860177 ps
CPU time 120.36 seconds
Started Jul 28 07:08:14 PM PDT 24
Finished Jul 28 07:10:15 PM PDT 24
Peak memory 200132 kb
Host smart-c6352215-be1a-4a1f-9ce0-6c93d808f77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697182586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2697182586
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1734608554
Short name T707
Test name
Test status
Simulation time 40485220 ps
CPU time 0.55 seconds
Started Jul 28 07:08:26 PM PDT 24
Finished Jul 28 07:08:27 PM PDT 24
Peak memory 194768 kb
Host smart-b8fd7f35-ad29-4337-ba24-89db742db896
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734608554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1734608554
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3975295783
Short name T161
Test name
Test status
Simulation time 46336800536 ps
CPU time 21.82 seconds
Started Jul 28 07:08:20 PM PDT 24
Finished Jul 28 07:08:42 PM PDT 24
Peak memory 200088 kb
Host smart-72a58048-59e0-4556-a713-b77ce2ab2442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975295783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3975295783
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.1877358192
Short name T626
Test name
Test status
Simulation time 10331369483 ps
CPU time 14.12 seconds
Started Jul 28 07:08:20 PM PDT 24
Finished Jul 28 07:08:34 PM PDT 24
Peak memory 200172 kb
Host smart-12350b22-b493-40ff-b621-879740aed9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877358192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1877358192
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.544108339
Short name T641
Test name
Test status
Simulation time 16541737851 ps
CPU time 21.76 seconds
Started Jul 28 07:08:21 PM PDT 24
Finished Jul 28 07:08:43 PM PDT 24
Peak memory 200232 kb
Host smart-ebde54d5-3a26-49e6-9e92-050d961e453d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544108339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.544108339
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.4141713065
Short name T1127
Test name
Test status
Simulation time 31295734618 ps
CPU time 13.05 seconds
Started Jul 28 07:08:23 PM PDT 24
Finished Jul 28 07:08:36 PM PDT 24
Peak memory 198528 kb
Host smart-adcd896b-37a2-4925-8be9-eac1d458f950
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141713065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.4141713065
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1271889665
Short name T652
Test name
Test status
Simulation time 100149593509 ps
CPU time 346.85 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:14:14 PM PDT 24
Peak memory 200196 kb
Host smart-5bbea25e-bf96-4d91-9031-ed16ed7ca6ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271889665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1271889665
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3507510539
Short name T480
Test name
Test status
Simulation time 3831801943 ps
CPU time 7.29 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:08:34 PM PDT 24
Peak memory 199820 kb
Host smart-6d62df82-1c4c-43b8-bb81-5a2bdccc8a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507510539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3507510539
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.1912011352
Short name T350
Test name
Test status
Simulation time 100235085991 ps
CPU time 40.11 seconds
Started Jul 28 07:08:24 PM PDT 24
Finished Jul 28 07:09:04 PM PDT 24
Peak memory 200308 kb
Host smart-788ff204-6916-4886-b4a3-d39056200386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912011352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1912011352
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2376433954
Short name T573
Test name
Test status
Simulation time 6072743062 ps
CPU time 338.82 seconds
Started Jul 28 07:08:26 PM PDT 24
Finished Jul 28 07:14:05 PM PDT 24
Peak memory 200180 kb
Host smart-20084429-127b-44bb-9229-3dcc48f3aafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376433954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2376433954
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2919127680
Short name T381
Test name
Test status
Simulation time 3051873647 ps
CPU time 19.12 seconds
Started Jul 28 07:08:21 PM PDT 24
Finished Jul 28 07:08:40 PM PDT 24
Peak memory 198120 kb
Host smart-0ae65da9-7c73-4cf6-b2a9-155d30b49feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919127680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2919127680
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1479525965
Short name T180
Test name
Test status
Simulation time 12320757258 ps
CPU time 16.24 seconds
Started Jul 28 07:08:24 PM PDT 24
Finished Jul 28 07:08:40 PM PDT 24
Peak memory 199836 kb
Host smart-cd88e567-bae3-4c96-963e-29b76a9e818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479525965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1479525965
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.3801914799
Short name T52
Test name
Test status
Simulation time 3256786982 ps
CPU time 2 seconds
Started Jul 28 07:08:23 PM PDT 24
Finished Jul 28 07:08:25 PM PDT 24
Peak memory 196348 kb
Host smart-4597b86a-1838-49e3-a8b1-3ce360d2bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801914799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.3801914799
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1759804431
Short name T451
Test name
Test status
Simulation time 743494908 ps
CPU time 2.78 seconds
Started Jul 28 07:08:21 PM PDT 24
Finished Jul 28 07:08:24 PM PDT 24
Peak memory 200028 kb
Host smart-703bda88-ca49-4134-9d8a-64e7fc5465a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759804431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1759804431
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.770996844
Short name T323
Test name
Test status
Simulation time 312381451670 ps
CPU time 80.73 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:09:48 PM PDT 24
Peak memory 200228 kb
Host smart-f369ce87-8838-4005-81ac-302fd920ae5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770996844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.770996844
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2148811045
Short name T953
Test name
Test status
Simulation time 12389115357 ps
CPU time 5.6 seconds
Started Jul 28 07:08:21 PM PDT 24
Finished Jul 28 07:08:27 PM PDT 24
Peak memory 200108 kb
Host smart-e65c651e-047a-4be3-8ba2-559f2b44ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148811045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2148811045
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.4150013273
Short name T1033
Test name
Test status
Simulation time 121691451652 ps
CPU time 78.05 seconds
Started Jul 28 07:08:22 PM PDT 24
Finished Jul 28 07:09:40 PM PDT 24
Peak memory 200192 kb
Host smart-cd48a054-5d1f-4e17-9f1c-b158302a4a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150013273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.4150013273
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3825342940
Short name T989
Test name
Test status
Simulation time 30360513 ps
CPU time 0.56 seconds
Started Jul 28 07:08:38 PM PDT 24
Finished Jul 28 07:08:39 PM PDT 24
Peak memory 195164 kb
Host smart-6c272479-9b77-42a9-af8f-724626804dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825342940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3825342940
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3025250821
Short name T787
Test name
Test status
Simulation time 41723049200 ps
CPU time 59.5 seconds
Started Jul 28 07:08:28 PM PDT 24
Finished Jul 28 07:09:27 PM PDT 24
Peak memory 200148 kb
Host smart-358e2c15-0f31-4327-9a5b-dc6b9cfb1fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025250821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3025250821
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.549115054
Short name T1017
Test name
Test status
Simulation time 109730737238 ps
CPU time 124.6 seconds
Started Jul 28 07:08:26 PM PDT 24
Finished Jul 28 07:10:31 PM PDT 24
Peak memory 200156 kb
Host smart-d687dd23-d081-492a-9492-e038aabf56de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549115054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.549115054
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1318244232
Short name T593
Test name
Test status
Simulation time 65847665485 ps
CPU time 25.96 seconds
Started Jul 28 07:08:25 PM PDT 24
Finished Jul 28 07:08:51 PM PDT 24
Peak memory 200168 kb
Host smart-683c1b88-0a1c-4db2-b380-84b590744aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318244232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1318244232
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2293749724
Short name T806
Test name
Test status
Simulation time 41686176593 ps
CPU time 16.77 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:08:44 PM PDT 24
Peak memory 200144 kb
Host smart-8950db3f-2ab8-46bc-ba63-3e72d457bbd5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293749724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2293749724
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.623708784
Short name T738
Test name
Test status
Simulation time 130987986861 ps
CPU time 892.69 seconds
Started Jul 28 07:08:28 PM PDT 24
Finished Jul 28 07:23:21 PM PDT 24
Peak memory 200192 kb
Host smart-aa8a7f63-f72b-4d92-94f4-7c76c8cd4b93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623708784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.623708784
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.2348746149
Short name T114
Test name
Test status
Simulation time 1830878446 ps
CPU time 3.83 seconds
Started Jul 28 07:08:33 PM PDT 24
Finished Jul 28 07:08:37 PM PDT 24
Peak memory 197248 kb
Host smart-22bcd465-423a-4b31-a65c-c07327279abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348746149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2348746149
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.4157934626
Short name T815
Test name
Test status
Simulation time 81579183318 ps
CPU time 58.38 seconds
Started Jul 28 07:08:32 PM PDT 24
Finished Jul 28 07:09:31 PM PDT 24
Peak memory 199876 kb
Host smart-45f9e610-83d9-4a3b-baa3-16028d8c5276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157934626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4157934626
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1532068000
Short name T513
Test name
Test status
Simulation time 5281481606 ps
CPU time 144.64 seconds
Started Jul 28 07:08:31 PM PDT 24
Finished Jul 28 07:10:56 PM PDT 24
Peak memory 200196 kb
Host smart-858466dd-2ce4-40cb-b375-07affea7543a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532068000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1532068000
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3768677103
Short name T22
Test name
Test status
Simulation time 5755433150 ps
CPU time 33.13 seconds
Started Jul 28 07:08:28 PM PDT 24
Finished Jul 28 07:09:01 PM PDT 24
Peak memory 199220 kb
Host smart-2d46af1f-47a3-4d0e-b189-f82b55f48d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3768677103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3768677103
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1298909502
Short name T1117
Test name
Test status
Simulation time 66150739043 ps
CPU time 20.25 seconds
Started Jul 28 07:08:33 PM PDT 24
Finished Jul 28 07:08:53 PM PDT 24
Peak memory 200064 kb
Host smart-ed9215c6-8567-4eff-b0d0-31e628466ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298909502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1298909502
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1909961326
Short name T845
Test name
Test status
Simulation time 45224973131 ps
CPU time 64.85 seconds
Started Jul 28 07:08:34 PM PDT 24
Finished Jul 28 07:09:39 PM PDT 24
Peak memory 196224 kb
Host smart-0ddb91b1-a8cb-406c-8de3-07cfcf391d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909961326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1909961326
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.245962875
Short name T332
Test name
Test status
Simulation time 775632296 ps
CPU time 1.18 seconds
Started Jul 28 07:08:25 PM PDT 24
Finished Jul 28 07:08:26 PM PDT 24
Peak memory 200048 kb
Host smart-a76d66bf-cbc7-400c-8f2e-5b66279023ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245962875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.245962875
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.574193901
Short name T527
Test name
Test status
Simulation time 164344001602 ps
CPU time 303.66 seconds
Started Jul 28 07:08:39 PM PDT 24
Finished Jul 28 07:13:43 PM PDT 24
Peak memory 200208 kb
Host smart-ef165e1b-cc9c-4568-8ec3-50a023dbdeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574193901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.574193901
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.3837822434
Short name T708
Test name
Test status
Simulation time 256997421696 ps
CPU time 891.63 seconds
Started Jul 28 07:08:31 PM PDT 24
Finished Jul 28 07:23:23 PM PDT 24
Peak memory 224980 kb
Host smart-a9824a0d-062e-4ff2-a47f-aa8e173e1d19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837822434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.3837822434
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.3331194662
Short name T857
Test name
Test status
Simulation time 349897396 ps
CPU time 1.23 seconds
Started Jul 28 07:08:31 PM PDT 24
Finished Jul 28 07:08:32 PM PDT 24
Peak memory 197460 kb
Host smart-658cb8b9-5d0c-4c1b-b745-044b708da654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331194662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.3331194662
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2663574998
Short name T286
Test name
Test status
Simulation time 74679728336 ps
CPU time 82.13 seconds
Started Jul 28 07:08:27 PM PDT 24
Finished Jul 28 07:09:49 PM PDT 24
Peak memory 200144 kb
Host smart-31c0d764-3ed1-446f-9548-5611c3817146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663574998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2663574998
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1133875676
Short name T1012
Test name
Test status
Simulation time 35097793 ps
CPU time 0.54 seconds
Started Jul 28 07:08:42 PM PDT 24
Finished Jul 28 07:08:43 PM PDT 24
Peak memory 195436 kb
Host smart-a35673d3-ba27-49ec-8bfe-4e00553343d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133875676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1133875676
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.507024897
Short name T442
Test name
Test status
Simulation time 121836439088 ps
CPU time 50.69 seconds
Started Jul 28 07:08:36 PM PDT 24
Finished Jul 28 07:09:27 PM PDT 24
Peak memory 200092 kb
Host smart-e2e04986-2ade-47d2-b618-c362457dc6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507024897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.507024897
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1831195895
Short name T296
Test name
Test status
Simulation time 227616088409 ps
CPU time 107.63 seconds
Started Jul 28 07:08:38 PM PDT 24
Finished Jul 28 07:10:25 PM PDT 24
Peak memory 200104 kb
Host smart-7d8d22a3-4c5f-461a-9931-b73ce3df22ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831195895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1831195895
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3251308180
Short name T571
Test name
Test status
Simulation time 8057086712 ps
CPU time 12.14 seconds
Started Jul 28 07:08:37 PM PDT 24
Finished Jul 28 07:08:49 PM PDT 24
Peak memory 198888 kb
Host smart-976f73d0-51b3-4147-93a7-182c78f8a25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251308180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3251308180
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.1960231968
Short name T348
Test name
Test status
Simulation time 211276249637 ps
CPU time 156.59 seconds
Started Jul 28 07:08:37 PM PDT 24
Finished Jul 28 07:11:13 PM PDT 24
Peak memory 197404 kb
Host smart-21138c8f-4ccf-47d8-b363-46db8764d19f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960231968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.1960231968
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2015009043
Short name T43
Test name
Test status
Simulation time 93728470262 ps
CPU time 394.06 seconds
Started Jul 28 07:08:36 PM PDT 24
Finished Jul 28 07:15:11 PM PDT 24
Peak memory 200200 kb
Host smart-6d873156-a1a3-46f5-aaa9-35f8c62a1dbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2015009043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2015009043
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3454409580
Short name T472
Test name
Test status
Simulation time 6162697598 ps
CPU time 4.43 seconds
Started Jul 28 07:08:39 PM PDT 24
Finished Jul 28 07:08:44 PM PDT 24
Peak memory 199152 kb
Host smart-c07df0cc-ef49-46fb-95d7-d70ec80a7190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454409580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3454409580
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1986650746
Short name T424
Test name
Test status
Simulation time 61507640559 ps
CPU time 31.54 seconds
Started Jul 28 07:08:40 PM PDT 24
Finished Jul 28 07:09:12 PM PDT 24
Peak memory 200300 kb
Host smart-bfc2a00d-a974-47d3-a84c-9cb5c6bbc230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986650746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1986650746
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2585985715
Short name T979
Test name
Test status
Simulation time 4729089131 ps
CPU time 136.28 seconds
Started Jul 28 07:08:36 PM PDT 24
Finished Jul 28 07:10:53 PM PDT 24
Peak memory 200124 kb
Host smart-80b83d1d-2919-44b7-8463-dea5376caea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585985715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2585985715
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3804000617
Short name T325
Test name
Test status
Simulation time 5899672225 ps
CPU time 29.35 seconds
Started Jul 28 07:08:33 PM PDT 24
Finished Jul 28 07:09:03 PM PDT 24
Peak memory 199408 kb
Host smart-defe9a45-0026-4115-b807-0afe2bae36ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3804000617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3804000617
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.2760957181
Short name T913
Test name
Test status
Simulation time 178238739298 ps
CPU time 64.95 seconds
Started Jul 28 07:08:36 PM PDT 24
Finished Jul 28 07:09:41 PM PDT 24
Peak memory 200100 kb
Host smart-404ceb19-0d9e-47d6-b725-c4480b25c40b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760957181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.2760957181
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.94299554
Short name T629
Test name
Test status
Simulation time 6707025760 ps
CPU time 11.05 seconds
Started Jul 28 07:08:37 PM PDT 24
Finished Jul 28 07:08:48 PM PDT 24
Peak memory 196964 kb
Host smart-f41d306b-3d27-47bc-bf7d-1f63fbf12a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94299554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.94299554
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.44290493
Short name T804
Test name
Test status
Simulation time 740244651 ps
CPU time 4.22 seconds
Started Jul 28 07:08:37 PM PDT 24
Finished Jul 28 07:08:41 PM PDT 24
Peak memory 199100 kb
Host smart-59fe2a61-b2cb-4f31-b5b0-f469fb9db4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44290493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.44290493
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3659514870
Short name T128
Test name
Test status
Simulation time 225461784641 ps
CPU time 1098.09 seconds
Started Jul 28 07:08:43 PM PDT 24
Finished Jul 28 07:27:01 PM PDT 24
Peak memory 200072 kb
Host smart-8d4a8a15-9afb-4bcc-81d3-2728b66115c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659514870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3659514870
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2675876563
Short name T35
Test name
Test status
Simulation time 84839707389 ps
CPU time 844.08 seconds
Started Jul 28 07:08:41 PM PDT 24
Finished Jul 28 07:22:46 PM PDT 24
Peak memory 225044 kb
Host smart-ed5f3542-5c0d-4efc-8c1c-42032d63e526
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675876563 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2675876563
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.1970756391
Short name T420
Test name
Test status
Simulation time 1167004076 ps
CPU time 2.96 seconds
Started Jul 28 07:08:39 PM PDT 24
Finished Jul 28 07:08:42 PM PDT 24
Peak memory 200040 kb
Host smart-b02dd88c-b75d-44c7-86e5-0ed01ffe107f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970756391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.1970756391
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3795988101
Short name T454
Test name
Test status
Simulation time 86590550384 ps
CPU time 159.38 seconds
Started Jul 28 07:08:37 PM PDT 24
Finished Jul 28 07:11:16 PM PDT 24
Peak memory 200124 kb
Host smart-c7af3812-44fb-4572-9d60-0673c79577db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795988101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3795988101
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3529670916
Short name T341
Test name
Test status
Simulation time 12126791 ps
CPU time 0.55 seconds
Started Jul 28 07:08:54 PM PDT 24
Finished Jul 28 07:08:55 PM PDT 24
Peak memory 194832 kb
Host smart-bf10e538-d56a-4660-851a-292a29c87c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529670916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3529670916
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.2359569484
Short name T817
Test name
Test status
Simulation time 33628029703 ps
CPU time 48.13 seconds
Started Jul 28 07:08:43 PM PDT 24
Finished Jul 28 07:09:32 PM PDT 24
Peak memory 200112 kb
Host smart-88490525-102a-4b37-af09-cdfc7807525c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359569484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.2359569484
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3570554892
Short name T810
Test name
Test status
Simulation time 144390540893 ps
CPU time 60.35 seconds
Started Jul 28 07:08:41 PM PDT 24
Finished Jul 28 07:09:42 PM PDT 24
Peak memory 200100 kb
Host smart-95c2a516-28be-426f-a1e7-3445e40cd5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570554892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3570554892
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.730634548
Short name T502
Test name
Test status
Simulation time 230680917871 ps
CPU time 130.49 seconds
Started Jul 28 07:08:42 PM PDT 24
Finished Jul 28 07:10:53 PM PDT 24
Peak memory 200236 kb
Host smart-060f620a-1824-4fba-8711-a88b3eb01f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730634548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.730634548
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.270471599
Short name T338
Test name
Test status
Simulation time 11824887700 ps
CPU time 10.77 seconds
Started Jul 28 07:08:43 PM PDT 24
Finished Jul 28 07:08:54 PM PDT 24
Peak memory 200168 kb
Host smart-47b157fe-93b6-4f0c-89f2-226b53bf13c0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270471599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.270471599
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1333534172
Short name T537
Test name
Test status
Simulation time 71449180419 ps
CPU time 129.82 seconds
Started Jul 28 07:08:48 PM PDT 24
Finished Jul 28 07:10:58 PM PDT 24
Peak memory 200124 kb
Host smart-2086c237-af5d-4a4c-8803-9fcf59c1cdc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333534172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1333534172
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.860858455
Short name T511
Test name
Test status
Simulation time 2724097252 ps
CPU time 2.35 seconds
Started Jul 28 07:08:50 PM PDT 24
Finished Jul 28 07:08:52 PM PDT 24
Peak memory 199152 kb
Host smart-e208d564-b69c-44e4-8f6c-7dc19fca825a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860858455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.860858455
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.2792622066
Short name T1080
Test name
Test status
Simulation time 29421782848 ps
CPU time 12.44 seconds
Started Jul 28 07:08:49 PM PDT 24
Finished Jul 28 07:09:01 PM PDT 24
Peak memory 197224 kb
Host smart-d09591b4-35e7-4da1-a588-b8a68fd2583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792622066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.2792622066
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1071766157
Short name T590
Test name
Test status
Simulation time 7297509986 ps
CPU time 87.89 seconds
Started Jul 28 07:08:48 PM PDT 24
Finished Jul 28 07:10:16 PM PDT 24
Peak memory 200208 kb
Host smart-5fdfee8f-7c87-4b73-ab2f-088ee0b06d4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1071766157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1071766157
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1523974896
Short name T740
Test name
Test status
Simulation time 4033339494 ps
CPU time 32.58 seconds
Started Jul 28 07:08:43 PM PDT 24
Finished Jul 28 07:09:16 PM PDT 24
Peak memory 198560 kb
Host smart-fb120f56-63b4-4ef0-bbb5-4579c4112071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523974896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1523974896
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.913822039
Short name T828
Test name
Test status
Simulation time 59698095379 ps
CPU time 23.19 seconds
Started Jul 28 07:08:47 PM PDT 24
Finished Jul 28 07:09:10 PM PDT 24
Peak memory 200160 kb
Host smart-65154779-d17d-4137-8d4b-9ca7b88dfe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913822039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.913822039
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.90313289
Short name T1073
Test name
Test status
Simulation time 3742018557 ps
CPU time 6.65 seconds
Started Jul 28 07:08:48 PM PDT 24
Finished Jul 28 07:08:55 PM PDT 24
Peak memory 197060 kb
Host smart-310f92c4-636c-4ec3-8d28-6abe75595c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90313289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.90313289
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3572378539
Short name T775
Test name
Test status
Simulation time 6238133681 ps
CPU time 21.54 seconds
Started Jul 28 07:08:42 PM PDT 24
Finished Jul 28 07:09:04 PM PDT 24
Peak memory 199956 kb
Host smart-113ef2ca-d981-4ef0-82d6-e16f9803daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572378539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3572378539
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1197471696
Short name T589
Test name
Test status
Simulation time 92758001037 ps
CPU time 136.58 seconds
Started Jul 28 07:08:53 PM PDT 24
Finished Jul 28 07:11:10 PM PDT 24
Peak memory 200232 kb
Host smart-e50b287a-287d-4696-a88f-0dd311315859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197471696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1197471696
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.4110951287
Short name T1049
Test name
Test status
Simulation time 70095479809 ps
CPU time 148.49 seconds
Started Jul 28 07:08:54 PM PDT 24
Finished Jul 28 07:11:23 PM PDT 24
Peak memory 208416 kb
Host smart-872fd5c8-e58a-47b1-80ed-a21b2ccbb771
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110951287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.4110951287
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.17134692
Short name T538
Test name
Test status
Simulation time 1491256586 ps
CPU time 1.48 seconds
Started Jul 28 07:08:47 PM PDT 24
Finished Jul 28 07:08:49 PM PDT 24
Peak memory 198920 kb
Host smart-ebd4da52-6a8b-4638-a855-88c0ba8053b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17134692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.17134692
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3840685779
Short name T279
Test name
Test status
Simulation time 17253557785 ps
CPU time 31.09 seconds
Started Jul 28 07:08:41 PM PDT 24
Finished Jul 28 07:09:13 PM PDT 24
Peak memory 200116 kb
Host smart-3a790a5a-1373-4a8c-9eb3-f105414e9350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840685779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3840685779
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3950553668
Short name T766
Test name
Test status
Simulation time 16541845 ps
CPU time 0.55 seconds
Started Jul 28 07:08:59 PM PDT 24
Finished Jul 28 07:09:00 PM PDT 24
Peak memory 195472 kb
Host smart-f01bdf92-a76c-423a-acb4-84e678a6b5c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950553668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3950553668
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1187961637
Short name T827
Test name
Test status
Simulation time 231753110245 ps
CPU time 19.49 seconds
Started Jul 28 07:08:55 PM PDT 24
Finished Jul 28 07:09:15 PM PDT 24
Peak memory 199744 kb
Host smart-badf8838-ba41-4205-a1b8-49ef79b34bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187961637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1187961637
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.1399435142
Short name T753
Test name
Test status
Simulation time 99007341534 ps
CPU time 112.42 seconds
Started Jul 28 07:08:54 PM PDT 24
Finished Jul 28 07:10:46 PM PDT 24
Peak memory 200128 kb
Host smart-65ba8b2e-fd6d-49ea-a27e-2d4402cfad4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399435142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.1399435142
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.277252130
Short name T179
Test name
Test status
Simulation time 328693881882 ps
CPU time 33.91 seconds
Started Jul 28 07:08:54 PM PDT 24
Finished Jul 28 07:09:28 PM PDT 24
Peak memory 200192 kb
Host smart-122066e4-90f7-403f-b849-5b5e153ed4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277252130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.277252130
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3579484549
Short name T834
Test name
Test status
Simulation time 9862574038 ps
CPU time 5.29 seconds
Started Jul 28 07:08:56 PM PDT 24
Finished Jul 28 07:09:02 PM PDT 24
Peak memory 197184 kb
Host smart-806474d2-2581-443a-901c-c79e890e476f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579484549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3579484549
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2106820768
Short name T559
Test name
Test status
Simulation time 61634050297 ps
CPU time 283.51 seconds
Started Jul 28 07:09:00 PM PDT 24
Finished Jul 28 07:13:43 PM PDT 24
Peak memory 200176 kb
Host smart-e231ca2a-45b9-4e98-b291-e802ffae3b03
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106820768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2106820768
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.1126274611
Short name T831
Test name
Test status
Simulation time 8240471980 ps
CPU time 5.13 seconds
Started Jul 28 07:08:59 PM PDT 24
Finished Jul 28 07:09:04 PM PDT 24
Peak memory 200000 kb
Host smart-3b3d76ce-e562-4998-83e0-b4ba08e1b679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126274611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1126274611
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.665849910
Short name T885
Test name
Test status
Simulation time 4489023081 ps
CPU time 6.03 seconds
Started Jul 28 07:08:55 PM PDT 24
Finished Jul 28 07:09:01 PM PDT 24
Peak memory 194756 kb
Host smart-fe527e8a-84e6-4c5d-b568-e07a586d4350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665849910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.665849910
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.1913030025
Short name T957
Test name
Test status
Simulation time 9689002910 ps
CPU time 95.06 seconds
Started Jul 28 07:08:58 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 200160 kb
Host smart-ce6d68e2-d6e2-4ae8-92a7-fb0477983f74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1913030025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.1913030025
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.1225085734
Short name T13
Test name
Test status
Simulation time 4352153221 ps
CPU time 35.94 seconds
Started Jul 28 07:08:51 PM PDT 24
Finished Jul 28 07:09:27 PM PDT 24
Peak memory 199504 kb
Host smart-13865b38-ef53-4d94-a2bb-adb8f7adb0a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225085734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1225085734
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2170547464
Short name T126
Test name
Test status
Simulation time 40874910795 ps
CPU time 44.47 seconds
Started Jul 28 07:08:59 PM PDT 24
Finished Jul 28 07:09:44 PM PDT 24
Peak memory 200088 kb
Host smart-814e7f36-8305-448a-a149-31cee3340b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170547464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2170547464
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.4017338374
Short name T453
Test name
Test status
Simulation time 27744332283 ps
CPU time 37.15 seconds
Started Jul 28 07:08:54 PM PDT 24
Finished Jul 28 07:09:31 PM PDT 24
Peak memory 195916 kb
Host smart-dca4a6b0-a8a2-4793-aa8d-0f924456cf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017338374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.4017338374
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3183308302
Short name T776
Test name
Test status
Simulation time 510929817 ps
CPU time 1.63 seconds
Started Jul 28 07:08:55 PM PDT 24
Finished Jul 28 07:08:56 PM PDT 24
Peak memory 199616 kb
Host smart-0aa3688b-a3cc-426d-9dbd-9230a8615f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183308302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3183308302
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3399170337
Short name T360
Test name
Test status
Simulation time 29603138245 ps
CPU time 210.37 seconds
Started Jul 28 07:09:00 PM PDT 24
Finished Jul 28 07:12:31 PM PDT 24
Peak memory 208492 kb
Host smart-d9d01e65-bba0-4a31-8538-52ae58600745
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399170337 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3399170337
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.490205191
Short name T760
Test name
Test status
Simulation time 6846832925 ps
CPU time 7.1 seconds
Started Jul 28 07:08:58 PM PDT 24
Finished Jul 28 07:09:06 PM PDT 24
Peak memory 199484 kb
Host smart-93bbdbb2-ebd7-4ef4-a9ff-ec9a7650efec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490205191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.490205191
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2204883151
Short name T494
Test name
Test status
Simulation time 32635676442 ps
CPU time 54.39 seconds
Started Jul 28 07:08:55 PM PDT 24
Finished Jul 28 07:09:49 PM PDT 24
Peak memory 200116 kb
Host smart-88a74acf-e522-49c6-8d0b-5ea7b78a2e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204883151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2204883151
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.3055437899
Short name T1169
Test name
Test status
Simulation time 27839100 ps
CPU time 0.55 seconds
Started Jul 28 07:09:12 PM PDT 24
Finished Jul 28 07:09:12 PM PDT 24
Peak memory 195884 kb
Host smart-586f04ac-5fee-4bf0-bc3c-9a1f31164ca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055437899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.3055437899
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.1415150281
Short name T1029
Test name
Test status
Simulation time 185899669881 ps
CPU time 96.54 seconds
Started Jul 28 07:08:57 PM PDT 24
Finished Jul 28 07:10:34 PM PDT 24
Peak memory 200296 kb
Host smart-487f9a7b-7153-47f3-8b45-4f1565bfabb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415150281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.1415150281
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2907868519
Short name T917
Test name
Test status
Simulation time 126366099953 ps
CPU time 53.51 seconds
Started Jul 28 07:08:59 PM PDT 24
Finished Jul 28 07:09:52 PM PDT 24
Peak memory 200072 kb
Host smart-cb76bdd8-b574-4aed-a5e0-0c8704db4199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907868519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2907868519
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.61332613
Short name T664
Test name
Test status
Simulation time 95765117517 ps
CPU time 123.26 seconds
Started Jul 28 07:08:57 PM PDT 24
Finished Jul 28 07:11:01 PM PDT 24
Peak memory 200180 kb
Host smart-9e8ecacd-09d2-48a5-8bcc-c9aba412c849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61332613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.61332613
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2896616037
Short name T956
Test name
Test status
Simulation time 47415488491 ps
CPU time 75 seconds
Started Jul 28 07:09:02 PM PDT 24
Finished Jul 28 07:10:17 PM PDT 24
Peak memory 200180 kb
Host smart-8200d174-932e-42e0-a160-46cb5a9a2e8c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896616037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2896616037
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.812213410
Short name T963
Test name
Test status
Simulation time 168321899162 ps
CPU time 270.17 seconds
Started Jul 28 07:09:03 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200180 kb
Host smart-32e3b7f5-9605-4e37-acec-4556d19791a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=812213410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.812213410
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.363266964
Short name T658
Test name
Test status
Simulation time 8580833849 ps
CPU time 2.96 seconds
Started Jul 28 07:09:05 PM PDT 24
Finished Jul 28 07:09:08 PM PDT 24
Peak memory 200132 kb
Host smart-56497064-6462-4d49-8cbb-cd73739a7554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363266964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.363266964
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.542583574
Short name T942
Test name
Test status
Simulation time 74230476400 ps
CPU time 120.59 seconds
Started Jul 28 07:09:04 PM PDT 24
Finished Jul 28 07:11:04 PM PDT 24
Peak memory 208244 kb
Host smart-b3400f07-a4f8-4e25-b9ce-d617be45f2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542583574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.542583574
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.924888057
Short name T919
Test name
Test status
Simulation time 27551394161 ps
CPU time 1297.76 seconds
Started Jul 28 07:09:06 PM PDT 24
Finished Jul 28 07:30:44 PM PDT 24
Peak memory 200216 kb
Host smart-c86613ed-ab6f-4079-a6f0-f24c31a046d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=924888057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.924888057
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.145066713
Short name T561
Test name
Test status
Simulation time 1795059408 ps
CPU time 6.12 seconds
Started Jul 28 07:09:02 PM PDT 24
Finished Jul 28 07:09:09 PM PDT 24
Peak memory 198672 kb
Host smart-be3d7d2f-04c2-4c1c-ab69-4ed62b61fc60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145066713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.145066713
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.878526481
Short name T1116
Test name
Test status
Simulation time 8997709870 ps
CPU time 14.59 seconds
Started Jul 28 07:09:03 PM PDT 24
Finished Jul 28 07:09:18 PM PDT 24
Peak memory 199588 kb
Host smart-f5439583-2f41-49a6-b231-33de7fcdb393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878526481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.878526481
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2368625936
Short name T882
Test name
Test status
Simulation time 5579600929 ps
CPU time 4.35 seconds
Started Jul 28 07:09:04 PM PDT 24
Finished Jul 28 07:09:08 PM PDT 24
Peak memory 196704 kb
Host smart-ec6f407a-d316-49ae-8988-e4f59fa1434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368625936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2368625936
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.2135740840
Short name T1032
Test name
Test status
Simulation time 524753700 ps
CPU time 1.3 seconds
Started Jul 28 07:08:58 PM PDT 24
Finished Jul 28 07:08:59 PM PDT 24
Peak memory 199324 kb
Host smart-b63761cc-7cc6-407b-a2d6-d90ac8494c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135740840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.2135740840
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2872774948
Short name T61
Test name
Test status
Simulation time 26201959295 ps
CPU time 664.13 seconds
Started Jul 28 07:09:28 PM PDT 24
Finished Jul 28 07:20:33 PM PDT 24
Peak memory 216828 kb
Host smart-ca922cfd-bdf4-491e-bc60-b07f9c6dcb19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872774948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2872774948
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3976945045
Short name T384
Test name
Test status
Simulation time 673211255 ps
CPU time 1.89 seconds
Started Jul 28 07:09:03 PM PDT 24
Finished Jul 28 07:09:05 PM PDT 24
Peak memory 198576 kb
Host smart-3c9e3367-0c22-48ef-b546-c94b02624fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976945045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3976945045
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.4253253945
Short name T405
Test name
Test status
Simulation time 36388473036 ps
CPU time 18.34 seconds
Started Jul 28 07:08:58 PM PDT 24
Finished Jul 28 07:09:17 PM PDT 24
Peak memory 200148 kb
Host smart-bfbe680c-2b46-41b3-b3a1-74e02a6640fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253253945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.4253253945
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.237061014
Short name T724
Test name
Test status
Simulation time 13185726 ps
CPU time 0.55 seconds
Started Jul 28 07:09:20 PM PDT 24
Finished Jul 28 07:09:21 PM PDT 24
Peak memory 195532 kb
Host smart-ae5ac5aa-3ede-4f6d-a674-09364b65ea41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237061014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.237061014
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2741345846
Short name T401
Test name
Test status
Simulation time 28536039489 ps
CPU time 43.92 seconds
Started Jul 28 07:09:09 PM PDT 24
Finished Jul 28 07:09:53 PM PDT 24
Peak memory 200112 kb
Host smart-4b573c84-468f-4f91-89b6-4b2813b2efc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741345846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2741345846
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4062253062
Short name T943
Test name
Test status
Simulation time 150479563777 ps
CPU time 67.99 seconds
Started Jul 28 07:09:07 PM PDT 24
Finished Jul 28 07:10:15 PM PDT 24
Peak memory 200184 kb
Host smart-efd07ec4-3d0c-4e30-91d6-11b0dca1896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062253062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4062253062
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_intr.3427063237
Short name T477
Test name
Test status
Simulation time 19923441078 ps
CPU time 30.13 seconds
Started Jul 28 07:09:15 PM PDT 24
Finished Jul 28 07:09:45 PM PDT 24
Peak memory 200160 kb
Host smart-a6524bb3-cbe5-4a69-bfc1-a97b7a4ff96f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427063237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.3427063237
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2035292162
Short name T813
Test name
Test status
Simulation time 96369352426 ps
CPU time 639.75 seconds
Started Jul 28 07:09:18 PM PDT 24
Finished Jul 28 07:19:58 PM PDT 24
Peak memory 200164 kb
Host smart-ad6e21d7-a1db-4cde-aa2b-c6e63329d7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2035292162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2035292162
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.466897653
Short name T425
Test name
Test status
Simulation time 10198455434 ps
CPU time 8.61 seconds
Started Jul 28 07:09:16 PM PDT 24
Finished Jul 28 07:09:25 PM PDT 24
Peak memory 200204 kb
Host smart-fd97c477-b128-4d5b-879c-095913acf5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466897653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.466897653
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.700283749
Short name T685
Test name
Test status
Simulation time 138804749701 ps
CPU time 113.49 seconds
Started Jul 28 07:09:15 PM PDT 24
Finished Jul 28 07:11:09 PM PDT 24
Peak memory 208452 kb
Host smart-aeb523a0-19f8-4b96-b8ad-f9458ec3a264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700283749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.700283749
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.2623507931
Short name T967
Test name
Test status
Simulation time 30826342128 ps
CPU time 146.61 seconds
Started Jul 28 07:09:18 PM PDT 24
Finished Jul 28 07:11:45 PM PDT 24
Peak memory 200064 kb
Host smart-39b01169-46b7-45d9-8a82-ef023f8131bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2623507931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.2623507931
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3167866855
Short name T570
Test name
Test status
Simulation time 6261317461 ps
CPU time 15.29 seconds
Started Jul 28 07:09:18 PM PDT 24
Finished Jul 28 07:09:33 PM PDT 24
Peak memory 198284 kb
Host smart-e1367463-14f1-49cc-8656-61acd4576628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3167866855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3167866855
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1799987070
Short name T305
Test name
Test status
Simulation time 48394950370 ps
CPU time 67.59 seconds
Started Jul 28 07:09:18 PM PDT 24
Finished Jul 28 07:10:25 PM PDT 24
Peak memory 200116 kb
Host smart-bc847de4-953b-4f3e-999a-c979c5205f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799987070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1799987070
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.558821414
Short name T558
Test name
Test status
Simulation time 37298501539 ps
CPU time 55.71 seconds
Started Jul 28 07:09:15 PM PDT 24
Finished Jul 28 07:10:11 PM PDT 24
Peak memory 196240 kb
Host smart-966444ac-c7cb-490b-abda-2bddb0eb266d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558821414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.558821414
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.4007662791
Short name T880
Test name
Test status
Simulation time 671760100 ps
CPU time 1.8 seconds
Started Jul 28 07:09:08 PM PDT 24
Finished Jul 28 07:09:10 PM PDT 24
Peak memory 200028 kb
Host smart-76f8654c-2f5f-4719-bc50-9f39ed49b1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007662791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.4007662791
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3131372149
Short name T1156
Test name
Test status
Simulation time 63271398804 ps
CPU time 109.39 seconds
Started Jul 28 07:09:19 PM PDT 24
Finished Jul 28 07:11:08 PM PDT 24
Peak memory 216528 kb
Host smart-127af1dd-8c90-494d-83a7-aea7e7c568e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131372149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3131372149
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1167564202
Short name T636
Test name
Test status
Simulation time 6789456148 ps
CPU time 18.85 seconds
Started Jul 28 07:09:15 PM PDT 24
Finished Jul 28 07:09:34 PM PDT 24
Peak memory 200148 kb
Host smart-35d0ca4e-692f-4459-9421-83b8a231a007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167564202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1167564202
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.257834656
Short name T430
Test name
Test status
Simulation time 42935631969 ps
CPU time 77.14 seconds
Started Jul 28 07:09:10 PM PDT 24
Finished Jul 28 07:10:27 PM PDT 24
Peak memory 200136 kb
Host smart-02b5a181-06e8-4111-a711-cb838c09f9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257834656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.257834656
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.352302310
Short name T1112
Test name
Test status
Simulation time 29521468 ps
CPU time 0.58 seconds
Started Jul 28 07:09:28 PM PDT 24
Finished Jul 28 07:09:29 PM PDT 24
Peak memory 195840 kb
Host smart-10cc3b67-8822-4e85-94fc-d6b98839b984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352302310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.352302310
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4290483797
Short name T308
Test name
Test status
Simulation time 88787534461 ps
CPU time 73.84 seconds
Started Jul 28 07:09:19 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 200180 kb
Host smart-e7008c01-b9bd-4862-b211-9ac6f660ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290483797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4290483797
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.4216105420
Short name T635
Test name
Test status
Simulation time 135232645249 ps
CPU time 100.95 seconds
Started Jul 28 07:09:19 PM PDT 24
Finished Jul 28 07:11:01 PM PDT 24
Peak memory 200212 kb
Host smart-6ca603b7-84c3-461d-8c91-734017b6310c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216105420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.4216105420
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.216985683
Short name T852
Test name
Test status
Simulation time 24775435536 ps
CPU time 40.73 seconds
Started Jul 28 07:09:19 PM PDT 24
Finished Jul 28 07:10:00 PM PDT 24
Peak memory 200108 kb
Host smart-db4c77dd-ee5c-4064-907b-fbc724ad130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216985683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.216985683
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.118722939
Short name T1065
Test name
Test status
Simulation time 68774439466 ps
CPU time 117.24 seconds
Started Jul 28 07:09:23 PM PDT 24
Finished Jul 28 07:11:20 PM PDT 24
Peak memory 199920 kb
Host smart-20ee861e-0e15-4c3b-8a59-bac6b55f9ddf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118722939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.118722939
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3323743293
Short name T821
Test name
Test status
Simulation time 36793250139 ps
CPU time 227.37 seconds
Started Jul 28 07:09:29 PM PDT 24
Finished Jul 28 07:13:17 PM PDT 24
Peak memory 200188 kb
Host smart-03a2ae66-1998-4cea-a274-9edd2f8f042d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3323743293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3323743293
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1598951047
Short name T586
Test name
Test status
Simulation time 3563732936 ps
CPU time 3 seconds
Started Jul 28 07:09:24 PM PDT 24
Finished Jul 28 07:09:27 PM PDT 24
Peak memory 199200 kb
Host smart-93bde3ea-2ef8-41d3-a2c3-3bcff13755a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598951047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1598951047
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3973517459
Short name T7
Test name
Test status
Simulation time 52523422658 ps
CPU time 22.88 seconds
Started Jul 28 07:09:25 PM PDT 24
Finished Jul 28 07:09:48 PM PDT 24
Peak memory 200184 kb
Host smart-37873e5f-e5f7-4ad5-ba9e-7cdcf7f30758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973517459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3973517459
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2435967040
Short name T596
Test name
Test status
Simulation time 25366733685 ps
CPU time 135.83 seconds
Started Jul 28 07:09:28 PM PDT 24
Finished Jul 28 07:11:44 PM PDT 24
Peak memory 200164 kb
Host smart-7f3df3f2-9619-479e-8388-4672190398a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2435967040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2435967040
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4097020805
Short name T383
Test name
Test status
Simulation time 2129830789 ps
CPU time 15.37 seconds
Started Jul 28 07:09:23 PM PDT 24
Finished Jul 28 07:09:39 PM PDT 24
Peak memory 198344 kb
Host smart-f99b215b-64d2-4f8e-ae60-6db4df172a1e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097020805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4097020805
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1766467995
Short name T45
Test name
Test status
Simulation time 40782631382 ps
CPU time 14.37 seconds
Started Jul 28 07:09:24 PM PDT 24
Finished Jul 28 07:09:39 PM PDT 24
Peak memory 198744 kb
Host smart-cd0be09c-151d-44d3-9f83-73c8db615a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766467995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1766467995
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2527387176
Short name T461
Test name
Test status
Simulation time 1886010328 ps
CPU time 1.63 seconds
Started Jul 28 07:09:24 PM PDT 24
Finished Jul 28 07:09:25 PM PDT 24
Peak memory 195744 kb
Host smart-09f8467f-c0ae-4474-9e30-a267fe052683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527387176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2527387176
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.1279464894
Short name T80
Test name
Test status
Simulation time 5329769062 ps
CPU time 7.37 seconds
Started Jul 28 07:09:19 PM PDT 24
Finished Jul 28 07:09:27 PM PDT 24
Peak memory 199520 kb
Host smart-fb740384-822a-484d-98f9-089f5df123e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279464894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.1279464894
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1792427163
Short name T688
Test name
Test status
Simulation time 319073263898 ps
CPU time 105.08 seconds
Started Jul 28 07:09:30 PM PDT 24
Finished Jul 28 07:11:15 PM PDT 24
Peak memory 200200 kb
Host smart-94a018ae-0fda-45d8-8041-accf88a25622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792427163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1792427163
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1218920379
Short name T1161
Test name
Test status
Simulation time 784544423 ps
CPU time 1.51 seconds
Started Jul 28 07:09:23 PM PDT 24
Finished Jul 28 07:09:25 PM PDT 24
Peak memory 198992 kb
Host smart-577700e0-cac8-4ef7-9f60-440818037b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218920379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1218920379
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.3438638881
Short name T400
Test name
Test status
Simulation time 28117771521 ps
CPU time 11.03 seconds
Started Jul 28 07:09:21 PM PDT 24
Finished Jul 28 07:09:32 PM PDT 24
Peak memory 197960 kb
Host smart-944b4650-bbf1-45dc-82d0-7f7a1386b746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438638881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.3438638881
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1465936669
Short name T597
Test name
Test status
Simulation time 20783496 ps
CPU time 0.53 seconds
Started Jul 28 07:09:40 PM PDT 24
Finished Jul 28 07:09:41 PM PDT 24
Peak memory 194456 kb
Host smart-9c6dbfa7-5a50-4e15-a406-07228ecb2118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465936669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1465936669
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1097926425
Short name T592
Test name
Test status
Simulation time 65737628424 ps
CPU time 33.18 seconds
Started Jul 28 07:09:27 PM PDT 24
Finished Jul 28 07:10:01 PM PDT 24
Peak memory 200152 kb
Host smart-f38e82a4-b395-437c-be80-239198df507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097926425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1097926425
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.295895008
Short name T1178
Test name
Test status
Simulation time 109118099162 ps
CPU time 35.57 seconds
Started Jul 28 07:09:26 PM PDT 24
Finished Jul 28 07:10:01 PM PDT 24
Peak memory 200220 kb
Host smart-1e6709ee-268e-49aa-a51f-a11dc731da8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295895008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.295895008
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1661580465
Short name T752
Test name
Test status
Simulation time 15454056971 ps
CPU time 6.66 seconds
Started Jul 28 07:09:29 PM PDT 24
Finished Jul 28 07:09:36 PM PDT 24
Peak memory 199772 kb
Host smart-25670cf5-3b2d-4252-a2ef-b513007f366d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661580465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1661580465
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1495787797
Short name T718
Test name
Test status
Simulation time 108118067820 ps
CPU time 181.07 seconds
Started Jul 28 07:09:37 PM PDT 24
Finished Jul 28 07:12:38 PM PDT 24
Peak memory 200172 kb
Host smart-78f97ebf-f44d-4a2c-932f-9b69e2ce262c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495787797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1495787797
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.3589266844
Short name T649
Test name
Test status
Simulation time 81537272613 ps
CPU time 415.93 seconds
Started Jul 28 07:09:38 PM PDT 24
Finished Jul 28 07:16:34 PM PDT 24
Peak memory 200160 kb
Host smart-6f4043a8-d18e-4d1b-bbb8-06873fc9a088
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589266844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.3589266844
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.3526270740
Short name T363
Test name
Test status
Simulation time 11304060010 ps
CPU time 19.04 seconds
Started Jul 28 07:09:42 PM PDT 24
Finished Jul 28 07:10:01 PM PDT 24
Peak memory 199704 kb
Host smart-dce31b20-384b-4555-b508-48e6803583d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526270740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3526270740
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3885619909
Short name T532
Test name
Test status
Simulation time 149144054619 ps
CPU time 72.07 seconds
Started Jul 28 07:09:35 PM PDT 24
Finished Jul 28 07:10:47 PM PDT 24
Peak memory 200104 kb
Host smart-b27c2554-502e-40e4-8a04-79722c2e225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885619909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3885619909
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.3233818375
Short name T518
Test name
Test status
Simulation time 16914865814 ps
CPU time 350.35 seconds
Started Jul 28 07:09:37 PM PDT 24
Finished Jul 28 07:15:27 PM PDT 24
Peak memory 200204 kb
Host smart-277f6e9d-98f5-4717-9ce6-21a93cb47616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3233818375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3233818375
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3783661369
Short name T553
Test name
Test status
Simulation time 5157878868 ps
CPU time 41.55 seconds
Started Jul 28 07:09:35 PM PDT 24
Finished Jul 28 07:10:16 PM PDT 24
Peak memory 198308 kb
Host smart-78b00b78-20b7-4816-9055-ec5c5142644b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783661369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3783661369
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3553476595
Short name T152
Test name
Test status
Simulation time 48223408694 ps
CPU time 36.29 seconds
Started Jul 28 07:09:41 PM PDT 24
Finished Jul 28 07:10:17 PM PDT 24
Peak memory 200116 kb
Host smart-a345a9c8-4a2b-446e-ad63-1db42fc7a0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553476595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3553476595
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.1556538750
Short name T580
Test name
Test status
Simulation time 5987933215 ps
CPU time 9.51 seconds
Started Jul 28 07:09:38 PM PDT 24
Finished Jul 28 07:09:48 PM PDT 24
Peak memory 196680 kb
Host smart-98aed0b9-a5c2-47c2-97bd-ccc2df148e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556538750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1556538750
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2377520792
Short name T842
Test name
Test status
Simulation time 6288494842 ps
CPU time 7.74 seconds
Started Jul 28 07:09:28 PM PDT 24
Finished Jul 28 07:09:36 PM PDT 24
Peak memory 200092 kb
Host smart-b03f6f4f-f364-4ce6-a8d7-94f9f5a7f88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377520792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2377520792
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3407338833
Short name T118
Test name
Test status
Simulation time 492306870433 ps
CPU time 338.42 seconds
Started Jul 28 07:09:39 PM PDT 24
Finished Jul 28 07:15:17 PM PDT 24
Peak memory 200168 kb
Host smart-7f6c76ef-2026-44d0-9777-bd47143a8418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407338833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3407338833
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4083637306
Short name T39
Test name
Test status
Simulation time 66534274014 ps
CPU time 454.81 seconds
Started Jul 28 07:09:41 PM PDT 24
Finished Jul 28 07:17:16 PM PDT 24
Peak memory 216664 kb
Host smart-64c0cee8-c1f6-4d3c-9af3-d51a20aa8657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083637306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4083637306
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.993557230
Short name T113
Test name
Test status
Simulation time 1453116387 ps
CPU time 1.72 seconds
Started Jul 28 07:09:41 PM PDT 24
Finished Jul 28 07:09:43 PM PDT 24
Peak memory 199300 kb
Host smart-8b6c2f94-3161-4bd3-8445-43c518992b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993557230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.993557230
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.2149088854
Short name T896
Test name
Test status
Simulation time 147531238383 ps
CPU time 63.91 seconds
Started Jul 28 07:09:29 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 200140 kb
Host smart-888b5091-9fb6-4163-aa8c-0a3c909ab632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149088854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.2149088854
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.84635831
Short name T1001
Test name
Test status
Simulation time 16924855 ps
CPU time 0.55 seconds
Started Jul 28 07:04:46 PM PDT 24
Finished Jul 28 07:04:47 PM PDT 24
Peak memory 194592 kb
Host smart-1f5fa89d-11f9-4f76-82e9-61515683778e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84635831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.84635831
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3535223970
Short name T715
Test name
Test status
Simulation time 34177866473 ps
CPU time 45.95 seconds
Started Jul 28 07:04:43 PM PDT 24
Finished Jul 28 07:05:29 PM PDT 24
Peak memory 200064 kb
Host smart-78c0d267-907d-4f27-a9c1-7ea0437c397b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535223970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3535223970
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.1045072539
Short name T660
Test name
Test status
Simulation time 115644182934 ps
CPU time 179.47 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:07:43 PM PDT 24
Peak memory 200032 kb
Host smart-d1d73c30-ff24-43b0-9d08-c4061ceca21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045072539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1045072539
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3738755076
Short name T701
Test name
Test status
Simulation time 33729560006 ps
CPU time 28.39 seconds
Started Jul 28 07:04:46 PM PDT 24
Finished Jul 28 07:05:14 PM PDT 24
Peak memory 200160 kb
Host smart-2401f80f-8847-43d5-afa8-d962fa38ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738755076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3738755076
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1512995282
Short name T904
Test name
Test status
Simulation time 10986624893 ps
CPU time 10.06 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:04:55 PM PDT 24
Peak memory 200116 kb
Host smart-d3890023-acc9-49db-b2bf-8b57857d3bc6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512995282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1512995282
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.4044379867
Short name T877
Test name
Test status
Simulation time 63263339258 ps
CPU time 265.14 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:09:07 PM PDT 24
Peak memory 200136 kb
Host smart-ae93c16d-a905-4b60-9268-a02ffea52e61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044379867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.4044379867
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.2259212006
Short name T876
Test name
Test status
Simulation time 7065476487 ps
CPU time 12.81 seconds
Started Jul 28 07:04:43 PM PDT 24
Finished Jul 28 07:04:56 PM PDT 24
Peak memory 199684 kb
Host smart-2be882a3-2c69-4856-bf6d-9a73164dcbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259212006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2259212006
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.558047376
Short name T1064
Test name
Test status
Simulation time 129396522310 ps
CPU time 57.15 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:05:39 PM PDT 24
Peak memory 208316 kb
Host smart-b8f37aaa-61b7-4c38-8239-f4b354a2e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558047376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.558047376
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1190303456
Short name T736
Test name
Test status
Simulation time 4153673874 ps
CPU time 210.69 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:08:15 PM PDT 24
Peak memory 200192 kb
Host smart-898e2c35-d3fb-48da-9c24-6333818a5282
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190303456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1190303456
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.2985130483
Short name T328
Test name
Test status
Simulation time 5447748621 ps
CPU time 3.86 seconds
Started Jul 28 07:04:41 PM PDT 24
Finished Jul 28 07:04:45 PM PDT 24
Peak memory 198340 kb
Host smart-d2252cc6-0b50-4c2d-aa12-5b139879f1da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985130483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.2985130483
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1701340807
Short name T391
Test name
Test status
Simulation time 114057770047 ps
CPU time 49.19 seconds
Started Jul 28 07:04:43 PM PDT 24
Finished Jul 28 07:05:33 PM PDT 24
Peak memory 200180 kb
Host smart-83d62f7c-5c4a-4e7b-9719-e4e07747560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701340807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1701340807
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1917341275
Short name T347
Test name
Test status
Simulation time 4704983568 ps
CPU time 4.72 seconds
Started Jul 28 07:04:48 PM PDT 24
Finished Jul 28 07:04:53 PM PDT 24
Peak memory 196376 kb
Host smart-0c9c8ea4-4735-45db-9b5b-17c6439f85c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917341275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1917341275
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2073747923
Short name T31
Test name
Test status
Simulation time 131074988 ps
CPU time 0.74 seconds
Started Jul 28 07:04:41 PM PDT 24
Finished Jul 28 07:04:42 PM PDT 24
Peak memory 218336 kb
Host smart-41adb720-58a4-4927-a44a-206a274b9b4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073747923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2073747923
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.2461075424
Short name T961
Test name
Test status
Simulation time 305474039 ps
CPU time 1.02 seconds
Started Jul 28 07:04:43 PM PDT 24
Finished Jul 28 07:04:45 PM PDT 24
Peak memory 198676 kb
Host smart-67d21dec-6f65-4209-8930-3cf98b68cb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461075424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.2461075424
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2845936835
Short name T485
Test name
Test status
Simulation time 1113317692915 ps
CPU time 668.2 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:15:52 PM PDT 24
Peak memory 200116 kb
Host smart-2cd356d3-eb0b-4b5c-9fe6-933ee00cf8a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845936835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2845936835
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.72247751
Short name T62
Test name
Test status
Simulation time 47827877573 ps
CPU time 493.17 seconds
Started Jul 28 07:04:44 PM PDT 24
Finished Jul 28 07:12:57 PM PDT 24
Peak memory 211156 kb
Host smart-207c6c5b-1266-4c8f-9f55-d0b904bb198f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72247751 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.72247751
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.4077496322
Short name T78
Test name
Test status
Simulation time 548326392 ps
CPU time 1.95 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:04:44 PM PDT 24
Peak memory 198896 kb
Host smart-ff3bd0e2-a489-4d8a-bc86-2088bc4f0538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077496322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.4077496322
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2130893030
Short name T41
Test name
Test status
Simulation time 122605533118 ps
CPU time 32.71 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:05:15 PM PDT 24
Peak memory 200176 kb
Host smart-ed557e24-8424-45ef-88ae-1ec1259fdabb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130893030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2130893030
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2241267338
Short name T638
Test name
Test status
Simulation time 16782340 ps
CPU time 0.55 seconds
Started Jul 28 07:09:50 PM PDT 24
Finished Jul 28 07:09:51 PM PDT 24
Peak memory 195852 kb
Host smart-53764e1a-5149-485a-a54d-1c153c4bb13d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241267338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2241267338
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3619305729
Short name T735
Test name
Test status
Simulation time 197017895219 ps
CPU time 68.42 seconds
Started Jul 28 07:09:39 PM PDT 24
Finished Jul 28 07:10:48 PM PDT 24
Peak memory 200184 kb
Host smart-747bec10-2030-41ea-b4b0-1a7795acfb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619305729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3619305729
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2058970804
Short name T762
Test name
Test status
Simulation time 292733516774 ps
CPU time 35.98 seconds
Started Jul 28 07:09:41 PM PDT 24
Finished Jul 28 07:10:17 PM PDT 24
Peak memory 200072 kb
Host smart-a65b6570-43e9-4f3f-a907-d93ad2d0c784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058970804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2058970804
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_intr.174400825
Short name T521
Test name
Test status
Simulation time 52875536299 ps
CPU time 40.17 seconds
Started Jul 28 07:09:44 PM PDT 24
Finished Jul 28 07:10:24 PM PDT 24
Peak memory 199180 kb
Host smart-c6e04321-9145-4089-a387-e6b938885828
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174400825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.174400825
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.4007504187
Short name T258
Test name
Test status
Simulation time 97938539713 ps
CPU time 285.19 seconds
Started Jul 28 07:09:48 PM PDT 24
Finished Jul 28 07:14:33 PM PDT 24
Peak memory 200156 kb
Host smart-c226952b-825e-41ab-816b-33bb6f3dbc8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4007504187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.4007504187
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2985613383
Short name T493
Test name
Test status
Simulation time 1473587377 ps
CPU time 3.19 seconds
Started Jul 28 07:09:44 PM PDT 24
Finished Jul 28 07:09:47 PM PDT 24
Peak memory 198652 kb
Host smart-93e5d565-7460-4c96-bb33-35b848d15220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985613383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2985613383
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1116338494
Short name T311
Test name
Test status
Simulation time 149631173395 ps
CPU time 61.66 seconds
Started Jul 28 07:09:43 PM PDT 24
Finished Jul 28 07:10:45 PM PDT 24
Peak memory 200316 kb
Host smart-64189ffa-6280-4f36-a8af-eefaee251e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116338494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1116338494
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.382542296
Short name T940
Test name
Test status
Simulation time 15439310849 ps
CPU time 228.28 seconds
Started Jul 28 07:09:49 PM PDT 24
Finished Jul 28 07:13:38 PM PDT 24
Peak memory 200188 kb
Host smart-55c6ab98-bf57-4ae3-860a-5a123ffd5d28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382542296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.382542296
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.4089227934
Short name T437
Test name
Test status
Simulation time 5659666957 ps
CPU time 23.7 seconds
Started Jul 28 07:09:44 PM PDT 24
Finished Jul 28 07:10:08 PM PDT 24
Peak memory 199360 kb
Host smart-0c6a4a09-deb5-4c32-8db9-3309782034c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089227934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.4089227934
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2620636274
Short name T526
Test name
Test status
Simulation time 106733756917 ps
CPU time 781.23 seconds
Started Jul 28 07:09:43 PM PDT 24
Finished Jul 28 07:22:45 PM PDT 24
Peak memory 200216 kb
Host smart-8f21f2ca-048a-463c-816c-b92e275e8e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620636274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2620636274
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.622261243
Short name T40
Test name
Test status
Simulation time 30555133352 ps
CPU time 5.65 seconds
Started Jul 28 07:09:43 PM PDT 24
Finished Jul 28 07:09:49 PM PDT 24
Peak memory 196192 kb
Host smart-718f685b-3d89-4e3a-97ed-c19d608b75a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622261243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.622261243
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.2336518326
Short name T653
Test name
Test status
Simulation time 129395342 ps
CPU time 0.84 seconds
Started Jul 28 07:09:40 PM PDT 24
Finished Jul 28 07:09:41 PM PDT 24
Peak memory 197152 kb
Host smart-6d711a26-0e7b-46a7-b86b-8369eb7a196e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336518326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.2336518326
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.760159587
Short name T178
Test name
Test status
Simulation time 511548298185 ps
CPU time 286.36 seconds
Started Jul 28 07:09:49 PM PDT 24
Finished Jul 28 07:14:35 PM PDT 24
Peak memory 200204 kb
Host smart-938f2f1a-d220-4190-bde9-281102842f19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760159587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.760159587
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.1714640066
Short name T1052
Test name
Test status
Simulation time 1586482536 ps
CPU time 2.15 seconds
Started Jul 28 07:09:44 PM PDT 24
Finished Jul 28 07:09:46 PM PDT 24
Peak memory 200136 kb
Host smart-dc09ca79-7830-432d-9b85-efdad8a6c0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714640066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1714640066
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.369772865
Short name T268
Test name
Test status
Simulation time 45304191265 ps
CPU time 71.2 seconds
Started Jul 28 07:09:42 PM PDT 24
Finished Jul 28 07:10:53 PM PDT 24
Peak memory 200212 kb
Host smart-d2f4ecdc-a432-4ed1-89af-8e291a8b2c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369772865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.369772865
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.1489216359
Short name T30
Test name
Test status
Simulation time 110011176 ps
CPU time 0.59 seconds
Started Jul 28 07:10:03 PM PDT 24
Finished Jul 28 07:10:04 PM PDT 24
Peak memory 195848 kb
Host smart-c961114a-5b7e-42e5-90e5-3087a4105bc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489216359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1489216359
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3722401726
Short name T475
Test name
Test status
Simulation time 94260231044 ps
CPU time 142.16 seconds
Started Jul 28 07:09:49 PM PDT 24
Finished Jul 28 07:12:12 PM PDT 24
Peak memory 200188 kb
Host smart-3e45c7f9-0a2f-4788-bf0b-05864e39eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722401726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3722401726
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2677990583
Short name T620
Test name
Test status
Simulation time 121832727878 ps
CPU time 52.25 seconds
Started Jul 28 07:09:48 PM PDT 24
Finished Jul 28 07:10:40 PM PDT 24
Peak memory 200116 kb
Host smart-d745e28e-a625-4172-b889-5c4f8ae08d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677990583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2677990583
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3696289070
Short name T172
Test name
Test status
Simulation time 34312297377 ps
CPU time 15.64 seconds
Started Jul 28 07:09:49 PM PDT 24
Finished Jul 28 07:10:04 PM PDT 24
Peak memory 200112 kb
Host smart-b6604908-22c3-456d-bdbb-a43f68029935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696289070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3696289070
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1403610528
Short name T15
Test name
Test status
Simulation time 39978227079 ps
CPU time 25.76 seconds
Started Jul 28 07:09:55 PM PDT 24
Finished Jul 28 07:10:20 PM PDT 24
Peak memory 199432 kb
Host smart-9cf8d678-67a4-4308-8de4-b2186312c819
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403610528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1403610528
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.849380893
Short name T668
Test name
Test status
Simulation time 82375554751 ps
CPU time 385.59 seconds
Started Jul 28 07:09:59 PM PDT 24
Finished Jul 28 07:16:25 PM PDT 24
Peak memory 200184 kb
Host smart-4c9fe744-a6e9-4011-824a-d1895dd747ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849380893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.849380893
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1817939659
Short name T342
Test name
Test status
Simulation time 1391160601 ps
CPU time 2.47 seconds
Started Jul 28 07:09:58 PM PDT 24
Finished Jul 28 07:10:00 PM PDT 24
Peak memory 199960 kb
Host smart-6b425881-ba75-4f0e-a3d0-0404eafa9c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817939659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1817939659
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1484545047
Short name T864
Test name
Test status
Simulation time 60857908030 ps
CPU time 103.64 seconds
Started Jul 28 07:09:55 PM PDT 24
Finished Jul 28 07:11:39 PM PDT 24
Peak memory 200296 kb
Host smart-ef36f266-7f97-411e-8caf-8d2a169325f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484545047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1484545047
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.665442249
Short name T566
Test name
Test status
Simulation time 8984531071 ps
CPU time 81.89 seconds
Started Jul 28 07:09:57 PM PDT 24
Finished Jul 28 07:11:19 PM PDT 24
Peak memory 200144 kb
Host smart-f0ec8eb3-f9dd-456c-90f0-81aa17a70a3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665442249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.665442249
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4101996811
Short name T469
Test name
Test status
Simulation time 4576735262 ps
CPU time 16.85 seconds
Started Jul 28 07:09:55 PM PDT 24
Finished Jul 28 07:10:12 PM PDT 24
Peak memory 198936 kb
Host smart-009af95f-72f2-4246-b153-a91e2f482c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4101996811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4101996811
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3170311559
Short name T1173
Test name
Test status
Simulation time 173260281005 ps
CPU time 100.55 seconds
Started Jul 28 07:09:52 PM PDT 24
Finished Jul 28 07:11:33 PM PDT 24
Peak memory 200156 kb
Host smart-62dde348-c167-4978-b706-3aec3a5a8017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170311559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3170311559
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2158458226
Short name T627
Test name
Test status
Simulation time 44056382024 ps
CPU time 33.18 seconds
Started Jul 28 07:09:54 PM PDT 24
Finished Jul 28 07:10:28 PM PDT 24
Peak memory 196292 kb
Host smart-d5a19547-d0b5-48f8-98be-7c36c795a036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158458226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2158458226
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1504337636
Short name T944
Test name
Test status
Simulation time 707397604 ps
CPU time 1.68 seconds
Started Jul 28 07:09:51 PM PDT 24
Finished Jul 28 07:09:52 PM PDT 24
Peak memory 198952 kb
Host smart-fb5efc67-a909-4914-853c-27ec01371d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504337636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1504337636
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2174404431
Short name T763
Test name
Test status
Simulation time 137392756477 ps
CPU time 483.58 seconds
Started Jul 28 07:10:08 PM PDT 24
Finished Jul 28 07:18:11 PM PDT 24
Peak memory 199996 kb
Host smart-e098bda2-9f6a-4d8d-a601-78072d103860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174404431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2174404431
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1711564078
Short name T759
Test name
Test status
Simulation time 132750738945 ps
CPU time 243.35 seconds
Started Jul 28 07:10:04 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 216232 kb
Host smart-db0fe62e-60c8-4bb4-a3d5-0fc2b67225b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711564078 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1711564078
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.581751830
Short name T966
Test name
Test status
Simulation time 419379407 ps
CPU time 1.65 seconds
Started Jul 28 07:09:57 PM PDT 24
Finished Jul 28 07:09:59 PM PDT 24
Peak memory 198716 kb
Host smart-24e63bde-b746-4205-a733-aeb3ebf33626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581751830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.581751830
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3598427232
Short name T1102
Test name
Test status
Simulation time 111702785203 ps
CPU time 44.75 seconds
Started Jul 28 07:09:49 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 200116 kb
Host smart-3121e152-24f7-4548-8d82-6283e9aaf99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598427232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3598427232
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.992308043
Short name T1097
Test name
Test status
Simulation time 19264470 ps
CPU time 0.55 seconds
Started Jul 28 07:10:07 PM PDT 24
Finished Jul 28 07:10:08 PM PDT 24
Peak memory 195776 kb
Host smart-b1886eda-b282-426c-9bff-bde4c426cca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992308043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.992308043
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2720555727
Short name T445
Test name
Test status
Simulation time 30874531976 ps
CPU time 39.87 seconds
Started Jul 28 07:10:00 PM PDT 24
Finished Jul 28 07:10:40 PM PDT 24
Peak memory 200184 kb
Host smart-723b35ac-3954-4d6c-ae75-58e05fc6fc1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720555727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2720555727
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.2134233703
Short name T958
Test name
Test status
Simulation time 12542950633 ps
CPU time 6.17 seconds
Started Jul 28 07:10:04 PM PDT 24
Finished Jul 28 07:10:11 PM PDT 24
Peak memory 199796 kb
Host smart-bcf08e8f-5a2a-4f6a-ad44-442e9071a44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134233703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.2134233703
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.1066526281
Short name T207
Test name
Test status
Simulation time 49285353339 ps
CPU time 66.85 seconds
Started Jul 28 07:10:06 PM PDT 24
Finished Jul 28 07:11:13 PM PDT 24
Peak memory 200000 kb
Host smart-8bcfc3ba-352c-4548-908b-9c39372a18e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066526281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1066526281
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.330695176
Short name T515
Test name
Test status
Simulation time 18446253630 ps
CPU time 7.43 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:10:18 PM PDT 24
Peak memory 197188 kb
Host smart-1cc8bc0a-f3dd-459e-891c-c1356142eb09
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330695176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.330695176
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1535492187
Short name T422
Test name
Test status
Simulation time 89770744411 ps
CPU time 438.42 seconds
Started Jul 28 07:10:08 PM PDT 24
Finished Jul 28 07:17:27 PM PDT 24
Peak memory 200120 kb
Host smart-da2cd8a5-dcf1-4de6-b7f7-5eaccf545c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1535492187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1535492187
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3277221720
Short name T1048
Test name
Test status
Simulation time 4054999254 ps
CPU time 4.89 seconds
Started Jul 28 07:10:12 PM PDT 24
Finished Jul 28 07:10:17 PM PDT 24
Peak memory 200076 kb
Host smart-106ffe2e-532b-4121-b3db-5402e97351cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277221720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3277221720
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.70561744
Short name T703
Test name
Test status
Simulation time 57922644274 ps
CPU time 92.7 seconds
Started Jul 28 07:10:09 PM PDT 24
Finished Jul 28 07:11:41 PM PDT 24
Peak memory 200168 kb
Host smart-4ef8298e-3eb5-4851-951e-d600329e1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70561744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.70561744
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.2136524993
Short name T895
Test name
Test status
Simulation time 15467027423 ps
CPU time 203.04 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:13:33 PM PDT 24
Peak memory 200068 kb
Host smart-a94c0abf-5007-4b9b-81e6-a8bad1e70fcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2136524993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.2136524993
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1545183434
Short name T977
Test name
Test status
Simulation time 3873371785 ps
CPU time 7.86 seconds
Started Jul 28 07:10:05 PM PDT 24
Finished Jul 28 07:10:13 PM PDT 24
Peak memory 198636 kb
Host smart-523a9679-041b-4d56-a856-79b7f8dbded2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1545183434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1545183434
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.127814341
Short name T167
Test name
Test status
Simulation time 20917873292 ps
CPU time 9.17 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:10:19 PM PDT 24
Peak memory 199992 kb
Host smart-c49a975b-12ff-4bd8-92e7-78a9dd6cd033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127814341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.127814341
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1260666284
Short name T719
Test name
Test status
Simulation time 5503822984 ps
CPU time 2.66 seconds
Started Jul 28 07:10:11 PM PDT 24
Finished Jul 28 07:10:14 PM PDT 24
Peak memory 196468 kb
Host smart-792c5fb3-fc5d-404c-b08f-bc1ab5fe74f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260666284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1260666284
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2851810823
Short name T429
Test name
Test status
Simulation time 5585246445 ps
CPU time 3.47 seconds
Started Jul 28 07:10:07 PM PDT 24
Finished Jul 28 07:10:11 PM PDT 24
Peak memory 199800 kb
Host smart-2cadf309-937e-4d83-8d75-c133e58d86e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851810823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2851810823
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3669191633
Short name T228
Test name
Test status
Simulation time 196275331911 ps
CPU time 98.94 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:11:49 PM PDT 24
Peak memory 200196 kb
Host smart-3607a234-6dc2-43f5-bc3c-a452934f1b33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669191633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3669191633
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3388120303
Short name T164
Test name
Test status
Simulation time 76038265729 ps
CPU time 889.51 seconds
Started Jul 28 07:10:09 PM PDT 24
Finished Jul 28 07:24:59 PM PDT 24
Peak memory 216652 kb
Host smart-9920a0c5-abca-4f17-b3e6-ad5dc72a742c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388120303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3388120303
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1532049040
Short name T1162
Test name
Test status
Simulation time 605145308 ps
CPU time 1.98 seconds
Started Jul 28 07:10:08 PM PDT 24
Finished Jul 28 07:10:11 PM PDT 24
Peak memory 199748 kb
Host smart-8b3b49d4-de38-4165-813f-cc799cd9d717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532049040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1532049040
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2004677639
Short name T898
Test name
Test status
Simulation time 77536279220 ps
CPU time 90.02 seconds
Started Jul 28 07:10:06 PM PDT 24
Finished Jul 28 07:11:36 PM PDT 24
Peak memory 200040 kb
Host smart-51f54374-4ca2-4401-9d47-53eece1a20f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004677639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2004677639
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.1551537977
Short name T659
Test name
Test status
Simulation time 24110357 ps
CPU time 0.56 seconds
Started Jul 28 07:10:22 PM PDT 24
Finished Jul 28 07:10:23 PM PDT 24
Peak memory 195720 kb
Host smart-09930a88-7904-472a-b461-2958b13697cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551537977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.1551537977
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1295127474
Short name T1106
Test name
Test status
Simulation time 74503184760 ps
CPU time 29.83 seconds
Started Jul 28 07:10:08 PM PDT 24
Finished Jul 28 07:10:38 PM PDT 24
Peak memory 200092 kb
Host smart-22664d18-59f9-4b39-af09-cb118858c50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295127474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1295127474
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2493307101
Short name T1069
Test name
Test status
Simulation time 23808903975 ps
CPU time 9.47 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:10:20 PM PDT 24
Peak memory 200100 kb
Host smart-8f182685-8a9c-47f5-9ec8-7bb1aa0627ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493307101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2493307101
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1285757237
Short name T897
Test name
Test status
Simulation time 39762957480 ps
CPU time 64.92 seconds
Started Jul 28 07:10:11 PM PDT 24
Finished Jul 28 07:11:16 PM PDT 24
Peak memory 200180 kb
Host smart-7d5d9be7-67f3-457c-8228-b8a6a7a1e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285757237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1285757237
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1349561206
Short name T1036
Test name
Test status
Simulation time 3052820466 ps
CPU time 5.24 seconds
Started Jul 28 07:10:15 PM PDT 24
Finished Jul 28 07:10:20 PM PDT 24
Peak memory 196816 kb
Host smart-7be8e47e-1e8d-4c0c-af9d-bab79717de2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349561206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1349561206
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3836588126
Short name T377
Test name
Test status
Simulation time 90487710148 ps
CPU time 259.76 seconds
Started Jul 28 07:10:14 PM PDT 24
Finished Jul 28 07:14:34 PM PDT 24
Peak memory 200168 kb
Host smart-c45f378b-3506-449a-ad66-a77c9e380220
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3836588126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3836588126
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1082007792
Short name T986
Test name
Test status
Simulation time 2845995386 ps
CPU time 5.37 seconds
Started Jul 28 07:10:14 PM PDT 24
Finished Jul 28 07:10:19 PM PDT 24
Peak memory 198952 kb
Host smart-50039ebd-eccc-46b9-b075-bbc675757fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082007792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1082007792
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.1482608901
Short name T389
Test name
Test status
Simulation time 58675209893 ps
CPU time 17.01 seconds
Started Jul 28 07:10:14 PM PDT 24
Finished Jul 28 07:10:32 PM PDT 24
Peak memory 199176 kb
Host smart-3305faba-2822-4526-a4f9-f7a984dbfb83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482608901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.1482608901
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1790599186
Short name T1057
Test name
Test status
Simulation time 8394632722 ps
CPU time 91.43 seconds
Started Jul 28 07:10:11 PM PDT 24
Finished Jul 28 07:11:43 PM PDT 24
Peak memory 200368 kb
Host smart-bc5ed470-adcf-431d-bc78-6d21f7d02026
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1790599186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1790599186
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3733730766
Short name T679
Test name
Test status
Simulation time 7498159708 ps
CPU time 17.42 seconds
Started Jul 28 07:10:08 PM PDT 24
Finished Jul 28 07:10:26 PM PDT 24
Peak memory 198016 kb
Host smart-5a4c5cfc-291b-41c7-a741-0224cf8a73f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733730766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3733730766
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.2032890887
Short name T53
Test name
Test status
Simulation time 103937893983 ps
CPU time 82.37 seconds
Started Jul 28 07:10:16 PM PDT 24
Finished Jul 28 07:11:38 PM PDT 24
Peak memory 200176 kb
Host smart-42ea1e6e-8eb3-47fe-a1ee-8a1321a71bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032890887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2032890887
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.882395916
Short name T788
Test name
Test status
Simulation time 1782001826 ps
CPU time 1.32 seconds
Started Jul 28 07:10:13 PM PDT 24
Finished Jul 28 07:10:14 PM PDT 24
Peak memory 195640 kb
Host smart-fe377f20-10aa-46cb-ba40-c792c38bc5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882395916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.882395916
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.694713103
Short name T651
Test name
Test status
Simulation time 6172754006 ps
CPU time 12.98 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:10:23 PM PDT 24
Peak memory 200200 kb
Host smart-0352f177-d1b3-4742-afcf-64b869fe9031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694713103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.694713103
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.3380927568
Short name T960
Test name
Test status
Simulation time 399699062854 ps
CPU time 290.86 seconds
Started Jul 28 07:10:21 PM PDT 24
Finished Jul 28 07:15:12 PM PDT 24
Peak memory 200124 kb
Host smart-c93396d3-4a2e-41cd-b669-39516a988d18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380927568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3380927568
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3256957306
Short name T734
Test name
Test status
Simulation time 202174783128 ps
CPU time 389.71 seconds
Started Jul 28 07:10:19 PM PDT 24
Finished Jul 28 07:16:49 PM PDT 24
Peak memory 216820 kb
Host smart-7f21513a-0360-44ac-beb2-549b46eef1e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256957306 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3256957306
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.769634520
Short name T583
Test name
Test status
Simulation time 1480165738 ps
CPU time 1.84 seconds
Started Jul 28 07:10:15 PM PDT 24
Finished Jul 28 07:10:17 PM PDT 24
Peak memory 199244 kb
Host smart-20466b65-37e0-4bae-97d5-2efd47370d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769634520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.769634520
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.912347722
Short name T687
Test name
Test status
Simulation time 45847884628 ps
CPU time 86.74 seconds
Started Jul 28 07:10:10 PM PDT 24
Finished Jul 28 07:11:36 PM PDT 24
Peak memory 200188 kb
Host smart-915a2424-0f20-4ded-b249-8ea558abd901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912347722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.912347722
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2533371908
Short name T460
Test name
Test status
Simulation time 23559218 ps
CPU time 0.56 seconds
Started Jul 28 07:10:26 PM PDT 24
Finished Jul 28 07:10:27 PM PDT 24
Peak memory 195792 kb
Host smart-08d94402-ca3a-46f1-b45a-647269110b11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533371908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2533371908
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.2352870607
Short name T581
Test name
Test status
Simulation time 94463363961 ps
CPU time 37.93 seconds
Started Jul 28 07:10:19 PM PDT 24
Finished Jul 28 07:10:57 PM PDT 24
Peak memory 200232 kb
Host smart-433e01f1-76a6-4465-9a8d-1f4ae8306efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352870607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.2352870607
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3017781806
Short name T1118
Test name
Test status
Simulation time 41967866384 ps
CPU time 55.93 seconds
Started Jul 28 07:10:26 PM PDT 24
Finished Jul 28 07:11:22 PM PDT 24
Peak memory 199996 kb
Host smart-b9c38126-ffc2-431e-b47b-c77568f4424c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017781806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3017781806
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.731000395
Short name T210
Test name
Test status
Simulation time 54933623596 ps
CPU time 40.23 seconds
Started Jul 28 07:10:25 PM PDT 24
Finished Jul 28 07:11:05 PM PDT 24
Peak memory 200188 kb
Host smart-c71f72db-bcee-4410-8e90-e3e0605361ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731000395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.731000395
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1584987413
Short name T379
Test name
Test status
Simulation time 27822029111 ps
CPU time 11.53 seconds
Started Jul 28 07:10:25 PM PDT 24
Finished Jul 28 07:10:36 PM PDT 24
Peak memory 198264 kb
Host smart-94d31b94-fa1c-4cb5-92bd-943938f38499
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584987413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1584987413
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2704923618
Short name T757
Test name
Test status
Simulation time 140665972020 ps
CPU time 1041.68 seconds
Started Jul 28 07:10:28 PM PDT 24
Finished Jul 28 07:27:50 PM PDT 24
Peak memory 200096 kb
Host smart-0633cc74-2c3b-4612-8605-8b179c808884
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2704923618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2704923618
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3061971759
Short name T326
Test name
Test status
Simulation time 5596598958 ps
CPU time 11.94 seconds
Started Jul 28 07:10:28 PM PDT 24
Finished Jul 28 07:10:40 PM PDT 24
Peak memory 200020 kb
Host smart-dda0d42a-bef0-4042-b095-26574a07651a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061971759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3061971759
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.2465870977
Short name T843
Test name
Test status
Simulation time 69110611775 ps
CPU time 115.31 seconds
Started Jul 28 07:10:27 PM PDT 24
Finished Jul 28 07:12:23 PM PDT 24
Peak memory 208340 kb
Host smart-e8949f87-474f-4fd1-bca5-46e8cfb55a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465870977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.2465870977
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.1124207019
Short name T992
Test name
Test status
Simulation time 8939594869 ps
CPU time 106.33 seconds
Started Jul 28 07:10:26 PM PDT 24
Finished Jul 28 07:12:12 PM PDT 24
Peak memory 200200 kb
Host smart-9032b21a-240a-4773-a8d2-31f32a37794a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1124207019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1124207019
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3929345858
Short name T476
Test name
Test status
Simulation time 1920945257 ps
CPU time 3.33 seconds
Started Jul 28 07:10:26 PM PDT 24
Finished Jul 28 07:10:29 PM PDT 24
Peak memory 198172 kb
Host smart-3c64f729-9143-419d-9304-b20df70df8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3929345858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3929345858
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1016961787
Short name T110
Test name
Test status
Simulation time 58451974042 ps
CPU time 179.14 seconds
Started Jul 28 07:10:27 PM PDT 24
Finished Jul 28 07:13:26 PM PDT 24
Peak memory 200060 kb
Host smart-d497d8be-1e03-4bb7-b14c-2d6d22c7fdea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016961787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1016961787
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1373205952
Short name T1009
Test name
Test status
Simulation time 2972186911 ps
CPU time 4.1 seconds
Started Jul 28 07:10:25 PM PDT 24
Finished Jul 28 07:10:30 PM PDT 24
Peak memory 196644 kb
Host smart-34820ff4-71b3-4be7-968b-0cd496885e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373205952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1373205952
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.2943385006
Short name T795
Test name
Test status
Simulation time 246821810 ps
CPU time 1.3 seconds
Started Jul 28 07:10:19 PM PDT 24
Finished Jul 28 07:10:21 PM PDT 24
Peak memory 198616 kb
Host smart-16b67797-29d5-479d-83d1-c125384da103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943385006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.2943385006
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2957067966
Short name T484
Test name
Test status
Simulation time 206048681100 ps
CPU time 625.85 seconds
Started Jul 28 07:10:24 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 200240 kb
Host smart-4d786878-b861-478f-87f4-6554b2ed76b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957067966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2957067966
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3050977623
Short name T306
Test name
Test status
Simulation time 63145361380 ps
CPU time 624.71 seconds
Started Jul 28 07:10:25 PM PDT 24
Finished Jul 28 07:20:50 PM PDT 24
Peak memory 216724 kb
Host smart-4ceaf46a-e929-4dc2-8ff2-d8b61fa0ee59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050977623 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3050977623
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2859127350
Short name T728
Test name
Test status
Simulation time 7665514234 ps
CPU time 11.04 seconds
Started Jul 28 07:10:25 PM PDT 24
Finished Jul 28 07:10:36 PM PDT 24
Peak memory 200164 kb
Host smart-bb093c87-0ad2-4b65-bdce-56c5b72f481e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859127350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2859127350
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.4134192130
Short name T918
Test name
Test status
Simulation time 150901330655 ps
CPU time 70.64 seconds
Started Jul 28 07:10:20 PM PDT 24
Finished Jul 28 07:11:31 PM PDT 24
Peak memory 200048 kb
Host smart-fa2414f0-ae6b-4413-b778-adc513bcbb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134192130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.4134192130
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.2876179976
Short name T378
Test name
Test status
Simulation time 30459706 ps
CPU time 0.58 seconds
Started Jul 28 07:10:42 PM PDT 24
Finished Jul 28 07:10:43 PM PDT 24
Peak memory 195488 kb
Host smart-17837429-9381-4ef6-b0aa-4cdd30421870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876179976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.2876179976
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.4221384332
Short name T166
Test name
Test status
Simulation time 34941049190 ps
CPU time 32.47 seconds
Started Jul 28 07:10:31 PM PDT 24
Finished Jul 28 07:11:04 PM PDT 24
Peak memory 200148 kb
Host smart-aa5197bd-fee5-411c-b26b-317724c18b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221384332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.4221384332
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.676688159
Short name T396
Test name
Test status
Simulation time 99017998072 ps
CPU time 78.7 seconds
Started Jul 28 07:10:31 PM PDT 24
Finished Jul 28 07:11:50 PM PDT 24
Peak memory 199952 kb
Host smart-f07ddf75-1be7-42eb-9c7d-ee6a9230c340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676688159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.676688159
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.16245915
Short name T1068
Test name
Test status
Simulation time 101429039722 ps
CPU time 29.58 seconds
Started Jul 28 07:10:32 PM PDT 24
Finished Jul 28 07:11:02 PM PDT 24
Peak memory 200120 kb
Host smart-28ee5777-7f06-47c7-810e-029a1cbd8322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16245915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.16245915
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.2510475948
Short name T851
Test name
Test status
Simulation time 49846151663 ps
CPU time 52.74 seconds
Started Jul 28 07:10:31 PM PDT 24
Finished Jul 28 07:11:23 PM PDT 24
Peak memory 200044 kb
Host smart-a119678f-f2ae-4aa6-ac93-d7c9aab82c17
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510475948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.2510475948
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.750444384
Short name T482
Test name
Test status
Simulation time 168054370625 ps
CPU time 822.44 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:24:19 PM PDT 24
Peak memory 200180 kb
Host smart-41076feb-ab49-4e6c-91d7-b803cd03a7e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750444384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.750444384
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1301423829
Short name T847
Test name
Test status
Simulation time 6644627657 ps
CPU time 12.75 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:10:49 PM PDT 24
Peak memory 200140 kb
Host smart-b6883a39-d037-4233-8002-dc32a02b7d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301423829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1301423829
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1754330424
Short name T1158
Test name
Test status
Simulation time 326350540932 ps
CPU time 34.8 seconds
Started Jul 28 07:10:37 PM PDT 24
Finished Jul 28 07:11:12 PM PDT 24
Peak memory 208432 kb
Host smart-0b179a7f-c9cb-41c0-bbb4-a6a5c9274fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754330424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1754330424
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3522732510
Short name T498
Test name
Test status
Simulation time 6585930274 ps
CPU time 109.74 seconds
Started Jul 28 07:10:37 PM PDT 24
Finished Jul 28 07:12:27 PM PDT 24
Peak memory 200052 kb
Host smart-8c52ce74-4faf-49fe-b754-b802ef587c7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522732510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3522732510
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2601226208
Short name T313
Test name
Test status
Simulation time 1719826491 ps
CPU time 1.91 seconds
Started Jul 28 07:10:31 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 198196 kb
Host smart-00c7a25e-9627-4b3e-ae9e-e5136759c0b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2601226208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2601226208
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3871142408
Short name T639
Test name
Test status
Simulation time 49719528497 ps
CPU time 38.28 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:11:15 PM PDT 24
Peak memory 200180 kb
Host smart-b7792d40-f3e2-46a6-afdf-7c0a3f951488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871142408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3871142408
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.730212191
Short name T514
Test name
Test status
Simulation time 42805313058 ps
CPU time 31.33 seconds
Started Jul 28 07:10:35 PM PDT 24
Finished Jul 28 07:11:07 PM PDT 24
Peak memory 196068 kb
Host smart-77792a50-68c5-40de-92a9-848fa894bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730212191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.730212191
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.2500366124
Short name T1131
Test name
Test status
Simulation time 125243266 ps
CPU time 1.22 seconds
Started Jul 28 07:10:31 PM PDT 24
Finished Jul 28 07:10:33 PM PDT 24
Peak memory 198668 kb
Host smart-452854e5-4385-4ae2-8537-8e8ed8fea5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500366124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.2500366124
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3397448770
Short name T1115
Test name
Test status
Simulation time 131040121119 ps
CPU time 202.68 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:13:59 PM PDT 24
Peak memory 200268 kb
Host smart-3dc89f1a-0ea8-4344-9731-f752ac6b864b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397448770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3397448770
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.3400039977
Short name T859
Test name
Test status
Simulation time 1255507119 ps
CPU time 3.31 seconds
Started Jul 28 07:10:36 PM PDT 24
Finished Jul 28 07:10:39 PM PDT 24
Peak memory 199440 kb
Host smart-c56610aa-e0c3-4ce5-a09d-755bc139a3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400039977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.3400039977
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1129947146
Short name T48
Test name
Test status
Simulation time 34812892389 ps
CPU time 24.55 seconds
Started Jul 28 07:10:29 PM PDT 24
Finished Jul 28 07:10:54 PM PDT 24
Peak memory 200128 kb
Host smart-389bdb49-c812-4c04-a4b7-5a36bf653b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129947146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1129947146
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1722973384
Short name T331
Test name
Test status
Simulation time 40924087 ps
CPU time 0.59 seconds
Started Jul 28 07:10:53 PM PDT 24
Finished Jul 28 07:10:54 PM PDT 24
Peak memory 195820 kb
Host smart-a8279710-9bcd-4377-a587-99876b5e7d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722973384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1722973384
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3846075248
Short name T829
Test name
Test status
Simulation time 173981873231 ps
CPU time 125.51 seconds
Started Jul 28 07:10:39 PM PDT 24
Finished Jul 28 07:12:44 PM PDT 24
Peak memory 200200 kb
Host smart-8bcad2ff-7f9c-40e3-ac79-ff0c59248907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846075248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3846075248
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.3616947193
Short name T1039
Test name
Test status
Simulation time 65995731436 ps
CPU time 48.61 seconds
Started Jul 28 07:10:47 PM PDT 24
Finished Jul 28 07:11:36 PM PDT 24
Peak memory 200156 kb
Host smart-23ce99d5-6e6c-4cde-840e-082ce746213f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616947193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.3616947193
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.913047504
Short name T1003
Test name
Test status
Simulation time 84489314786 ps
CPU time 120.47 seconds
Started Jul 28 07:10:41 PM PDT 24
Finished Jul 28 07:12:42 PM PDT 24
Peak memory 199860 kb
Host smart-26b5e830-eba9-4f4b-9dfe-252a495fcccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913047504 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.913047504
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.1901256968
Short name T289
Test name
Test status
Simulation time 20649996158 ps
CPU time 36.01 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:11:28 PM PDT 24
Peak memory 200120 kb
Host smart-3a91ec57-5fb9-4c77-8455-e49951fd3012
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901256968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.1901256968
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_loopback.1746379209
Short name T878
Test name
Test status
Simulation time 10216150925 ps
CPU time 17.97 seconds
Started Jul 28 07:10:48 PM PDT 24
Finished Jul 28 07:11:06 PM PDT 24
Peak memory 199468 kb
Host smart-968751fb-3865-464f-8462-46abcb30c040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746379209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1746379209
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3442280123
Short name T998
Test name
Test status
Simulation time 51369687978 ps
CPU time 41.68 seconds
Started Jul 28 07:10:47 PM PDT 24
Finished Jul 28 07:11:28 PM PDT 24
Peak memory 199708 kb
Host smart-2841d7f9-1546-4ba5-b688-41ae543a3efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442280123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3442280123
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1770174098
Short name T833
Test name
Test status
Simulation time 11819908329 ps
CPU time 188.12 seconds
Started Jul 28 07:10:46 PM PDT 24
Finished Jul 28 07:13:54 PM PDT 24
Peak memory 200132 kb
Host smart-00d0c4c8-d18d-40ed-9c67-31cb53649224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770174098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1770174098
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.31552379
Short name T1153
Test name
Test status
Simulation time 3620589063 ps
CPU time 25.78 seconds
Started Jul 28 07:10:48 PM PDT 24
Finished Jul 28 07:11:14 PM PDT 24
Peak memory 198228 kb
Host smart-286a7a8d-aeef-40ad-ac56-d02ae4416d05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=31552379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.31552379
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.465174142
Short name T140
Test name
Test status
Simulation time 48367378401 ps
CPU time 18.28 seconds
Started Jul 28 07:10:44 PM PDT 24
Finished Jul 28 07:11:02 PM PDT 24
Peak memory 200032 kb
Host smart-b5fa9b4a-2aee-48b9-a54c-d4ea866cf3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465174142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.465174142
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.738747595
Short name T432
Test name
Test status
Simulation time 5314095090 ps
CPU time 5.81 seconds
Started Jul 28 07:10:51 PM PDT 24
Finished Jul 28 07:10:56 PM PDT 24
Peak memory 196680 kb
Host smart-e5368a05-e587-44d8-9d1f-83a7ab13f41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738747595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.738747595
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.168075701
Short name T865
Test name
Test status
Simulation time 955809363 ps
CPU time 1.98 seconds
Started Jul 28 07:10:41 PM PDT 24
Finished Jul 28 07:10:43 PM PDT 24
Peak memory 198504 kb
Host smart-f51f90d7-c3cd-490e-b883-466ea2d01fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168075701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.168075701
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.3536010740
Short name T388
Test name
Test status
Simulation time 68218682940 ps
CPU time 572.82 seconds
Started Jul 28 07:10:46 PM PDT 24
Finished Jul 28 07:20:19 PM PDT 24
Peak memory 216748 kb
Host smart-1f80796b-99be-43ef-b461-c37044be90e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536010740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.3536010740
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.887809602
Short name T295
Test name
Test status
Simulation time 1822328845 ps
CPU time 3.83 seconds
Started Jul 28 07:10:47 PM PDT 24
Finished Jul 28 07:10:51 PM PDT 24
Peak memory 198540 kb
Host smart-b5e55f03-62fb-40ff-879b-5a978c0755bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887809602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.887809602
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2346369463
Short name T264
Test name
Test status
Simulation time 15104969059 ps
CPU time 23.78 seconds
Started Jul 28 07:10:41 PM PDT 24
Finished Jul 28 07:11:05 PM PDT 24
Peak memory 200180 kb
Host smart-35e3d170-f583-42cc-b923-1e482b40acf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346369463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2346369463
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3149541040
Short name T82
Test name
Test status
Simulation time 11486356 ps
CPU time 0.54 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:10:52 PM PDT 24
Peak memory 194528 kb
Host smart-b03154b1-9881-4b79-9499-7a8833c55b49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149541040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3149541040
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3983223475
Short name T746
Test name
Test status
Simulation time 32653509032 ps
CPU time 50.55 seconds
Started Jul 28 07:10:53 PM PDT 24
Finished Jul 28 07:11:44 PM PDT 24
Peak memory 200040 kb
Host smart-bf7e67b3-3453-4af2-bf83-8d82894f2871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983223475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3983223475
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3802341846
Short name T633
Test name
Test status
Simulation time 29035892818 ps
CPU time 51.55 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:11:51 PM PDT 24
Peak memory 200116 kb
Host smart-a7683eb7-8c3d-4d52-aa21-0d82cd397389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802341846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3802341846
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2275412174
Short name T76
Test name
Test status
Simulation time 16018131369 ps
CPU time 29.49 seconds
Started Jul 28 07:10:51 PM PDT 24
Finished Jul 28 07:11:21 PM PDT 24
Peak memory 200172 kb
Host smart-85a44a19-6e65-4794-ada3-e116b998176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275412174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2275412174
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3339897440
Short name T309
Test name
Test status
Simulation time 28518667198 ps
CPU time 46.45 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:11:39 PM PDT 24
Peak memory 200112 kb
Host smart-c27a65c0-5f01-4d6a-a32d-0e4181365256
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339897440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3339897440
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.30140920
Short name T1100
Test name
Test status
Simulation time 183329815497 ps
CPU time 1061.25 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:28:33 PM PDT 24
Peak memory 200120 kb
Host smart-defb055b-d02a-4695-8b26-b020b7929be6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=30140920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.30140920
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3480352593
Short name T1130
Test name
Test status
Simulation time 7925484388 ps
CPU time 4.12 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:11:04 PM PDT 24
Peak memory 200104 kb
Host smart-62f2486e-e5c3-4d1a-9530-b69058b63b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480352593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3480352593
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.4176520865
Short name T671
Test name
Test status
Simulation time 64964531384 ps
CPU time 22.22 seconds
Started Jul 28 07:10:58 PM PDT 24
Finished Jul 28 07:11:20 PM PDT 24
Peak memory 199500 kb
Host smart-42fa1caa-903e-49ce-a86a-17d9e7841489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176520865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.4176520865
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.2095150641
Short name T443
Test name
Test status
Simulation time 20779450770 ps
CPU time 210.35 seconds
Started Jul 28 07:10:53 PM PDT 24
Finished Jul 28 07:14:24 PM PDT 24
Peak memory 200160 kb
Host smart-a5d36705-14fb-4f7f-a581-94e8f26425a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2095150641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.2095150641
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3663116865
Short name T1185
Test name
Test status
Simulation time 2862101014 ps
CPU time 5.39 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:10:58 PM PDT 24
Peak memory 198324 kb
Host smart-7c339b68-4888-4ce4-ab8c-5b0e201a37c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3663116865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3663116865
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3521001508
Short name T371
Test name
Test status
Simulation time 34403256413 ps
CPU time 14.91 seconds
Started Jul 28 07:10:58 PM PDT 24
Finished Jul 28 07:11:13 PM PDT 24
Peak memory 200008 kb
Host smart-917cd1bc-711c-437d-8348-2a5fa6b4f49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521001508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3521001508
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.567451029
Short name T282
Test name
Test status
Simulation time 4238197008 ps
CPU time 2.11 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:10:54 PM PDT 24
Peak memory 196296 kb
Host smart-f70914db-ccf1-4175-b4f7-0ada000e6bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567451029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.567451029
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.3742725112
Short name T937
Test name
Test status
Simulation time 565316112 ps
CPU time 1.42 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:10:53 PM PDT 24
Peak memory 198656 kb
Host smart-69d83ec3-5940-4c39-afff-36a7a2ff46e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742725112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.3742725112
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.2745140260
Short name T805
Test name
Test status
Simulation time 227682684312 ps
CPU time 300.25 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:16:00 PM PDT 24
Peak memory 208464 kb
Host smart-c40d3102-9592-490b-bd08-5c7454919344
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745140260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.2745140260
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1644470763
Short name T706
Test name
Test status
Simulation time 44769908174 ps
CPU time 295.2 seconds
Started Jul 28 07:10:52 PM PDT 24
Finished Jul 28 07:15:48 PM PDT 24
Peak memory 216752 kb
Host smart-c15125b3-d1e0-45bd-b11a-d4cb11802b4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644470763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1644470763
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1216682361
Short name T346
Test name
Test status
Simulation time 570488879 ps
CPU time 1.7 seconds
Started Jul 28 07:10:53 PM PDT 24
Finished Jul 28 07:10:55 PM PDT 24
Peak memory 198732 kb
Host smart-f0c103b7-87f4-415e-8bd7-f2aea2ad1f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216682361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1216682361
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.563076522
Short name T1075
Test name
Test status
Simulation time 19648743217 ps
CPU time 30.36 seconds
Started Jul 28 07:10:48 PM PDT 24
Finished Jul 28 07:11:18 PM PDT 24
Peak memory 200132 kb
Host smart-2baeac90-c016-4496-9ac3-05f77f92a330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563076522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.563076522
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.1826667113
Short name T28
Test name
Test status
Simulation time 13377815 ps
CPU time 0.56 seconds
Started Jul 28 07:11:07 PM PDT 24
Finished Jul 28 07:11:07 PM PDT 24
Peak memory 194996 kb
Host smart-e3c58b7b-6f9c-4565-885b-b85566b52624
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826667113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.1826667113
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1552293885
Short name T1137
Test name
Test status
Simulation time 182955434124 ps
CPU time 32.37 seconds
Started Jul 28 07:11:00 PM PDT 24
Finished Jul 28 07:11:32 PM PDT 24
Peak memory 200184 kb
Host smart-d3e85d3b-f385-460b-a299-3054804f022b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552293885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1552293885
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.385260123
Short name T275
Test name
Test status
Simulation time 218829504260 ps
CPU time 87.49 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:12:27 PM PDT 24
Peak memory 200132 kb
Host smart-917ee9c7-223a-4646-837a-292143dbfda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385260123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.385260123
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1281333345
Short name T189
Test name
Test status
Simulation time 14412943761 ps
CPU time 22.6 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:11:22 PM PDT 24
Peak memory 200108 kb
Host smart-936fcb68-395a-40a9-b084-452c2b777fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281333345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1281333345
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.3376639410
Short name T314
Test name
Test status
Simulation time 221864322222 ps
CPU time 235.15 seconds
Started Jul 28 07:11:04 PM PDT 24
Finished Jul 28 07:14:59 PM PDT 24
Peak memory 199888 kb
Host smart-0dfdaffa-7c15-4489-9829-9e363cc94e28
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376639410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.3376639410
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3755052825
Short name T577
Test name
Test status
Simulation time 81375924338 ps
CPU time 454.01 seconds
Started Jul 28 07:11:02 PM PDT 24
Finished Jul 28 07:18:36 PM PDT 24
Peak memory 200088 kb
Host smart-3757b4b8-fd02-470a-9aed-0c367c79d688
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3755052825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3755052825
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.3207104856
Short name T364
Test name
Test status
Simulation time 98967276 ps
CPU time 0.61 seconds
Started Jul 28 07:11:03 PM PDT 24
Finished Jul 28 07:11:04 PM PDT 24
Peak memory 196116 kb
Host smart-6dde0e3d-1193-40c8-b908-0b349e477b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207104856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.3207104856
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1527636144
Short name T137
Test name
Test status
Simulation time 119309651757 ps
CPU time 57.47 seconds
Started Jul 28 07:10:58 PM PDT 24
Finished Jul 28 07:11:55 PM PDT 24
Peak memory 200332 kb
Host smart-846cd866-c73d-474b-9ac5-90a499e33348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527636144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1527636144
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.466902937
Short name T905
Test name
Test status
Simulation time 4558055026 ps
CPU time 67.38 seconds
Started Jul 28 07:11:00 PM PDT 24
Finished Jul 28 07:12:08 PM PDT 24
Peak memory 200188 kb
Host smart-47b3bde1-7531-4e0e-895d-3d2d8f05870f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466902937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.466902937
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3512045956
Short name T366
Test name
Test status
Simulation time 6213126400 ps
CPU time 28.1 seconds
Started Jul 28 07:10:58 PM PDT 24
Finished Jul 28 07:11:27 PM PDT 24
Peak memory 198248 kb
Host smart-819d0afa-6a2e-461c-9788-c7f4bc451c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3512045956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3512045956
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.960005492
Short name T16
Test name
Test status
Simulation time 66123217558 ps
CPU time 102.91 seconds
Started Jul 28 07:11:02 PM PDT 24
Finished Jul 28 07:12:45 PM PDT 24
Peak memory 200120 kb
Host smart-34f3d09f-0ff5-4e2f-9fcd-daa3c4d68f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960005492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.960005492
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.968326571
Short name T452
Test name
Test status
Simulation time 49185085460 ps
CPU time 74.93 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:12:14 PM PDT 24
Peak memory 196068 kb
Host smart-c7b0d551-a002-41a5-8df3-579835ea4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968326571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.968326571
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.272088637
Short name T387
Test name
Test status
Simulation time 503535576 ps
CPU time 1.44 seconds
Started Jul 28 07:10:58 PM PDT 24
Finished Jul 28 07:11:00 PM PDT 24
Peak memory 198496 kb
Host smart-45e04c57-ecfe-4b0c-94d1-c040dc9245c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272088637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.272088637
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3554802745
Short name T488
Test name
Test status
Simulation time 105721522809 ps
CPU time 344.23 seconds
Started Jul 28 07:11:02 PM PDT 24
Finished Jul 28 07:16:46 PM PDT 24
Peak memory 200364 kb
Host smart-c3f6a1ff-6c10-4974-99ac-d00e16737956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554802745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3554802745
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2526402347
Short name T582
Test name
Test status
Simulation time 50230620331 ps
CPU time 119.1 seconds
Started Jul 28 07:11:03 PM PDT 24
Finished Jul 28 07:13:02 PM PDT 24
Peak memory 216808 kb
Host smart-946c6872-689d-4c40-8ef1-d193a41e2c82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526402347 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2526402347
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.42787668
Short name T730
Test name
Test status
Simulation time 524159316 ps
CPU time 2.23 seconds
Started Jul 28 07:11:05 PM PDT 24
Finished Jul 28 07:11:07 PM PDT 24
Peak memory 198636 kb
Host smart-68db3657-ab78-47ab-9dd3-e26647a33e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42787668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.42787668
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.2616932415
Short name T935
Test name
Test status
Simulation time 141815958068 ps
CPU time 28.7 seconds
Started Jul 28 07:10:59 PM PDT 24
Finished Jul 28 07:11:28 PM PDT 24
Peak memory 200128 kb
Host smart-68103494-1e2f-4ec9-8acf-bc5c844a8589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616932415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2616932415
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.1131360819
Short name T982
Test name
Test status
Simulation time 59334915 ps
CPU time 0.56 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:11:11 PM PDT 24
Peak memory 195560 kb
Host smart-337f4bf1-3979-4821-a21f-8c7081c86bca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131360819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1131360819
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.4269849314
Short name T1072
Test name
Test status
Simulation time 59004582277 ps
CPU time 29.65 seconds
Started Jul 28 07:11:00 PM PDT 24
Finished Jul 28 07:11:30 PM PDT 24
Peak memory 200196 kb
Host smart-fbbc0197-707d-4674-8a13-bd045ac60669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269849314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.4269849314
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.3716633129
Short name T948
Test name
Test status
Simulation time 60153750784 ps
CPU time 28.3 seconds
Started Jul 28 07:11:05 PM PDT 24
Finished Jul 28 07:11:34 PM PDT 24
Peak memory 200176 kb
Host smart-291c1953-9116-46c3-b6c8-f3967983ee4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716633129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.3716633129
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.1277224419
Short name T322
Test name
Test status
Simulation time 225276959735 ps
CPU time 440.54 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:18:32 PM PDT 24
Peak memory 200120 kb
Host smart-88e9a15b-a9a2-4aac-a438-26e4475f7c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277224419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.1277224419
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1448130823
Short name T1051
Test name
Test status
Simulation time 222649491852 ps
CPU time 116.81 seconds
Started Jul 28 07:11:06 PM PDT 24
Finished Jul 28 07:13:03 PM PDT 24
Peak memory 200164 kb
Host smart-aca8ce21-912b-4c2f-ad28-c0bf8080ea20
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448130823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1448130823
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1292079975
Short name T965
Test name
Test status
Simulation time 49245088218 ps
CPU time 420.3 seconds
Started Jul 28 07:11:08 PM PDT 24
Finished Jul 28 07:18:08 PM PDT 24
Peak memory 200140 kb
Host smart-7ed71b4a-6264-4b1c-8334-80ca84d46abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1292079975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1292079975
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1293253179
Short name T980
Test name
Test status
Simulation time 6966229390 ps
CPU time 11.7 seconds
Started Jul 28 07:11:06 PM PDT 24
Finished Jul 28 07:11:18 PM PDT 24
Peak memory 199400 kb
Host smart-4d9d3d6c-922a-465c-b17f-925fe16d0445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293253179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1293253179
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1068831635
Short name T686
Test name
Test status
Simulation time 499739483195 ps
CPU time 57.03 seconds
Started Jul 28 07:11:07 PM PDT 24
Finished Jul 28 07:12:04 PM PDT 24
Peak memory 208488 kb
Host smart-db3575d8-ec09-4735-b114-b4cafc97df46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068831635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1068831635
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3890677280
Short name T868
Test name
Test status
Simulation time 11165522280 ps
CPU time 160 seconds
Started Jul 28 07:11:07 PM PDT 24
Finished Jul 28 07:13:47 PM PDT 24
Peak memory 200196 kb
Host smart-79b80e84-6d4b-488b-a50a-941e991fd449
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3890677280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3890677280
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1631603559
Short name T646
Test name
Test status
Simulation time 2290879653 ps
CPU time 1.96 seconds
Started Jul 28 07:11:08 PM PDT 24
Finished Jul 28 07:11:10 PM PDT 24
Peak memory 198312 kb
Host smart-abc84b7d-d132-4278-a2f9-03a1ebf39a29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1631603559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1631603559
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.1170588919
Short name T415
Test name
Test status
Simulation time 86958019471 ps
CPU time 70.59 seconds
Started Jul 28 07:11:03 PM PDT 24
Finished Jul 28 07:12:13 PM PDT 24
Peak memory 200176 kb
Host smart-f6c0f131-736f-4df9-8198-4a1f737bcce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170588919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1170588919
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.3398986667
Short name T540
Test name
Test status
Simulation time 4945625338 ps
CPU time 4.93 seconds
Started Jul 28 07:11:09 PM PDT 24
Finished Jul 28 07:11:14 PM PDT 24
Peak memory 196296 kb
Host smart-f6c0b08d-b818-44ce-9a46-a500dc2eaa99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398986667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.3398986667
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2173976498
Short name T1007
Test name
Test status
Simulation time 947254110 ps
CPU time 1.52 seconds
Started Jul 28 07:11:04 PM PDT 24
Finished Jul 28 07:11:05 PM PDT 24
Peak memory 199068 kb
Host smart-9e378b78-9890-4390-a2d2-529480dca27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173976498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2173976498
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1359259480
Short name T251
Test name
Test status
Simulation time 109557454159 ps
CPU time 113.96 seconds
Started Jul 28 07:11:05 PM PDT 24
Finished Jul 28 07:12:59 PM PDT 24
Peak memory 208472 kb
Host smart-2e33d3c8-ca3b-4b03-8251-d751457c7030
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359259480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1359259480
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.838630578
Short name T124
Test name
Test status
Simulation time 70650683215 ps
CPU time 404.98 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:17:56 PM PDT 24
Peak memory 216320 kb
Host smart-70c83f24-9bbb-408f-861b-9624ce3ca5be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838630578 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.838630578
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2745699059
Short name T699
Test name
Test status
Simulation time 2359748648 ps
CPU time 2.47 seconds
Started Jul 28 07:11:08 PM PDT 24
Finished Jul 28 07:11:11 PM PDT 24
Peak memory 200148 kb
Host smart-642b0180-02b4-4ed5-b601-99d3f4e00a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745699059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2745699059
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.2675508106
Short name T479
Test name
Test status
Simulation time 103280193833 ps
CPU time 174.77 seconds
Started Jul 28 07:11:00 PM PDT 24
Finished Jul 28 07:13:55 PM PDT 24
Peak memory 200120 kb
Host smart-b029b732-6fc4-44db-ba13-a82cde8357d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675508106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.2675508106
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2412694160
Short name T1027
Test name
Test status
Simulation time 29882265 ps
CPU time 0.56 seconds
Started Jul 28 07:04:50 PM PDT 24
Finished Jul 28 07:04:51 PM PDT 24
Peak memory 195544 kb
Host smart-ae696308-c6f2-4e52-9523-21e52d994ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412694160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2412694160
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1141669242
Short name T978
Test name
Test status
Simulation time 158078131314 ps
CPU time 219.43 seconds
Started Jul 28 07:04:47 PM PDT 24
Finished Jul 28 07:08:27 PM PDT 24
Peak memory 200232 kb
Host smart-bea70629-3534-408f-b35c-f64af7bd1ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141669242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1141669242
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3470344339
Short name T790
Test name
Test status
Simulation time 12279872723 ps
CPU time 20.85 seconds
Started Jul 28 07:04:48 PM PDT 24
Finished Jul 28 07:05:09 PM PDT 24
Peak memory 200084 kb
Host smart-e0988f80-c997-4bec-8252-3ff81c2a220d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470344339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3470344339
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1570881488
Short name T820
Test name
Test status
Simulation time 104747283247 ps
CPU time 50.88 seconds
Started Jul 28 07:04:50 PM PDT 24
Finished Jul 28 07:05:41 PM PDT 24
Peak memory 199960 kb
Host smart-302522df-fbc1-4254-bef8-d803b530a487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570881488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1570881488
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.4168154134
Short name T1166
Test name
Test status
Simulation time 40605929921 ps
CPU time 73.96 seconds
Started Jul 28 07:04:46 PM PDT 24
Finished Jul 28 07:06:00 PM PDT 24
Peak memory 200200 kb
Host smart-a1c29953-770b-43f4-8573-2e72b78df494
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168154134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.4168154134
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2269725985
Short name T952
Test name
Test status
Simulation time 202136733390 ps
CPU time 713.88 seconds
Started Jul 28 07:04:48 PM PDT 24
Finished Jul 28 07:16:42 PM PDT 24
Peak memory 200048 kb
Host smart-119c5f0e-fb2a-4d99-a099-1e1ef22dce2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269725985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2269725985
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2341204121
Short name T964
Test name
Test status
Simulation time 4587635247 ps
CPU time 4.36 seconds
Started Jul 28 07:04:50 PM PDT 24
Finished Jul 28 07:04:54 PM PDT 24
Peak memory 199968 kb
Host smart-325562dd-661f-4133-add0-faddf2de7395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341204121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2341204121
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2802879587
Short name T373
Test name
Test status
Simulation time 135958085260 ps
CPU time 60.44 seconds
Started Jul 28 07:04:51 PM PDT 24
Finished Jul 28 07:05:51 PM PDT 24
Peak memory 200500 kb
Host smart-333cd1e6-49d1-43d5-96ea-f76e39ddac35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802879587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2802879587
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2185818841
Short name T866
Test name
Test status
Simulation time 9226313197 ps
CPU time 561.23 seconds
Started Jul 28 07:04:48 PM PDT 24
Finished Jul 28 07:14:09 PM PDT 24
Peak memory 200184 kb
Host smart-9134007e-cabb-4fe7-8865-1ed6b742fd98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185818841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2185818841
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3777856465
Short name T419
Test name
Test status
Simulation time 2550044273 ps
CPU time 4.89 seconds
Started Jul 28 07:04:50 PM PDT 24
Finished Jul 28 07:04:55 PM PDT 24
Peak memory 199512 kb
Host smart-d9a59e31-3735-4356-a895-103eef240cda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3777856465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3777856465
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1791912028
Short name T390
Test name
Test status
Simulation time 49943409620 ps
CPU time 87.86 seconds
Started Jul 28 07:04:49 PM PDT 24
Finished Jul 28 07:06:17 PM PDT 24
Peak memory 200040 kb
Host smart-4d1af000-944a-4118-a0d1-996365b05b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791912028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1791912028
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3655282496
Short name T927
Test name
Test status
Simulation time 1602391444 ps
CPU time 2.93 seconds
Started Jul 28 07:04:47 PM PDT 24
Finished Jul 28 07:04:50 PM PDT 24
Peak memory 195680 kb
Host smart-849385dc-2abf-4706-98fe-e3e15af178a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655282496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3655282496
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.760918678
Short name T274
Test name
Test status
Simulation time 5386080805 ps
CPU time 8.19 seconds
Started Jul 28 07:04:41 PM PDT 24
Finished Jul 28 07:04:49 PM PDT 24
Peak memory 199548 kb
Host smart-13afb687-5d23-41d0-a218-5db5a612c95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760918678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.760918678
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.1932203271
Short name T768
Test name
Test status
Simulation time 200998072796 ps
CPU time 638.85 seconds
Started Jul 28 07:04:49 PM PDT 24
Finished Jul 28 07:15:28 PM PDT 24
Peak memory 200212 kb
Host smart-6a72a43e-c221-439f-9789-7f0629ff359c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932203271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.1932203271
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2897447849
Short name T648
Test name
Test status
Simulation time 73536143837 ps
CPU time 185.4 seconds
Started Jul 28 07:04:50 PM PDT 24
Finished Jul 28 07:07:55 PM PDT 24
Peak memory 217008 kb
Host smart-379dbcba-1463-40fd-abf4-34136490f144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897447849 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2897447849
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.3281342647
Short name T575
Test name
Test status
Simulation time 969724847 ps
CPU time 2.7 seconds
Started Jul 28 07:04:48 PM PDT 24
Finished Jul 28 07:04:51 PM PDT 24
Peak memory 199820 kb
Host smart-8c170341-7a97-4274-8c41-bbd3b6996878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281342647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.3281342647
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.629210672
Short name T354
Test name
Test status
Simulation time 37094231669 ps
CPU time 59.54 seconds
Started Jul 28 07:04:42 PM PDT 24
Finished Jul 28 07:05:42 PM PDT 24
Peak memory 200168 kb
Host smart-d6bc5ffb-b460-4674-acb0-982ca6a198c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629210672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.629210672
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2786514653
Short name T205
Test name
Test status
Simulation time 116715358334 ps
CPU time 31.88 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:11:43 PM PDT 24
Peak memory 200092 kb
Host smart-c87f1582-abdb-415b-8c86-bce955f8cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786514653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2786514653
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.4136101147
Short name T972
Test name
Test status
Simulation time 80926970710 ps
CPU time 704.31 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:22:55 PM PDT 24
Peak memory 224856 kb
Host smart-3b4d3c87-42ef-4046-a2d6-47b8e969c1d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136101147 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.4136101147
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.317640618
Short name T162
Test name
Test status
Simulation time 117444602244 ps
CPU time 36.17 seconds
Started Jul 28 07:11:10 PM PDT 24
Finished Jul 28 07:11:46 PM PDT 24
Peak memory 200192 kb
Host smart-bb7f1711-09e6-411e-ada4-3238f5f31dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317640618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.317640618
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2846140488
Short name T883
Test name
Test status
Simulation time 18752915910 ps
CPU time 562.48 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:20:33 PM PDT 24
Peak memory 216724 kb
Host smart-8add324d-408d-49cd-9e47-e0a73144362b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846140488 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2846140488
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.3279968543
Short name T149
Test name
Test status
Simulation time 99614760312 ps
CPU time 58.1 seconds
Started Jul 28 07:11:11 PM PDT 24
Finished Jul 28 07:12:09 PM PDT 24
Peak memory 199916 kb
Host smart-b8a8a79f-d3fa-4247-a314-e2b0b125efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279968543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3279968543
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3091989938
Short name T794
Test name
Test status
Simulation time 36862274507 ps
CPU time 405.9 seconds
Started Jul 28 07:11:10 PM PDT 24
Finished Jul 28 07:17:56 PM PDT 24
Peak memory 215936 kb
Host smart-03410fc9-b26d-4def-b497-85dd416b1eb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091989938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3091989938
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.3225698449
Short name T983
Test name
Test status
Simulation time 133432354614 ps
CPU time 131.84 seconds
Started Jul 28 07:11:16 PM PDT 24
Finished Jul 28 07:13:28 PM PDT 24
Peak memory 200152 kb
Host smart-1962dff9-72ad-4637-9969-115bd43eb1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225698449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.3225698449
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3532171184
Short name T1089
Test name
Test status
Simulation time 43372799676 ps
CPU time 690.72 seconds
Started Jul 28 07:11:18 PM PDT 24
Finished Jul 28 07:22:49 PM PDT 24
Peak memory 211572 kb
Host smart-6abb9a5a-ded3-469c-806e-1e04ebcb3cbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532171184 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3532171184
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.769183165
Short name T1008
Test name
Test status
Simulation time 175949518252 ps
CPU time 50.42 seconds
Started Jul 28 07:11:16 PM PDT 24
Finished Jul 28 07:12:06 PM PDT 24
Peak memory 200120 kb
Host smart-4300209b-d7d3-467c-a014-902a5f79df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769183165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.769183165
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.400824378
Short name T604
Test name
Test status
Simulation time 76348985231 ps
CPU time 922.65 seconds
Started Jul 28 07:11:18 PM PDT 24
Finished Jul 28 07:26:41 PM PDT 24
Peak memory 216556 kb
Host smart-2bbe15e9-dbba-4142-9d64-768d7e9bb356
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400824378 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.400824378
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1243634906
Short name T136
Test name
Test status
Simulation time 45174849859 ps
CPU time 17.17 seconds
Started Jul 28 07:11:17 PM PDT 24
Finished Jul 28 07:11:34 PM PDT 24
Peak memory 199948 kb
Host smart-365c1214-c7fe-4225-87c6-a97d65098c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243634906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1243634906
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4169062129
Short name T473
Test name
Test status
Simulation time 6907968817 ps
CPU time 10.92 seconds
Started Jul 28 07:11:19 PM PDT 24
Finished Jul 28 07:11:30 PM PDT 24
Peak memory 199352 kb
Host smart-32d7ff9e-a3c1-41a9-92c3-ee6f25d6c429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169062129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4169062129
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3674714772
Short name T784
Test name
Test status
Simulation time 33043479994 ps
CPU time 61.66 seconds
Started Jul 28 07:11:16 PM PDT 24
Finished Jul 28 07:12:18 PM PDT 24
Peak memory 200120 kb
Host smart-c8c8fd13-38a5-43a6-bb0b-60c5042e1c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674714772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3674714772
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1240955752
Short name T1078
Test name
Test status
Simulation time 194712324219 ps
CPU time 147.76 seconds
Started Jul 28 07:11:17 PM PDT 24
Finished Jul 28 07:13:45 PM PDT 24
Peak memory 200160 kb
Host smart-e95059a2-10ec-4f5e-9303-32463c53ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240955752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1240955752
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2063424039
Short name T602
Test name
Test status
Simulation time 26822471505 ps
CPU time 159.09 seconds
Started Jul 28 07:11:14 PM PDT 24
Finished Jul 28 07:13:53 PM PDT 24
Peak memory 210952 kb
Host smart-fc996395-45b8-459d-a3ce-6922beea9368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063424039 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2063424039
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3947034935
Short name T988
Test name
Test status
Simulation time 47477963067 ps
CPU time 16.75 seconds
Started Jul 28 07:11:20 PM PDT 24
Finished Jul 28 07:11:37 PM PDT 24
Peak memory 200196 kb
Host smart-0be2c8fa-9b80-4ee7-afba-3e087d9e3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947034935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3947034935
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.832793663
Short name T650
Test name
Test status
Simulation time 67332822169 ps
CPU time 195.25 seconds
Started Jul 28 07:11:22 PM PDT 24
Finished Jul 28 07:14:37 PM PDT 24
Peak memory 216476 kb
Host smart-92850a24-cc5b-481d-9207-fe6ad4dc1c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832793663 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.832793663
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1246187326
Short name T504
Test name
Test status
Simulation time 24205020 ps
CPU time 0.56 seconds
Started Jul 28 07:04:57 PM PDT 24
Finished Jul 28 07:04:58 PM PDT 24
Peak memory 195556 kb
Host smart-cfef3c87-48a6-4906-9207-b351179b1c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246187326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1246187326
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.510055152
Short name T1122
Test name
Test status
Simulation time 187369439409 ps
CPU time 204.75 seconds
Started Jul 28 07:04:54 PM PDT 24
Finished Jul 28 07:08:19 PM PDT 24
Peak memory 200096 kb
Host smart-f8d4c7a1-9a2d-42ed-8184-fed1519cf9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510055152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.510055152
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.4137832756
Short name T666
Test name
Test status
Simulation time 68273903432 ps
CPU time 28.31 seconds
Started Jul 28 07:04:55 PM PDT 24
Finished Jul 28 07:05:23 PM PDT 24
Peak memory 200020 kb
Host smart-1dbea9a8-c5cd-49f2-bfb9-a17ed2c28a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137832756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.4137832756
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1731934636
Short name T765
Test name
Test status
Simulation time 63529567204 ps
CPU time 17.68 seconds
Started Jul 28 07:04:55 PM PDT 24
Finished Jul 28 07:05:13 PM PDT 24
Peak memory 200076 kb
Host smart-3ad85ecd-2f72-44dd-9dc8-504baabb6bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731934636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1731934636
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2611518746
Short name T835
Test name
Test status
Simulation time 23233091562 ps
CPU time 19.9 seconds
Started Jul 28 07:04:53 PM PDT 24
Finished Jul 28 07:05:13 PM PDT 24
Peak memory 200076 kb
Host smart-4a2fbb16-d5d0-4838-811f-9690fe03e7e2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611518746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2611518746
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1904208920
Short name T449
Test name
Test status
Simulation time 85005430745 ps
CPU time 211.31 seconds
Started Jul 28 07:04:59 PM PDT 24
Finished Jul 28 07:08:31 PM PDT 24
Peak memory 200172 kb
Host smart-6d52a707-2b8c-4236-91fe-d5cccf1dae17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1904208920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1904208920
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2051974489
Short name T758
Test name
Test status
Simulation time 7083865088 ps
CPU time 13.27 seconds
Started Jul 28 07:04:53 PM PDT 24
Finished Jul 28 07:05:07 PM PDT 24
Peak memory 198928 kb
Host smart-92530f2d-aea2-47a4-962d-fc58eec525fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051974489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2051974489
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.2782744373
Short name T1175
Test name
Test status
Simulation time 8077913730 ps
CPU time 12.84 seconds
Started Jul 28 07:04:55 PM PDT 24
Finished Jul 28 07:05:08 PM PDT 24
Peak memory 194676 kb
Host smart-e81f4e64-fbdf-4f2c-8cc6-94b9435516dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782744373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.2782744373
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.1091786696
Short name T519
Test name
Test status
Simulation time 16592087976 ps
CPU time 215.65 seconds
Started Jul 28 07:04:58 PM PDT 24
Finished Jul 28 07:08:34 PM PDT 24
Peak memory 200184 kb
Host smart-87bd44af-ab4e-4268-98f6-f5c5d6165b78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1091786696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.1091786696
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.230780620
Short name T949
Test name
Test status
Simulation time 7685776744 ps
CPU time 36.9 seconds
Started Jul 28 07:04:55 PM PDT 24
Finished Jul 28 07:05:32 PM PDT 24
Peak memory 198456 kb
Host smart-6edde910-ddad-4412-8a62-1c05ec000cce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230780620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.230780620
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2081758990
Short name T497
Test name
Test status
Simulation time 9797406734 ps
CPU time 14.88 seconds
Started Jul 28 07:04:56 PM PDT 24
Finished Jul 28 07:05:11 PM PDT 24
Peak memory 199952 kb
Host smart-ed638c55-0023-4594-bed5-b37612eb5d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081758990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2081758990
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1717396973
Short name T271
Test name
Test status
Simulation time 3325970460 ps
CPU time 5.23 seconds
Started Jul 28 07:04:56 PM PDT 24
Finished Jul 28 07:05:01 PM PDT 24
Peak memory 196316 kb
Host smart-096d572c-80ff-4caa-b606-c4f477924269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717396973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1717396973
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.519024809
Short name T397
Test name
Test status
Simulation time 738967808 ps
CPU time 1.24 seconds
Started Jul 28 07:04:53 PM PDT 24
Finished Jul 28 07:04:54 PM PDT 24
Peak memory 200092 kb
Host smart-6ab71e22-3812-488d-877c-4fdc5008e13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519024809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.519024809
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.3206061481
Short name T173
Test name
Test status
Simulation time 224717082517 ps
CPU time 145.7 seconds
Started Jul 28 07:05:03 PM PDT 24
Finished Jul 28 07:07:28 PM PDT 24
Peak memory 208500 kb
Host smart-66bc8d61-7716-4653-bf41-a5affbd3a17c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206061481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3206061481
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3435075932
Short name T123
Test name
Test status
Simulation time 101566776694 ps
CPU time 160.25 seconds
Started Jul 28 07:04:59 PM PDT 24
Finished Jul 28 07:07:40 PM PDT 24
Peak memory 215600 kb
Host smart-4e1500e0-5926-4a10-a184-ccc46ea9ca20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435075932 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3435075932
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.448284423
Short name T1021
Test name
Test status
Simulation time 6277626648 ps
CPU time 12.04 seconds
Started Jul 28 07:04:54 PM PDT 24
Finished Jul 28 07:05:06 PM PDT 24
Peak memory 200204 kb
Host smart-e872aa49-9ae2-4f57-8949-23b634d87fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448284423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.448284423
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3723081593
Short name T353
Test name
Test status
Simulation time 55075503528 ps
CPU time 82.76 seconds
Started Jul 28 07:04:54 PM PDT 24
Finished Jul 28 07:06:17 PM PDT 24
Peak memory 200148 kb
Host smart-7e97eedf-8be9-4131-b03d-5640323506b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723081593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3723081593
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4086229128
Short name T169
Test name
Test status
Simulation time 67787904286 ps
CPU time 311.82 seconds
Started Jul 28 07:11:22 PM PDT 24
Finished Jul 28 07:16:34 PM PDT 24
Peak memory 200180 kb
Host smart-dc965386-55a8-4421-96b7-1512a3f1fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086229128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4086229128
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3934467037
Short name T375
Test name
Test status
Simulation time 5837710149 ps
CPU time 69.69 seconds
Started Jul 28 07:11:22 PM PDT 24
Finished Jul 28 07:12:31 PM PDT 24
Peak memory 208444 kb
Host smart-b954107b-aecf-4a8c-b128-c2c583131e07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934467037 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3934467037
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.1209105071
Short name T987
Test name
Test status
Simulation time 109807203887 ps
CPU time 48.14 seconds
Started Jul 28 07:11:22 PM PDT 24
Finished Jul 28 07:12:10 PM PDT 24
Peak memory 200108 kb
Host smart-65cfd4ff-876e-44d7-8015-2c681c603a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209105071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1209105071
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.980558405
Short name T946
Test name
Test status
Simulation time 134038072571 ps
CPU time 21.94 seconds
Started Jul 28 07:11:18 PM PDT 24
Finished Jul 28 07:11:40 PM PDT 24
Peak memory 200112 kb
Host smart-debd4af1-7e57-4ca6-8159-311a25a2831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980558405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.980558405
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1327499542
Short name T915
Test name
Test status
Simulation time 36389638988 ps
CPU time 607.83 seconds
Started Jul 28 07:11:21 PM PDT 24
Finished Jul 28 07:21:29 PM PDT 24
Peak memory 216860 kb
Host smart-83f89773-4f61-4ead-8906-25b51b10d10b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327499542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1327499542
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.112603301
Short name T616
Test name
Test status
Simulation time 87897481068 ps
CPU time 57.85 seconds
Started Jul 28 07:11:25 PM PDT 24
Finished Jul 28 07:12:22 PM PDT 24
Peak memory 200016 kb
Host smart-a22b97d9-3726-4df8-acfa-0e2a5222842c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112603301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.112603301
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.657906240
Short name T307
Test name
Test status
Simulation time 51663307775 ps
CPU time 314.31 seconds
Started Jul 28 07:11:27 PM PDT 24
Finished Jul 28 07:16:41 PM PDT 24
Peak memory 208488 kb
Host smart-5c9f598d-e794-4fd9-b4ed-63b8903ca36b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657906240 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.657906240
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2959333128
Short name T1108
Test name
Test status
Simulation time 30221347260 ps
CPU time 27.33 seconds
Started Jul 28 07:11:25 PM PDT 24
Finished Jul 28 07:11:53 PM PDT 24
Peak memory 200160 kb
Host smart-43dd5b10-bdba-4a98-80de-cea528ad001d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959333128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2959333128
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2358305667
Short name T1060
Test name
Test status
Simulation time 205868052959 ps
CPU time 615.05 seconds
Started Jul 28 07:11:28 PM PDT 24
Finished Jul 28 07:21:43 PM PDT 24
Peak memory 216812 kb
Host smart-60e7db05-cf5f-4c7e-bb0e-83aa08eae83d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358305667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2358305667
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3351272343
Short name T418
Test name
Test status
Simulation time 41380114224 ps
CPU time 59.22 seconds
Started Jul 28 07:11:27 PM PDT 24
Finished Jul 28 07:12:26 PM PDT 24
Peak memory 200060 kb
Host smart-45978ee3-c25c-4a28-b577-f2c9f95e7ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351272343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3351272343
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.3277530291
Short name T202
Test name
Test status
Simulation time 104428103679 ps
CPU time 75.77 seconds
Started Jul 28 07:11:26 PM PDT 24
Finished Jul 28 07:12:41 PM PDT 24
Peak memory 200120 kb
Host smart-4ed58179-e2b8-40ca-bc26-1b734c485c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277530291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.3277530291
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3098764269
Short name T1174
Test name
Test status
Simulation time 85014671275 ps
CPU time 194.12 seconds
Started Jul 28 07:11:27 PM PDT 24
Finished Jul 28 07:14:41 PM PDT 24
Peak memory 216772 kb
Host smart-5e71a0db-66e3-468a-8c28-30b9f7e5b83b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098764269 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3098764269
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.2652236829
Short name T349
Test name
Test status
Simulation time 7669959197 ps
CPU time 11.65 seconds
Started Jul 28 07:11:24 PM PDT 24
Finished Jul 28 07:11:35 PM PDT 24
Peak memory 199756 kb
Host smart-fc143b71-21da-4c91-872e-f8db3a7ff1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652236829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2652236829
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.3603509029
Short name T119
Test name
Test status
Simulation time 415709220959 ps
CPU time 627.4 seconds
Started Jul 28 07:11:30 PM PDT 24
Finished Jul 28 07:21:57 PM PDT 24
Peak memory 224956 kb
Host smart-acc3945f-909f-43fd-b2d5-440bb609dd51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603509029 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.3603509029
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3340262082
Short name T585
Test name
Test status
Simulation time 33577777839 ps
CPU time 50.8 seconds
Started Jul 28 07:11:28 PM PDT 24
Finished Jul 28 07:12:19 PM PDT 24
Peak memory 200188 kb
Host smart-158814d7-ebc5-4631-b94b-bec17f855226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340262082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3340262082
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1207260670
Short name T574
Test name
Test status
Simulation time 135955103093 ps
CPU time 39.66 seconds
Started Jul 28 07:11:26 PM PDT 24
Finished Jul 28 07:12:05 PM PDT 24
Peak memory 200196 kb
Host smart-c8584196-1405-411c-8991-60a253a9e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207260670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1207260670
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2415652672
Short name T1030
Test name
Test status
Simulation time 187999781621 ps
CPU time 892.64 seconds
Started Jul 28 07:11:30 PM PDT 24
Finished Jul 28 07:26:23 PM PDT 24
Peak memory 216676 kb
Host smart-43fb9375-491a-4268-93a7-2db6905f0e6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415652672 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2415652672
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.3978456054
Short name T361
Test name
Test status
Simulation time 11170347 ps
CPU time 0.54 seconds
Started Jul 28 07:05:10 PM PDT 24
Finished Jul 28 07:05:10 PM PDT 24
Peak memory 195488 kb
Host smart-9be064b1-1d89-47a2-ad08-7a26d2d5e9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978456054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.3978456054
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2320688450
Short name T248
Test name
Test status
Simulation time 99013671658 ps
CPU time 97.82 seconds
Started Jul 28 07:05:06 PM PDT 24
Finished Jul 28 07:06:44 PM PDT 24
Peak memory 199932 kb
Host smart-58288626-23cb-4128-a562-a7af16a08729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320688450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2320688450
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2793351644
Short name T1026
Test name
Test status
Simulation time 116653670514 ps
CPU time 21.93 seconds
Started Jul 28 07:05:05 PM PDT 24
Finished Jul 28 07:05:27 PM PDT 24
Peak memory 200080 kb
Host smart-8ac9892b-ee25-4a12-bdbb-4ffd14626fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793351644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2793351644
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.387567275
Short name T777
Test name
Test status
Simulation time 86904767963 ps
CPU time 75.62 seconds
Started Jul 28 07:05:05 PM PDT 24
Finished Jul 28 07:06:21 PM PDT 24
Peak memory 200096 kb
Host smart-414607a8-0492-4434-b871-58e1342e2f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387567275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.387567275
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.4014941496
Short name T705
Test name
Test status
Simulation time 9610055768 ps
CPU time 5.78 seconds
Started Jul 28 07:05:06 PM PDT 24
Finished Jul 28 07:05:12 PM PDT 24
Peak memory 199560 kb
Host smart-8b4cec08-e2d4-4a6b-9ced-2a0bc863a1f8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014941496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.4014941496
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.745786365
Short name T534
Test name
Test status
Simulation time 103064445769 ps
CPU time 220.94 seconds
Started Jul 28 07:05:09 PM PDT 24
Finished Jul 28 07:08:50 PM PDT 24
Peak memory 200096 kb
Host smart-e670da52-9599-40c7-ba0a-540e29ad2b6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=745786365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.745786365
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3006503319
Short name T729
Test name
Test status
Simulation time 9368433003 ps
CPU time 18.71 seconds
Started Jul 28 07:05:04 PM PDT 24
Finished Jul 28 07:05:23 PM PDT 24
Peak memory 199956 kb
Host smart-fac6fe8a-bd1d-4d39-9610-7780df84f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006503319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3006503319
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2643392686
Short name T555
Test name
Test status
Simulation time 3071204010 ps
CPU time 7.19 seconds
Started Jul 28 07:05:05 PM PDT 24
Finished Jul 28 07:05:12 PM PDT 24
Peak memory 198044 kb
Host smart-f0f2ce1e-eb88-4087-9f69-bf8e1d1effdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643392686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2643392686
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2185960911
Short name T46
Test name
Test status
Simulation time 12329948926 ps
CPU time 698.14 seconds
Started Jul 28 07:05:09 PM PDT 24
Finished Jul 28 07:16:47 PM PDT 24
Peak memory 200104 kb
Host smart-92676846-e9aa-414d-9479-876ecd178577
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2185960911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2185960911
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.4043250542
Short name T549
Test name
Test status
Simulation time 4441591241 ps
CPU time 36.37 seconds
Started Jul 28 07:05:06 PM PDT 24
Finished Jul 28 07:05:43 PM PDT 24
Peak memory 198576 kb
Host smart-e001373f-c1ec-4ab0-b75d-787ade2a87c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043250542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.4043250542
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1435403568
Short name T111
Test name
Test status
Simulation time 117908712742 ps
CPU time 45.73 seconds
Started Jul 28 07:05:05 PM PDT 24
Finished Jul 28 07:05:51 PM PDT 24
Peak memory 200232 kb
Host smart-baaf62b2-a965-4a01-a537-946b6487f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435403568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1435403568
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3536945227
Short name T278
Test name
Test status
Simulation time 5003689606 ps
CPU time 1.29 seconds
Started Jul 28 07:05:05 PM PDT 24
Finished Jul 28 07:05:07 PM PDT 24
Peak memory 196764 kb
Host smart-77de0041-7143-4057-9c18-5c4efb83e9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536945227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3536945227
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2731491897
Short name T1103
Test name
Test status
Simulation time 6306620304 ps
CPU time 7.93 seconds
Started Jul 28 07:04:59 PM PDT 24
Finished Jul 28 07:05:07 PM PDT 24
Peak memory 200068 kb
Host smart-d7110816-39ee-42d0-a94b-80cc56da6117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731491897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2731491897
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1840684581
Short name T117
Test name
Test status
Simulation time 95342067197 ps
CPU time 74.78 seconds
Started Jul 28 07:05:08 PM PDT 24
Finished Jul 28 07:06:23 PM PDT 24
Peak memory 200392 kb
Host smart-1f3d6160-7a32-402c-b3b4-53c43688b539
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840684581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1840684581
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3151012991
Short name T1163
Test name
Test status
Simulation time 41793817039 ps
CPU time 473.72 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:13:07 PM PDT 24
Peak memory 225040 kb
Host smart-71b6c3b8-fd6b-488d-ad73-5e2046b66c68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151012991 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3151012991
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1234228234
Short name T747
Test name
Test status
Simulation time 908598288 ps
CPU time 1.85 seconds
Started Jul 28 07:05:04 PM PDT 24
Finished Jul 28 07:05:06 PM PDT 24
Peak memory 198976 kb
Host smart-ad5682c8-7951-4d71-b26a-14bd3296aeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234228234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1234228234
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3794065125
Short name T709
Test name
Test status
Simulation time 80052424191 ps
CPU time 141.47 seconds
Started Jul 28 07:04:59 PM PDT 24
Finished Jul 28 07:07:21 PM PDT 24
Peak memory 200128 kb
Host smart-22e88b48-e791-41c2-b67c-799bc49527da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794065125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3794065125
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2854198671
Short name T206
Test name
Test status
Simulation time 35600508362 ps
CPU time 37.04 seconds
Started Jul 28 07:11:24 PM PDT 24
Finished Jul 28 07:12:01 PM PDT 24
Peak memory 200188 kb
Host smart-e04dac80-6dc7-40d8-bff8-5fe6a333e86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854198671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2854198671
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.645784609
Short name T67
Test name
Test status
Simulation time 378822329913 ps
CPU time 1070.01 seconds
Started Jul 28 07:11:27 PM PDT 24
Finished Jul 28 07:29:17 PM PDT 24
Peak memory 232776 kb
Host smart-8c900f89-7140-4098-996d-3d7570eeaf0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645784609 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.645784609
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3252804931
Short name T891
Test name
Test status
Simulation time 101324282957 ps
CPU time 34.67 seconds
Started Jul 28 07:11:28 PM PDT 24
Finished Jul 28 07:12:03 PM PDT 24
Peak memory 200140 kb
Host smart-94086344-5f0d-4708-81bc-7f09d7710cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252804931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3252804931
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.1218480338
Short name T133
Test name
Test status
Simulation time 114676597923 ps
CPU time 179.92 seconds
Started Jul 28 07:11:33 PM PDT 24
Finished Jul 28 07:14:33 PM PDT 24
Peak memory 216720 kb
Host smart-df7ccb66-e9c8-4cca-a05e-d24492ef6f12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218480338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.1218480338
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2609931728
Short name T4
Test name
Test status
Simulation time 7485446120 ps
CPU time 14.23 seconds
Started Jul 28 07:11:30 PM PDT 24
Finished Jul 28 07:11:45 PM PDT 24
Peak memory 200116 kb
Host smart-67a8b82d-6e4d-4dfb-9d5f-af1768f30db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609931728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2609931728
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.2639046038
Short name T487
Test name
Test status
Simulation time 59752246373 ps
CPU time 270.75 seconds
Started Jul 28 07:11:30 PM PDT 24
Finished Jul 28 07:16:01 PM PDT 24
Peak memory 216676 kb
Host smart-b89ed47f-0746-4bcc-b497-11ba092010b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639046038 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.2639046038
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.196245191
Short name T1151
Test name
Test status
Simulation time 14257969533 ps
CPU time 15.39 seconds
Started Jul 28 07:11:33 PM PDT 24
Finished Jul 28 07:11:49 PM PDT 24
Peak memory 199992 kb
Host smart-7722c103-0fdb-4693-8c00-78b518f3a5b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196245191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.196245191
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1040531974
Short name T1022
Test name
Test status
Simulation time 24540378930 ps
CPU time 148.93 seconds
Started Jul 28 07:11:32 PM PDT 24
Finished Jul 28 07:14:01 PM PDT 24
Peak memory 208476 kb
Host smart-8eb74240-ad4f-41e5-8faa-b83f73b13edc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040531974 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1040531974
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1270565768
Short name T611
Test name
Test status
Simulation time 34930337719 ps
CPU time 27.6 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:12:03 PM PDT 24
Peak memory 199860 kb
Host smart-1c372a83-9c81-4007-ab29-9f97df3acc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270565768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1270565768
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1538105308
Short name T122
Test name
Test status
Simulation time 30668020926 ps
CPU time 181.83 seconds
Started Jul 28 07:11:33 PM PDT 24
Finished Jul 28 07:14:34 PM PDT 24
Peak memory 216852 kb
Host smart-4ea30332-e110-4b42-9218-277071dcf161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538105308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1538105308
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1761292548
Short name T224
Test name
Test status
Simulation time 38803822677 ps
CPU time 21.86 seconds
Started Jul 28 07:11:32 PM PDT 24
Finished Jul 28 07:11:54 PM PDT 24
Peak memory 200176 kb
Host smart-598ba4e7-a448-408c-b2f1-9e568c364af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761292548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1761292548
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3307955683
Short name T49
Test name
Test status
Simulation time 113581506013 ps
CPU time 669.39 seconds
Started Jul 28 07:11:31 PM PDT 24
Finished Jul 28 07:22:40 PM PDT 24
Peak memory 216884 kb
Host smart-0b3acc2e-bb31-44c3-ae3d-2f830f6fa6e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307955683 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3307955683
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1190336743
Short name T483
Test name
Test status
Simulation time 92212321421 ps
CPU time 36.08 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:12:12 PM PDT 24
Peak memory 199992 kb
Host smart-14e998ff-84ce-4c46-a2d6-b0c01ff003b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190336743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1190336743
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.513060807
Short name T853
Test name
Test status
Simulation time 134788764561 ps
CPU time 1444.14 seconds
Started Jul 28 07:11:37 PM PDT 24
Finished Jul 28 07:35:41 PM PDT 24
Peak memory 227244 kb
Host smart-cc492bb8-e78a-4d0c-9199-42ad35757ace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513060807 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.513060807
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1575107146
Short name T1147
Test name
Test status
Simulation time 18171965937 ps
CPU time 22.5 seconds
Started Jul 28 07:11:32 PM PDT 24
Finished Jul 28 07:11:55 PM PDT 24
Peak memory 200156 kb
Host smart-0f8d2e3f-d91a-4957-9989-cfce202ab528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575107146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1575107146
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2366859633
Short name T63
Test name
Test status
Simulation time 67088600313 ps
CPU time 931.72 seconds
Started Jul 28 07:11:32 PM PDT 24
Finished Jul 28 07:27:04 PM PDT 24
Peak memory 216696 kb
Host smart-e1399293-d993-448e-a27f-014f721dc4ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366859633 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2366859633
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.720850132
Short name T1056
Test name
Test status
Simulation time 87410106616 ps
CPU time 39.32 seconds
Started Jul 28 07:11:32 PM PDT 24
Finished Jul 28 07:12:12 PM PDT 24
Peak memory 200124 kb
Host smart-46e0fd14-1e88-4d10-bdc8-36ff3b5960ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720850132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.720850132
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.1045208235
Short name T614
Test name
Test status
Simulation time 56796276936 ps
CPU time 372.45 seconds
Started Jul 28 07:11:31 PM PDT 24
Finished Jul 28 07:17:43 PM PDT 24
Peak memory 216776 kb
Host smart-3656734d-ea5e-4d74-a3d0-6b8337959d9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045208235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.1045208235
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3019460797
Short name T1138
Test name
Test status
Simulation time 92004123954 ps
CPU time 152.57 seconds
Started Jul 28 07:11:38 PM PDT 24
Finished Jul 28 07:14:11 PM PDT 24
Peak memory 200116 kb
Host smart-bf12e5ef-2b18-4bec-b2e5-653c259e7c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019460797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3019460797
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3073485842
Short name T971
Test name
Test status
Simulation time 22222774153 ps
CPU time 88.06 seconds
Started Jul 28 07:11:37 PM PDT 24
Finished Jul 28 07:13:05 PM PDT 24
Peak memory 215844 kb
Host smart-fd86d4c6-378f-4314-a407-a65b35cfa065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073485842 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3073485842
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1664797712
Short name T962
Test name
Test status
Simulation time 73282210 ps
CPU time 0.58 seconds
Started Jul 28 07:05:17 PM PDT 24
Finished Jul 28 07:05:18 PM PDT 24
Peak memory 195572 kb
Host smart-0ba4df0a-a0fb-4843-aef7-a3907c7a544f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664797712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1664797712
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2151927480
Short name T662
Test name
Test status
Simulation time 105263117395 ps
CPU time 101.01 seconds
Started Jul 28 07:05:10 PM PDT 24
Finished Jul 28 07:06:51 PM PDT 24
Peak memory 200168 kb
Host smart-d73b89ee-6f02-43de-8bb0-61c6057c400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151927480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2151927480
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.787876553
Short name T291
Test name
Test status
Simulation time 57006119610 ps
CPU time 22.18 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:05:35 PM PDT 24
Peak memory 199676 kb
Host smart-50a7feb2-c5fe-4d77-8608-76a33b316462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787876553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.787876553
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3316276955
Short name T1070
Test name
Test status
Simulation time 57025556285 ps
CPU time 22.41 seconds
Started Jul 28 07:05:14 PM PDT 24
Finished Jul 28 07:05:36 PM PDT 24
Peak memory 200128 kb
Host smart-f181aa3f-4b78-4653-b20d-9798bf576c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316276955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3316276955
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.3406098512
Short name T879
Test name
Test status
Simulation time 46911862641 ps
CPU time 43.04 seconds
Started Jul 28 07:05:15 PM PDT 24
Finished Jul 28 07:05:58 PM PDT 24
Peak memory 200160 kb
Host smart-320b8848-7ad3-4a50-b4d0-529158340f04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406098512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.3406098512
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3185766486
Short name T249
Test name
Test status
Simulation time 206660394871 ps
CPU time 326.29 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:10:40 PM PDT 24
Peak memory 200140 kb
Host smart-e283581e-cc78-4f36-b10e-af8434cfbe1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185766486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3185766486
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.442806243
Short name T654
Test name
Test status
Simulation time 9087724819 ps
CPU time 18.32 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:05:31 PM PDT 24
Peak memory 200140 kb
Host smart-88424418-291f-4a1d-8384-16ca2a3161a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442806243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.442806243
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1973857866
Short name T284
Test name
Test status
Simulation time 591157139612 ps
CPU time 79.52 seconds
Started Jul 28 07:05:16 PM PDT 24
Finished Jul 28 07:06:36 PM PDT 24
Peak memory 208696 kb
Host smart-13f0eba4-332d-4090-9024-124746ba07ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973857866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1973857866
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3683220349
Short name T560
Test name
Test status
Simulation time 9335615462 ps
CPU time 133.79 seconds
Started Jul 28 07:05:12 PM PDT 24
Finished Jul 28 07:07:26 PM PDT 24
Peak memory 200116 kb
Host smart-8d49c617-91c4-43c1-923f-8ac8e4f7dac2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683220349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3683220349
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1162047634
Short name T628
Test name
Test status
Simulation time 3907887933 ps
CPU time 7.45 seconds
Started Jul 28 07:05:15 PM PDT 24
Finished Jul 28 07:05:22 PM PDT 24
Peak memory 198216 kb
Host smart-3ab23b27-2bc0-42eb-b66b-9cd852019729
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162047634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1162047634
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.1618354791
Short name T1099
Test name
Test status
Simulation time 18384878288 ps
CPU time 7.3 seconds
Started Jul 28 07:05:15 PM PDT 24
Finished Jul 28 07:05:22 PM PDT 24
Peak memory 198440 kb
Host smart-8cf6afb5-9024-4b2e-9891-70bc35026a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618354791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1618354791
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1808431422
Short name T697
Test name
Test status
Simulation time 5235721262 ps
CPU time 4.72 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:05:18 PM PDT 24
Peak memory 196672 kb
Host smart-6b23846c-3813-4942-9000-fbc0fc10277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808431422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1808431422
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.4281621736
Short name T529
Test name
Test status
Simulation time 138190783 ps
CPU time 0.81 seconds
Started Jul 28 07:05:08 PM PDT 24
Finished Jul 28 07:05:09 PM PDT 24
Peak memory 197352 kb
Host smart-3c40b696-15d2-4757-bfe3-7ac647c48de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281621736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.4281621736
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1131799250
Short name T933
Test name
Test status
Simulation time 173078060681 ps
CPU time 1116.36 seconds
Started Jul 28 07:05:20 PM PDT 24
Finished Jul 28 07:23:57 PM PDT 24
Peak memory 200112 kb
Host smart-d14e0c7b-4027-43f9-8f8d-55d8716fa635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131799250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1131799250
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3611989878
Short name T355
Test name
Test status
Simulation time 262253491462 ps
CPU time 1009.19 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:22:03 PM PDT 24
Peak memory 225004 kb
Host smart-3a7505b2-d399-427a-b22c-baee5c00b958
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611989878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3611989878
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3646312908
Short name T310
Test name
Test status
Simulation time 7665327902 ps
CPU time 10.3 seconds
Started Jul 28 07:05:13 PM PDT 24
Finished Jul 28 07:05:23 PM PDT 24
Peak memory 200056 kb
Host smart-6f8fbf2a-5527-4ca8-916c-d92f0b377d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646312908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3646312908
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.180489352
Short name T410
Test name
Test status
Simulation time 117487592094 ps
CPU time 58.05 seconds
Started Jul 28 07:05:10 PM PDT 24
Finished Jul 28 07:06:08 PM PDT 24
Peak memory 200132 kb
Host smart-b5ab41ac-b5c4-4c54-b4e7-9501887b61d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180489352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.180489352
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.3545947295
Short name T743
Test name
Test status
Simulation time 77887538397 ps
CPU time 84.53 seconds
Started Jul 28 07:11:39 PM PDT 24
Finished Jul 28 07:13:03 PM PDT 24
Peak memory 200144 kb
Host smart-eda60e2a-4619-4825-a3d0-c875a32f19ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545947295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3545947295
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1075829938
Short name T890
Test name
Test status
Simulation time 1165649323515 ps
CPU time 1009.33 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:28:26 PM PDT 24
Peak memory 233208 kb
Host smart-8ab8c258-ae55-49f1-8c53-53e3b6ab64e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075829938 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1075829938
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.440778991
Short name T58
Test name
Test status
Simulation time 104004271489 ps
CPU time 59.21 seconds
Started Jul 28 07:11:39 PM PDT 24
Finished Jul 28 07:12:38 PM PDT 24
Peak memory 200196 kb
Host smart-6b248fda-1e0f-46e7-94df-09dbd81ae8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440778991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.440778991
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.3349974431
Short name T545
Test name
Test status
Simulation time 456531333815 ps
CPU time 835.36 seconds
Started Jul 28 07:11:37 PM PDT 24
Finished Jul 28 07:25:33 PM PDT 24
Peak memory 225016 kb
Host smart-d6e2d138-1545-47b8-945f-1236b8a7e5e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349974431 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.3349974431
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.99267539
Short name T234
Test name
Test status
Simulation time 83252862289 ps
CPU time 34.16 seconds
Started Jul 28 07:11:40 PM PDT 24
Finished Jul 28 07:12:14 PM PDT 24
Peak memory 200140 kb
Host smart-3a8b320c-bb97-47a8-8c6b-f719f7a98e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99267539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.99267539
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1110389010
Short name T81
Test name
Test status
Simulation time 184731976947 ps
CPU time 971.84 seconds
Started Jul 28 07:11:37 PM PDT 24
Finished Jul 28 07:27:49 PM PDT 24
Peak memory 225036 kb
Host smart-f66642d4-de8b-4fee-a826-061e7a3116c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110389010 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1110389010
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3813981740
Short name T1140
Test name
Test status
Simulation time 150799560688 ps
CPU time 205.15 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:15:01 PM PDT 24
Peak memory 200028 kb
Host smart-cf8f095a-c2b4-4cee-8711-ef5f346c4d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813981740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3813981740
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.65938203
Short name T908
Test name
Test status
Simulation time 11215094186 ps
CPU time 181.71 seconds
Started Jul 28 07:11:38 PM PDT 24
Finished Jul 28 07:14:40 PM PDT 24
Peak memory 208420 kb
Host smart-e14d9a4c-28e3-45c9-821f-adfe6dda564d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65938203 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.65938203
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.1108487790
Short name T1104
Test name
Test status
Simulation time 60305805975 ps
CPU time 45.95 seconds
Started Jul 28 07:11:39 PM PDT 24
Finished Jul 28 07:12:25 PM PDT 24
Peak memory 199904 kb
Host smart-20f82d0b-f59f-454b-bb6e-36da38649e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108487790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1108487790
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3060677425
Short name T287
Test name
Test status
Simulation time 314569788807 ps
CPU time 1002.68 seconds
Started Jul 28 07:11:36 PM PDT 24
Finished Jul 28 07:28:19 PM PDT 24
Peak memory 225096 kb
Host smart-a93f0f4e-0f41-46bb-8ca6-f0e6f1b6b842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060677425 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3060677425
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.4064304781
Short name T802
Test name
Test status
Simulation time 575194645919 ps
CPU time 766.62 seconds
Started Jul 28 07:11:42 PM PDT 24
Finished Jul 28 07:24:29 PM PDT 24
Peak memory 230724 kb
Host smart-904ade8a-a97a-4e6d-a56e-c4ab11066a1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064304781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.4064304781
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2876535995
Short name T239
Test name
Test status
Simulation time 14132269137 ps
CPU time 12.66 seconds
Started Jul 28 07:11:42 PM PDT 24
Finished Jul 28 07:11:55 PM PDT 24
Peak memory 200200 kb
Host smart-ada46f81-3dcd-410b-85ca-c3eb64509784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876535995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2876535995
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2355998673
Short name T921
Test name
Test status
Simulation time 348425237119 ps
CPU time 245.53 seconds
Started Jul 28 07:11:43 PM PDT 24
Finished Jul 28 07:15:49 PM PDT 24
Peak memory 215656 kb
Host smart-1a5c4792-afdc-4c9c-b1c7-640a1bba5d86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355998673 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2355998673
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2360637829
Short name T150
Test name
Test status
Simulation time 37280597801 ps
CPU time 32.67 seconds
Started Jul 28 07:11:41 PM PDT 24
Finished Jul 28 07:12:14 PM PDT 24
Peak memory 200212 kb
Host smart-8b7b7397-2775-497c-9236-3a5d4e32755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360637829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2360637829
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.597482459
Short name T34
Test name
Test status
Simulation time 68520399509 ps
CPU time 219.8 seconds
Started Jul 28 07:11:42 PM PDT 24
Finished Jul 28 07:15:22 PM PDT 24
Peak memory 216644 kb
Host smart-e59adbea-f858-4f7b-a919-3b8dc30e5c7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597482459 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.597482459
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2641811402
Short name T655
Test name
Test status
Simulation time 142093380660 ps
CPU time 54.23 seconds
Started Jul 28 07:11:41 PM PDT 24
Finished Jul 28 07:12:35 PM PDT 24
Peak memory 200152 kb
Host smart-a21d4885-0c28-4436-a66c-f3a2dc8687ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641811402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2641811402
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4194196731
Short name T563
Test name
Test status
Simulation time 41484945430 ps
CPU time 348.4 seconds
Started Jul 28 07:11:40 PM PDT 24
Finished Jul 28 07:17:29 PM PDT 24
Peak memory 216668 kb
Host smart-938ae8e4-1246-45ce-b590-c2a1450cfa36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194196731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4194196731
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.442819659
Short name T906
Test name
Test status
Simulation time 12316961167 ps
CPU time 18.43 seconds
Started Jul 28 07:11:43 PM PDT 24
Finished Jul 28 07:12:01 PM PDT 24
Peak memory 200188 kb
Host smart-c031abf8-b011-46aa-adb6-39bf580d5a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442819659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.442819659
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3632176707
Short name T1114
Test name
Test status
Simulation time 33755367827 ps
CPU time 683.32 seconds
Started Jul 28 07:11:43 PM PDT 24
Finished Jul 28 07:23:07 PM PDT 24
Peak memory 216704 kb
Host smart-01f551c0-245b-483f-8f27-073306734893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632176707 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3632176707
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3355715730
Short name T603
Test name
Test status
Simulation time 52256755 ps
CPU time 0.6 seconds
Started Jul 28 07:05:24 PM PDT 24
Finished Jul 28 07:05:24 PM PDT 24
Peak memory 195564 kb
Host smart-b9978727-5fa3-4689-afb2-23ac60f75273
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355715730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3355715730
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.500572876
Short name T457
Test name
Test status
Simulation time 183581053350 ps
CPU time 134.52 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:07:39 PM PDT 24
Peak memory 200096 kb
Host smart-0995aef7-0415-4040-a8f1-57ead2f7608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500572876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.500572876
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1765857848
Short name T680
Test name
Test status
Simulation time 55821342934 ps
CPU time 83.72 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:06:43 PM PDT 24
Peak memory 200208 kb
Host smart-86c8ab82-4ffe-4791-8c5c-d7dcf3d61f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765857848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1765857848
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3869456062
Short name T1136
Test name
Test status
Simulation time 49838436842 ps
CPU time 82.38 seconds
Started Jul 28 07:05:18 PM PDT 24
Finished Jul 28 07:06:41 PM PDT 24
Peak memory 199992 kb
Host smart-e048855e-a5e8-408d-b346-baad1c026497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869456062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3869456062
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.786580046
Short name T826
Test name
Test status
Simulation time 151416240713 ps
CPU time 87.74 seconds
Started Jul 28 07:05:20 PM PDT 24
Finished Jul 28 07:06:48 PM PDT 24
Peak memory 200184 kb
Host smart-524ddde5-0548-4aff-9f55-c45840c9d08a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786580046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.786580046
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1754548252
Short name T257
Test name
Test status
Simulation time 115013091112 ps
CPU time 395.09 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:11:54 PM PDT 24
Peak memory 200164 kb
Host smart-5d5a6747-c3b6-4a1b-b1d7-b46738e3a276
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754548252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1754548252
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2309267960
Short name T406
Test name
Test status
Simulation time 13100227730 ps
CPU time 5.51 seconds
Started Jul 28 07:05:24 PM PDT 24
Finished Jul 28 07:05:30 PM PDT 24
Peak memory 200144 kb
Host smart-c3c713df-d2eb-43f3-ad38-bf063b4f4417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309267960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2309267960
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1223545370
Short name T792
Test name
Test status
Simulation time 163261103331 ps
CPU time 140.44 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:07:40 PM PDT 24
Peak memory 200292 kb
Host smart-f6472f36-6172-4d8a-b21e-16b1ab377b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223545370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1223545370
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.757471471
Short name T1084
Test name
Test status
Simulation time 34164982475 ps
CPU time 769.17 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:18:09 PM PDT 24
Peak memory 200172 kb
Host smart-a32d8d75-36f0-41a1-90c3-de58fe1f145f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=757471471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.757471471
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2053265502
Short name T968
Test name
Test status
Simulation time 5805400406 ps
CPU time 13.35 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:05:32 PM PDT 24
Peak memory 198240 kb
Host smart-c93815bb-f059-4017-82db-9affff7384b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2053265502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2053265502
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2873626539
Short name T512
Test name
Test status
Simulation time 13719531866 ps
CPU time 11.43 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:05:36 PM PDT 24
Peak memory 199880 kb
Host smart-b43277b2-0569-455b-ab02-b4c767a053d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873626539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2873626539
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3234667959
Short name T256
Test name
Test status
Simulation time 7460913227 ps
CPU time 6.94 seconds
Started Jul 28 07:05:20 PM PDT 24
Finished Jul 28 07:05:27 PM PDT 24
Peak memory 196728 kb
Host smart-a1701f11-3e70-4acf-b1b1-9923d77e5fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234667959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3234667959
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2402004831
Short name T438
Test name
Test status
Simulation time 457463337 ps
CPU time 1.89 seconds
Started Jul 28 07:05:18 PM PDT 24
Finished Jul 28 07:05:20 PM PDT 24
Peak memory 200128 kb
Host smart-e0a07fa1-89b9-41e0-a3a3-968bbe71149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402004831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2402004831
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.723371120
Short name T1013
Test name
Test status
Simulation time 4295405814 ps
CPU time 3.81 seconds
Started Jul 28 07:05:19 PM PDT 24
Finished Jul 28 07:05:23 PM PDT 24
Peak memory 198272 kb
Host smart-fc5530d4-5eb6-4e99-b509-78abcc91ea29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723371120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.723371120
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.4140287091
Short name T435
Test name
Test status
Simulation time 1146097322 ps
CPU time 2 seconds
Started Jul 28 07:05:20 PM PDT 24
Finished Jul 28 07:05:22 PM PDT 24
Peak memory 199956 kb
Host smart-3d68ae6c-a9ec-489f-82a5-0b92a1abde5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140287091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.4140287091
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2281082072
Short name T902
Test name
Test status
Simulation time 46602805741 ps
CPU time 33.37 seconds
Started Jul 28 07:05:25 PM PDT 24
Finished Jul 28 07:05:58 PM PDT 24
Peak memory 200180 kb
Host smart-e4dca3e9-08c3-4389-8e3f-753d5c9de657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281082072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2281082072
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4181613927
Short name T151
Test name
Test status
Simulation time 139865063119 ps
CPU time 16.96 seconds
Started Jul 28 07:11:44 PM PDT 24
Finished Jul 28 07:12:01 PM PDT 24
Peak memory 200188 kb
Host smart-49d17269-c218-4fac-8fd9-5de450a80faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181613927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4181613927
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3647835069
Short name T1019
Test name
Test status
Simulation time 206442991549 ps
CPU time 431.8 seconds
Started Jul 28 07:11:42 PM PDT 24
Finished Jul 28 07:18:54 PM PDT 24
Peak memory 216744 kb
Host smart-78ec7a87-eae7-47c2-90bc-537922f85dfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647835069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3647835069
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.3674707073
Short name T737
Test name
Test status
Simulation time 17103760495 ps
CPU time 25.39 seconds
Started Jul 28 07:11:44 PM PDT 24
Finished Jul 28 07:12:09 PM PDT 24
Peak memory 200180 kb
Host smart-8f7b7ec4-8a40-4eee-81dc-4ad0bf78bb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674707073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.3674707073
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.922268894
Short name T778
Test name
Test status
Simulation time 9519578514 ps
CPU time 97.82 seconds
Started Jul 28 07:11:44 PM PDT 24
Finished Jul 28 07:13:22 PM PDT 24
Peak memory 209692 kb
Host smart-2ce52401-7c35-4e3b-badf-e86aaa86c9fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922268894 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.922268894
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3620962821
Short name T211
Test name
Test status
Simulation time 238190670124 ps
CPU time 33.61 seconds
Started Jul 28 07:11:41 PM PDT 24
Finished Jul 28 07:12:14 PM PDT 24
Peak memory 200300 kb
Host smart-8618c2e8-d6cd-4111-b18b-520832af580f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620962821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3620962821
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.4000640126
Short name T767
Test name
Test status
Simulation time 170643414816 ps
CPU time 686.86 seconds
Started Jul 28 07:11:43 PM PDT 24
Finished Jul 28 07:23:11 PM PDT 24
Peak memory 225008 kb
Host smart-e1fba96f-06c9-40ee-a363-fc50d604e681
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000640126 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.4000640126
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1387064941
Short name T528
Test name
Test status
Simulation time 17977226668 ps
CPU time 23.63 seconds
Started Jul 28 07:11:40 PM PDT 24
Finished Jul 28 07:12:04 PM PDT 24
Peak memory 200360 kb
Host smart-fc5b813f-7598-4642-84be-2a8f5c31fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387064941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1387064941
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.2975399015
Short name T550
Test name
Test status
Simulation time 11660657292 ps
CPU time 119.85 seconds
Started Jul 28 07:11:42 PM PDT 24
Finished Jul 28 07:13:42 PM PDT 24
Peak memory 216140 kb
Host smart-a8dd6d80-54b3-4afb-b350-7b93c6432f0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975399015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.2975399015
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3305661721
Short name T229
Test name
Test status
Simulation time 440926245271 ps
CPU time 1424.31 seconds
Started Jul 28 07:11:48 PM PDT 24
Finished Jul 28 07:35:33 PM PDT 24
Peak memory 227252 kb
Host smart-bb8a3221-0510-4a83-81c0-47e2a1f99274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305661721 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3305661721
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3945417989
Short name T682
Test name
Test status
Simulation time 27751574883 ps
CPU time 121.06 seconds
Started Jul 28 07:11:48 PM PDT 24
Finished Jul 28 07:13:49 PM PDT 24
Peak memory 215744 kb
Host smart-99b982d9-c58b-40a2-be4f-f49c08797855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945417989 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3945417989
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.4243389451
Short name T51
Test name
Test status
Simulation time 35164793196 ps
CPU time 30.14 seconds
Started Jul 28 07:11:49 PM PDT 24
Finished Jul 28 07:12:19 PM PDT 24
Peak memory 200176 kb
Host smart-19da645b-7502-447a-8a8c-6b2f7abce7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243389451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.4243389451
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2245517995
Short name T18
Test name
Test status
Simulation time 31171013371 ps
CPU time 380.41 seconds
Started Jul 28 07:11:48 PM PDT 24
Finished Jul 28 07:18:09 PM PDT 24
Peak memory 214172 kb
Host smart-77e28ffe-58d4-4166-a98c-53e69269ed39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245517995 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2245517995
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.3523545905
Short name T214
Test name
Test status
Simulation time 184425785131 ps
CPU time 37.24 seconds
Started Jul 28 07:11:46 PM PDT 24
Finished Jul 28 07:12:24 PM PDT 24
Peak memory 200048 kb
Host smart-096240bc-8bcc-4ae4-921e-9e334cf495cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523545905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.3523545905
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1785351764
Short name T464
Test name
Test status
Simulation time 132927998596 ps
CPU time 1745.62 seconds
Started Jul 28 07:11:47 PM PDT 24
Finished Jul 28 07:40:53 PM PDT 24
Peak memory 216640 kb
Host smart-2d393d5d-aa4e-4734-bb6e-cc1a3791409a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785351764 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1785351764
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.3663602874
Short name T188
Test name
Test status
Simulation time 29698316577 ps
CPU time 46.47 seconds
Started Jul 28 07:11:47 PM PDT 24
Finished Jul 28 07:12:33 PM PDT 24
Peak memory 200152 kb
Host smart-ca165790-1d21-40c3-874d-7cf1bc575062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663602874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.3663602874
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2036514948
Short name T1164
Test name
Test status
Simulation time 41717450363 ps
CPU time 217.07 seconds
Started Jul 28 07:11:47 PM PDT 24
Finished Jul 28 07:15:25 PM PDT 24
Peak memory 216228 kb
Host smart-27035406-3cf5-4d02-80fd-47367738599f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036514948 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2036514948
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.4117226350
Short name T184
Test name
Test status
Simulation time 167712080069 ps
CPU time 140.61 seconds
Started Jul 28 07:11:46 PM PDT 24
Finished Jul 28 07:14:07 PM PDT 24
Peak memory 200188 kb
Host smart-0d8446a2-b129-4104-a48c-5b0447a36df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117226350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4117226350
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1244523422
Short name T920
Test name
Test status
Simulation time 12544826370 ps
CPU time 116.43 seconds
Started Jul 28 07:11:46 PM PDT 24
Finished Jul 28 07:13:43 PM PDT 24
Peak memory 216828 kb
Host smart-66c39a8d-5f99-4542-83cd-68ef413d0f2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244523422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1244523422
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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