Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	103244	1			T1	1		T2	53		T3	46
all_values[1]	103244	1			T1	1		T2	53		T3	46
all_values[2]	103244	1			T1	1		T2	53		T3	46
all_values[3]	103244	1			T1	1		T2	53		T3	46
all_values[4]	103244	1			T1	1		T2	53		T3	46
all_values[5]	103244	1			T1	1		T2	53		T3	46
all_values[6]	103244	1			T1	1		T2	53		T3	46
all_values[7]	103244	1			T1	1		T2	53		T3	46
all_values[8]	103244	1			T1	1		T2	53		T3	46

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

467070

1

T1

5

T2

300

T3

204

auto[1]

462126

1

T1

4

T2

177

T3

210

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

833881

1

T1

7

T2

469

T3

335

auto[1]

95315

1

T1

2

T2

8

T3

79

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	27633	1			T2	43		T3	3		T4	332
all_values[0]	auto[0]	auto[1]	22096	1			T1	1		T3	35		T4	9
all_values[0]	auto[1]	auto[0]	28598	1			T2	7		T3	7		T4	26
all_values[0]	auto[1]	auto[1]	24917	1			T2	3		T3	1		T5	2
all_values[1]	auto[0]	auto[0]	50261	1			T1	1		T2	8		T3	1
all_values[1]	auto[0]	auto[1]	1911	1			T7	15		T10	1		T34	7
all_values[1]	auto[1]	auto[0]	49594	1			T2	45		T3	41		T4	123
all_values[1]	auto[1]	auto[1]	1478	1			T3	4		T7	5		T10	2
all_values[2]	auto[0]	auto[0]	53224	1			T2	45		T3	26		T4	264
all_values[2]	auto[0]	auto[1]	2887	1			T2	3		T3	2		T4	3
all_values[2]	auto[1]	auto[0]	44619	1			T1	1		T2	5		T3	17
all_values[2]	auto[1]	auto[1]	2514	1			T3	1		T4	3		T6	3
all_values[3]	auto[0]	auto[0]	50497	1			T1	1		T2	4		T3	19
all_values[3]	auto[0]	auto[1]	348	1			T7	7		T10	2		T13	2
all_values[3]	auto[1]	auto[0]	52072	1			T2	49		T3	27		T4	78
all_values[3]	auto[1]	auto[1]	327	1			T7	2		T8	1		T10	2
all_values[4]	auto[0]	auto[0]	50578	1			T2	48		T3	23		T4	264
all_values[4]	auto[0]	auto[1]	543	1			T7	4		T10	3		T13	1
all_values[4]	auto[1]	auto[0]	51638	1			T1	1		T2	5		T3	23
all_values[4]	auto[1]	auto[1]	485	1			T7	6		T15	1		T20	4
all_values[5]	auto[0]	auto[0]	54073	1			T2	2		T3	24		T4	311
all_values[5]	auto[0]	auto[1]	195	1			T7	2		T10	4		T13	2
all_values[5]	auto[1]	auto[0]	48791	1			T1	1		T2	51		T3	22
all_values[5]	auto[1]	auto[1]	185	1			T7	8		T10	1		T13	2
all_values[6]	auto[0]	auto[0]	49124	1			T1	1		T2	45		T3	5
all_values[6]	auto[0]	auto[1]	208	1			T7	4		T10	1		T13	3
all_values[6]	auto[1]	auto[0]	53708	1			T2	8		T3	41		T4	100
all_values[6]	auto[1]	auto[1]	204	1			T7	4		T10	3		T15	3
all_values[7]	auto[0]	auto[0]	54954	1			T1	1		T2	53		T3	42
all_values[7]	auto[0]	auto[1]	356	1			T7	4		T10	2		T13	2
all_values[7]	auto[1]	auto[0]	47571	1			T3	4		T4	106		T5	35
all_values[7]	auto[1]	auto[1]	363	1			T7	6		T10	3		T13	1
all_values[8]	auto[0]	auto[0]	29596	1			T2	47		T4	49		T5	8
all_values[8]	auto[0]	auto[1]	18586	1			T2	2		T3	24		T4	6
all_values[8]	auto[1]	auto[0]	37350	1			T2	4		T3	10		T4	311
all_values[8]	auto[1]	auto[1]	17712	1			T1	1		T3	12		T4	1