Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2407	1			T1	12		T2	3		T3	3
auto[BaudRate115200]	2101	1			T1	3		T2	2		T3	4
auto[BaudRate230400]	2107	1			T4	7		T7	8		T8	2
auto[BaudRate128Kbps]	2074	1			T2	1		T4	4		T7	6
auto[BaudRate256Kbps]	2156	1			T1	3		T2	1		T3	2
auto[BaudRate1Mbps]	1904	1			T3	1		T4	10		T5	2
auto[BaudRate1p5Mbps]	1301	1			T4	8		T5	1		T7	6

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1445	1			T7	48		T35	10		T15	17
freqs[25]	1273	1			T3	10		T40	2		T29	91
freqs[48]	448	1			T37	10		T19	57		T279	2
freqs[50]	452	1			T127	8		T295	7		T323	1
freqs[100]	1012	1			T20	30		T42	7		T304	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	162	1			T7	6		T15	2		T48	1
auto[BaudRate9600]	freqs[25]	299	1			T3	3		T40	1		T29	12
auto[BaudRate9600]	freqs[48]	78	1			T19	12		T279	1		T43	1
auto[BaudRate9600]	freqs[50]	72	1			T127	1		T295	1		T273	1
auto[BaudRate9600]	freqs[100]	170	1			T20	3		T42	1		T148	1
auto[BaudRate115200]	freqs[24]	242	1			T7	8		T15	2		T46	1
auto[BaudRate115200]	freqs[25]	206	1			T3	4		T40	1		T29	17
auto[BaudRate115200]	freqs[48]	64	1			T37	1		T19	6		T279	1
auto[BaudRate115200]	freqs[50]	52	1			T127	1		T277	1		T273	1
auto[BaudRate115200]	freqs[100]	123	1			T20	4		T42	1		T261	2
auto[BaudRate230400]	freqs[24]	230	1			T7	8		T15	3		T46	1
auto[BaudRate230400]	freqs[25]	167	1			T29	5		T175	3		T330	3
auto[BaudRate230400]	freqs[48]	49	1			T37	3		T47	12		T66	1
auto[BaudRate230400]	freqs[50]	74	1			T127	3		T295	2		T323	1
auto[BaudRate230400]	freqs[100]	146	1			T20	1		T42	1		T304	1
auto[BaudRate128Kbps]	freqs[24]	200	1			T7	6		T15	4		T129	1
auto[BaudRate128Kbps]	freqs[25]	172	1			T29	16		T18	1		T256	1
auto[BaudRate128Kbps]	freqs[48]	52	1			T37	1		T19	9		T47	9
auto[BaudRate128Kbps]	freqs[50]	63	1			T127	1		T295	1		T277	1
auto[BaudRate128Kbps]	freqs[100]	142	1			T20	4		T136	5		T63	1
auto[BaudRate256Kbps]	freqs[24]	177	1			T7	5		T35	3		T15	1
auto[BaudRate256Kbps]	freqs[25]	172	1			T3	2		T29	14		T256	2
auto[BaudRate256Kbps]	freqs[48]	69	1			T37	2		T19	9		T41	3
auto[BaudRate256Kbps]	freqs[50]	69	1			T295	1		T273	1		T121	3
auto[BaudRate256Kbps]	freqs[100]	138	1			T20	10		T261	2		T63	1
auto[BaudRate1Mbps]	freqs[24]	279	1			T7	9		T35	6		T15	5
auto[BaudRate1Mbps]	freqs[25]	166	1			T3	1		T29	20		T256	2
auto[BaudRate1Mbps]	freqs[48]	58	1			T37	1		T19	9		T41	3
auto[BaudRate1Mbps]	freqs[50]	58	1			T273	1		T260	1		T121	1
auto[BaudRate1Mbps]	freqs[100]	137	1			T20	4		T42	1		T261	2
auto[BaudRate1p5Mbps]	freqs[25]	91	1			T29	7		T17	13		T288	5
auto[BaudRate1p5Mbps]	freqs[48]	78	1			T37	2		T19	12		T41	4
auto[BaudRate1p5Mbps]	freqs[50]	64	1			T127	2		T295	2		T273	1
auto[BaudRate1p5Mbps]	freqs[100]	156	1			T20	4		T42	3		T304	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded