Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.94	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	8	122	93.85

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	8	122	93.85	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29716877	1			T1	6		T2	105		T3	85
all_levels[1]	206767	1			T2	4		T3	8		T4	25
all_levels[2]	2634	1			T2	2		T3	12		T4	1
all_levels[3]	1050	1			T2	1		T3	4		T4	1
all_levels[4]	703	1			T2	1		T3	8		T7	2
all_levels[5]	489	1			T3	2		T4	1		T7	3
all_levels[6]	398	1			T3	3		T7	1		T34	1
all_levels[7]	354	1			T2	1		T3	5		T4	2
all_levels[8]	281	1			T2	1		T3	2		T4	2
all_levels[9]	281	1			T2	1		T3	3		T4	1
all_levels[10]	211	1			T3	2		T34	1		T92	1
all_levels[11]	187	1			T4	2		T8	1		T116	1
all_levels[12]	170	1			T3	2		T4	1		T127	1
all_levels[13]	159	1			T34	1		T20	1		T128	2
all_levels[14]	141	1			T127	1		T116	1		T28	1
all_levels[15]	138	1			T3	1		T4	2		T34	2
all_levels[16]	87	1			T128	1		T118	1		T28	1
all_levels[17]	102	1			T2	1		T15	1		T28	1
all_levels[18]	106	1			T2	3		T127	1		T117	1
all_levels[19]	94	1			T8	1		T15	1		T42	1
all_levels[20]	76	1			T30	1		T129	2		T130	1
all_levels[21]	76	1			T34	1		T20	2		T117	1
all_levels[22]	72	1			T116	1		T117	1		T131	1
all_levels[23]	64	1			T127	1		T42	1		T117	1
all_levels[24]	51	1			T28	1		T130	1		T132	1
all_levels[25]	65	1			T3	1		T10	1		T133	2
all_levels[26]	77	1			T8	1		T34	1		T127	1
all_levels[27]	52	1			T127	1		T118	1		T28	1
all_levels[28]	43	1			T34	1		T134	1		T135	1
all_levels[29]	43	1			T117	1		T136	1		T67	2
all_levels[30]	37	1			T34	1		T118	1		T130	1
all_levels[31]	29	1			T32	2		T137	1		T138	1
all_levels[32]	33	1			T11	2		T28	1		T135	1
all_levels[33]	28	1			T129	1		T50	1		T64	1
all_levels[34]	23	1			T28	2		T139	1		T140	1
all_levels[35]	38	1			T34	1		T127	1		T131	1
all_levels[36]	30	1			T127	1		T17	1		T141	1
all_levels[37]	19	1			T20	1		T66	1		T142	1
all_levels[38]	28	1			T50	1		T64	1		T66	1
all_levels[39]	18	1			T32	2		T15	1		T67	1
all_levels[40]	18	1			T28	1		T143	1		T144	1
all_levels[41]	25	1			T145	1		T146	1		T147	1
all_levels[42]	24	1			T7	3		T28	2		T148	1
all_levels[43]	13	1			T32	1		T143	1		T108	1
all_levels[44]	18	1			T132	1		T148	1		T52	1
all_levels[45]	21	1			T65	2		T149	1		T150	1
all_levels[46]	22	1			T67	1		T151	1		T152	4
all_levels[47]	9	1			T112	1		T153	2		T154	1
all_levels[48]	10	1			T155	1		T156	2		T157	1
all_levels[49]	4	1			T158	1		T159	1		T51	1
all_levels[50]	20	1			T129	1		T130	2		T143	1
all_levels[51]	10	1			T145	1		T160	1		T161	1
all_levels[52]	15	1			T162	2		T138	1		T163	1
all_levels[53]	16	1			T132	1		T164	1		T165	1
all_levels[54]	9	1			T127	1		T166	1		T167	2
all_levels[55]	8	1			T168	1		T52	1		T169	1
all_levels[56]	14	1			T151	1		T120	1		T138	1
all_levels[57]	15	1			T142	3		T137	1		T167	1
all_levels[58]	3	1			T170	2		T171	1		-	-
all_levels[59]	4	1			T159	1		T172	1		T79	2
all_levels[60]	6	1			T34	1		T173	1		T174	1
all_levels[61]	6	1			T175	1		T176	1		T177	1
all_levels[62]	8	1			T178	1		T179	1		T180	1
all_levels[63]	1	1			T181	1		-	-		-	-
all_levels[64]	101	1			T132	1		T182	2		T183	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29927577

1

T2

116

T3

131

T4

146512

auto[1]

4954

1

T1

6

T2

4

T3

7

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	8	122	93.85	8

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[43]]	[auto[1]]	0	1	1
[all_levels[48] , all_levels[49]]	[auto[1]]	--	--	2
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[59]]	[auto[1]]	0	1	1
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29712410	1			T2	103		T3	79		T4	146474
all_levels[0]	auto[1]	4467	1			T1	6		T2	2		T3	6
all_levels[1]	auto[0]	206679	1			T2	4		T3	8		T4	25
all_levels[1]	auto[1]	88	1			T33	2		T106	4		T117	2
all_levels[2]	auto[0]	2599	1			T2	2		T3	12		T4	1
all_levels[2]	auto[1]	35	1			T130	1		T66	2		T184	2
all_levels[3]	auto[0]	1033	1			T2	1		T3	4		T4	1
all_levels[3]	auto[1]	17	1			T162	2		T185	1		T186	2
all_levels[4]	auto[0]	674	1			T2	1		T3	8		T7	2
all_levels[4]	auto[1]	29	1			T128	1		T187	2		T188	2
all_levels[5]	auto[0]	477	1			T3	2		T4	1		T7	3
all_levels[5]	auto[1]	12	1			T50	1		T150	1		T189	1
all_levels[6]	auto[0]	380	1			T3	3		T7	1		T34	1
all_levels[6]	auto[1]	18	1			T133	1		T153	2		T190	1
all_levels[7]	auto[0]	343	1			T2	1		T3	5		T4	2
all_levels[7]	auto[1]	11	1			T92	1		T118	1		T63	1
all_levels[8]	auto[0]	275	1			T2	1		T3	2		T4	2
all_levels[8]	auto[1]	6	1			T191	1		T192	1		T193	1
all_levels[9]	auto[0]	255	1			T2	1		T3	3		T4	1
all_levels[9]	auto[1]	26	1			T11	1		T130	1		T194	1
all_levels[10]	auto[0]	196	1			T3	2		T34	1		T92	1
all_levels[10]	auto[1]	15	1			T38	3		T195	1		T196	2
all_levels[11]	auto[0]	178	1			T4	2		T8	1		T116	1
all_levels[11]	auto[1]	9	1			T128	1		T197	1		T198	2
all_levels[12]	auto[0]	164	1			T3	1		T4	1		T127	1
all_levels[12]	auto[1]	6	1			T3	1		T199	1		T200	1
all_levels[13]	auto[0]	146	1			T34	1		T20	1		T128	2
all_levels[13]	auto[1]	13	1			T117	1		T67	4		T184	3
all_levels[14]	auto[0]	137	1			T127	1		T116	1		T28	1
all_levels[14]	auto[1]	4	1			T176	1		T201	1		T202	1
all_levels[15]	auto[0]	127	1			T3	1		T4	2		T34	2
all_levels[15]	auto[1]	11	1			T159	1		T179	2		T203	1
all_levels[16]	auto[0]	84	1			T128	1		T118	1		T28	1
all_levels[16]	auto[1]	3	1			T142	1		T204	2		-	-
all_levels[17]	auto[0]	95	1			T2	1		T15	1		T28	1
all_levels[17]	auto[1]	7	1			T141	2		T188	1		T205	1
all_levels[18]	auto[0]	91	1			T2	1		T127	1		T117	1
all_levels[18]	auto[1]	15	1			T2	2		T206	2		T188	1
all_levels[19]	auto[0]	88	1			T8	1		T15	1		T42	1
all_levels[19]	auto[1]	6	1			T184	2		T207	1		T208	1
all_levels[20]	auto[0]	71	1			T30	1		T129	1		T130	1
all_levels[20]	auto[1]	5	1			T129	1		T141	1		T209	2
all_levels[21]	auto[0]	67	1			T34	1		T20	2		T117	1
all_levels[21]	auto[1]	9	1			T136	1		T168	1		T210	1
all_levels[22]	auto[0]	68	1			T116	1		T117	1		T131	1
all_levels[22]	auto[1]	4	1			T149	1		T211	1		T212	2
all_levels[23]	auto[0]	55	1			T127	1		T42	1		T117	1
all_levels[23]	auto[1]	9	1			T169	1		T213	3		T214	1
all_levels[24]	auto[0]	50	1			T28	1		T130	1		T132	1
all_levels[24]	auto[1]	1	1			T215	1		-	-		-	-
all_levels[25]	auto[0]	57	1			T3	1		T10	1		T133	1
all_levels[25]	auto[1]	8	1			T133	1		T216	3		T217	1
all_levels[26]	auto[0]	71	1			T8	1		T34	1		T127	1
all_levels[26]	auto[1]	6	1			T42	4		T218	1		T185	1
all_levels[27]	auto[0]	49	1			T127	1		T118	1		T28	1
all_levels[27]	auto[1]	3	1			T219	1		T220	1		T221	1
all_levels[28]	auto[0]	39	1			T34	1		T134	1		T135	1
all_levels[28]	auto[1]	4	1			T51	2		T222	2		-	-
all_levels[29]	auto[0]	40	1			T117	1		T136	1		T67	1
all_levels[29]	auto[1]	3	1			T67	1		T223	1		T224	1
all_levels[30]	auto[0]	30	1			T34	1		T118	1		T130	1
all_levels[30]	auto[1]	7	1			T63	2		T225	2		T226	1
all_levels[31]	auto[0]	23	1			T32	1		T137	1		T138	1
all_levels[31]	auto[1]	6	1			T32	1		T139	4		T212	1
all_levels[32]	auto[0]	29	1			T11	1		T28	1		T135	1
all_levels[32]	auto[1]	4	1			T11	1		T227	1		T228	1
all_levels[33]	auto[0]	25	1			T129	1		T50	1		T64	1
all_levels[33]	auto[1]	3	1			T150	1		T179	1		T229	1
all_levels[34]	auto[0]	22	1			T28	2		T139	1		T140	1
all_levels[34]	auto[1]	1	1			T230	1		-	-		-	-
all_levels[35]	auto[0]	34	1			T34	1		T127	1		T131	1
all_levels[35]	auto[1]	4	1			T209	1		T231	1		T232	1
all_levels[36]	auto[0]	25	1			T127	1		T17	1		T141	1
all_levels[36]	auto[1]	5	1			T193	1		T233	1		T217	2
all_levels[37]	auto[0]	18	1			T20	1		T66	1		T142	1
all_levels[37]	auto[1]	1	1			T234	1		-	-		-	-
all_levels[38]	auto[0]	26	1			T50	1		T64	1		T66	1
all_levels[38]	auto[1]	2	1			T235	1		T236	1		-	-
all_levels[39]	auto[0]	16	1			T32	1		T15	1		T67	1
all_levels[39]	auto[1]	2	1			T32	1		T237	1		-	-
all_levels[40]	auto[0]	17	1			T28	1		T143	1		T144	1
all_levels[40]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[41]	auto[0]	19	1			T145	1		T146	1		T147	1
all_levels[41]	auto[1]	6	1			T239	3		T240	1		T241	1
all_levels[42]	auto[0]	21	1			T7	2		T28	1		T148	1
all_levels[42]	auto[1]	3	1			T7	1		T28	1		T241	1
all_levels[43]	auto[0]	13	1			T32	1		T143	1		T108	1
all_levels[44]	auto[0]	15	1			T132	1		T148	1		T52	1
all_levels[44]	auto[1]	3	1			T211	1		T242	1		T243	1
all_levels[45]	auto[0]	16	1			T65	1		T149	1		T150	1
all_levels[45]	auto[1]	5	1			T65	1		T244	1		T57	1
all_levels[46]	auto[0]	14	1			T67	1		T151	1		T152	1
all_levels[46]	auto[1]	8	1			T152	3		T218	1		T245	4
all_levels[47]	auto[0]	7	1			T112	1		T153	1		T154	1
all_levels[47]	auto[1]	2	1			T153	1		T246	1		-	-
all_levels[48]	auto[0]	10	1			T155	1		T156	2		T157	1
all_levels[49]	auto[0]	4	1			T158	1		T159	1		T51	1
all_levels[50]	auto[0]	15	1			T129	1		T130	1		T143	1
all_levels[50]	auto[1]	5	1			T130	1		T247	1		T233	2
all_levels[51]	auto[0]	9	1			T145	1		T160	1		T161	1
all_levels[51]	auto[1]	1	1			T248	1		-	-		-	-
all_levels[52]	auto[0]	12	1			T162	1		T138	1		T163	1
all_levels[52]	auto[1]	3	1			T162	1		T249	1		T250	1
all_levels[53]	auto[0]	13	1			T132	1		T164	1		T165	1
all_levels[53]	auto[1]	3	1			T251	3		-	-		-	-
all_levels[54]	auto[0]	9	1			T127	1		T166	1		T167	2
all_levels[55]	auto[0]	8	1			T168	1		T52	1		T169	1
all_levels[56]	auto[0]	12	1			T151	1		T120	1		T138	1
all_levels[56]	auto[1]	2	1			T234	1		T211	1		-	-
all_levels[57]	auto[0]	12	1			T142	1		T137	1		T167	1
all_levels[57]	auto[1]	3	1			T142	2		T252	1		-	-
all_levels[58]	auto[0]	2	1			T170	1		T171	1		-	-
all_levels[58]	auto[1]	1	1			T170	1		-	-		-	-
all_levels[59]	auto[0]	4	1			T159	1		T172	1		T79	2
all_levels[60]	auto[0]	5	1			T34	1		T173	1		T174	1
all_levels[60]	auto[1]	1	1			T253	1		-	-		-	-
all_levels[61]	auto[0]	5	1			T175	1		T176	1		T177	1
all_levels[61]	auto[1]	1	1			T254	1		-	-		-	-
all_levels[62]	auto[0]	8	1			T178	1		T179	1		T180	1
all_levels[63]	auto[0]	1	1			T181	1		-	-		-	-
all_levels[64]	auto[0]	80	1			T132	1		T182	2		T183	2
all_levels[64]	auto[1]	21	1			T123	2		T227	4		T223	2