Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	103244	1			T1	1		T2	53		T3	46
all_pins[1]	103244	1			T1	1		T2	53		T3	46
all_pins[2]	103244	1			T1	1		T2	53		T3	46
all_pins[3]	103244	1			T1	1		T2	53		T3	46
all_pins[4]	103244	1			T1	1		T2	53		T3	46
all_pins[5]	103244	1			T1	1		T2	53		T3	46
all_pins[6]	103244	1			T1	1		T2	53		T3	46
all_pins[7]	103244	1			T1	1		T2	53		T3	46
all_pins[8]	103244	1			T1	1		T2	53		T3	46

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	880011	1			T1	8		T2	474		T3	395
values[0x1]	49185	1			T1	1		T2	3		T3	19
transitions[0x0=>0x1]	39035	1			T2	3		T3	19		T4	4
transitions[0x1=>0x0]	38870	1			T1	1		T2	2		T3	18

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	78247	1			T1	1		T2	50		T3	45
all_pins[0]	values[0x1]	24997	1			T2	3		T3	1		T5	2
all_pins[0]	transitions[0x0=>0x1]	24408	1			T2	3		T3	1		T5	2
all_pins[0]	transitions[0x1=>0x0]	882	1			T3	4		T7	2		T37	7
all_pins[1]	values[0x0]	101773	1			T1	1		T2	53		T3	42
all_pins[1]	values[0x1]	1471	1			T3	4		T7	5		T10	2
all_pins[1]	transitions[0x0=>0x1]	1359	1			T3	4		T7	5		T10	2
all_pins[1]	transitions[0x1=>0x0]	2473	1			T3	1		T4	3		T6	3
all_pins[2]	values[0x0]	100659	1			T1	1		T2	53		T3	45
all_pins[2]	values[0x1]	2585	1			T3	1		T4	3		T6	3
all_pins[2]	transitions[0x0=>0x1]	2505	1			T3	1		T4	3		T6	3
all_pins[2]	transitions[0x1=>0x0]	247	1			T7	2		T20	5		T50	3
all_pins[3]	values[0x0]	102917	1			T1	1		T2	53		T3	46
all_pins[3]	values[0x1]	327	1			T7	2		T8	1		T10	2
all_pins[3]	transitions[0x0=>0x1]	280	1			T7	2		T8	1		T10	2
all_pins[3]	transitions[0x1=>0x0]	438	1			T7	6		T20	2		T16	6
all_pins[4]	values[0x0]	102759	1			T1	1		T2	53		T3	46
all_pins[4]	values[0x1]	485	1			T7	6		T15	1		T20	4
all_pins[4]	transitions[0x0=>0x1]	417	1			T7	6		T15	1		T20	4
all_pins[4]	transitions[0x1=>0x0]	182	1			T7	8		T10	1		T13	2
all_pins[5]	values[0x0]	102994	1			T1	1		T2	53		T3	46
all_pins[5]	values[0x1]	250	1			T7	8		T10	1		T13	2
all_pins[5]	transitions[0x0=>0x1]	202	1			T7	5		T10	1		T13	2
all_pins[5]	transitions[0x1=>0x0]	863	1			T3	1		T7	1		T10	3
all_pins[6]	values[0x0]	102333	1			T1	1		T2	53		T3	45
all_pins[6]	values[0x1]	911	1			T3	1		T7	4		T10	3
all_pins[6]	transitions[0x0=>0x1]	854	1			T3	1		T7	3		T116	9
all_pins[6]	transitions[0x1=>0x0]	306	1			T7	5		T13	1		T15	3
all_pins[7]	values[0x0]	102881	1			T1	1		T2	53		T3	46
all_pins[7]	values[0x1]	363	1			T7	6		T10	3		T13	1
all_pins[7]	transitions[0x0=>0x1]	220	1			T7	3		T10	3		T13	1
all_pins[7]	transitions[0x1=>0x0]	17653	1			T1	1		T3	12		T4	1
all_pins[8]	values[0x0]	85448	1			T2	53		T3	34		T4	366
all_pins[8]	values[0x1]	17796	1			T1	1		T3	12		T4	1
all_pins[8]	transitions[0x0=>0x1]	8790	1			T3	12		T4	1		T5	1
all_pins[8]	transitions[0x1=>0x0]	15826	1			T2	2		T5	1		T6	3