Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8263956	1			T2	2		T3	104		T4	85
all_levels[1]	1608481	1			T2	11		T3	5		T4	140
all_levels[2]	246039	1			T4	167		T6	5		T7	21
all_levels[3]	303194	1			T3	3		T4	163		T6	1
all_levels[4]	549513	1			T4	163		T6	3		T7	13
all_levels[5]	191459	1			T3	3		T4	163		T6	1
all_levels[6]	209438	1			T3	3		T4	167		T6	1
all_levels[7]	214546	1			T3	3		T4	159		T7	27
all_levels[8]	307072	1			T4	111		T6	1		T7	27
all_levels[9]	203245	1			T2	3		T4	84		T7	28
all_levels[10]	192510	1			T3	1		T4	81		T6	2
all_levels[11]	186186	1			T4	82		T7	26		T32	2
all_levels[12]	180793	1			T2	1		T4	81		T7	48
all_levels[13]	306093	1			T2	1		T3	1		T4	126
all_levels[14]	189897	1			T2	64		T4	163		T7	27
all_levels[15]	202360	1			T4	163		T7	24		T14	1894
all_levels[16]	289956	1			T2	1		T3	1		T4	153
all_levels[17]	279485	1			T2	3		T4	163		T7	29
all_levels[18]	196743	1			T4	163		T7	20		T32	1
all_levels[19]	163676	1			T4	91		T7	15		T33	1
all_levels[20]	364202	1			T4	87		T7	23		T33	3
all_levels[21]	153131	1			T2	3		T4	81		T7	21
all_levels[22]	152504	1			T2	3		T4	125		T6	2
all_levels[23]	149812	1			T2	1		T4	311		T6	2
all_levels[24]	163293	1			T2	3		T4	312		T6	5
all_levels[25]	240595	1			T2	2		T4	319		T7	19
all_levels[26]	277039	1			T2	1		T4	305		T7	24
all_levels[27]	514988	1			T2	3		T4	309		T7	28
all_levels[28]	192987	1			T2	2		T3	3		T4	310
all_levels[29]	345006	1			T2	3		T4	307		T7	17
all_levels[30]	215182	1			T2	2		T3	6		T4	310
all_levels[31]	497737	1			T2	3		T4	36748		T7	405
all_levels[32]	12380953	1			T2	10		T3	7		T4	104323

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29927577

1

T2

116

T3

131

T4

146512

auto[1]

4494

1

T2

6

T3

9

T4

3

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8261484	1			T2	2		T3	99		T4	85
all_levels[0]	auto[1]	2472	1			T3	5		T7	13		T8	4
all_levels[1]	auto[0]	1608127	1			T2	9		T3	5		T4	140
all_levels[1]	auto[1]	354	1			T2	2		T92	1		T106	2
all_levels[2]	auto[0]	245990	1			T4	167		T6	5		T7	21
all_levels[2]	auto[1]	49	1			T118	1		T117	1		T268	2
all_levels[3]	auto[0]	303069	1			T3	3		T4	163		T6	1
all_levels[3]	auto[1]	125	1			T277	4		T308	4		T331	2
all_levels[4]	auto[0]	549482	1			T4	163		T6	2		T7	13
all_levels[4]	auto[1]	31	1			T6	1		T278	3		T150	1
all_levels[5]	auto[0]	191432	1			T3	3		T4	163		T6	1
all_levels[5]	auto[1]	27	1			T133	1		T260	1		T195	1
all_levels[6]	auto[0]	209399	1			T3	3		T4	165		T6	1
all_levels[6]	auto[1]	39	1			T4	2		T118	2		T135	3
all_levels[7]	auto[0]	214472	1			T3	3		T4	159		T7	26
all_levels[7]	auto[1]	74	1			T7	1		T32	1		T184	1
all_levels[8]	auto[0]	307039	1			T4	111		T6	1		T7	27
all_levels[8]	auto[1]	33	1			T12	1		T123	4		T332	1
all_levels[9]	auto[0]	203200	1			T2	3		T4	84		T7	28
all_levels[9]	auto[1]	45	1			T118	2		T28	1		T333	1
all_levels[10]	auto[0]	192487	1			T3	1		T4	81		T6	2
all_levels[10]	auto[1]	23	1			T64	1		T223	2		T334	1
all_levels[11]	auto[0]	186163	1			T4	82		T7	26		T32	2
all_levels[11]	auto[1]	23	1			T152	2		T120	1		T187	1
all_levels[12]	auto[0]	180762	1			T2	1		T4	81		T7	48
all_levels[12]	auto[1]	31	1			T33	1		T295	1		T118	1
all_levels[13]	auto[0]	306073	1			T2	1		T3	1		T4	126
all_levels[13]	auto[1]	20	1			T117	1		T65	1		T162	1
all_levels[14]	auto[0]	189842	1			T2	63		T4	163		T7	27
all_levels[14]	auto[1]	55	1			T2	1		T15	1		T31	1
all_levels[15]	auto[0]	202152	1			T4	163		T7	24		T14	1894
all_levels[15]	auto[1]	208	1			T18	2		T129	1		T291	6
all_levels[16]	auto[0]	289932	1			T2	1		T3	1		T4	153
all_levels[16]	auto[1]	24	1			T20	1		T120	2		T141	1
all_levels[17]	auto[0]	279470	1			T2	3		T4	163		T7	29
all_levels[17]	auto[1]	15	1			T273	2		T167	1		T189	3
all_levels[18]	auto[0]	196722	1			T4	163		T7	20		T32	1
all_levels[18]	auto[1]	21	1			T12	1		T335	2		T336	1
all_levels[19]	auto[0]	163641	1			T4	91		T7	15		T33	1
all_levels[19]	auto[1]	35	1			T337	1		T195	1		T163	1
all_levels[20]	auto[0]	364159	1			T4	86		T7	23		T33	1
all_levels[20]	auto[1]	43	1			T4	1		T33	2		T92	2
all_levels[21]	auto[0]	153108	1			T2	3		T4	81		T7	21
all_levels[21]	auto[1]	23	1			T271	1		T120	1		T109	1
all_levels[22]	auto[0]	152486	1			T2	2		T4	125		T6	2
all_levels[22]	auto[1]	18	1			T2	1		T141	1		T332	1
all_levels[23]	auto[0]	149800	1			T2	1		T4	311		T6	2
all_levels[23]	auto[1]	12	1			T184	2		T167	1		T338	1
all_levels[24]	auto[0]	163277	1			T2	3		T4	312		T6	5
all_levels[24]	auto[1]	16	1			T7	4		T118	1		T339	3
all_levels[25]	auto[0]	240578	1			T2	2		T4	319		T7	19
all_levels[25]	auto[1]	17	1			T143	1		T340	1		T252	1
all_levels[26]	auto[0]	277024	1			T2	1		T4	305		T7	24
all_levels[26]	auto[1]	15	1			T128	2		T133	1		T136	2
all_levels[27]	auto[0]	514969	1			T2	3		T4	309		T7	28
all_levels[27]	auto[1]	19	1			T28	2		T141	1		T197	1
all_levels[28]	auto[0]	192971	1			T2	2		T3	2		T4	310
all_levels[28]	auto[1]	16	1			T3	1		T8	1		T341	1
all_levels[29]	auto[0]	344995	1			T2	3		T4	307		T7	17
all_levels[29]	auto[1]	11	1			T227	1		T342	1		T332	3
all_levels[30]	auto[0]	215168	1			T2	2		T3	4		T4	310
all_levels[30]	auto[1]	14	1			T3	2		T163	1		T209	2
all_levels[31]	auto[0]	497704	1			T2	3		T4	36748		T7	405
all_levels[31]	auto[1]	33	1			T133	1		T272	1		T143	1
all_levels[32]	auto[0]	12380400	1			T2	8		T3	6		T4	104323
all_levels[32]	auto[1]	553	1			T2	2		T3	1		T5	1