Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	867	1			T7	15		T10	7		T13	7
all_values[1]	867	1			T7	15		T10	7		T13	7
all_values[2]	867	1			T7	15		T10	7		T13	7
all_values[3]	867	1			T7	15		T10	7		T13	7
all_values[4]	867	1			T7	15		T10	7		T13	7
all_values[5]	867	1			T7	15		T10	7		T13	7
all_values[6]	867	1			T7	15		T10	7		T13	7
all_values[7]	867	1			T7	15		T10	7		T13	7
all_values[8]	867	1			T7	15		T10	7		T13	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4237

1

T7

72

T10

35

T13

34

auto[1]

3566

1

T7

63

T10

28

T13

29

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2588

1

T7

48

T10

15

T13

20

auto[1]

5215

1

T7

87

T10

48

T13

43

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4635

1

T7

85

T10

34

T13

37

auto[1]

3168

1

T7

50

T10

29

T13

26

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	254	1			T7	2		T10	1		T13	2
all_values[0]	auto[0]	auto[1]	auto[1]	253	1			T7	7		T10	5		T13	1
all_values[0]	auto[1]	auto[0]	auto[1]	201	1			T7	5		T10	1		T13	3
all_values[0]	auto[1]	auto[1]	auto[1]	159	1			T7	1		T13	1		T20	3
all_values[1]	auto[0]	auto[0]	auto[0]	278	1			T7	5		T13	1		T15	2
all_values[1]	auto[0]	auto[1]	auto[0]	240	1			T7	3		T10	4		T13	5
all_values[1]	auto[1]	auto[0]	auto[1]	199	1			T7	2		T15	4		T20	2
all_values[1]	auto[1]	auto[1]	auto[1]	150	1			T7	5		T10	3		T13	1
all_values[2]	auto[0]	auto[0]	auto[0]	190	1			T7	8		T10	2		T13	1
all_values[2]	auto[0]	auto[0]	auto[1]	111	1			T7	2		T10	1		T13	1
all_values[2]	auto[0]	auto[1]	auto[0]	120	1			T7	2		T20	3		T125	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T7	1		T13	1		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	182	1			T7	2		T10	2		T13	2
all_values[2]	auto[1]	auto[1]	auto[1]	174	1			T10	2		T13	2		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	187	1			T7	2		T10	1		T13	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T7	2		T10	1		T13	1
all_values[3]	auto[0]	auto[1]	auto[0]	159	1			T7	5		T10	1		T13	1
all_values[3]	auto[0]	auto[1]	auto[1]	81	1			T7	1		T10	1		T13	1
all_values[3]	auto[1]	auto[0]	auto[1]	181	1			T7	4		T10	2		T13	2
all_values[3]	auto[1]	auto[1]	auto[1]	171	1			T7	1		T10	1		T13	1
all_values[4]	auto[0]	auto[0]	auto[0]	150	1			T7	3		T10	1		T13	1
all_values[4]	auto[0]	auto[0]	auto[1]	85	1			T7	2		T10	2		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	197	1			T7	5		T10	1		T13	4
all_values[4]	auto[0]	auto[1]	auto[1]	82	1			T7	1		T20	3		T125	2
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T7	3		T10	3		T13	2
all_values[4]	auto[1]	auto[1]	auto[1]	153	1			T7	1		T15	2		T20	5
all_values[5]	auto[0]	auto[0]	auto[0]	207	1			T7	3		T10	1		T20	4
all_values[5]	auto[0]	auto[0]	auto[1]	76	1			T10	1		T20	2		T30	1
all_values[5]	auto[0]	auto[1]	auto[0]	161	1			T7	1		T13	1		T20	3
all_values[5]	auto[0]	auto[1]	auto[1]	94	1			T7	4		T10	1		T13	2
all_values[5]	auto[1]	auto[0]	auto[1]	202	1			T7	3		T10	3		T13	2
all_values[5]	auto[1]	auto[1]	auto[1]	127	1			T7	4		T10	1		T13	2
all_values[6]	auto[0]	auto[0]	auto[0]	178	1			T7	4		T10	2		T13	1
all_values[6]	auto[0]	auto[0]	auto[1]	95	1			T7	1		T13	2		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	145	1			T7	2		T13	1		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	90	1			T7	2		T10	1		T13	1
all_values[6]	auto[1]	auto[0]	auto[1]	205	1			T7	2		T10	2		T13	2
all_values[6]	auto[1]	auto[1]	auto[1]	154	1			T7	4		T10	2		T15	2
all_values[7]	auto[0]	auto[0]	auto[0]	206	1			T7	3		T10	2		T13	1
all_values[7]	auto[0]	auto[0]	auto[1]	73	1			T7	1		T13	1		T28	2
all_values[7]	auto[0]	auto[1]	auto[0]	170	1			T7	2		T13	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	73	1			T7	2		T10	1		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T7	4		T10	3		T13	2
all_values[7]	auto[1]	auto[1]	auto[1]	151	1			T7	3		T10	1		T13	1
all_values[8]	auto[0]	auto[0]	auto[1]	282	1			T7	6		T10	3		T13	3
all_values[8]	auto[0]	auto[1]	auto[1]	220	1			T7	3		T10	1		T13	1
all_values[8]	auto[1]	auto[0]	auto[1]	213	1			T7	3		T10	1		T13	3
all_values[8]	auto[1]	auto[1]	auto[1]	152	1			T7	3		T10	2		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal