Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.59


Total test records in report: 1315
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T1255 /workspace/coverage/cover_reg_top/3.uart_intr_test.2112035023 Jul 29 06:44:33 PM PDT 24 Jul 29 06:44:34 PM PDT 24 74515358 ps
T1256 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1576083738 Jul 29 06:44:46 PM PDT 24 Jul 29 06:44:47 PM PDT 24 53171898 ps
T1257 /workspace/coverage/cover_reg_top/36.uart_intr_test.3537744527 Jul 29 06:45:13 PM PDT 24 Jul 29 06:45:14 PM PDT 24 19026644 ps
T1258 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.370924382 Jul 29 06:44:46 PM PDT 24 Jul 29 06:44:48 PM PDT 24 169719162 ps
T1259 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1373657492 Jul 29 06:44:48 PM PDT 24 Jul 29 06:44:49 PM PDT 24 102432412 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_intr_test.3141410268 Jul 29 06:44:22 PM PDT 24 Jul 29 06:44:23 PM PDT 24 51779068 ps
T1261 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4286815145 Jul 29 06:44:58 PM PDT 24 Jul 29 06:44:58 PM PDT 24 114514332 ps
T1262 /workspace/coverage/cover_reg_top/41.uart_intr_test.65423342 Jul 29 06:45:14 PM PDT 24 Jul 29 06:45:14 PM PDT 24 22056996 ps
T1263 /workspace/coverage/cover_reg_top/16.uart_tl_errors.1554634147 Jul 29 06:45:02 PM PDT 24 Jul 29 06:45:04 PM PDT 24 55872177 ps
T1264 /workspace/coverage/cover_reg_top/14.uart_csr_rw.449833832 Jul 29 06:45:03 PM PDT 24 Jul 29 06:45:04 PM PDT 24 25231267 ps
T1265 /workspace/coverage/cover_reg_top/15.uart_intr_test.1517502192 Jul 29 06:45:03 PM PDT 24 Jul 29 06:45:04 PM PDT 24 15341775 ps
T1266 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.191591571 Jul 29 06:44:57 PM PDT 24 Jul 29 06:44:58 PM PDT 24 85726493 ps
T1267 /workspace/coverage/cover_reg_top/5.uart_intr_test.3705500527 Jul 29 06:44:45 PM PDT 24 Jul 29 06:44:46 PM PDT 24 17928753 ps
T1268 /workspace/coverage/cover_reg_top/21.uart_intr_test.2858786347 Jul 29 06:45:11 PM PDT 24 Jul 29 06:45:12 PM PDT 24 45396100 ps
T1269 /workspace/coverage/cover_reg_top/8.uart_csr_rw.438640827 Jul 29 06:44:50 PM PDT 24 Jul 29 06:44:51 PM PDT 24 13046924 ps
T76 /workspace/coverage/cover_reg_top/3.uart_csr_rw.2453507165 Jul 29 06:44:34 PM PDT 24 Jul 29 06:44:34 PM PDT 24 41060785 ps
T1270 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2007305269 Jul 29 06:44:34 PM PDT 24 Jul 29 06:44:36 PM PDT 24 178096464 ps
T1271 /workspace/coverage/cover_reg_top/11.uart_intr_test.3043631639 Jul 29 06:44:58 PM PDT 24 Jul 29 06:44:59 PM PDT 24 36849061 ps
T1272 /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.967939195 Jul 29 06:44:22 PM PDT 24 Jul 29 06:44:23 PM PDT 24 71549658 ps
T1273 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1769669202 Jul 29 06:45:05 PM PDT 24 Jul 29 06:45:06 PM PDT 24 15494524 ps
T1274 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3174586636 Jul 29 06:44:27 PM PDT 24 Jul 29 06:44:27 PM PDT 24 32580572 ps
T1275 /workspace/coverage/cover_reg_top/29.uart_intr_test.3160945449 Jul 29 06:45:14 PM PDT 24 Jul 29 06:45:15 PM PDT 24 13191605 ps
T1276 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1399706281 Jul 29 06:44:34 PM PDT 24 Jul 29 06:44:34 PM PDT 24 41849604 ps
T1277 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3993306715 Jul 29 06:44:51 PM PDT 24 Jul 29 06:44:52 PM PDT 24 54593500 ps
T1278 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1153400553 Jul 29 06:44:40 PM PDT 24 Jul 29 06:44:42 PM PDT 24 32002080 ps
T1279 /workspace/coverage/cover_reg_top/6.uart_intr_test.1267664667 Jul 29 06:44:48 PM PDT 24 Jul 29 06:44:49 PM PDT 24 14656199 ps
T1280 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.504430605 Jul 29 06:44:51 PM PDT 24 Jul 29 06:44:52 PM PDT 24 184285078 ps
T1281 /workspace/coverage/cover_reg_top/44.uart_intr_test.2294291653 Jul 29 06:45:12 PM PDT 24 Jul 29 06:45:13 PM PDT 24 50510648 ps
T1282 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3018558752 Jul 29 06:44:39 PM PDT 24 Jul 29 06:44:40 PM PDT 24 21327989 ps
T1283 /workspace/coverage/cover_reg_top/22.uart_intr_test.2746848903 Jul 29 06:45:08 PM PDT 24 Jul 29 06:45:08 PM PDT 24 19254031 ps
T1284 /workspace/coverage/cover_reg_top/15.uart_csr_rw.612590579 Jul 29 06:45:01 PM PDT 24 Jul 29 06:45:02 PM PDT 24 41757897 ps
T1285 /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2228881853 Jul 29 06:44:27 PM PDT 24 Jul 29 06:44:28 PM PDT 24 33193842 ps
T1286 /workspace/coverage/cover_reg_top/7.uart_intr_test.953205954 Jul 29 06:44:48 PM PDT 24 Jul 29 06:44:49 PM PDT 24 16878330 ps
T1287 /workspace/coverage/cover_reg_top/2.uart_tl_errors.1781943536 Jul 29 06:44:29 PM PDT 24 Jul 29 06:44:30 PM PDT 24 23132364 ps
T1288 /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3080108462 Jul 29 06:44:47 PM PDT 24 Jul 29 06:44:48 PM PDT 24 16012258 ps
T1289 /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3025742378 Jul 29 06:44:46 PM PDT 24 Jul 29 06:44:47 PM PDT 24 16885954 ps
T1290 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4100381965 Jul 29 06:44:52 PM PDT 24 Jul 29 06:44:53 PM PDT 24 37165061 ps
T1291 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3948913163 Jul 29 06:44:39 PM PDT 24 Jul 29 06:44:41 PM PDT 24 101069760 ps
T1292 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3897600011 Jul 29 06:45:02 PM PDT 24 Jul 29 06:45:04 PM PDT 24 16392280 ps
T1293 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1010310659 Jul 29 06:44:27 PM PDT 24 Jul 29 06:44:28 PM PDT 24 99150630 ps
T1294 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2672876839 Jul 29 06:44:21 PM PDT 24 Jul 29 06:44:22 PM PDT 24 76481784 ps
T1295 /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1956073780 Jul 29 06:44:59 PM PDT 24 Jul 29 06:45:00 PM PDT 24 95925698 ps
T1296 /workspace/coverage/cover_reg_top/24.uart_intr_test.2995297430 Jul 29 06:45:10 PM PDT 24 Jul 29 06:45:10 PM PDT 24 48400741 ps
T1297 /workspace/coverage/cover_reg_top/17.uart_csr_rw.3894694467 Jul 29 06:45:01 PM PDT 24 Jul 29 06:45:02 PM PDT 24 18509805 ps
T1298 /workspace/coverage/cover_reg_top/8.uart_intr_test.311617144 Jul 29 06:44:52 PM PDT 24 Jul 29 06:44:53 PM PDT 24 14954948 ps
T1299 /workspace/coverage/cover_reg_top/25.uart_intr_test.2422896359 Jul 29 06:45:08 PM PDT 24 Jul 29 06:45:09 PM PDT 24 15251227 ps
T1300 /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1625643005 Jul 29 06:44:34 PM PDT 24 Jul 29 06:44:35 PM PDT 24 42357873 ps
T1301 /workspace/coverage/cover_reg_top/47.uart_intr_test.2346346805 Jul 29 06:45:12 PM PDT 24 Jul 29 06:45:12 PM PDT 24 56519126 ps
T1302 /workspace/coverage/cover_reg_top/10.uart_intr_test.4205337239 Jul 29 06:45:05 PM PDT 24 Jul 29 06:45:06 PM PDT 24 12326017 ps
T102 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.571781459 Jul 29 06:44:57 PM PDT 24 Jul 29 06:44:59 PM PDT 24 89777975 ps
T1303 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3501511612 Jul 29 06:44:32 PM PDT 24 Jul 29 06:44:34 PM PDT 24 68319499 ps
T1304 /workspace/coverage/cover_reg_top/49.uart_intr_test.3670196544 Jul 29 06:45:15 PM PDT 24 Jul 29 06:45:16 PM PDT 24 20185778 ps
T1305 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2792935206 Jul 29 06:44:29 PM PDT 24 Jul 29 06:44:30 PM PDT 24 156693887 ps
T1306 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3681364316 Jul 29 06:45:02 PM PDT 24 Jul 29 06:45:04 PM PDT 24 53350084 ps
T77 /workspace/coverage/cover_reg_top/9.uart_csr_rw.2674538068 Jul 29 06:44:58 PM PDT 24 Jul 29 06:44:59 PM PDT 24 19709213 ps
T1307 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1491029210 Jul 29 06:45:04 PM PDT 24 Jul 29 06:45:05 PM PDT 24 30270117 ps
T1308 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.145326806 Jul 29 06:44:57 PM PDT 24 Jul 29 06:44:58 PM PDT 24 41019186 ps
T1309 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2256075445 Jul 29 06:45:01 PM PDT 24 Jul 29 06:45:02 PM PDT 24 23070916 ps
T1310 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3691281216 Jul 29 06:45:03 PM PDT 24 Jul 29 06:45:03 PM PDT 24 44798917 ps
T126 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.870181001 Jul 29 06:45:04 PM PDT 24 Jul 29 06:45:05 PM PDT 24 255155799 ps
T1311 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2776352302 Jul 29 06:44:44 PM PDT 24 Jul 29 06:44:45 PM PDT 24 48535596 ps
T1312 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3986954921 Jul 29 06:44:47 PM PDT 24 Jul 29 06:44:48 PM PDT 24 26521799 ps
T1313 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2351603950 Jul 29 06:45:09 PM PDT 24 Jul 29 06:45:10 PM PDT 24 16784149 ps
T1314 /workspace/coverage/cover_reg_top/13.uart_intr_test.4125522447 Jul 29 06:44:58 PM PDT 24 Jul 29 06:44:59 PM PDT 24 51219453 ps
T1315 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.711363579 Jul 29 06:45:09 PM PDT 24 Jul 29 06:45:11 PM PDT 24 72582374 ps

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1837694957
Short name T7
Test name
Test status
Simulation time 301462200084 ps
CPU time 721.38 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:29:34 PM PDT 24
Peak memory 224808 kb
Host smart-c3749ac2-00cb-4ac1-b951-18bb8d4b3ea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837694957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1837694957
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2147854067
Short name T29
Test name
Test status
Simulation time 219149176330 ps
CPU time 1123.38 seconds
Started Jul 29 07:16:49 PM PDT 24
Finished Jul 29 07:35:33 PM PDT 24
Peak memory 224824 kb
Host smart-6c55cc9d-d36a-48d5-bff3-07c425858135
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147854067 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2147854067
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3726909346
Short name T116
Test name
Test status
Simulation time 140335251000 ps
CPU time 481.57 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:20:25 PM PDT 24
Peak memory 199996 kb
Host smart-5bab5dde-a024-4d9e-9b26-66357d2bce65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726909346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3726909346
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4129339139
Short name T31
Test name
Test status
Simulation time 242803966815 ps
CPU time 939.35 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:28:04 PM PDT 24
Peak memory 224784 kb
Host smart-ea33a359-c075-40a8-828f-c23742f03df5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129339139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4129339139
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.574081006
Short name T67
Test name
Test status
Simulation time 122633642071 ps
CPU time 963.82 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 228528 kb
Host smart-76529e12-31e5-4ad9-87fa-75f9f55cd626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574081006 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.574081006
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.1762014382
Short name T143
Test name
Test status
Simulation time 209726747303 ps
CPU time 723.78 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:29:35 PM PDT 24
Peak memory 216468 kb
Host smart-227c5134-8729-41a0-a0f5-a77790e2cfe3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762014382 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.1762014382
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2580426957
Short name T50
Test name
Test status
Simulation time 113665563124 ps
CPU time 1023.05 seconds
Started Jul 29 07:12:30 PM PDT 24
Finished Jul 29 07:29:34 PM PDT 24
Peak memory 227552 kb
Host smart-c17dff47-b6da-4017-a736-526305e539da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580426957 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2580426957
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.910422096
Short name T2
Test name
Test status
Simulation time 228992299092 ps
CPU time 192.45 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:32:45 PM PDT 24
Peak memory 200092 kb
Host smart-f0e6948e-49ad-4e3e-9b41-ae17b252714c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910422096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.910422096
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3761581021
Short name T25
Test name
Test status
Simulation time 66210319 ps
CPU time 0.85 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 218348 kb
Host smart-5eb39aca-48e6-4ab6-803c-df9344ac8899
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761581021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3761581021
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/49.uart_stress_all.1064492343
Short name T121
Test name
Test status
Simulation time 466021646307 ps
CPU time 419.01 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:24:10 PM PDT 24
Peak memory 199980 kb
Host smart-f480d64c-602d-4389-97f5-ddd751761e7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064492343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1064492343
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2526890105
Short name T20
Test name
Test status
Simulation time 64916689964 ps
CPU time 641.87 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:28:09 PM PDT 24
Peak memory 216632 kb
Host smart-a136e474-159a-469b-b3c9-61d4d990aa07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526890105 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2526890105
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2499307685
Short name T108
Test name
Test status
Simulation time 724834268690 ps
CPU time 834.3 seconds
Started Jul 29 07:17:34 PM PDT 24
Finished Jul 29 07:31:28 PM PDT 24
Peak memory 216640 kb
Host smart-da596aeb-206a-435a-a5b7-a0dd75b89486
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499307685 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2499307685
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2457884840
Short name T41
Test name
Test status
Simulation time 142803128751 ps
CPU time 505.35 seconds
Started Jul 29 07:12:39 PM PDT 24
Finished Jul 29 07:21:05 PM PDT 24
Peak memory 200000 kb
Host smart-6567c6ec-fbae-4f1b-8508-026f3b761788
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457884840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2457884840
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1822822262
Short name T328
Test name
Test status
Simulation time 167277446998 ps
CPU time 2282.03 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:55:29 PM PDT 24
Peak memory 233036 kb
Host smart-302bf209-0484-4359-91b1-b2e16d6d21cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822822262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1822822262
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_stress_all.845514314
Short name T156
Test name
Test status
Simulation time 378962047951 ps
CPU time 93.09 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:14:35 PM PDT 24
Peak memory 199940 kb
Host smart-ba2d8dc0-9a41-49eb-8de3-5b1c4b6b9ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845514314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.845514314
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2644534409
Short name T97
Test name
Test status
Simulation time 82865916 ps
CPU time 1.29 seconds
Started Jul 29 06:44:22 PM PDT 24
Finished Jul 29 06:44:24 PM PDT 24
Peak memory 199620 kb
Host smart-2ab8c9f2-6a42-4141-8098-e28f09d8d9be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644534409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2644534409
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/12.uart_stress_all.4081024160
Short name T132
Test name
Test status
Simulation time 168095736436 ps
CPU time 260.53 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:17:09 PM PDT 24
Peak memory 199980 kb
Host smart-f5a3d262-8bef-4a48-94b7-69974137478b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081024160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.4081024160
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3566374760
Short name T127
Test name
Test status
Simulation time 94589146162 ps
CPU time 74.75 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:14:27 PM PDT 24
Peak memory 199860 kb
Host smart-b93d71e4-c63b-4d3a-bbc3-2fa2d69a2e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566374760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3566374760
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_alert_test.2386773791
Short name T400
Test name
Test status
Simulation time 41210865 ps
CPU time 0.55 seconds
Started Jul 29 07:13:04 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 194776 kb
Host smart-5ca69c91-7a7e-4061-9cf8-966c476e985e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386773791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2386773791
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.394880579
Short name T117
Test name
Test status
Simulation time 83506019089 ps
CPU time 127.56 seconds
Started Jul 29 07:29:32 PM PDT 24
Finished Jul 29 07:31:40 PM PDT 24
Peak memory 200032 kb
Host smart-9e49170a-3c04-4f28-8969-b32a3fbd073d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394880579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.394880579
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1909935767
Short name T28
Test name
Test status
Simulation time 77322324853 ps
CPU time 903.99 seconds
Started Jul 29 07:17:08 PM PDT 24
Finished Jul 29 07:32:12 PM PDT 24
Peak memory 216512 kb
Host smart-7c367a8f-08c2-40a2-81f2-269eb2fa6f8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909935767 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1909935767
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_stress_all.421778260
Short name T272
Test name
Test status
Simulation time 169222762408 ps
CPU time 285.6 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:17:11 PM PDT 24
Peak memory 199972 kb
Host smart-612cf199-6714-4c21-a1b7-923b7b01cb0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421778260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.421778260
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1642994450
Short name T12
Test name
Test status
Simulation time 241275571711 ps
CPU time 161.31 seconds
Started Jul 29 07:29:37 PM PDT 24
Finished Jul 29 07:32:18 PM PDT 24
Peak memory 199980 kb
Host smart-514b22a4-d76e-47ce-a8fc-71fe48908272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642994450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1642994450
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1126679466
Short name T72
Test name
Test status
Simulation time 321196262 ps
CPU time 1.47 seconds
Started Jul 29 06:44:24 PM PDT 24
Finished Jul 29 06:44:26 PM PDT 24
Peak memory 198108 kb
Host smart-e0a8136c-512b-47d2-b13d-b00006f0d42e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126679466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1126679466
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.157159903
Short name T91
Test name
Test status
Simulation time 111923923 ps
CPU time 0.74 seconds
Started Jul 29 06:44:26 PM PDT 24
Finished Jul 29 06:44:27 PM PDT 24
Peak memory 197244 kb
Host smart-079ced76-d9e5-415b-be33-32de3f5138fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157159903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.157159903
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1757003483
Short name T215
Test name
Test status
Simulation time 99693925373 ps
CPU time 46.56 seconds
Started Jul 29 07:17:25 PM PDT 24
Finished Jul 29 07:18:11 PM PDT 24
Peak memory 200016 kb
Host smart-e4c0efbe-bb71-4415-9554-866bff25ec7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757003483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1757003483
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.870181001
Short name T126
Test name
Test status
Simulation time 255155799 ps
CPU time 0.96 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:05 PM PDT 24
Peak memory 199196 kb
Host smart-e77744f8-5713-4495-94f8-d00ef69ef154
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870181001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.870181001
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.3954719372
Short name T159
Test name
Test status
Simulation time 58986646766 ps
CPU time 59.54 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:57 PM PDT 24
Peak memory 199912 kb
Host smart-edd5ba03-45fb-4830-8194-4fe2771dd817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954719372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.3954719372
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.3972089630
Short name T183
Test name
Test status
Simulation time 110251298173 ps
CPU time 176.98 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:15:22 PM PDT 24
Peak memory 199956 kb
Host smart-6ad89e4e-b64b-4a9e-aeb2-21ae27b78633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972089630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.3972089630
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.511666709
Short name T118
Test name
Test status
Simulation time 87286543661 ps
CPU time 105.18 seconds
Started Jul 29 07:12:54 PM PDT 24
Finished Jul 29 07:14:39 PM PDT 24
Peak memory 199948 kb
Host smart-9fb5b351-eea7-4b66-bd7f-07eedfca6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511666709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.511666709
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all.2465580666
Short name T181
Test name
Test status
Simulation time 277998337357 ps
CPU time 109.29 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:16:04 PM PDT 24
Peak memory 199892 kb
Host smart-baecf5c5-67d5-4509-a8db-e7d30c6a46ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465580666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.2465580666
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.1053043459
Short name T209
Test name
Test status
Simulation time 212702129443 ps
CPU time 110.79 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:19:37 PM PDT 24
Peak memory 199844 kb
Host smart-c575c028-7c6a-4f61-abe4-3fc961d4f2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053043459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.1053043459
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.4054844544
Short name T223
Test name
Test status
Simulation time 157965453101 ps
CPU time 132.01 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:31:34 PM PDT 24
Peak memory 199980 kb
Host smart-b2c13d1e-106d-4b0f-9711-dbbceb14c32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054844544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.4054844544
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.1571715992
Short name T145
Test name
Test status
Simulation time 237659335377 ps
CPU time 771.05 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:26:56 PM PDT 24
Peak memory 224708 kb
Host smart-e057e009-616f-494e-9100-ec4ba0087fde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571715992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.1571715992
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.749343276
Short name T153
Test name
Test status
Simulation time 150759952256 ps
CPU time 71.64 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:19:07 PM PDT 24
Peak memory 199972 kb
Host smart-29c4b67a-002e-41ce-b893-803b8e8e0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749343276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.749343276
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_stress_all.1089629715
Short name T130
Test name
Test status
Simulation time 123330223430 ps
CPU time 222.23 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:17:06 PM PDT 24
Peak memory 199912 kb
Host smart-b237af43-1a33-4d48-bdd0-382455f61892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089629715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1089629715
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3466331011
Short name T32
Test name
Test status
Simulation time 145348235358 ps
CPU time 51.56 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:30:14 PM PDT 24
Peak memory 200104 kb
Host smart-0a111386-fdbd-4f5a-b1b8-4ce495260e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466331011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3466331011
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.271426104
Short name T152
Test name
Test status
Simulation time 41356239407 ps
CPU time 18.08 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:17:31 PM PDT 24
Peak memory 200036 kb
Host smart-fbc27cd8-5fa0-4f92-91a0-b6d924717e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271426104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.271426104
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1603467954
Short name T253
Test name
Test status
Simulation time 21213455974 ps
CPU time 35 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:23 PM PDT 24
Peak memory 199976 kb
Host smart-ad470641-5fc8-4a92-aa63-38ad76aeb322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603467954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1603467954
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.3717591943
Short name T249
Test name
Test status
Simulation time 49118097717 ps
CPU time 69.05 seconds
Started Jul 29 07:29:38 PM PDT 24
Finished Jul 29 07:30:48 PM PDT 24
Peak memory 199876 kb
Host smart-976ada3b-be56-4d25-b516-8342fc09af7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717591943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.3717591943
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.213669223
Short name T169
Test name
Test status
Simulation time 18639711583 ps
CPU time 32.9 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 199988 kb
Host smart-364246f4-0289-4b6f-83fb-2864a1598ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213669223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.213669223
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1605490211
Short name T1010
Test name
Test status
Simulation time 272669753124 ps
CPU time 169.59 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:20:02 PM PDT 24
Peak memory 199924 kb
Host smart-35b01b06-f9a6-4403-8911-e04200100159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605490211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1605490211
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3928881794
Short name T170
Test name
Test status
Simulation time 23284899400 ps
CPU time 4.65 seconds
Started Jul 29 07:17:50 PM PDT 24
Finished Jul 29 07:17:54 PM PDT 24
Peak memory 199972 kb
Host smart-907ee83b-0cba-4e1a-a581-04d76a24d6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928881794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3928881794
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1444127782
Short name T322
Test name
Test status
Simulation time 51558467859 ps
CPU time 166.4 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:20:32 PM PDT 24
Peak memory 200008 kb
Host smart-6f053c9e-ce73-4b71-b127-1919a8b03287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444127782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1444127782
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.453450629
Short name T211
Test name
Test status
Simulation time 162983039002 ps
CPU time 88.12 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:13:52 PM PDT 24
Peak memory 199956 kb
Host smart-5e8b326a-8ae4-4d28-aad6-d2e69d862418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453450629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.453450629
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.677457574
Short name T254
Test name
Test status
Simulation time 416098036164 ps
CPU time 850.62 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:27:45 PM PDT 24
Peak memory 231408 kb
Host smart-9d472f49-17d0-48c7-b6db-30d7992febaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677457574 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.677457574
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.2998380669
Short name T225
Test name
Test status
Simulation time 22811584736 ps
CPU time 44.51 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:30:07 PM PDT 24
Peak memory 200040 kb
Host smart-43c0754f-ee66-4601-aff2-a553fde86233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998380669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.2998380669
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.3416152202
Short name T151
Test name
Test status
Simulation time 130928775513 ps
CPU time 194.55 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:18:15 PM PDT 24
Peak memory 199984 kb
Host smart-4d859b3b-8805-46f4-b9ab-b7fbbc225ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416152202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.3416152202
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.2162409777
Short name T128
Test name
Test status
Simulation time 9733938549 ps
CPU time 17.35 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:17:48 PM PDT 24
Peak memory 199896 kb
Host smart-d93ffb5e-ebfe-4bac-b4df-c1b9e3416b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162409777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2162409777
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.719668856
Short name T208
Test name
Test status
Simulation time 70624444472 ps
CPU time 261.81 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:21:52 PM PDT 24
Peak memory 199956 kb
Host smart-15fa6b32-c2a0-4e00-9395-b5b26e673d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719668856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.719668856
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.3448919251
Short name T167
Test name
Test status
Simulation time 134356409465 ps
CPU time 107.74 seconds
Started Jul 29 07:17:48 PM PDT 24
Finished Jul 29 07:19:36 PM PDT 24
Peak memory 199904 kb
Host smart-4f8b8f46-6f0a-4b9a-94a6-04ee4e0299b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448919251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.3448919251
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.3258694835
Short name T241
Test name
Test status
Simulation time 169542806960 ps
CPU time 108.68 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:19:34 PM PDT 24
Peak memory 200100 kb
Host smart-77714d3c-2bbe-4a6c-8147-f272d259f7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258694835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.3258694835
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.2892832835
Short name T195
Test name
Test status
Simulation time 18508486134 ps
CPU time 25.2 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:13:52 PM PDT 24
Peak memory 199704 kb
Host smart-c6af4ef0-8879-4b2f-a9c8-38277b86de7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892832835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.2892832835
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3039848709
Short name T453
Test name
Test status
Simulation time 129214564954 ps
CPU time 562.51 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:23:18 PM PDT 24
Peak memory 223936 kb
Host smart-ce5a71c4-4460-4241-8f9e-3eeba637956d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039848709 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3039848709
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.525308671
Short name T142
Test name
Test status
Simulation time 34904272936 ps
CPU time 42.52 seconds
Started Jul 29 07:29:51 PM PDT 24
Finished Jul 29 07:30:33 PM PDT 24
Peak memory 199920 kb
Host smart-e6282e44-315f-46b1-b725-15265b1026e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525308671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.525308671
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.195645022
Short name T218
Test name
Test status
Simulation time 59636533373 ps
CPU time 17.34 seconds
Started Jul 29 07:17:29 PM PDT 24
Finished Jul 29 07:17:47 PM PDT 24
Peak memory 200056 kb
Host smart-7a8bda75-9880-4b4b-80c5-6d709c849053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195645022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.195645022
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2772033865
Short name T135
Test name
Test status
Simulation time 23625040848 ps
CPU time 33.35 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:20 PM PDT 24
Peak memory 199968 kb
Host smart-61543f96-7d76-4a8e-8433-b0c35a4efc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772033865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2772033865
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.343747997
Short name T182
Test name
Test status
Simulation time 6678513935 ps
CPU time 3.01 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:13:03 PM PDT 24
Peak memory 198384 kb
Host smart-0428fdda-4b21-4de9-9749-b037f067af26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343747997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.343747997
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2161315197
Short name T234
Test name
Test status
Simulation time 19942537685 ps
CPU time 36.06 seconds
Started Jul 29 07:17:50 PM PDT 24
Finished Jul 29 07:18:26 PM PDT 24
Peak memory 199972 kb
Host smart-2bbbc2f9-87b8-44ec-9ebe-5fd2f6c0fb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161315197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2161315197
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3157019130
Short name T906
Test name
Test status
Simulation time 34660580416 ps
CPU time 62.3 seconds
Started Jul 29 07:17:48 PM PDT 24
Finished Jul 29 07:18:51 PM PDT 24
Peak memory 199920 kb
Host smart-2df36a83-08e4-4807-b8e0-a319bf909649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157019130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3157019130
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3206826480
Short name T230
Test name
Test status
Simulation time 10194690679 ps
CPU time 20.42 seconds
Started Jul 29 07:17:49 PM PDT 24
Finished Jul 29 07:18:09 PM PDT 24
Peak memory 199924 kb
Host smart-dd362bd1-d811-47d9-9460-ad6d0a68d2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206826480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3206826480
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.2827482364
Short name T1079
Test name
Test status
Simulation time 158147533199 ps
CPU time 54.84 seconds
Started Jul 29 07:17:55 PM PDT 24
Finished Jul 29 07:18:50 PM PDT 24
Peak memory 199932 kb
Host smart-d4316088-9be5-4219-b1fa-b0cd612444eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827482364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2827482364
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1713873318
Short name T847
Test name
Test status
Simulation time 63215872203 ps
CPU time 23.87 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:21 PM PDT 24
Peak memory 199896 kb
Host smart-70c2d589-fc5e-4f26-93b9-9708fd00d763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713873318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1713873318
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.169231552
Short name T994
Test name
Test status
Simulation time 88449609379 ps
CPU time 42.79 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:41 PM PDT 24
Peak memory 200032 kb
Host smart-8a560bdd-d20e-42bf-b847-2a1a50d29f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169231552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.169231552
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1058488914
Short name T179
Test name
Test status
Simulation time 75135118595 ps
CPU time 33.6 seconds
Started Jul 29 07:18:10 PM PDT 24
Finished Jul 29 07:18:43 PM PDT 24
Peak memory 199924 kb
Host smart-6a985698-e8bf-44c9-bafa-8329cc95af85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058488914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1058488914
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.269941197
Short name T248
Test name
Test status
Simulation time 32795366372 ps
CPU time 23.92 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 199968 kb
Host smart-b5798b2e-6ad7-40de-b2b1-7fa5cb52bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269941197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.269941197
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3858932073
Short name T251
Test name
Test status
Simulation time 52755357603 ps
CPU time 74.89 seconds
Started Jul 29 07:29:29 PM PDT 24
Finished Jul 29 07:30:44 PM PDT 24
Peak memory 199932 kb
Host smart-b2f623a7-92f4-4743-9708-f480195b13bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858932073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3858932073
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.189838513
Short name T235
Test name
Test status
Simulation time 39579436306 ps
CPU time 7.08 seconds
Started Jul 29 07:29:38 PM PDT 24
Finished Jul 29 07:29:45 PM PDT 24
Peak memory 199856 kb
Host smart-86639893-6229-4ac9-8911-b378bc2b52fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189838513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.189838513
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all.286717440
Short name T221
Test name
Test status
Simulation time 253192817968 ps
CPU time 331.23 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:17:59 PM PDT 24
Peak memory 199964 kb
Host smart-b08be2d3-891c-480f-9195-2dd3593f9b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286717440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.286717440
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3538523900
Short name T51
Test name
Test status
Simulation time 724327996140 ps
CPU time 914.62 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 224704 kb
Host smart-2a9f93a9-2d8e-4b24-b7c2-df63ae037d66
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538523900 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3538523900
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.2781414785
Short name T238
Test name
Test status
Simulation time 26210077680 ps
CPU time 55.16 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:18:29 PM PDT 24
Peak memory 199988 kb
Host smart-c9df4021-917b-4b11-ada6-d03f5ed82be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781414785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.2781414785
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3635699453
Short name T80
Test name
Test status
Simulation time 64595362 ps
CPU time 0.72 seconds
Started Jul 29 06:44:23 PM PDT 24
Finished Jul 29 06:44:24 PM PDT 24
Peak memory 195256 kb
Host smart-a2be1f12-4920-4bc6-8d57-c117e8da0b9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635699453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3635699453
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.606715096
Short name T1204
Test name
Test status
Simulation time 24070745 ps
CPU time 0.58 seconds
Started Jul 29 06:44:23 PM PDT 24
Finished Jul 29 06:44:23 PM PDT 24
Peak memory 195816 kb
Host smart-35cb87e6-8dd6-4baa-8b0d-37b9f48bec38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606715096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.606715096
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.967939195
Short name T1272
Test name
Test status
Simulation time 71549658 ps
CPU time 1.39 seconds
Started Jul 29 06:44:22 PM PDT 24
Finished Jul 29 06:44:23 PM PDT 24
Peak memory 200504 kb
Host smart-3d8a2801-8cf4-4e58-8ed1-56bad2e03999
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967939195 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.967939195
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1814522019
Short name T1254
Test name
Test status
Simulation time 14408153 ps
CPU time 0.63 seconds
Started Jul 29 06:44:21 PM PDT 24
Finished Jul 29 06:44:22 PM PDT 24
Peak memory 195904 kb
Host smart-a99a18fe-3f08-4845-aeb1-e90a98c01421
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814522019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1814522019
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3141410268
Short name T1260
Test name
Test status
Simulation time 51779068 ps
CPU time 0.57 seconds
Started Jul 29 06:44:22 PM PDT 24
Finished Jul 29 06:44:23 PM PDT 24
Peak memory 194672 kb
Host smart-24832e61-6b8b-43a1-beaf-48c31de0e0fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141410268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3141410268
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.2672876839
Short name T1294
Test name
Test status
Simulation time 76481784 ps
CPU time 0.6 seconds
Started Jul 29 06:44:21 PM PDT 24
Finished Jul 29 06:44:22 PM PDT 24
Peak memory 195812 kb
Host smart-b5f316a1-77bf-46b0-88b5-908f3e4b4cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672876839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.2672876839
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.1678790482
Short name T1202
Test name
Test status
Simulation time 99696832 ps
CPU time 1.83 seconds
Started Jul 29 06:44:18 PM PDT 24
Finished Jul 29 06:44:20 PM PDT 24
Peak memory 200488 kb
Host smart-7bb0571f-22e3-4bb5-977e-4bc8177cab82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678790482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.1678790482
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.2013110873
Short name T1188
Test name
Test status
Simulation time 69695552 ps
CPU time 0.67 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:30 PM PDT 24
Peak memory 195812 kb
Host smart-1d2dcf05-b84e-40df-923a-f11570547a63
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013110873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.2013110873
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1441331921
Short name T73
Test name
Test status
Simulation time 271821492 ps
CPU time 1.46 seconds
Started Jul 29 06:44:26 PM PDT 24
Finished Jul 29 06:44:28 PM PDT 24
Peak memory 197984 kb
Host smart-467f21e4-1721-4ab2-a3e8-0bc2c2c9929b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441331921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1441331921
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.4041289065
Short name T1223
Test name
Test status
Simulation time 17555754 ps
CPU time 0.55 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:29 PM PDT 24
Peak memory 195804 kb
Host smart-1d1c7701-a385-4e00-b344-8b287ec2cc97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041289065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4041289065
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1010310659
Short name T1293
Test name
Test status
Simulation time 99150630 ps
CPU time 0.76 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:28 PM PDT 24
Peak memory 199816 kb
Host smart-68650c8c-f3a7-42c1-aeca-e9d7511756f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010310659 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1010310659
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3174586636
Short name T1274
Test name
Test status
Simulation time 32580572 ps
CPU time 0.58 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:27 PM PDT 24
Peak memory 195864 kb
Host smart-14cfcd4d-8686-40fb-8fde-c773d895a14c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174586636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3174586636
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3670345129
Short name T1225
Test name
Test status
Simulation time 13732525 ps
CPU time 0.58 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:30 PM PDT 24
Peak memory 194800 kb
Host smart-a07c2d89-7afb-4c74-a1ae-ce90d2e4c089
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670345129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3670345129
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.1690925111
Short name T1205
Test name
Test status
Simulation time 46419450 ps
CPU time 2.28 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:29 PM PDT 24
Peak memory 200388 kb
Host smart-3b490964-daf1-4fff-a584-2b546b327888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690925111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.1690925111
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2792935206
Short name T1305
Test name
Test status
Simulation time 156693887 ps
CPU time 1.01 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:30 PM PDT 24
Peak memory 199576 kb
Host smart-44cfdff8-403c-40e5-bb22-5ade67dfb654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792935206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2792935206
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.438132393
Short name T1193
Test name
Test status
Simulation time 58636127 ps
CPU time 0.96 seconds
Started Jul 29 06:45:05 PM PDT 24
Finished Jul 29 06:45:07 PM PDT 24
Peak memory 200160 kb
Host smart-f386d0cb-2a65-4bdb-a392-23b325bcabcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438132393 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.438132393
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2506604815
Short name T74
Test name
Test status
Simulation time 13051054 ps
CPU time 0.63 seconds
Started Jul 29 06:44:56 PM PDT 24
Finished Jul 29 06:44:57 PM PDT 24
Peak memory 195896 kb
Host smart-f00ec1ea-c7e8-4a1b-b985-594d823baf02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506604815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2506604815
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.4205337239
Short name T1302
Test name
Test status
Simulation time 12326017 ps
CPU time 0.57 seconds
Started Jul 29 06:45:05 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 194656 kb
Host smart-2fe020f3-7b3e-4b5a-adf3-1161c3df681e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205337239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4205337239
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.191591571
Short name T1266
Test name
Test status
Simulation time 85726493 ps
CPU time 0.76 seconds
Started Jul 29 06:44:57 PM PDT 24
Finished Jul 29 06:44:58 PM PDT 24
Peak memory 196364 kb
Host smart-cb4ff04c-5274-4689-965e-5d59e7cd8d76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191591571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_csr
_outstanding.191591571
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.50506279
Short name T1221
Test name
Test status
Simulation time 88112849 ps
CPU time 1.37 seconds
Started Jul 29 06:44:59 PM PDT 24
Finished Jul 29 06:45:00 PM PDT 24
Peak memory 200472 kb
Host smart-1763f405-49e5-49dd-9c60-bf5d08b547ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50506279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.50506279
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1498045399
Short name T96
Test name
Test status
Simulation time 83473248 ps
CPU time 0.96 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:05 PM PDT 24
Peak memory 199516 kb
Host smart-7725b732-a1e6-4742-aa74-26fddb33ed9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498045399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1498045399
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1621938500
Short name T1212
Test name
Test status
Simulation time 99219491 ps
CPU time 0.62 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 198140 kb
Host smart-aee710b6-3581-4e6c-9894-5ab85328fa63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621938500 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1621938500
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1533062618
Short name T83
Test name
Test status
Simulation time 20900137 ps
CPU time 0.64 seconds
Started Jul 29 06:45:00 PM PDT 24
Finished Jul 29 06:45:01 PM PDT 24
Peak memory 195912 kb
Host smart-602da80c-9d28-416a-a94d-83523a9a270d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533062618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1533062618
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.3043631639
Short name T1271
Test name
Test status
Simulation time 36849061 ps
CPU time 0.56 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 194792 kb
Host smart-30e00490-25ce-416b-b499-a4be81b8641f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043631639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3043631639
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1411113649
Short name T1219
Test name
Test status
Simulation time 17809686 ps
CPU time 0.73 seconds
Started Jul 29 06:45:05 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 196176 kb
Host smart-95289830-6365-40da-8983-ec49e8e9e625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411113649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1411113649
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.672047070
Short name T1234
Test name
Test status
Simulation time 116926351 ps
CPU time 1.67 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:45:00 PM PDT 24
Peak memory 200420 kb
Host smart-d5399111-9f73-4100-9612-1cd02bc59817
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672047070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.672047070
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.571781459
Short name T102
Test name
Test status
Simulation time 89777975 ps
CPU time 1.28 seconds
Started Jul 29 06:44:57 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 199824 kb
Host smart-bb53c6d4-25d4-48c7-9d10-df7592f44f56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571781459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.571781459
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2590211471
Short name T1227
Test name
Test status
Simulation time 64782379 ps
CPU time 0.65 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 198252 kb
Host smart-45e1ed2b-bb18-4718-a691-ac1f4dba1c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590211471 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2590211471
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1914153506
Short name T1230
Test name
Test status
Simulation time 54116371 ps
CPU time 0.57 seconds
Started Jul 29 06:44:59 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 195828 kb
Host smart-74f79704-eb3f-444c-b01b-7f7f55734919
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914153506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1914153506
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.640567334
Short name T1195
Test name
Test status
Simulation time 36292181 ps
CPU time 0.56 seconds
Started Jul 29 06:45:05 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 194720 kb
Host smart-cfd80789-1783-497a-bfb2-8679789e00f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640567334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.640567334
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.145326806
Short name T1308
Test name
Test status
Simulation time 41019186 ps
CPU time 0.73 seconds
Started Jul 29 06:44:57 PM PDT 24
Finished Jul 29 06:44:58 PM PDT 24
Peak memory 196188 kb
Host smart-c7258e9a-3831-4d9d-82d3-facb7eb37f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145326806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_csr
_outstanding.145326806
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1067361812
Short name T1245
Test name
Test status
Simulation time 223961413 ps
CPU time 1.24 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 200488 kb
Host smart-41ddb969-c5e7-427d-9f6e-2b0c81368df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067361812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1067361812
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1379385791
Short name T100
Test name
Test status
Simulation time 132754304 ps
CPU time 0.98 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 199508 kb
Host smart-b21042e7-d2b6-47a0-a9cd-2e2ef6dc6cf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379385791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1379385791
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2314690046
Short name T1192
Test name
Test status
Simulation time 68555788 ps
CPU time 0.74 seconds
Started Jul 29 06:44:57 PM PDT 24
Finished Jul 29 06:44:58 PM PDT 24
Peak memory 199416 kb
Host smart-659fdead-8f8e-42cf-87b9-0b2684a1757e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314690046 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2314690046
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1769669202
Short name T1273
Test name
Test status
Simulation time 15494524 ps
CPU time 0.58 seconds
Started Jul 29 06:45:05 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 195752 kb
Host smart-b928ddaa-dd64-4401-bef4-500c32cbf06f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769669202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1769669202
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4125522447
Short name T1314
Test name
Test status
Simulation time 51219453 ps
CPU time 0.57 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 194852 kb
Host smart-7ed0a73d-af38-4cf7-af46-b5ca244b1e7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125522447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4125522447
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.4286815145
Short name T1261
Test name
Test status
Simulation time 114514332 ps
CPU time 0.64 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:58 PM PDT 24
Peak memory 196888 kb
Host smart-aebaf588-5799-41d1-92e1-f42203d34be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286815145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.4286815145
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1517245963
Short name T1239
Test name
Test status
Simulation time 81501461 ps
CPU time 1.06 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 200236 kb
Host smart-ac28bfe4-5e9a-4cc6-9629-1c1920234a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517245963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1517245963
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2256075445
Short name T1309
Test name
Test status
Simulation time 23070916 ps
CPU time 0.74 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 198944 kb
Host smart-240a9660-236b-44d4-9a59-2cdc6d84e18d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256075445 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2256075445
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.449833832
Short name T1264
Test name
Test status
Simulation time 25231267 ps
CPU time 0.62 seconds
Started Jul 29 06:45:03 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 195980 kb
Host smart-7780db19-b1e1-446d-9e65-735fce0784e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449833832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.449833832
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.3873184025
Short name T1226
Test name
Test status
Simulation time 33764338 ps
CPU time 0.56 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 194780 kb
Host smart-f3ce96ff-9870-493b-8a7e-3dbfd8f24263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873184025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.3873184025
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.3897600011
Short name T1292
Test name
Test status
Simulation time 16392280 ps
CPU time 0.77 seconds
Started Jul 29 06:45:02 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 197468 kb
Host smart-1f14c9a7-da9f-488d-83b6-c137cd20ef4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897600011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.3897600011
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2081953202
Short name T1220
Test name
Test status
Simulation time 64545608 ps
CPU time 0.94 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 200124 kb
Host smart-5e4ad0ef-5506-4ea4-91ab-964250c05467
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081953202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2081953202
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.2840263438
Short name T94
Test name
Test status
Simulation time 75658454 ps
CPU time 1.36 seconds
Started Jul 29 06:45:03 PM PDT 24
Finished Jul 29 06:45:05 PM PDT 24
Peak memory 199756 kb
Host smart-d4c2790a-a0de-4ac1-9c26-f5cada4b9044
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840263438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.2840263438
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2822805305
Short name T1196
Test name
Test status
Simulation time 14445157 ps
CPU time 0.81 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 198472 kb
Host smart-08c3a0d0-11ed-4ef6-90ed-3c6e9bed21e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822805305 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2822805305
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.612590579
Short name T1284
Test name
Test status
Simulation time 41757897 ps
CPU time 0.63 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 195916 kb
Host smart-8aaa3f54-38db-4126-ab71-5d3c8fc779c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612590579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.612590579
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.1517502192
Short name T1265
Test name
Test status
Simulation time 15341775 ps
CPU time 0.58 seconds
Started Jul 29 06:45:03 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 194748 kb
Host smart-f2c2b725-8137-4bb4-8bc3-e4e4a4af0aaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517502192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.1517502192
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.3708088536
Short name T1247
Test name
Test status
Simulation time 49169119 ps
CPU time 0.76 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:05 PM PDT 24
Peak memory 196936 kb
Host smart-f0330598-2efd-40f0-ae69-01f6ab24946d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708088536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.3708088536
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1246701308
Short name T1237
Test name
Test status
Simulation time 309256540 ps
CPU time 1.21 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 200436 kb
Host smart-9f4d7d2c-033c-48fc-bb99-6ad9f76e3d25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246701308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1246701308
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3153183308
Short name T101
Test name
Test status
Simulation time 52836998 ps
CPU time 0.97 seconds
Started Jul 29 06:45:00 PM PDT 24
Finished Jul 29 06:45:01 PM PDT 24
Peak memory 199544 kb
Host smart-2d71de88-d61e-47d0-852b-97d8f6a06cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153183308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3153183308
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.5785165
Short name T1187
Test name
Test status
Simulation time 287350529 ps
CPU time 0.9 seconds
Started Jul 29 06:45:00 PM PDT 24
Finished Jul 29 06:45:01 PM PDT 24
Peak memory 200136 kb
Host smart-61bc30f0-cdd7-4ebe-aee2-7b8b09e09f1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5785165 -assert nopostproc +UVM_TESTNAME=ua
rt_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.5785165
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.1786951151
Short name T89
Test name
Test status
Simulation time 32603754 ps
CPU time 0.6 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 196000 kb
Host smart-12a9f719-f99e-4553-a3a8-c81cf3db89ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786951151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.1786951151
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.3840315735
Short name T1231
Test name
Test status
Simulation time 20853398 ps
CPU time 0.58 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 194816 kb
Host smart-9299999e-1c21-4313-a1ac-a2d2cf9835af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840315735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.3840315735
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3691281216
Short name T1310
Test name
Test status
Simulation time 44798917 ps
CPU time 0.72 seconds
Started Jul 29 06:45:03 PM PDT 24
Finished Jul 29 06:45:03 PM PDT 24
Peak memory 197232 kb
Host smart-999d3573-f7b8-42be-b90a-fa3fb609cdb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691281216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3691281216
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1554634147
Short name T1263
Test name
Test status
Simulation time 55872177 ps
CPU time 1.3 seconds
Started Jul 29 06:45:02 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 200432 kb
Host smart-f77ce019-83b5-41f4-8063-ad444b9653c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554634147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1554634147
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3044991531
Short name T1251
Test name
Test status
Simulation time 73851801 ps
CPU time 1.32 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 199576 kb
Host smart-84591a34-c188-4abb-b3a2-0962ed01d3ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044991531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3044991531
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2351603950
Short name T1313
Test name
Test status
Simulation time 16784149 ps
CPU time 0.73 seconds
Started Jul 29 06:45:09 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 199056 kb
Host smart-0d94be1d-4824-4ddf-a181-533af780e4d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351603950 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2351603950
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3894694467
Short name T1297
Test name
Test status
Simulation time 18509805 ps
CPU time 0.68 seconds
Started Jul 29 06:45:01 PM PDT 24
Finished Jul 29 06:45:02 PM PDT 24
Peak memory 195940 kb
Host smart-892b6180-dea4-4fe4-ba95-9b0a00643529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894694467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3894694467
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2869232476
Short name T1241
Test name
Test status
Simulation time 46003919 ps
CPU time 0.61 seconds
Started Jul 29 06:45:02 PM PDT 24
Finished Jul 29 06:45:03 PM PDT 24
Peak memory 194780 kb
Host smart-91820c8b-d2ea-4d74-a7f2-6764c8d3636a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869232476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2869232476
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2024059407
Short name T1235
Test name
Test status
Simulation time 164093350 ps
CPU time 0.65 seconds
Started Jul 29 06:45:09 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 196116 kb
Host smart-13e9b895-c788-47eb-94a6-f8309787480e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024059407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2024059407
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3006516610
Short name T1253
Test name
Test status
Simulation time 118012491 ps
CPU time 1.41 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:06 PM PDT 24
Peak memory 200468 kb
Host smart-61909297-9e15-441f-87ef-766e0c143c0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006516610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3006516610
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3681364316
Short name T1306
Test name
Test status
Simulation time 53350084 ps
CPU time 1.03 seconds
Started Jul 29 06:45:02 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 199372 kb
Host smart-2d8de8b6-cb30-4a69-8dc0-9fb733a4cf20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681364316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3681364316
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1862023528
Short name T1222
Test name
Test status
Simulation time 81641614 ps
CPU time 0.8 seconds
Started Jul 29 06:45:09 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 199524 kb
Host smart-c74694bc-7b30-4fd1-be70-a331d0f8c115
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862023528 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1862023528
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3750376522
Short name T1248
Test name
Test status
Simulation time 171818152 ps
CPU time 0.66 seconds
Started Jul 29 06:45:11 PM PDT 24
Finished Jul 29 06:45:12 PM PDT 24
Peak memory 196036 kb
Host smart-d5b159cb-bda1-45f8-be8a-4d010f18a942
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750376522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3750376522
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.2238835388
Short name T1199
Test name
Test status
Simulation time 11594310 ps
CPU time 0.56 seconds
Started Jul 29 06:45:10 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 194812 kb
Host smart-a061629b-59fd-4076-9436-e987c1c4344b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238835388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2238835388
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.2189223224
Short name T1240
Test name
Test status
Simulation time 34924869 ps
CPU time 0.65 seconds
Started Jul 29 06:45:11 PM PDT 24
Finished Jul 29 06:45:11 PM PDT 24
Peak memory 196192 kb
Host smart-52abbd25-2ffa-46c7-aa88-b808a42baeca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189223224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.2189223224
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.3426478747
Short name T1236
Test name
Test status
Simulation time 225685198 ps
CPU time 1.2 seconds
Started Jul 29 06:45:07 PM PDT 24
Finished Jul 29 06:45:09 PM PDT 24
Peak memory 200476 kb
Host smart-ac896503-7cbc-46a2-9d7e-f4b16a2faf14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426478747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.3426478747
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.343066472
Short name T98
Test name
Test status
Simulation time 75764653 ps
CPU time 0.93 seconds
Started Jul 29 06:45:07 PM PDT 24
Finished Jul 29 06:45:08 PM PDT 24
Peak memory 199384 kb
Host smart-845e7cb9-4841-45d7-a4ce-d4e1f1f66417
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343066472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.343066472
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.711363579
Short name T1315
Test name
Test status
Simulation time 72582374 ps
CPU time 1.16 seconds
Started Jul 29 06:45:09 PM PDT 24
Finished Jul 29 06:45:11 PM PDT 24
Peak memory 200512 kb
Host smart-81d3b535-2695-4090-b107-f760171f9fd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711363579 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.711363579
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.2216160614
Short name T90
Test name
Test status
Simulation time 26888995 ps
CPU time 0.61 seconds
Started Jul 29 06:45:08 PM PDT 24
Finished Jul 29 06:45:09 PM PDT 24
Peak memory 195996 kb
Host smart-60a8ae67-a445-478b-8f27-bf369e25e1b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216160614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.2216160614
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3036248085
Short name T1203
Test name
Test status
Simulation time 37730335 ps
CPU time 0.6 seconds
Started Jul 29 06:45:11 PM PDT 24
Finished Jul 29 06:45:11 PM PDT 24
Peak memory 194844 kb
Host smart-6e8433e4-47e0-4036-b38b-e238e7e80e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036248085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3036248085
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.3959218205
Short name T1249
Test name
Test status
Simulation time 13940322 ps
CPU time 0.62 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 196060 kb
Host smart-4fffd15a-d6c9-427c-b6f8-bad934db3bc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959218205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.3959218205
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2111569631
Short name T1238
Test name
Test status
Simulation time 67045505 ps
CPU time 2.12 seconds
Started Jul 29 06:45:09 PM PDT 24
Finished Jul 29 06:45:11 PM PDT 24
Peak memory 200356 kb
Host smart-880d639f-a3ac-49f5-9e73-202df9cb98ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111569631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2111569631
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.75690501
Short name T1198
Test name
Test status
Simulation time 104810566 ps
CPU time 1.39 seconds
Started Jul 29 06:45:08 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 199952 kb
Host smart-852121db-d944-4f62-8e99-d8145e003a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75690501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.75690501
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3004059677
Short name T1190
Test name
Test status
Simulation time 57471431 ps
CPU time 0.82 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:35 PM PDT 24
Peak memory 196676 kb
Host smart-6b45fff6-515b-4850-bcdb-55ba736eee91
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004059677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3004059677
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.2228881853
Short name T1285
Test name
Test status
Simulation time 33193842 ps
CPU time 1.39 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:28 PM PDT 24
Peak memory 198148 kb
Host smart-83124563-bf2c-46e7-ac1e-d71cc4ec6e65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228881853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.2228881853
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1694277900
Short name T71
Test name
Test status
Simulation time 14831716 ps
CPU time 0.61 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:28 PM PDT 24
Peak memory 195844 kb
Host smart-63f872a0-26bf-4193-9274-063a913665c1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694277900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1694277900
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2101784052
Short name T1201
Test name
Test status
Simulation time 77924172 ps
CPU time 0.83 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:35 PM PDT 24
Peak memory 199144 kb
Host smart-a6804c41-555e-459e-8db5-b6cc67667ea3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101784052 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2101784052
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.1789846033
Short name T1211
Test name
Test status
Simulation time 135610324 ps
CPU time 0.59 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:30 PM PDT 24
Peak memory 195760 kb
Host smart-2bddf306-7c08-4274-9e03-11339569abb1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789846033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.1789846033
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.4160837130
Short name T1244
Test name
Test status
Simulation time 121471771 ps
CPU time 0.56 seconds
Started Jul 29 06:44:28 PM PDT 24
Finished Jul 29 06:44:29 PM PDT 24
Peak memory 194800 kb
Host smart-911f5cd2-3934-49d3-90f1-c6de09d5bfb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160837130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.4160837130
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.1399706281
Short name T1276
Test name
Test status
Simulation time 41849604 ps
CPU time 0.7 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:34 PM PDT 24
Peak memory 195980 kb
Host smart-f374af2b-f0aa-4879-9a07-7f5aa7c02209
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399706281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.1399706281
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1781943536
Short name T1287
Test name
Test status
Simulation time 23132364 ps
CPU time 1.13 seconds
Started Jul 29 06:44:29 PM PDT 24
Finished Jul 29 06:44:30 PM PDT 24
Peak memory 200440 kb
Host smart-5e616a29-17ee-482a-9a6c-374e252be8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781943536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1781943536
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2775120062
Short name T99
Test name
Test status
Simulation time 293017178 ps
CPU time 1.31 seconds
Started Jul 29 06:44:27 PM PDT 24
Finished Jul 29 06:44:28 PM PDT 24
Peak memory 200348 kb
Host smart-b89aaf5e-5a75-4c51-9849-0cb5e6f1bb41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775120062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2775120062
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.482327276
Short name T1185
Test name
Test status
Simulation time 41857818 ps
CPU time 0.57 seconds
Started Jul 29 06:45:07 PM PDT 24
Finished Jul 29 06:45:08 PM PDT 24
Peak memory 194800 kb
Host smart-ba3ea8d6-8b74-452c-9edc-39814f1ceb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482327276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.482327276
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.2858786347
Short name T1268
Test name
Test status
Simulation time 45396100 ps
CPU time 0.58 seconds
Started Jul 29 06:45:11 PM PDT 24
Finished Jul 29 06:45:12 PM PDT 24
Peak memory 194728 kb
Host smart-79c84ce8-3e62-4a02-b2ee-bdf9000888ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858786347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2858786347
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2746848903
Short name T1283
Test name
Test status
Simulation time 19254031 ps
CPU time 0.56 seconds
Started Jul 29 06:45:08 PM PDT 24
Finished Jul 29 06:45:08 PM PDT 24
Peak memory 194736 kb
Host smart-bccd0e99-0cf8-4a7d-b691-e57bb6e54605
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746848903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2746848903
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2501557585
Short name T1182
Test name
Test status
Simulation time 15360037 ps
CPU time 0.55 seconds
Started Jul 29 06:45:07 PM PDT 24
Finished Jul 29 06:45:08 PM PDT 24
Peak memory 194744 kb
Host smart-654ad5c6-acdf-48b6-8b65-fcbaefae46d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501557585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2501557585
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2995297430
Short name T1296
Test name
Test status
Simulation time 48400741 ps
CPU time 0.57 seconds
Started Jul 29 06:45:10 PM PDT 24
Finished Jul 29 06:45:10 PM PDT 24
Peak memory 194800 kb
Host smart-bdb46d7d-4018-4d33-aef9-ab92e4c4dc6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995297430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2995297430
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2422896359
Short name T1299
Test name
Test status
Simulation time 15251227 ps
CPU time 0.59 seconds
Started Jul 29 06:45:08 PM PDT 24
Finished Jul 29 06:45:09 PM PDT 24
Peak memory 194708 kb
Host smart-3d62f559-eccf-4b1d-b059-f460c7eca405
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422896359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2422896359
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3382852602
Short name T1217
Test name
Test status
Simulation time 12546911 ps
CPU time 0.55 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194764 kb
Host smart-8ba6d50c-74bd-466b-ad45-d87bf3aabc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382852602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3382852602
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3728914564
Short name T1208
Test name
Test status
Simulation time 184831475 ps
CPU time 0.63 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194808 kb
Host smart-616a7757-5082-4367-b0d5-3c6ff063905b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728914564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3728914564
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.235317398
Short name T1229
Test name
Test status
Simulation time 49869499 ps
CPU time 0.58 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194732 kb
Host smart-aa61bd39-8663-4d07-822d-a5ac8f9deec7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235317398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.235317398
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.3160945449
Short name T1275
Test name
Test status
Simulation time 13191605 ps
CPU time 0.58 seconds
Started Jul 29 06:45:14 PM PDT 24
Finished Jul 29 06:45:15 PM PDT 24
Peak memory 194776 kb
Host smart-eb0cad16-ba15-4944-afe7-02b082b667f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160945449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.3160945449
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1854672133
Short name T1243
Test name
Test status
Simulation time 34926804 ps
CPU time 0.66 seconds
Started Jul 29 06:44:33 PM PDT 24
Finished Jul 29 06:44:34 PM PDT 24
Peak memory 195796 kb
Host smart-b5684c5c-0ef0-415e-a080-7d13111c00f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854672133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1854672133
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.345299741
Short name T1246
Test name
Test status
Simulation time 661581347 ps
CPU time 2.32 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:37 PM PDT 24
Peak memory 198204 kb
Host smart-813a0c2d-6775-4853-98b4-751ab3c8fa9d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345299741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.345299741
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.1625643005
Short name T1300
Test name
Test status
Simulation time 42357873 ps
CPU time 0.63 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:35 PM PDT 24
Peak memory 195748 kb
Host smart-7a069ee6-a0da-47cc-86d1-1a1d30bdff06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625643005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.1625643005
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.1153400553
Short name T1278
Test name
Test status
Simulation time 32002080 ps
CPU time 1.37 seconds
Started Jul 29 06:44:40 PM PDT 24
Finished Jul 29 06:44:42 PM PDT 24
Peak memory 200496 kb
Host smart-46e44c62-c0da-45c0-8580-4a879a0a3ead
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153400553 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.1153400553
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.2453507165
Short name T76
Test name
Test status
Simulation time 41060785 ps
CPU time 0.58 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:34 PM PDT 24
Peak memory 195816 kb
Host smart-4369f022-239f-482c-a4eb-b421b141392b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453507165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.2453507165
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.2112035023
Short name T1255
Test name
Test status
Simulation time 74515358 ps
CPU time 0.57 seconds
Started Jul 29 06:44:33 PM PDT 24
Finished Jul 29 06:44:34 PM PDT 24
Peak memory 194776 kb
Host smart-b8c4dbd5-7fa7-4030-be95-9f1a476ae7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112035023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.2112035023
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3244765209
Short name T82
Test name
Test status
Simulation time 22034257 ps
CPU time 0.65 seconds
Started Jul 29 06:44:40 PM PDT 24
Finished Jul 29 06:44:41 PM PDT 24
Peak memory 195036 kb
Host smart-456d7307-5758-47fe-b950-28396d2516b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244765209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.3244765209
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2007305269
Short name T1270
Test name
Test status
Simulation time 178096464 ps
CPU time 1.21 seconds
Started Jul 29 06:44:34 PM PDT 24
Finished Jul 29 06:44:36 PM PDT 24
Peak memory 200480 kb
Host smart-736fea3b-0f04-487d-8551-0345fea19609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007305269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2007305269
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3501511612
Short name T1303
Test name
Test status
Simulation time 68319499 ps
CPU time 1.25 seconds
Started Jul 29 06:44:32 PM PDT 24
Finished Jul 29 06:44:34 PM PDT 24
Peak memory 199664 kb
Host smart-17ae407c-8640-45a3-b4f7-6ab094bcb945
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501511612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3501511612
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.1151083444
Short name T1233
Test name
Test status
Simulation time 38762160 ps
CPU time 0.57 seconds
Started Jul 29 06:45:16 PM PDT 24
Finished Jul 29 06:45:16 PM PDT 24
Peak memory 194816 kb
Host smart-d000c3ba-5cbf-4276-85b4-d94f7379ab9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151083444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1151083444
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.1824171116
Short name T1184
Test name
Test status
Simulation time 24946235 ps
CPU time 0.57 seconds
Started Jul 29 06:45:19 PM PDT 24
Finished Jul 29 06:45:19 PM PDT 24
Peak memory 194720 kb
Host smart-3432eda0-28c0-47d9-9f4b-78001cf7b136
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824171116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.1824171116
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.531834572
Short name T1183
Test name
Test status
Simulation time 14383556 ps
CPU time 0.58 seconds
Started Jul 29 06:45:14 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194808 kb
Host smart-29a7b25d-4f07-40de-b251-07be35144990
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531834572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.531834572
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.916118074
Short name T1209
Test name
Test status
Simulation time 23950655 ps
CPU time 0.59 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194744 kb
Host smart-8388bd24-9e41-4304-b394-58231a409fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916118074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.916118074
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3702516386
Short name T1186
Test name
Test status
Simulation time 53509646 ps
CPU time 0.58 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194764 kb
Host smart-1dd5a2e5-e3dc-4c27-a0e2-6219db41b6d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702516386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3702516386
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.750358951
Short name T1194
Test name
Test status
Simulation time 14331545 ps
CPU time 0.59 seconds
Started Jul 29 06:45:16 PM PDT 24
Finished Jul 29 06:45:16 PM PDT 24
Peak memory 194796 kb
Host smart-bf6d6e4c-0d7a-4acc-ad9f-b943fef1cde2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750358951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.750358951
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3537744527
Short name T1257
Test name
Test status
Simulation time 19026644 ps
CPU time 0.59 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194812 kb
Host smart-24e7eb60-6b49-416f-8bc3-767dd7dd5757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537744527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3537744527
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.914946818
Short name T1200
Test name
Test status
Simulation time 36677506 ps
CPU time 0.58 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194820 kb
Host smart-b151d6fb-3601-45be-bc7d-3243660d756f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914946818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.914946818
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.431723457
Short name T1218
Test name
Test status
Simulation time 12788961 ps
CPU time 0.57 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194808 kb
Host smart-27cbbf3c-739b-4687-bea0-88778656382a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431723457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.431723457
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1908463453
Short name T1207
Test name
Test status
Simulation time 14820104 ps
CPU time 0.58 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194700 kb
Host smart-9b49f886-2362-40c1-9fc9-1ea703012d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908463453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1908463453
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3018558752
Short name T1282
Test name
Test status
Simulation time 21327989 ps
CPU time 0.66 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:40 PM PDT 24
Peak memory 195216 kb
Host smart-f2d64db1-4eba-4d1c-8c18-8c64471088ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018558752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3018558752
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3607732246
Short name T1181
Test name
Test status
Simulation time 260790520 ps
CPU time 1.58 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:40 PM PDT 24
Peak memory 198132 kb
Host smart-558cc2ee-56a9-4c3b-a469-8f9da1021329
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607732246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3607732246
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.224603324
Short name T81
Test name
Test status
Simulation time 49186912 ps
CPU time 0.56 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:40 PM PDT 24
Peak memory 195772 kb
Host smart-f3c99062-f1c9-4644-8674-c571188bb409
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224603324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.224603324
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2776352302
Short name T1311
Test name
Test status
Simulation time 48535596 ps
CPU time 0.89 seconds
Started Jul 29 06:44:44 PM PDT 24
Finished Jul 29 06:44:45 PM PDT 24
Peak memory 199960 kb
Host smart-cdb9df8d-63e0-4021-923f-937cd7ebbc81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776352302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2776352302
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1431059172
Short name T85
Test name
Test status
Simulation time 113839909 ps
CPU time 0.6 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:40 PM PDT 24
Peak memory 195784 kb
Host smart-91763d83-cb14-46fc-bd3c-b0e33c8d9e35
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431059172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1431059172
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.367808886
Short name T1191
Test name
Test status
Simulation time 95660240 ps
CPU time 0.55 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:39 PM PDT 24
Peak memory 194780 kb
Host smart-5afa1f30-e86d-438c-b8ff-a5cb60032ce8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367808886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.367808886
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4041955011
Short name T88
Test name
Test status
Simulation time 33877475 ps
CPU time 0.74 seconds
Started Jul 29 06:44:40 PM PDT 24
Finished Jul 29 06:44:41 PM PDT 24
Peak memory 198180 kb
Host smart-4ab3b8cb-ab45-4800-9960-64eb6db04290
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041955011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4041955011
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3948913163
Short name T1291
Test name
Test status
Simulation time 101069760 ps
CPU time 2.2 seconds
Started Jul 29 06:44:39 PM PDT 24
Finished Jul 29 06:44:41 PM PDT 24
Peak memory 200436 kb
Host smart-fa3c3bdf-dc38-46a4-a484-ccd45865c038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948913163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3948913163
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.2644555436
Short name T93
Test name
Test status
Simulation time 88654596 ps
CPU time 1.37 seconds
Started Jul 29 06:44:40 PM PDT 24
Finished Jul 29 06:44:42 PM PDT 24
Peak memory 199848 kb
Host smart-741e6731-5047-4f0a-95be-603ca66c42b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644555436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.2644555436
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2706488887
Short name T1215
Test name
Test status
Simulation time 17896531 ps
CPU time 0.57 seconds
Started Jul 29 06:45:16 PM PDT 24
Finished Jul 29 06:45:16 PM PDT 24
Peak memory 194816 kb
Host smart-c3517aac-7f14-4c51-9caa-8547ad6ff0d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706488887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2706488887
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.65423342
Short name T1262
Test name
Test status
Simulation time 22056996 ps
CPU time 0.56 seconds
Started Jul 29 06:45:14 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194676 kb
Host smart-07c367de-4275-4e87-afbf-acecaf5240d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65423342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.65423342
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.3232558399
Short name T1189
Test name
Test status
Simulation time 14252962 ps
CPU time 0.55 seconds
Started Jul 29 06:45:14 PM PDT 24
Finished Jul 29 06:45:14 PM PDT 24
Peak memory 194760 kb
Host smart-83db1889-fa8f-46fb-aa7a-4d33bfca470a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232558399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.3232558399
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.3009845411
Short name T1252
Test name
Test status
Simulation time 38383609 ps
CPU time 0.54 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:12 PM PDT 24
Peak memory 194712 kb
Host smart-a18bf117-ab7c-4ece-a9f5-ce94dbe75207
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009845411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3009845411
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.2294291653
Short name T1281
Test name
Test status
Simulation time 50510648 ps
CPU time 0.58 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194832 kb
Host smart-bc6292ea-f7db-4d98-a9b3-9c8ce0469161
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294291653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.2294291653
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2551480163
Short name T1242
Test name
Test status
Simulation time 31773919 ps
CPU time 0.56 seconds
Started Jul 29 06:45:14 PM PDT 24
Finished Jul 29 06:45:15 PM PDT 24
Peak memory 194800 kb
Host smart-f99bb591-8105-4429-84e5-0a9a4c09def5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551480163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2551480163
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2817661423
Short name T1250
Test name
Test status
Simulation time 14757460 ps
CPU time 0.57 seconds
Started Jul 29 06:45:19 PM PDT 24
Finished Jul 29 06:45:19 PM PDT 24
Peak memory 194728 kb
Host smart-cf7ab30c-ea2a-45a9-badb-35a8eb189fcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817661423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2817661423
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.2346346805
Short name T1301
Test name
Test status
Simulation time 56519126 ps
CPU time 0.56 seconds
Started Jul 29 06:45:12 PM PDT 24
Finished Jul 29 06:45:12 PM PDT 24
Peak memory 194780 kb
Host smart-76cce7ec-c9c9-4a39-8546-e6965763af2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346346805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.2346346805
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3284872691
Short name T1214
Test name
Test status
Simulation time 29919642 ps
CPU time 0.55 seconds
Started Jul 29 06:45:13 PM PDT 24
Finished Jul 29 06:45:13 PM PDT 24
Peak memory 194668 kb
Host smart-61024ecc-e2b9-4768-8290-e7d1283d84b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284872691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3284872691
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3670196544
Short name T1304
Test name
Test status
Simulation time 20185778 ps
CPU time 0.55 seconds
Started Jul 29 06:45:15 PM PDT 24
Finished Jul 29 06:45:16 PM PDT 24
Peak memory 194732 kb
Host smart-e30c28ad-7916-4cec-9654-f139437ca0a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670196544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3670196544
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.3986954921
Short name T1312
Test name
Test status
Simulation time 26521799 ps
CPU time 0.65 seconds
Started Jul 29 06:44:47 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 197668 kb
Host smart-d246a94b-6720-40f0-917c-7d1b4f295d3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986954921 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.3986954921
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.550531610
Short name T1206
Test name
Test status
Simulation time 55178168 ps
CPU time 0.62 seconds
Started Jul 29 06:44:47 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 196000 kb
Host smart-62e3c737-f426-4220-b694-3a69c03aa365
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550531610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.550531610
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3705500527
Short name T1267
Test name
Test status
Simulation time 17928753 ps
CPU time 0.57 seconds
Started Jul 29 06:44:45 PM PDT 24
Finished Jul 29 06:44:46 PM PDT 24
Peak memory 194796 kb
Host smart-e290d856-3b56-49fc-bec6-93366c28ef76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705500527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3705500527
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3080108462
Short name T1288
Test name
Test status
Simulation time 16012258 ps
CPU time 0.64 seconds
Started Jul 29 06:44:47 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 196176 kb
Host smart-6b23cf9a-b1f4-4f56-9c5c-103b343fa185
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080108462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3080108462
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2341664447
Short name T1210
Test name
Test status
Simulation time 295750497 ps
CPU time 1.88 seconds
Started Jul 29 06:44:49 PM PDT 24
Finished Jul 29 06:44:51 PM PDT 24
Peak memory 200472 kb
Host smart-533b6a7c-1730-4c37-b841-bf9f4d7d5dd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341664447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2341664447
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.370924382
Short name T1258
Test name
Test status
Simulation time 169719162 ps
CPU time 1.44 seconds
Started Jul 29 06:44:46 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 199976 kb
Host smart-f54c5f31-adea-453f-84b8-c2124ebf7904
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370924382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.370924382
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1373657492
Short name T1259
Test name
Test status
Simulation time 102432412 ps
CPU time 0.81 seconds
Started Jul 29 06:44:48 PM PDT 24
Finished Jul 29 06:44:49 PM PDT 24
Peak memory 200236 kb
Host smart-29ecbdf7-333d-4b4b-b9b0-72decd6984bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373657492 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1373657492
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1101129113
Short name T75
Test name
Test status
Simulation time 24767364 ps
CPU time 0.6 seconds
Started Jul 29 06:44:49 PM PDT 24
Finished Jul 29 06:44:50 PM PDT 24
Peak memory 195832 kb
Host smart-dbff32ba-fd67-4b28-9b64-16cfa843b295
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101129113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1101129113
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1267664667
Short name T1279
Test name
Test status
Simulation time 14656199 ps
CPU time 0.56 seconds
Started Jul 29 06:44:48 PM PDT 24
Finished Jul 29 06:44:49 PM PDT 24
Peak memory 194792 kb
Host smart-5c30616b-fac7-4bfc-aa60-318fce484db4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267664667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1267664667
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3025742378
Short name T1289
Test name
Test status
Simulation time 16885954 ps
CPU time 0.72 seconds
Started Jul 29 06:44:46 PM PDT 24
Finished Jul 29 06:44:47 PM PDT 24
Peak memory 196192 kb
Host smart-b553ae56-0039-46ad-9e30-d5cbb18742d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025742378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3025742378
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.829868892
Short name T1232
Test name
Test status
Simulation time 126642240 ps
CPU time 0.94 seconds
Started Jul 29 06:44:50 PM PDT 24
Finished Jul 29 06:44:51 PM PDT 24
Peak memory 199312 kb
Host smart-0a9be3c2-ab8d-4d6f-a12e-db538a5c36ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829868892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.829868892
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3001161413
Short name T95
Test name
Test status
Simulation time 330802994 ps
CPU time 1.3 seconds
Started Jul 29 06:44:46 PM PDT 24
Finished Jul 29 06:44:47 PM PDT 24
Peak memory 199792 kb
Host smart-dbd49dd3-3ffc-426e-bba4-4d7f437955bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001161413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3001161413
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4100381965
Short name T1290
Test name
Test status
Simulation time 37165061 ps
CPU time 0.91 seconds
Started Jul 29 06:44:52 PM PDT 24
Finished Jul 29 06:44:53 PM PDT 24
Peak memory 200240 kb
Host smart-c5537270-17ce-48db-ad77-9f70c97e6d3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100381965 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4100381965
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.444604692
Short name T86
Test name
Test status
Simulation time 14691717 ps
CPU time 0.63 seconds
Started Jul 29 06:44:47 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 195800 kb
Host smart-f6e66122-b4b0-4822-8b86-a4673f08ea98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444604692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.444604692
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.953205954
Short name T1286
Test name
Test status
Simulation time 16878330 ps
CPU time 0.58 seconds
Started Jul 29 06:44:48 PM PDT 24
Finished Jul 29 06:44:49 PM PDT 24
Peak memory 194736 kb
Host smart-443db7d6-345d-4087-a99a-3d49307df922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953205954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.953205954
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2767553187
Short name T87
Test name
Test status
Simulation time 20304950 ps
CPU time 0.62 seconds
Started Jul 29 06:44:48 PM PDT 24
Finished Jul 29 06:44:49 PM PDT 24
Peak memory 195816 kb
Host smart-e823f2e3-5f13-46bf-9805-82daf8f91d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767553187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2767553187
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2575306284
Short name T1213
Test name
Test status
Simulation time 55472964 ps
CPU time 1.37 seconds
Started Jul 29 06:44:46 PM PDT 24
Finished Jul 29 06:44:48 PM PDT 24
Peak memory 200520 kb
Host smart-a2079cd1-92c4-4512-bc0b-d0347510c73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575306284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2575306284
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.1576083738
Short name T1256
Test name
Test status
Simulation time 53171898 ps
CPU time 0.97 seconds
Started Jul 29 06:44:46 PM PDT 24
Finished Jul 29 06:44:47 PM PDT 24
Peak memory 199484 kb
Host smart-71e615a0-e7c0-4619-899d-3beab32683e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576083738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.1576083738
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3993306715
Short name T1277
Test name
Test status
Simulation time 54593500 ps
CPU time 0.8 seconds
Started Jul 29 06:44:51 PM PDT 24
Finished Jul 29 06:44:52 PM PDT 24
Peak memory 198916 kb
Host smart-d1765f03-d50d-45d1-8c34-e41e583173c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993306715 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3993306715
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.438640827
Short name T1269
Test name
Test status
Simulation time 13046924 ps
CPU time 0.6 seconds
Started Jul 29 06:44:50 PM PDT 24
Finished Jul 29 06:44:51 PM PDT 24
Peak memory 195792 kb
Host smart-10c81186-c8b5-4850-969f-ddb5d3db3f81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438640827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.438640827
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.311617144
Short name T1298
Test name
Test status
Simulation time 14954948 ps
CPU time 0.58 seconds
Started Jul 29 06:44:52 PM PDT 24
Finished Jul 29 06:44:53 PM PDT 24
Peak memory 194784 kb
Host smart-10f32df9-1e94-43c0-ba5d-d867a7ce550e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311617144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.311617144
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3299473534
Short name T84
Test name
Test status
Simulation time 105455205 ps
CPU time 0.76 seconds
Started Jul 29 06:44:51 PM PDT 24
Finished Jul 29 06:44:52 PM PDT 24
Peak memory 196284 kb
Host smart-d4660e56-38bd-4ee7-9d10-5aff83eb490b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299473534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3299473534
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1156213734
Short name T1197
Test name
Test status
Simulation time 134278223 ps
CPU time 1.16 seconds
Started Jul 29 06:44:51 PM PDT 24
Finished Jul 29 06:44:52 PM PDT 24
Peak memory 200444 kb
Host smart-76ab4436-ea50-4087-8f84-6dd4d686b8e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156213734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1156213734
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.504430605
Short name T1280
Test name
Test status
Simulation time 184285078 ps
CPU time 0.94 seconds
Started Jul 29 06:44:51 PM PDT 24
Finished Jul 29 06:44:52 PM PDT 24
Peak memory 199220 kb
Host smart-5e96818a-b833-4d52-9386-6ebdd1bfd9a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504430605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.504430605
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1491029210
Short name T1307
Test name
Test status
Simulation time 30270117 ps
CPU time 0.92 seconds
Started Jul 29 06:45:04 PM PDT 24
Finished Jul 29 06:45:05 PM PDT 24
Peak memory 200124 kb
Host smart-bad3ac75-e40b-4b22-ad88-c222caecdc7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491029210 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1491029210
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.2674538068
Short name T77
Test name
Test status
Simulation time 19709213 ps
CPU time 0.63 seconds
Started Jul 29 06:44:58 PM PDT 24
Finished Jul 29 06:44:59 PM PDT 24
Peak memory 195784 kb
Host smart-64360bfa-c9cd-4abb-911c-f176017880d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674538068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.2674538068
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1075424515
Short name T1216
Test name
Test status
Simulation time 49554506 ps
CPU time 0.59 seconds
Started Jul 29 06:45:03 PM PDT 24
Finished Jul 29 06:45:04 PM PDT 24
Peak memory 194772 kb
Host smart-0c18e00f-fdbd-49ed-821f-bbf871c7346b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075424515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1075424515
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1956073780
Short name T1295
Test name
Test status
Simulation time 95925698 ps
CPU time 0.63 seconds
Started Jul 29 06:44:59 PM PDT 24
Finished Jul 29 06:45:00 PM PDT 24
Peak memory 195900 kb
Host smart-4dc848d5-f562-4ed9-b194-0fb80307cf0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956073780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1956073780
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1301916299
Short name T1228
Test name
Test status
Simulation time 191392182 ps
CPU time 1.14 seconds
Started Jul 29 06:44:52 PM PDT 24
Finished Jul 29 06:44:53 PM PDT 24
Peak memory 200460 kb
Host smart-e118efdf-fb5a-47cf-91c2-0bc19635b64b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301916299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1301916299
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2945926330
Short name T1224
Test name
Test status
Simulation time 271162986 ps
CPU time 1.31 seconds
Started Jul 29 06:44:53 PM PDT 24
Finished Jul 29 06:44:54 PM PDT 24
Peak memory 199712 kb
Host smart-142d07b3-4875-4b0c-953a-c51bbb63b78e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945926330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2945926330
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1980730653
Short name T491
Test name
Test status
Simulation time 10841585 ps
CPU time 0.55 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 195164 kb
Host smart-b0e10f89-f8c5-4ce1-bdfb-a554cac93696
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980730653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1980730653
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1396150619
Short name T174
Test name
Test status
Simulation time 37924666707 ps
CPU time 13.34 seconds
Started Jul 29 07:12:12 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 200040 kb
Host smart-3d38a7c4-1422-4a38-a03a-6e1a726a46ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396150619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1396150619
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3026327423
Short name T1023
Test name
Test status
Simulation time 80843736018 ps
CPU time 74.55 seconds
Started Jul 29 07:12:19 PM PDT 24
Finished Jul 29 07:13:33 PM PDT 24
Peak memory 199944 kb
Host smart-ec2d2f7a-39a2-4b78-9d20-1a9358b60a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026327423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3026327423
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.556479725
Short name T335
Test name
Test status
Simulation time 75106234449 ps
CPU time 26.12 seconds
Started Jul 29 07:12:17 PM PDT 24
Finished Jul 29 07:12:43 PM PDT 24
Peak memory 199752 kb
Host smart-09955f1a-460b-404b-933c-b24f89ef08dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556479725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.556479725
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_intr.1041576388
Short name T1061
Test name
Test status
Simulation time 38357565550 ps
CPU time 20.65 seconds
Started Jul 29 07:12:10 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 199976 kb
Host smart-2f680c41-ca16-4fd3-a209-0df850c73259
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041576388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1041576388
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2935243431
Short name T724
Test name
Test status
Simulation time 106859618419 ps
CPU time 313.59 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:17:39 PM PDT 24
Peak memory 199888 kb
Host smart-f2e0e99b-2da3-4334-89f4-9d703b283eef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935243431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2935243431
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.964272762
Short name T408
Test name
Test status
Simulation time 5495111805 ps
CPU time 4.97 seconds
Started Jul 29 07:12:19 PM PDT 24
Finished Jul 29 07:12:24 PM PDT 24
Peak memory 199848 kb
Host smart-5d125893-4e58-4c39-96b4-baa8fb6207e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964272762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.964272762
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.1958085561
Short name T665
Test name
Test status
Simulation time 55038751284 ps
CPU time 87.1 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:13:52 PM PDT 24
Peak memory 199912 kb
Host smart-dc5eb0ba-5199-42a9-a762-749f087d0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958085561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1958085561
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.264894237
Short name T596
Test name
Test status
Simulation time 9559460512 ps
CPU time 298.83 seconds
Started Jul 29 07:12:17 PM PDT 24
Finished Jul 29 07:17:16 PM PDT 24
Peak memory 199984 kb
Host smart-f15c6f5d-1391-4e67-8ad8-34824ea356e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=264894237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.264894237
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.229800219
Short name T640
Test name
Test status
Simulation time 1704143355 ps
CPU time 2.78 seconds
Started Jul 29 07:12:19 PM PDT 24
Finished Jul 29 07:12:22 PM PDT 24
Peak memory 198428 kb
Host smart-db43ebe5-6c46-43da-91df-f3dc7985f485
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=229800219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.229800219
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.3780895557
Short name T898
Test name
Test status
Simulation time 107662772168 ps
CPU time 16.69 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:42 PM PDT 24
Peak memory 199760 kb
Host smart-84b74ed7-503f-4e31-a471-7d439741d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780895557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.3780895557
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1433860522
Short name T905
Test name
Test status
Simulation time 4641960885 ps
CPU time 3.71 seconds
Started Jul 29 07:12:17 PM PDT 24
Finished Jul 29 07:12:21 PM PDT 24
Peak memory 196112 kb
Host smart-23ddeec2-641d-4f9f-a526-5f7721e99e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433860522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1433860522
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2268520014
Short name T105
Test name
Test status
Simulation time 1242748857 ps
CPU time 1.13 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 218340 kb
Host smart-614328e4-6cd2-4720-b4e5-142383955a01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268520014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2268520014
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2505210880
Short name T679
Test name
Test status
Simulation time 665918892 ps
CPU time 1.77 seconds
Started Jul 29 07:12:17 PM PDT 24
Finished Jul 29 07:12:19 PM PDT 24
Peak memory 198560 kb
Host smart-2aee2d84-cc40-4ba8-b9a6-fde81b0dc757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505210880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2505210880
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.1572186619
Short name T768
Test name
Test status
Simulation time 113589871835 ps
CPU time 76.13 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:13:40 PM PDT 24
Peak memory 199832 kb
Host smart-311586c4-9080-4f7b-86d4-458ccbab3d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572186619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1572186619
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.2138213117
Short name T789
Test name
Test status
Simulation time 14511372566 ps
CPU time 181.21 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:15:27 PM PDT 24
Peak memory 216520 kb
Host smart-7f3eaeea-3c44-42cc-bcb2-c7ac3e68fa98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138213117 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.2138213117
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.2381051106
Short name T279
Test name
Test status
Simulation time 7011258913 ps
CPU time 17.65 seconds
Started Jul 29 07:12:11 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 199912 kb
Host smart-11ff2e78-44f5-4235-b9d4-719a9c9d8a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381051106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.2381051106
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.664365395
Short name T541
Test name
Test status
Simulation time 10224032379 ps
CPU time 15.14 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:41 PM PDT 24
Peak memory 199848 kb
Host smart-e19fc424-10ef-4209-86ee-57320d07c45a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664365395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.664365395
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.3638543332
Short name T1081
Test name
Test status
Simulation time 18315540 ps
CPU time 0.56 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 195348 kb
Host smart-448b3760-b0fd-4db5-8971-1f442104c8bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638543332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3638543332
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.3338730062
Short name T305
Test name
Test status
Simulation time 156348856906 ps
CPU time 41.78 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:13:07 PM PDT 24
Peak memory 199952 kb
Host smart-b5a8a585-b074-42fe-af09-f701bd0a8069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338730062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3338730062
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.89060250
Short name T369
Test name
Test status
Simulation time 72852239905 ps
CPU time 25.55 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:50 PM PDT 24
Peak memory 199672 kb
Host smart-932a6184-e835-46f4-b89a-b4fd72cbdad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89060250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.89060250
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.2047592198
Short name T1076
Test name
Test status
Simulation time 134794028005 ps
CPU time 265.88 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:16:50 PM PDT 24
Peak memory 199980 kb
Host smart-5c7ebd80-d986-4c41-849b-28bee26ea80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047592198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.2047592198
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.911023400
Short name T1111
Test name
Test status
Simulation time 5835597449 ps
CPU time 3.5 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 198336 kb
Host smart-20861c7f-4b60-4fe7-8f4f-c4e70dfe504d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911023400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.911023400
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1462412985
Short name T503
Test name
Test status
Simulation time 278115890668 ps
CPU time 67.22 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:13:33 PM PDT 24
Peak memory 199968 kb
Host smart-534ec0b0-5ec6-4dfb-9e9e-d73ff6b313c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462412985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1462412985
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2784451026
Short name T710
Test name
Test status
Simulation time 3600751069 ps
CPU time 7.72 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:32 PM PDT 24
Peak memory 198352 kb
Host smart-10c432a8-4405-401d-9b36-c8850d258ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784451026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2784451026
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2291869551
Short name T1132
Test name
Test status
Simulation time 103965161441 ps
CPU time 16.4 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:42 PM PDT 24
Peak memory 200024 kb
Host smart-b87b9480-7515-4ebc-b0da-a67cf35f63dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291869551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2291869551
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2716427961
Short name T281
Test name
Test status
Simulation time 12403336872 ps
CPU time 153.56 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:14:58 PM PDT 24
Peak memory 199996 kb
Host smart-81adbab6-05cf-436c-a06d-60bea708ba70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2716427961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2716427961
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3850095740
Short name T574
Test name
Test status
Simulation time 7235707763 ps
CPU time 62.19 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 198220 kb
Host smart-03aa4d4c-5af8-4aa9-bf77-53cef087cbfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3850095740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3850095740
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.584411595
Short name T173
Test name
Test status
Simulation time 73409417261 ps
CPU time 119.33 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 199992 kb
Host smart-c27a67d9-df98-40bf-b86f-d6e0d633c911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584411595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.584411595
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.792420454
Short name T824
Test name
Test status
Simulation time 6061638355 ps
CPU time 2.69 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 196056 kb
Host smart-b549cd20-f3d3-49ec-b02b-da5907ecaceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792420454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.792420454
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.3034756798
Short name T26
Test name
Test status
Simulation time 142183978 ps
CPU time 0.77 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 218416 kb
Host smart-fd9f6896-99f0-412f-8592-1527de42e335
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034756798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.3034756798
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.3654802035
Short name T463
Test name
Test status
Simulation time 5333028690 ps
CPU time 18.36 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:43 PM PDT 24
Peak memory 199912 kb
Host smart-d3a6976a-7c97-4f3c-8c9a-b3bd462517ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654802035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.3654802035
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.1032598610
Short name T777
Test name
Test status
Simulation time 45190193003 ps
CPU time 61.67 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:13:28 PM PDT 24
Peak memory 208284 kb
Host smart-4ba815d0-3ca1-4b9f-a06e-646f0eac0ec9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032598610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1032598610
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3412900079
Short name T617
Test name
Test status
Simulation time 274000920808 ps
CPU time 962.55 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:28:28 PM PDT 24
Peak memory 216016 kb
Host smart-128196e9-9f44-40f2-99d5-500115d2397f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412900079 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3412900079
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.2019513468
Short name T530
Test name
Test status
Simulation time 8881357140 ps
CPU time 9.96 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:36 PM PDT 24
Peak memory 199416 kb
Host smart-f0a76310-f582-4a0f-8dee-ec5e6edb9108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019513468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.2019513468
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.201564646
Short name T606
Test name
Test status
Simulation time 17697490242 ps
CPU time 27.23 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 199988 kb
Host smart-f5a2df02-56ea-4b53-ac0e-cdb9fa5c883a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201564646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.201564646
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.367463078
Short name T880
Test name
Test status
Simulation time 10460286 ps
CPU time 0.55 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:46 PM PDT 24
Peak memory 195344 kb
Host smart-54596f75-3226-4cd3-b8ea-0bbed48e093d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367463078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.367463078
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2988708428
Short name T166
Test name
Test status
Simulation time 144280479780 ps
CPU time 191.02 seconds
Started Jul 29 07:12:43 PM PDT 24
Finished Jul 29 07:15:54 PM PDT 24
Peak memory 199880 kb
Host smart-08144ba9-ea36-41de-85e4-7745a419ff2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988708428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2988708428
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3033333845
Short name T314
Test name
Test status
Simulation time 93077822022 ps
CPU time 24.28 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:13:09 PM PDT 24
Peak memory 199900 kb
Host smart-80b0f638-d2a8-4b10-9145-d184a26401f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033333845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3033333845
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3726630157
Short name T240
Test name
Test status
Simulation time 66969291485 ps
CPU time 29.66 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 199988 kb
Host smart-cb0bfd4f-c2d2-4f0a-bda4-2a811e92372a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726630157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3726630157
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3569344089
Short name T657
Test name
Test status
Simulation time 22252963898 ps
CPU time 11.72 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:58 PM PDT 24
Peak memory 200080 kb
Host smart-dd76168f-46b4-418c-9550-607c9896b081
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569344089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3569344089
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1705262233
Short name T557
Test name
Test status
Simulation time 76418074976 ps
CPU time 593.21 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:22:43 PM PDT 24
Peak memory 199920 kb
Host smart-cd140c7f-05b8-4a72-b5e5-d1158a21030b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705262233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1705262233
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2113345783
Short name T1030
Test name
Test status
Simulation time 136889035 ps
CPU time 0.71 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 196844 kb
Host smart-34ed4898-23d8-471a-a631-422fd9b58377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113345783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2113345783
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3018042581
Short name T386
Test name
Test status
Simulation time 136221473778 ps
CPU time 52.84 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:38 PM PDT 24
Peak memory 199908 kb
Host smart-bf598bbf-263b-45fe-b547-083fe40d777e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018042581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3018042581
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.4181411003
Short name T438
Test name
Test status
Simulation time 21758353004 ps
CPU time 203.93 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:16:12 PM PDT 24
Peak memory 199924 kb
Host smart-1fdc5c8c-3df1-4fab-9a22-645ce55b9154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4181411003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.4181411003
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.248880943
Short name T537
Test name
Test status
Simulation time 7471663590 ps
CPU time 17.32 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:13:02 PM PDT 24
Peak memory 198592 kb
Host smart-c9bece03-0cba-43d4-ae52-ce36a6884f68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248880943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.248880943
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.2036401871
Short name T296
Test name
Test status
Simulation time 14793324595 ps
CPU time 25.27 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:10 PM PDT 24
Peak memory 199912 kb
Host smart-5ca17a35-0594-4e35-8a34-2a1c93a8c9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036401871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2036401871
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.2123136069
Short name T396
Test name
Test status
Simulation time 3825950710 ps
CPU time 2.2 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 196280 kb
Host smart-7ec4584a-6891-4e33-a27b-b2a10efdcb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123136069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2123136069
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.3646068355
Short name T1056
Test name
Test status
Simulation time 5792693847 ps
CPU time 13.1 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:59 PM PDT 24
Peak memory 199952 kb
Host smart-7f5598ac-038b-4588-8150-71deb8727055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646068355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.3646068355
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.311826958
Short name T1066
Test name
Test status
Simulation time 75997319474 ps
CPU time 988.7 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:29:18 PM PDT 24
Peak memory 215952 kb
Host smart-347331d2-d9ce-4c08-a98d-f53d1617c6c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311826958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.311826958
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3399031812
Short name T17
Test name
Test status
Simulation time 107653910292 ps
CPU time 314.19 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:18:04 PM PDT 24
Peak memory 216432 kb
Host smart-a71aad4b-03d8-4bc1-893d-2f37445ea0ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399031812 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3399031812
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1654911542
Short name T1047
Test name
Test status
Simulation time 762350763 ps
CPU time 2.34 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:12:48 PM PDT 24
Peak memory 198636 kb
Host smart-a47c3e0e-9ebf-4a91-85d2-5a1d24933468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654911542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1654911542
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2106179559
Short name T660
Test name
Test status
Simulation time 21360773918 ps
CPU time 8.98 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:12:58 PM PDT 24
Peak memory 196704 kb
Host smart-34a11af9-e5d3-497e-a906-0fb77f0faa2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106179559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2106179559
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.1132528069
Short name T823
Test name
Test status
Simulation time 109432615316 ps
CPU time 47.03 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:18:18 PM PDT 24
Peak memory 199956 kb
Host smart-502e57ae-85b3-4ce6-8591-9a3cbffd6207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132528069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1132528069
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3522441268
Short name T247
Test name
Test status
Simulation time 72649387716 ps
CPU time 129.91 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:19:43 PM PDT 24
Peak memory 200036 kb
Host smart-f13d0edc-73ff-4856-adc7-74c005d41df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522441268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3522441268
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1578500688
Short name T992
Test name
Test status
Simulation time 18546133486 ps
CPU time 26.68 seconds
Started Jul 29 07:17:34 PM PDT 24
Finished Jul 29 07:18:00 PM PDT 24
Peak memory 199652 kb
Host smart-744904de-8a1b-458a-8104-2dafac30cd32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578500688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1578500688
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1397364764
Short name T588
Test name
Test status
Simulation time 12291041813 ps
CPU time 13.6 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:17:47 PM PDT 24
Peak memory 199980 kb
Host smart-649cbd1c-e57c-4e01-a9e0-5c96be7fef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397364764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1397364764
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3146126586
Short name T331
Test name
Test status
Simulation time 94115847854 ps
CPU time 29.01 seconds
Started Jul 29 07:17:34 PM PDT 24
Finished Jul 29 07:18:03 PM PDT 24
Peak memory 199972 kb
Host smart-ac78def4-8f8b-4c1c-b410-7899fd1be6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146126586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3146126586
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2827799620
Short name T987
Test name
Test status
Simulation time 108041536034 ps
CPU time 428.32 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:24:42 PM PDT 24
Peak memory 199984 kb
Host smart-e1f23b56-a21a-4c88-ab02-81abf73f973d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827799620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2827799620
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.1994155025
Short name T189
Test name
Test status
Simulation time 252426129406 ps
CPU time 40.6 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:18:25 PM PDT 24
Peak memory 199928 kb
Host smart-6a6c057b-fbd6-4047-9816-f8384f9c449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994155025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1994155025
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.3090437746
Short name T891
Test name
Test status
Simulation time 55167638249 ps
CPU time 27.98 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:18:14 PM PDT 24
Peak memory 199960 kb
Host smart-1a6070b4-290d-450d-85c2-007407a19de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090437746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3090437746
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2235055658
Short name T712
Test name
Test status
Simulation time 12194288 ps
CPU time 0.55 seconds
Started Jul 29 07:12:41 PM PDT 24
Finished Jul 29 07:12:42 PM PDT 24
Peak memory 194284 kb
Host smart-352f8266-1349-487d-b98e-979d6530ce0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235055658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2235055658
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.817723178
Short name T586
Test name
Test status
Simulation time 164156170657 ps
CPU time 140.87 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:15:06 PM PDT 24
Peak memory 199992 kb
Host smart-69f207bb-2cae-4b60-8ec5-9d6ff2a2bddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817723178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.817723178
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.2256136965
Short name T936
Test name
Test status
Simulation time 25149379005 ps
CPU time 37.52 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 199672 kb
Host smart-e0be617a-47bd-4b18-85ba-40ff7718db72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256136965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2256136965
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.430828898
Short name T1154
Test name
Test status
Simulation time 65703470909 ps
CPU time 33.89 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:19 PM PDT 24
Peak memory 199876 kb
Host smart-23648a72-70ac-4b2b-b20e-06f6a5f5fa8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430828898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.430828898
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.97601676
Short name T1148
Test name
Test status
Simulation time 70243680099 ps
CPU time 22.45 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:13:11 PM PDT 24
Peak memory 199812 kb
Host smart-5f64400a-3296-49ac-8ff9-f9985a5f4d37
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97601676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.97601676
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.3551657130
Short name T428
Test name
Test status
Simulation time 110191408605 ps
CPU time 412.23 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:19:42 PM PDT 24
Peak memory 199876 kb
Host smart-c4a81d70-5f55-4bcd-9f80-38836acec08d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3551657130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.3551657130
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.202018294
Short name T901
Test name
Test status
Simulation time 4222556263 ps
CPU time 1.93 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 195824 kb
Host smart-874122b0-5e37-4516-aee1-1e1f5372b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202018294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.202018294
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.440494124
Short name T263
Test name
Test status
Simulation time 180131328757 ps
CPU time 36.85 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:13:25 PM PDT 24
Peak memory 200032 kb
Host smart-666139c0-28c1-45d7-b2a3-0c0f531e7019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440494124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.440494124
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.4292277
Short name T375
Test name
Test status
Simulation time 13457612398 ps
CPU time 624.42 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:23:14 PM PDT 24
Peak memory 199864 kb
Host smart-0b8f3776-afb5-4e47-a233-c96723f24caa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4292277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.4292277
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.504084666
Short name T1138
Test name
Test status
Simulation time 5016129502 ps
CPU time 3.2 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 198708 kb
Host smart-36c46ed2-b0ec-4557-bedb-804b7481b919
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=504084666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.504084666
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.154472995
Short name T912
Test name
Test status
Simulation time 163292535650 ps
CPU time 50.49 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 199872 kb
Host smart-5f4c3243-652e-4699-950a-d403c7c00086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154472995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.154472995
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2008984534
Short name T310
Test name
Test status
Simulation time 2630701702 ps
CPU time 1.4 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 195892 kb
Host smart-7a79ef41-dedb-4da2-a808-dabc7dac9bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008984534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2008984534
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.715869653
Short name T603
Test name
Test status
Simulation time 6105564692 ps
CPU time 7.14 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:54 PM PDT 24
Peak memory 199908 kb
Host smart-09c1c4de-5b3a-47da-9ab0-45f5738c78cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715869653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.715869653
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.751002800
Short name T154
Test name
Test status
Simulation time 178770281009 ps
CPU time 348.82 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:18:39 PM PDT 24
Peak memory 199936 kb
Host smart-95c95c38-a3aa-44b0-8c32-3f4bf9fae8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751002800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.751002800
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4112344936
Short name T922
Test name
Test status
Simulation time 6406285354 ps
CPU time 14.81 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:13:04 PM PDT 24
Peak memory 199884 kb
Host smart-7f565ee1-010d-41e1-b772-df2cfc26559b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112344936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4112344936
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1987707221
Short name T691
Test name
Test status
Simulation time 82404416721 ps
CPU time 348.22 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:18:38 PM PDT 24
Peak memory 199936 kb
Host smart-968b61f8-c155-4de5-86e4-247ec19b162b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987707221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1987707221
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.3363278381
Short name T232
Test name
Test status
Simulation time 288776748971 ps
CPU time 216.72 seconds
Started Jul 29 07:17:48 PM PDT 24
Finished Jul 29 07:21:24 PM PDT 24
Peak memory 199924 kb
Host smart-8faa2e56-b4bb-410b-90e7-059d1694493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363278381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.3363278381
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1454871976
Short name T176
Test name
Test status
Simulation time 111768100137 ps
CPU time 14.27 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:18:00 PM PDT 24
Peak memory 199664 kb
Host smart-cc995895-ce47-42a5-be8e-28ee4fd81816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454871976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1454871976
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1256713301
Short name T556
Test name
Test status
Simulation time 121121256356 ps
CPU time 95.84 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:19:22 PM PDT 24
Peak memory 199888 kb
Host smart-eef1ba01-9e32-4389-a896-a9a4f2206f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256713301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1256713301
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.685788815
Short name T988
Test name
Test status
Simulation time 26260903251 ps
CPU time 20.37 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:18:05 PM PDT 24
Peak memory 199968 kb
Host smart-ff9cc2ba-cf1a-4701-a506-367b9fdc06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685788815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.685788815
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.2798148330
Short name T494
Test name
Test status
Simulation time 16798959776 ps
CPU time 36.53 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:34 PM PDT 24
Peak memory 199928 kb
Host smart-671c7744-6174-4d4c-b6d0-53b19552a75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798148330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.2798148330
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2524183552
Short name T146
Test name
Test status
Simulation time 87058618707 ps
CPU time 39.07 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:35 PM PDT 24
Peak memory 199932 kb
Host smart-89fb9e92-1853-432b-8609-651abbb33944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524183552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2524183552
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.4117144601
Short name T1171
Test name
Test status
Simulation time 6054379314 ps
CPU time 10.11 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:17:56 PM PDT 24
Peak memory 199908 kb
Host smart-c5a720b3-66ae-4511-894f-f00f4fb8f565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117144601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.4117144601
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4194916973
Short name T1137
Test name
Test status
Simulation time 15111171 ps
CPU time 0.55 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 195288 kb
Host smart-991e1087-9b2a-42ae-80c5-2fef1ed594fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194916973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4194916973
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.3303533843
Short name T814
Test name
Test status
Simulation time 93514775327 ps
CPU time 85.66 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:14:13 PM PDT 24
Peak memory 199960 kb
Host smart-85c688d3-5daf-486c-93ac-3395914a9070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303533843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.3303533843
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3706672352
Short name T822
Test name
Test status
Simulation time 111590297356 ps
CPU time 126.09 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:14:53 PM PDT 24
Peak memory 199968 kb
Host smart-c9f46ac9-56aa-4ad3-98f8-ba708968eb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706672352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3706672352
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2822274507
Short name T667
Test name
Test status
Simulation time 188064926670 ps
CPU time 56.36 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:13:47 PM PDT 24
Peak memory 199940 kb
Host smart-ecf23242-4bfc-48e3-9cce-79407b027763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822274507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2822274507
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.661601329
Short name T809
Test name
Test status
Simulation time 59717042394 ps
CPU time 57.95 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:13:45 PM PDT 24
Peak memory 199912 kb
Host smart-0ebb1008-1b57-4e1d-b8c4-ca18a7af906c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661601329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.661601329
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.1796056749
Short name T872
Test name
Test status
Simulation time 139088607435 ps
CPU time 212.68 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:16:23 PM PDT 24
Peak memory 199936 kb
Host smart-fe71debb-abbd-44c8-99fe-c04c4d971742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796056749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.1796056749
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.665458086
Short name T571
Test name
Test status
Simulation time 2460756054 ps
CPU time 5.09 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:55 PM PDT 24
Peak memory 198824 kb
Host smart-77414b9d-e797-4265-a8a2-5df4206d5635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665458086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.665458086
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.935170297
Short name T1035
Test name
Test status
Simulation time 27811922428 ps
CPU time 47.86 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:13:36 PM PDT 24
Peak memory 198456 kb
Host smart-f1f22ade-da52-401e-a024-b1c792686491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935170297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.935170297
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4070956165
Short name T919
Test name
Test status
Simulation time 12581296313 ps
CPU time 155.25 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:15:23 PM PDT 24
Peak memory 199952 kb
Host smart-ac1d912b-a376-4efe-9cee-3dd873194154
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4070956165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4070956165
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3859225649
Short name T857
Test name
Test status
Simulation time 3916137058 ps
CPU time 7.67 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:58 PM PDT 24
Peak memory 198084 kb
Host smart-cd7ab704-3fa4-4258-ab9d-6fe6eda8dd6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859225649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3859225649
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.1681579743
Short name T870
Test name
Test status
Simulation time 119580269907 ps
CPU time 201.94 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:16:07 PM PDT 24
Peak memory 200128 kb
Host smart-e58add33-77a8-4a0d-881e-c070172f06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681579743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.1681579743
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1581647205
Short name T9
Test name
Test status
Simulation time 4709635931 ps
CPU time 1 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 196252 kb
Host smart-990870b2-cc76-4bf5-9bb6-9d504cc4c407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581647205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1581647205
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2831122308
Short name T686
Test name
Test status
Simulation time 927848123 ps
CPU time 3.8 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 198312 kb
Host smart-e2ea480e-fcf8-4f2e-872c-177b307ec3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831122308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2831122308
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.995411330
Short name T591
Test name
Test status
Simulation time 31476442699 ps
CPU time 346.52 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:18:34 PM PDT 24
Peak memory 215520 kb
Host smart-913e4fa7-26f3-4390-965c-47c43c749112
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995411330 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.995411330
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3746108068
Short name T311
Test name
Test status
Simulation time 1322622309 ps
CPU time 2.31 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:52 PM PDT 24
Peak memory 198636 kb
Host smart-744e2cb7-2549-452f-9a19-50ed84eed306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746108068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3746108068
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.3696763145
Short name T806
Test name
Test status
Simulation time 107644251219 ps
CPU time 169.18 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:15:37 PM PDT 24
Peak memory 199832 kb
Host smart-2ef7d1c0-4d47-4446-9195-6dccae30d878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696763145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.3696763145
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1838625778
Short name T42
Test name
Test status
Simulation time 34991794515 ps
CPU time 58.48 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:18:50 PM PDT 24
Peak memory 199924 kb
Host smart-7db4dc07-4002-4d94-89be-685ad7a9339d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838625778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1838625778
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3370791834
Short name T207
Test name
Test status
Simulation time 41234052067 ps
CPU time 61.62 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:57 PM PDT 24
Peak memory 199968 kb
Host smart-2ebb2cc6-4519-4a6d-a172-3a5844b8e61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370791834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3370791834
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2798189126
Short name T843
Test name
Test status
Simulation time 92635459470 ps
CPU time 146.06 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:20:13 PM PDT 24
Peak memory 199668 kb
Host smart-c8811f26-4209-4fde-9da7-ef47e695139e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798189126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2798189126
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3068818046
Short name T158
Test name
Test status
Simulation time 378212496076 ps
CPU time 38.56 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:18:23 PM PDT 24
Peak memory 199960 kb
Host smart-7e86e7db-bc7a-4b61-a1f6-2c02b7046fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068818046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3068818046
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.3374088024
Short name T592
Test name
Test status
Simulation time 92880666932 ps
CPU time 122.83 seconds
Started Jul 29 07:17:48 PM PDT 24
Finished Jul 29 07:19:51 PM PDT 24
Peak memory 199980 kb
Host smart-8bfa50d3-5a35-46dd-80a3-a7325190f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374088024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.3374088024
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.1094992628
Short name T129
Test name
Test status
Simulation time 32399618061 ps
CPU time 11.48 seconds
Started Jul 29 07:17:52 PM PDT 24
Finished Jul 29 07:18:03 PM PDT 24
Peak memory 199976 kb
Host smart-ffc535be-b9f1-4de9-902b-537e42543def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094992628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1094992628
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.1507767017
Short name T1149
Test name
Test status
Simulation time 42134689442 ps
CPU time 45.27 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:18:31 PM PDT 24
Peak memory 200116 kb
Host smart-fc5714f4-e200-4e4f-bd0c-8059deaeded4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507767017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.1507767017
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1893734285
Short name T1044
Test name
Test status
Simulation time 22460529 ps
CPU time 0.57 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:13:00 PM PDT 24
Peak memory 195288 kb
Host smart-fe25b22c-0aa1-4530-bf31-7f73a9fe2710
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893734285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1893734285
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3158214110
Short name T707
Test name
Test status
Simulation time 130270236022 ps
CPU time 62.42 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:13:46 PM PDT 24
Peak memory 200096 kb
Host smart-a0adca1e-d38c-4ee5-ac02-13b10987c608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158214110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3158214110
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.2878661062
Short name T124
Test name
Test status
Simulation time 106710689924 ps
CPU time 26.9 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:13:14 PM PDT 24
Peak memory 199976 kb
Host smart-bac51698-d166-4da3-9e9b-ac337e445ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878661062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2878661062
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2918776708
Short name T902
Test name
Test status
Simulation time 27581082948 ps
CPU time 40.75 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:13:29 PM PDT 24
Peak memory 199924 kb
Host smart-e7672035-075b-4433-88d4-169f058512f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918776708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2918776708
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1826423611
Short name T733
Test name
Test status
Simulation time 80990900410 ps
CPU time 116.09 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:14:56 PM PDT 24
Peak memory 199904 kb
Host smart-bd003b4f-7ed8-4f27-9221-ad0a8ace1ad9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826423611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1826423611
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.151922619
Short name T533
Test name
Test status
Simulation time 341262013055 ps
CPU time 251.47 seconds
Started Jul 29 07:12:55 PM PDT 24
Finished Jul 29 07:17:06 PM PDT 24
Peak memory 199800 kb
Host smart-932f94f3-7be2-490b-b825-a5a5ed67c864
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=151922619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.151922619
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.2538288424
Short name T917
Test name
Test status
Simulation time 1819451133 ps
CPU time 2.58 seconds
Started Jul 29 07:12:51 PM PDT 24
Finished Jul 29 07:12:54 PM PDT 24
Peak memory 199660 kb
Host smart-5634dc66-e425-4afd-9483-7c58ba416d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538288424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.2538288424
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.692358674
Short name T723
Test name
Test status
Simulation time 7939847910 ps
CPU time 6.32 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:57 PM PDT 24
Peak memory 199148 kb
Host smart-e863b581-cc51-45b6-8d32-8f5fefe81096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692358674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.692358674
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.4023280912
Short name T315
Test name
Test status
Simulation time 24837667438 ps
CPU time 380.41 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:19:17 PM PDT 24
Peak memory 199920 kb
Host smart-754aacd3-d805-4432-b7ac-9c9e327c83ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023280912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.4023280912
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.4115185259
Short name T1090
Test name
Test status
Simulation time 6308294870 ps
CPU time 27.82 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:13:17 PM PDT 24
Peak memory 199320 kb
Host smart-3d7c802d-7451-4ba2-8bb8-166632fe0b50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115185259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.4115185259
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3288998433
Short name T1015
Test name
Test status
Simulation time 60499491610 ps
CPU time 30.63 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:13:31 PM PDT 24
Peak memory 199984 kb
Host smart-c43b29ae-82d0-49ae-8290-6e30cf92c616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288998433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3288998433
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.4121478248
Short name T1084
Test name
Test status
Simulation time 4002988702 ps
CPU time 2.02 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:12:52 PM PDT 24
Peak memory 196084 kb
Host smart-21287ec1-d48a-43df-8e76-a5fcc5128ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121478248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.4121478248
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4013234827
Short name T755
Test name
Test status
Simulation time 561355298 ps
CPU time 1.54 seconds
Started Jul 29 07:12:42 PM PDT 24
Finished Jul 29 07:12:44 PM PDT 24
Peak memory 198652 kb
Host smart-651ec8b3-ebbc-4f6e-928e-b0ae3faef0e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013234827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4013234827
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.56822646
Short name T464
Test name
Test status
Simulation time 131038404451 ps
CPU time 95.98 seconds
Started Jul 29 07:12:52 PM PDT 24
Finished Jul 29 07:14:28 PM PDT 24
Peak memory 199928 kb
Host smart-9f09f85e-4671-4bf8-84cb-177a90260652
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56822646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.56822646
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.2710238505
Short name T871
Test name
Test status
Simulation time 663961751 ps
CPU time 1.59 seconds
Started Jul 29 07:12:51 PM PDT 24
Finished Jul 29 07:12:52 PM PDT 24
Peak memory 200044 kb
Host smart-e0566366-00f1-4646-9ddc-36cd1e19c4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710238505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.2710238505
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.4005063263
Short name T363
Test name
Test status
Simulation time 66279867001 ps
CPU time 26.2 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:12 PM PDT 24
Peak memory 200028 kb
Host smart-b714f34d-d61a-4716-9e8c-c11cd536402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005063263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.4005063263
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2525653064
Short name T916
Test name
Test status
Simulation time 22725591490 ps
CPU time 30.02 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:18 PM PDT 24
Peak memory 199892 kb
Host smart-76a81101-398c-4e5d-bf4d-ddd88c44754d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525653064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2525653064
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3774298698
Short name T721
Test name
Test status
Simulation time 125998354180 ps
CPU time 86.57 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:19:14 PM PDT 24
Peak memory 199944 kb
Host smart-fbd992d9-f01c-4bf6-b365-3de982d824c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774298698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3774298698
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.3830454566
Short name T144
Test name
Test status
Simulation time 347411448880 ps
CPU time 70.5 seconds
Started Jul 29 07:17:48 PM PDT 24
Finished Jul 29 07:18:59 PM PDT 24
Peak memory 199848 kb
Host smart-9ca77a82-3e2b-48d6-82ce-999b27fc4dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830454566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.3830454566
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1414671400
Short name T927
Test name
Test status
Simulation time 30184298241 ps
CPU time 45.77 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:42 PM PDT 24
Peak memory 199980 kb
Host smart-01756626-59bd-4ccc-bf85-6997bc641a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414671400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1414671400
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2466932259
Short name T1001
Test name
Test status
Simulation time 30289950866 ps
CPU time 58.76 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:56 PM PDT 24
Peak memory 199868 kb
Host smart-d48e19bf-45f0-4edb-8bd4-c141a0eef11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466932259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2466932259
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3904442578
Short name T65
Test name
Test status
Simulation time 31405905568 ps
CPU time 11.83 seconds
Started Jul 29 07:17:52 PM PDT 24
Finished Jul 29 07:18:04 PM PDT 24
Peak memory 199956 kb
Host smart-3c04332b-aec2-4504-b149-dcbf0bd17980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904442578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3904442578
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.979586253
Short name T519
Test name
Test status
Simulation time 119039178475 ps
CPU time 44.31 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:41 PM PDT 24
Peak memory 199700 kb
Host smart-e4b05740-4662-45c2-b36b-d65ce2984598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979586253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.979586253
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.1194268169
Short name T629
Test name
Test status
Simulation time 96101577473 ps
CPU time 75.31 seconds
Started Jul 29 07:17:49 PM PDT 24
Finished Jul 29 07:19:04 PM PDT 24
Peak memory 199968 kb
Host smart-98cfd4aa-cf76-4d69-93ea-835432e1d5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194268169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1194268169
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.1341414381
Short name T348
Test name
Test status
Simulation time 17583107262 ps
CPU time 8.45 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:17:56 PM PDT 24
Peak memory 199916 kb
Host smart-35d204b6-efe3-4eac-b9ac-281d459876db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341414381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.1341414381
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2309730426
Short name T581
Test name
Test status
Simulation time 17064969 ps
CPU time 0.55 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:13:01 PM PDT 24
Peak memory 195348 kb
Host smart-689e4583-5687-4e64-8462-050690be09e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309730426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2309730426
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1351095732
Short name T1082
Test name
Test status
Simulation time 76295454360 ps
CPU time 34.22 seconds
Started Jul 29 07:12:57 PM PDT 24
Finished Jul 29 07:13:31 PM PDT 24
Peak memory 199960 kb
Host smart-ca681497-e783-4076-a257-b974d256148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351095732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1351095732
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.1496043189
Short name T802
Test name
Test status
Simulation time 133634547855 ps
CPU time 35.97 seconds
Started Jul 29 07:12:52 PM PDT 24
Finished Jul 29 07:13:28 PM PDT 24
Peak memory 200016 kb
Host smart-37da0b03-8df0-4e29-8cfe-114a4f9dc521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496043189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.1496043189
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3019284778
Short name T18
Test name
Test status
Simulation time 27647224976 ps
CPU time 11.94 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:13:11 PM PDT 24
Peak memory 199096 kb
Host smart-434d9e3b-7795-4ce5-8eec-24e604b6406b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019284778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3019284778
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3066577812
Short name T853
Test name
Test status
Simulation time 135072680478 ps
CPU time 717.05 seconds
Started Jul 29 07:12:54 PM PDT 24
Finished Jul 29 07:24:51 PM PDT 24
Peak memory 199916 kb
Host smart-c19ae4b8-b7ab-4a69-b7f3-4f6e4cee4918
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3066577812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3066577812
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1705325213
Short name T945
Test name
Test status
Simulation time 5212392562 ps
CPU time 9.16 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:13:06 PM PDT 24
Peak memory 199620 kb
Host smart-092fe333-a827-4972-845f-cd179194c1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705325213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1705325213
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3741329963
Short name T636
Test name
Test status
Simulation time 164660048489 ps
CPU time 112.63 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:14:41 PM PDT 24
Peak memory 199812 kb
Host smart-2ce4d639-3917-4b15-98b2-f882071f2474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741329963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3741329963
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.2406001957
Short name T817
Test name
Test status
Simulation time 20625492248 ps
CPU time 1208.26 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 199968 kb
Host smart-f7a8d6e7-db87-4f8d-adac-996608e6d780
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2406001957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.2406001957
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.530723390
Short name T633
Test name
Test status
Simulation time 3972484501 ps
CPU time 38.87 seconds
Started Jul 29 07:12:55 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 199064 kb
Host smart-4b0dc424-c647-4b1d-b9dd-14a7a5eb1085
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530723390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.530723390
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.3257703658
Short name T839
Test name
Test status
Simulation time 103875656709 ps
CPU time 233 seconds
Started Jul 29 07:12:54 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 199860 kb
Host smart-97b7470c-e440-4c45-abe2-7d5a2dd8d53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257703658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.3257703658
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3261151556
Short name T552
Test name
Test status
Simulation time 6694723228 ps
CPU time 2.2 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:53 PM PDT 24
Peak memory 196152 kb
Host smart-b9b9c7a0-4ecd-47ab-a8d8-91d793dbae62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261151556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3261151556
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3456241176
Short name T1094
Test name
Test status
Simulation time 510352699 ps
CPU time 2.11 seconds
Started Jul 29 07:12:58 PM PDT 24
Finished Jul 29 07:13:01 PM PDT 24
Peak memory 198736 kb
Host smart-a557e850-732f-4fa6-b2e1-65ed5855ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456241176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3456241176
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.29210623
Short name T623
Test name
Test status
Simulation time 804297134978 ps
CPU time 119.47 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:14:49 PM PDT 24
Peak memory 208260 kb
Host smart-61403765-a882-4ed1-b1bf-e8f2acbb1a43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29210623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.29210623
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.3052971077
Short name T674
Test name
Test status
Simulation time 60452842320 ps
CPU time 816.24 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:26:32 PM PDT 24
Peak memory 216596 kb
Host smart-b8966d46-7820-44a5-b196-943e6d4f645c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052971077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.3052971077
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1881295390
Short name T1070
Test name
Test status
Simulation time 2990384718 ps
CPU time 1.98 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:12:58 PM PDT 24
Peak memory 198920 kb
Host smart-79f1b6cd-53d9-4d97-9f8f-c033657e8c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881295390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1881295390
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3840836191
Short name T805
Test name
Test status
Simulation time 70792931505 ps
CPU time 67.27 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:14:03 PM PDT 24
Peak memory 199992 kb
Host smart-cb717bf7-291a-403e-aa19-90f9ca332a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840836191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3840836191
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.4174826102
Short name T250
Test name
Test status
Simulation time 71434764638 ps
CPU time 33.78 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 199992 kb
Host smart-19b50b65-baf6-4b44-b528-fc9ac087ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174826102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.4174826102
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2882580937
Short name T949
Test name
Test status
Simulation time 115413374441 ps
CPU time 161.97 seconds
Started Jul 29 07:17:45 PM PDT 24
Finished Jul 29 07:20:27 PM PDT 24
Peak memory 199900 kb
Host smart-ed8cc58f-31ce-463d-8a67-6be24e7635f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882580937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2882580937
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.2074598465
Short name T198
Test name
Test status
Simulation time 98929261927 ps
CPU time 24.48 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:22 PM PDT 24
Peak memory 199928 kb
Host smart-f3a41c93-a3d7-4776-b09a-510049efafa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074598465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.2074598465
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2631733484
Short name T293
Test name
Test status
Simulation time 119766750320 ps
CPU time 166.78 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:20:44 PM PDT 24
Peak memory 199856 kb
Host smart-809cf224-0c2a-4e52-9322-0d775914ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631733484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2631733484
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2174841054
Short name T8
Test name
Test status
Simulation time 136793236511 ps
CPU time 27.86 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 199992 kb
Host smart-0496152d-9147-4d48-98cf-0f01bbd9ac8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174841054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2174841054
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.3797895221
Short name T338
Test name
Test status
Simulation time 34310907093 ps
CPU time 55.64 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:43 PM PDT 24
Peak memory 199908 kb
Host smart-cf890cb3-647b-4b0a-9c19-b70840b3f452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797895221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.3797895221
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4157767240
Short name T334
Test name
Test status
Simulation time 190394379285 ps
CPU time 241.27 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:21:59 PM PDT 24
Peak memory 199936 kb
Host smart-ea82365e-9121-47ff-a019-c1790c0d7bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157767240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4157767240
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.195648111
Short name T190
Test name
Test status
Simulation time 38957750331 ps
CPU time 24.22 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:21 PM PDT 24
Peak memory 199900 kb
Host smart-a5aa6815-5f7a-4240-b672-5976c7324f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195648111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.195648111
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2768904332
Short name T895
Test name
Test status
Simulation time 21320647 ps
CPU time 0.55 seconds
Started Jul 29 07:12:55 PM PDT 24
Finished Jul 29 07:12:56 PM PDT 24
Peak memory 195372 kb
Host smart-63bfc6ff-781c-48b7-a9cb-c813b2e5c799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768904332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2768904332
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.395932240
Short name T178
Test name
Test status
Simulation time 198991993247 ps
CPU time 71.56 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:14:12 PM PDT 24
Peak memory 199992 kb
Host smart-a2b54b17-d649-4882-b234-96c3f0f9d8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395932240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.395932240
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4204673835
Short name T368
Test name
Test status
Simulation time 71073139383 ps
CPU time 113.03 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:14:54 PM PDT 24
Peak memory 199940 kb
Host smart-32b0ce0a-d655-4604-9561-ae601da09d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204673835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4204673835
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_intr.2790090954
Short name T787
Test name
Test status
Simulation time 19888621403 ps
CPU time 6.16 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 198584 kb
Host smart-2afb4fa1-e6fc-42ce-bb6a-761cd062a1ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790090954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2790090954
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1614373034
Short name T999
Test name
Test status
Simulation time 94215097112 ps
CPU time 184.58 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:16:05 PM PDT 24
Peak memory 199984 kb
Host smart-5ef4a0e6-6bbe-41a4-ba65-4aede5668f6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1614373034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1614373034
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3673521566
Short name T745
Test name
Test status
Simulation time 10420927825 ps
CPU time 4.94 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:13:01 PM PDT 24
Peak memory 199644 kb
Host smart-1836966a-20c9-4075-9969-a18d97067870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673521566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3673521566
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.199872779
Short name T869
Test name
Test status
Simulation time 65259192901 ps
CPU time 66.69 seconds
Started Jul 29 07:12:58 PM PDT 24
Finished Jul 29 07:14:05 PM PDT 24
Peak memory 200152 kb
Host smart-2c9a2846-3c01-4617-87f3-a003be73d3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199872779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.199872779
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1888361248
Short name T573
Test name
Test status
Simulation time 22589850319 ps
CPU time 331.24 seconds
Started Jul 29 07:12:58 PM PDT 24
Finished Jul 29 07:18:29 PM PDT 24
Peak memory 200032 kb
Host smart-a01fcfdf-5a48-439f-bf00-c342b95f77e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888361248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1888361248
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3010324127
Short name T699
Test name
Test status
Simulation time 3472783780 ps
CPU time 12.98 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:13:14 PM PDT 24
Peak memory 197880 kb
Host smart-f727a285-620e-4cd7-aba3-e225fd164426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010324127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3010324127
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.3859564819
Short name T851
Test name
Test status
Simulation time 63087728402 ps
CPU time 9.25 seconds
Started Jul 29 07:12:56 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 199912 kb
Host smart-7157d67a-2d79-44a8-aa18-b839c347d34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859564819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3859564819
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2567307076
Short name T466
Test name
Test status
Simulation time 1901079855 ps
CPU time 3.15 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 195400 kb
Host smart-28238c23-b3b2-4884-affa-8e10b59fc632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567307076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2567307076
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.177665146
Short name T729
Test name
Test status
Simulation time 430914036 ps
CPU time 1.32 seconds
Started Jul 29 07:12:58 PM PDT 24
Finished Jul 29 07:13:00 PM PDT 24
Peak memory 199888 kb
Host smart-8e91fdd0-73cf-4d90-951f-d7e3d116d81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177665146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.177665146
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.3345607528
Short name T70
Test name
Test status
Simulation time 222081488148 ps
CPU time 451.91 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:20:31 PM PDT 24
Peak memory 216384 kb
Host smart-8e5299a2-15f7-4827-9af8-03f0bd6b1eb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345607528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.3345607528
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2713038395
Short name T963
Test name
Test status
Simulation time 1499323054 ps
CPU time 1.67 seconds
Started Jul 29 07:12:55 PM PDT 24
Finished Jul 29 07:12:57 PM PDT 24
Peak memory 198332 kb
Host smart-179b1ddc-2a77-4bf2-93c1-fed8eae2a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713038395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2713038395
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3379852784
Short name T615
Test name
Test status
Simulation time 309292819447 ps
CPU time 69.81 seconds
Started Jul 29 07:12:51 PM PDT 24
Finished Jul 29 07:14:01 PM PDT 24
Peak memory 199980 kb
Host smart-d2710606-4e2f-47f6-b3f9-6413217232d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379852784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3379852784
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1411299721
Short name T967
Test name
Test status
Simulation time 99571999820 ps
CPU time 17.5 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:05 PM PDT 24
Peak memory 199768 kb
Host smart-a346c8ee-b9a6-41a4-9dda-7de64d0da67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411299721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1411299721
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1416863335
Short name T1016
Test name
Test status
Simulation time 37158876643 ps
CPU time 13.44 seconds
Started Jul 29 07:17:46 PM PDT 24
Finished Jul 29 07:18:00 PM PDT 24
Peak memory 199944 kb
Host smart-43cbd3b2-b5bb-4b66-9db1-47014c8bb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416863335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1416863335
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1123907082
Short name T868
Test name
Test status
Simulation time 57516557140 ps
CPU time 90.54 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:19:21 PM PDT 24
Peak memory 199880 kb
Host smart-8e8866bf-52c8-4986-a2f0-2a52dcb23816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123907082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1123907082
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2631894457
Short name T846
Test name
Test status
Simulation time 200280272390 ps
CPU time 41.91 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:18:29 PM PDT 24
Peak memory 199968 kb
Host smart-bc7bd415-dc5f-4352-a8cd-6ab82726eb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631894457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2631894457
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1053224778
Short name T274
Test name
Test status
Simulation time 39950967083 ps
CPU time 32.39 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:30 PM PDT 24
Peak memory 199932 kb
Host smart-65adc2e8-db96-4a0b-807b-0c42ca0737f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053224778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1053224778
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.916042777
Short name T1160
Test name
Test status
Simulation time 10337538334 ps
CPU time 16.92 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:15 PM PDT 24
Peak memory 199848 kb
Host smart-ebb84d18-85c9-4395-bf84-b99f250c8420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916042777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.916042777
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1986837523
Short name T252
Test name
Test status
Simulation time 14637726889 ps
CPU time 20.97 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:17 PM PDT 24
Peak memory 199704 kb
Host smart-cfc12ae5-695a-4198-9cdf-e3af14c69297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986837523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1986837523
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1329142229
Short name T558
Test name
Test status
Simulation time 88441402853 ps
CPU time 16.91 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:14 PM PDT 24
Peak memory 199852 kb
Host smart-f936e1bc-7586-4fad-a6c0-df89a5ee197e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329142229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1329142229
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2214515008
Short name T680
Test name
Test status
Simulation time 22869054165 ps
CPU time 9.94 seconds
Started Jul 29 07:17:47 PM PDT 24
Finished Jul 29 07:17:57 PM PDT 24
Peak memory 199880 kb
Host smart-9a893597-71b3-4df0-ad33-2988dd30dab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214515008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2214515008
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.2963130336
Short name T569
Test name
Test status
Simulation time 68953863652 ps
CPU time 98.95 seconds
Started Jul 29 07:12:52 PM PDT 24
Finished Jul 29 07:14:31 PM PDT 24
Peak memory 200096 kb
Host smart-929218b1-593e-426b-b80e-b67193d6a1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963130336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.2963130336
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1497627141
Short name T48
Test name
Test status
Simulation time 100163856850 ps
CPU time 94.24 seconds
Started Jul 29 07:13:01 PM PDT 24
Finished Jul 29 07:14:35 PM PDT 24
Peak memory 199868 kb
Host smart-2d3d28d4-16a7-495e-b8ad-f6b28a8a4e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497627141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1497627141
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.281925633
Short name T659
Test name
Test status
Simulation time 160394401086 ps
CPU time 66.07 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 199980 kb
Host smart-aceb8324-ab84-470d-b132-bb6d18cb58b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281925633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.281925633
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1865039450
Short name T277
Test name
Test status
Simulation time 9261553000 ps
CPU time 18.46 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:13:18 PM PDT 24
Peak memory 199980 kb
Host smart-4706d863-2978-4368-8194-74b79313dc74
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865039450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1865039450
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.2644468490
Short name T1025
Test name
Test status
Simulation time 143699535219 ps
CPU time 207.25 seconds
Started Jul 29 07:13:04 PM PDT 24
Finished Jul 29 07:16:32 PM PDT 24
Peak memory 199968 kb
Host smart-df23fead-18ae-4fbe-bd31-6cdcc88ae1f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644468490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2644468490
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.2376377147
Short name T465
Test name
Test status
Simulation time 1617515544 ps
CPU time 1.57 seconds
Started Jul 29 07:13:03 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 198236 kb
Host smart-de1f523f-318d-421b-922b-1e49eac95d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376377147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.2376377147
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.2057386827
Short name T509
Test name
Test status
Simulation time 106911091720 ps
CPU time 60.2 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:14:02 PM PDT 24
Peak memory 199932 kb
Host smart-9d35a0dd-d13e-4b01-9703-4fb395b8cef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057386827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2057386827
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.3933396734
Short name T855
Test name
Test status
Simulation time 6595016905 ps
CPU time 300.33 seconds
Started Jul 29 07:13:01 PM PDT 24
Finished Jul 29 07:18:01 PM PDT 24
Peak memory 200052 kb
Host smart-8f1cc983-e293-444e-9199-6c5cf789cb48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3933396734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.3933396734
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1604700697
Short name T816
Test name
Test status
Simulation time 3415812412 ps
CPU time 14.38 seconds
Started Jul 29 07:12:55 PM PDT 24
Finished Jul 29 07:13:10 PM PDT 24
Peak memory 197816 kb
Host smart-4ba0fae8-ca92-4905-b8bb-e426ab2aa5e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1604700697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1604700697
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2042841928
Short name T137
Test name
Test status
Simulation time 156035862825 ps
CPU time 76.45 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:14:15 PM PDT 24
Peak memory 199968 kb
Host smart-f5c02ec6-4e06-4d0c-abed-0dadf7db884c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042841928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2042841928
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2638898776
Short name T1052
Test name
Test status
Simulation time 3743669554 ps
CPU time 2.02 seconds
Started Jul 29 07:12:59 PM PDT 24
Finished Jul 29 07:13:02 PM PDT 24
Peak memory 195808 kb
Host smart-d2a687df-60f5-4a5b-a46c-c0b24aaaa5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638898776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2638898776
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.3657578027
Short name T700
Test name
Test status
Simulation time 5576308347 ps
CPU time 8.25 seconds
Started Jul 29 07:12:57 PM PDT 24
Finished Jul 29 07:13:06 PM PDT 24
Peak memory 199872 kb
Host smart-0f6fe13d-448d-4732-b736-85274fe8c94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657578027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.3657578027
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.570980096
Short name T1164
Test name
Test status
Simulation time 133949832604 ps
CPU time 207.54 seconds
Started Jul 29 07:13:03 PM PDT 24
Finished Jul 29 07:16:31 PM PDT 24
Peak memory 199904 kb
Host smart-870915e7-ff63-4daf-86a5-9d1e9e96ddfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570980096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.570980096
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.3530530895
Short name T79
Test name
Test status
Simulation time 261199374129 ps
CPU time 1186.78 seconds
Started Jul 29 07:13:01 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 225752 kb
Host smart-eba12bab-a3d4-4071-8c23-8da26a73bada
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530530895 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.3530530895
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.490093331
Short name T1018
Test name
Test status
Simulation time 2168187888 ps
CPU time 1.88 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:04 PM PDT 24
Peak memory 198464 kb
Host smart-ec3147aa-ca58-4be0-b946-e2afe102443a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490093331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.490093331
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.685944581
Short name T678
Test name
Test status
Simulation time 19971251177 ps
CPU time 18.66 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:21 PM PDT 24
Peak memory 199864 kb
Host smart-f16220c1-fdcf-4086-a7db-ed23364835de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685944581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.685944581
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3764760530
Short name T1040
Test name
Test status
Simulation time 53187789114 ps
CPU time 49 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:47 PM PDT 24
Peak memory 199940 kb
Host smart-208e5caa-731a-4137-bb7b-368f970be4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764760530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3764760530
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.1466717
Short name T655
Test name
Test status
Simulation time 27121855139 ps
CPU time 9.84 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:06 PM PDT 24
Peak memory 199888 kb
Host smart-d055d9d1-c7b2-42d3-81a1-bb6778b0ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.1466717
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2240864151
Short name T191
Test name
Test status
Simulation time 47471554888 ps
CPU time 88.04 seconds
Started Jul 29 07:17:50 PM PDT 24
Finished Jul 29 07:19:18 PM PDT 24
Peak memory 199956 kb
Host smart-4e28f951-cc50-4c39-b247-c19c89616817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240864151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2240864151
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.134729156
Short name T711
Test name
Test status
Simulation time 51814199136 ps
CPU time 24.09 seconds
Started Jul 29 07:17:50 PM PDT 24
Finished Jul 29 07:18:14 PM PDT 24
Peak memory 199884 kb
Host smart-b3257eb0-7a24-4033-bb74-030687d13551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134729156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.134729156
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2181713921
Short name T231
Test name
Test status
Simulation time 34625849168 ps
CPU time 68.99 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:19:06 PM PDT 24
Peak memory 199932 kb
Host smart-e6adc699-17ec-4613-976e-f38b3f5de227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181713921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2181713921
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1592824561
Short name T397
Test name
Test status
Simulation time 285264092248 ps
CPU time 43.59 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:42 PM PDT 24
Peak memory 199904 kb
Host smart-d7aec7ab-3d4b-464f-a566-e2e53e2716a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592824561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1592824561
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.1957723885
Short name T228
Test name
Test status
Simulation time 17581837059 ps
CPU time 29.12 seconds
Started Jul 29 07:17:49 PM PDT 24
Finished Jul 29 07:18:18 PM PDT 24
Peak memory 199952 kb
Host smart-be97287f-8a2b-4747-b77e-028769cec4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957723885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1957723885
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3439845416
Short name T278
Test name
Test status
Simulation time 82051362212 ps
CPU time 62.39 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:58 PM PDT 24
Peak memory 199992 kb
Host smart-d2c52721-3ac1-4f49-98d8-fe2dc4221b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439845416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3439845416
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.3760369665
Short name T882
Test name
Test status
Simulation time 12164967 ps
CPU time 0.58 seconds
Started Jul 29 07:13:07 PM PDT 24
Finished Jul 29 07:13:07 PM PDT 24
Peak memory 195348 kb
Host smart-d38aab83-0631-42bf-8a38-8441a21e0f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760369665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3760369665
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1163400328
Short name T292
Test name
Test status
Simulation time 14154675211 ps
CPU time 20.24 seconds
Started Jul 29 07:13:04 PM PDT 24
Finished Jul 29 07:13:24 PM PDT 24
Peak memory 199936 kb
Host smart-fb2d3cad-db7d-4f54-b627-683916397c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163400328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1163400328
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.549135532
Short name T703
Test name
Test status
Simulation time 69449946270 ps
CPU time 20.47 seconds
Started Jul 29 07:13:00 PM PDT 24
Finished Jul 29 07:13:21 PM PDT 24
Peak memory 199904 kb
Host smart-27dafffd-a144-41cf-a3f2-956312b53361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549135532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.549135532
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.913272009
Short name T33
Test name
Test status
Simulation time 17442261149 ps
CPU time 33.9 seconds
Started Jul 29 07:13:08 PM PDT 24
Finished Jul 29 07:13:42 PM PDT 24
Peak memory 199972 kb
Host smart-4db8d908-ee3c-4a45-9513-24da67b0c663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913272009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.913272009
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2343850762
Short name T555
Test name
Test status
Simulation time 15842400089 ps
CPU time 8.61 seconds
Started Jul 29 07:13:08 PM PDT 24
Finished Jul 29 07:13:17 PM PDT 24
Peak memory 199976 kb
Host smart-bc00e8cc-51d8-4419-a625-83808f5258bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343850762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2343850762
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.3312732780
Short name T358
Test name
Test status
Simulation time 103142935278 ps
CPU time 521.65 seconds
Started Jul 29 07:13:01 PM PDT 24
Finished Jul 29 07:21:42 PM PDT 24
Peak memory 199956 kb
Host smart-4c395c79-04e0-4866-b7e4-93857c87eda6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3312732780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.3312732780
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2335574195
Short name T1
Test name
Test status
Simulation time 5961287208 ps
CPU time 2.03 seconds
Started Jul 29 07:13:06 PM PDT 24
Finished Jul 29 07:13:08 PM PDT 24
Peak memory 195872 kb
Host smart-d671be10-c07b-4578-8761-3a44cf4f3aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335574195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2335574195
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.3703571437
Short name T521
Test name
Test status
Simulation time 55709955242 ps
CPU time 92.94 seconds
Started Jul 29 07:13:04 PM PDT 24
Finished Jul 29 07:14:37 PM PDT 24
Peak memory 198912 kb
Host smart-8ff371ec-a76d-4eff-bc46-3d355d62c799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703571437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.3703571437
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.427878985
Short name T918
Test name
Test status
Simulation time 16724516391 ps
CPU time 952.63 seconds
Started Jul 29 07:13:07 PM PDT 24
Finished Jul 29 07:28:59 PM PDT 24
Peak memory 199960 kb
Host smart-fdd26ff2-325b-48b1-8bef-bb2e5f7493e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427878985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.427878985
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.808900864
Short name T351
Test name
Test status
Simulation time 3147165135 ps
CPU time 12.89 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 197892 kb
Host smart-d5ec51fe-2543-4a35-a985-75415df5a7d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=808900864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.808900864
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.1153017074
Short name T266
Test name
Test status
Simulation time 105640854735 ps
CPU time 37.04 seconds
Started Jul 29 07:13:07 PM PDT 24
Finished Jul 29 07:13:44 PM PDT 24
Peak memory 199756 kb
Host smart-78c93521-6c96-4100-9499-969ea466b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153017074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.1153017074
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.2896980105
Short name T367
Test name
Test status
Simulation time 32066442090 ps
CPU time 24.67 seconds
Started Jul 29 07:13:06 PM PDT 24
Finished Jul 29 07:13:31 PM PDT 24
Peak memory 195832 kb
Host smart-8367efff-794f-44fc-ad75-d77737fbe0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896980105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.2896980105
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.137606601
Short name T649
Test name
Test status
Simulation time 895223280 ps
CPU time 2.27 seconds
Started Jul 29 07:13:08 PM PDT 24
Finished Jul 29 07:13:11 PM PDT 24
Peak memory 198872 kb
Host smart-311e95bc-46a7-46fc-8654-394abec436e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137606601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.137606601
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.310900753
Short name T15
Test name
Test status
Simulation time 214155977383 ps
CPU time 85.92 seconds
Started Jul 29 07:13:01 PM PDT 24
Finished Jul 29 07:14:27 PM PDT 24
Peak memory 199636 kb
Host smart-a662c99c-9349-4da0-80af-e92cd6265705
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310900753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.310900753
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.464065764
Short name T107
Test name
Test status
Simulation time 70136290271 ps
CPU time 939.46 seconds
Started Jul 29 07:13:03 PM PDT 24
Finished Jul 29 07:28:42 PM PDT 24
Peak memory 224832 kb
Host smart-39940d51-3562-4a5f-84cf-cf45b71d2e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464065764 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.464065764
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1446132690
Short name T826
Test name
Test status
Simulation time 1921301864 ps
CPU time 2.16 seconds
Started Jul 29 07:13:08 PM PDT 24
Finished Jul 29 07:13:10 PM PDT 24
Peak memory 199900 kb
Host smart-40466431-3b3b-40c9-8c70-65985ca27f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446132690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1446132690
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.3908162363
Short name T828
Test name
Test status
Simulation time 19345473589 ps
CPU time 7.82 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:10 PM PDT 24
Peak memory 199832 kb
Host smart-56e30845-6b00-4834-8dc9-72b92258e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908162363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.3908162363
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.3518536934
Short name T1113
Test name
Test status
Simulation time 173015734040 ps
CPU time 35.31 seconds
Started Jul 29 07:17:49 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 199972 kb
Host smart-e94ffbad-7946-46df-98d8-da8cfd3be138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518536934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.3518536934
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1966561947
Short name T227
Test name
Test status
Simulation time 103028457689 ps
CPU time 42.77 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:40 PM PDT 24
Peak memory 199920 kb
Host smart-49b59a2c-7e75-4940-852f-92bf50c655cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966561947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1966561947
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2824159115
Short name T381
Test name
Test status
Simulation time 49363246360 ps
CPU time 42.47 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:38 PM PDT 24
Peak memory 199920 kb
Host smart-2f57169a-8181-498b-bfef-decde333cda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824159115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2824159115
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2895079542
Short name T141
Test name
Test status
Simulation time 38741409678 ps
CPU time 31.32 seconds
Started Jul 29 07:17:56 PM PDT 24
Finished Jul 29 07:18:27 PM PDT 24
Peak memory 199860 kb
Host smart-62f4932c-ae3b-413e-a7fd-9d22f8cd6822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895079542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2895079542
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1527268588
Short name T829
Test name
Test status
Simulation time 40437069731 ps
CPU time 11.82 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:09 PM PDT 24
Peak memory 199848 kb
Host smart-b2b68028-bec1-4516-88d1-b3d003696cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527268588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1527268588
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.1911844478
Short name T748
Test name
Test status
Simulation time 18541334234 ps
CPU time 12.86 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:10 PM PDT 24
Peak memory 199916 kb
Host smart-f518ff9f-2d13-458a-83b2-f0693b4eefcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911844478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.1911844478
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.2925063395
Short name T620
Test name
Test status
Simulation time 17369062217 ps
CPU time 24.58 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:22 PM PDT 24
Peak memory 199928 kb
Host smart-579d3aa4-35ce-4031-9af6-812c98935f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925063395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.2925063395
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4292891334
Short name T631
Test name
Test status
Simulation time 82832295580 ps
CPU time 133.25 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:20:04 PM PDT 24
Peak memory 199884 kb
Host smart-0946aa3d-9977-4f5b-8194-d5fa6c9f4dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292891334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4292891334
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3806375927
Short name T268
Test name
Test status
Simulation time 46418559012 ps
CPU time 102.93 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:19:40 PM PDT 24
Peak memory 199924 kb
Host smart-35311406-c16e-4aa4-896b-a66ecf685e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806375927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3806375927
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.3747071336
Short name T406
Test name
Test status
Simulation time 36510672 ps
CPU time 0.53 seconds
Started Jul 29 07:13:14 PM PDT 24
Finished Jul 29 07:13:14 PM PDT 24
Peak memory 195356 kb
Host smart-ebf77f4e-9562-4c56-80f5-6bf83892dede
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747071336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.3747071336
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.3423140622
Short name T934
Test name
Test status
Simulation time 122939617197 ps
CPU time 78.41 seconds
Started Jul 29 07:13:07 PM PDT 24
Finished Jul 29 07:14:25 PM PDT 24
Peak memory 199896 kb
Host smart-af3e56dc-c07d-4dc3-a934-3386f56d3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423140622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.3423140622
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2874716263
Short name T1022
Test name
Test status
Simulation time 37053604989 ps
CPU time 33.23 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:35 PM PDT 24
Peak memory 199328 kb
Host smart-6cea97a4-28eb-4b44-824a-6db6f4f9566e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874716263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2874716263
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.1380824741
Short name T384
Test name
Test status
Simulation time 27602212719 ps
CPU time 46.98 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:14:00 PM PDT 24
Peak memory 199904 kb
Host smart-84f1c8d1-8296-48dd-a500-78555426d4cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380824741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1380824741
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3938767803
Short name T410
Test name
Test status
Simulation time 13360874638 ps
CPU time 4.15 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:17 PM PDT 24
Peak memory 196528 kb
Host smart-b67c614c-7c97-4e75-ae64-2ad91765eb3e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938767803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3938767803
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.4090318728
Short name T610
Test name
Test status
Simulation time 75390539702 ps
CPU time 544.32 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:22:17 PM PDT 24
Peak memory 199948 kb
Host smart-2424b80b-a364-4480-ad0c-feb1a2615975
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4090318728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.4090318728
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.775619468
Short name T1172
Test name
Test status
Simulation time 6232067595 ps
CPU time 13.38 seconds
Started Jul 29 07:13:11 PM PDT 24
Finished Jul 29 07:13:25 PM PDT 24
Peak memory 199384 kb
Host smart-8e1267d1-9505-43b1-b659-6f4b223ac195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775619468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.775619468
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3367240179
Short name T730
Test name
Test status
Simulation time 164825619393 ps
CPU time 38.89 seconds
Started Jul 29 07:13:15 PM PDT 24
Finished Jul 29 07:13:54 PM PDT 24
Peak memory 208304 kb
Host smart-5611c126-17f6-4d81-8f80-009d256d9507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367240179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3367240179
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2057832226
Short name T1110
Test name
Test status
Simulation time 18609387459 ps
CPU time 542.85 seconds
Started Jul 29 07:13:14 PM PDT 24
Finished Jul 29 07:22:17 PM PDT 24
Peak memory 200108 kb
Host smart-cccf4342-d461-4bf1-a28f-36f15af957f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2057832226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2057832226
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.3725313471
Short name T646
Test name
Test status
Simulation time 2109390784 ps
CPU time 9.89 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:22 PM PDT 24
Peak memory 198584 kb
Host smart-d4711b04-36a9-4de2-99ad-025434daa368
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725313471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.3725313471
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.824543944
Short name T807
Test name
Test status
Simulation time 34798619968 ps
CPU time 61.46 seconds
Started Jul 29 07:13:18 PM PDT 24
Finished Jul 29 07:14:20 PM PDT 24
Peak memory 199988 kb
Host smart-6b711b54-9ce3-4a5f-a192-6d2774d784a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824543944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.824543944
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2522767206
Short name T482
Test name
Test status
Simulation time 1909451839 ps
CPU time 2.45 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 195460 kb
Host smart-ed6b848b-7260-4a79-9f91-e484cbae5479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522767206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2522767206
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.1991345201
Short name T643
Test name
Test status
Simulation time 285509806 ps
CPU time 1.92 seconds
Started Jul 29 07:13:06 PM PDT 24
Finished Jul 29 07:13:08 PM PDT 24
Peak memory 199828 kb
Host smart-00e1ad0c-d10b-4201-bc1c-e47186e94642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991345201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1991345201
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.2857109565
Short name T619
Test name
Test status
Simulation time 75131068172 ps
CPU time 123.99 seconds
Started Jul 29 07:13:10 PM PDT 24
Finished Jul 29 07:15:14 PM PDT 24
Peak memory 199932 kb
Host smart-5cd31a9d-fd33-42c3-8fd2-889da5388694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857109565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2857109565
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1675759858
Short name T1049
Test name
Test status
Simulation time 51400437039 ps
CPU time 635.73 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:23:48 PM PDT 24
Peak memory 216460 kb
Host smart-b3a5f961-c61b-4dbe-9a71-c0e9f9aa4fcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675759858 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1675759858
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2043415303
Short name T374
Test name
Test status
Simulation time 1497444628 ps
CPU time 2.15 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 199672 kb
Host smart-85d4531c-2de9-40e5-8481-d13ad95f2391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043415303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2043415303
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.26943222
Short name T59
Test name
Test status
Simulation time 54064985372 ps
CPU time 24.36 seconds
Started Jul 29 07:13:02 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 199856 kb
Host smart-a090a5b3-813a-4963-8fb5-11d9a7521f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26943222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.26943222
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1485789371
Short name T1163
Test name
Test status
Simulation time 68742926080 ps
CPU time 32.58 seconds
Started Jul 29 07:17:52 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 199968 kb
Host smart-cf9f0719-0ecd-4d19-90c2-3cd642cca41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485789371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1485789371
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.862705332
Short name T526
Test name
Test status
Simulation time 11464293491 ps
CPU time 5.41 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:17:56 PM PDT 24
Peak memory 199064 kb
Host smart-5421d861-f39d-4cf8-9186-e6ccd977926e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862705332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.862705332
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.3656200091
Short name T168
Test name
Test status
Simulation time 28045605052 ps
CPU time 13.86 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:18:05 PM PDT 24
Peak memory 199968 kb
Host smart-f92fd306-66ea-400e-b75b-84b7e1a74362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656200091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.3656200091
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.1500782269
Short name T625
Test name
Test status
Simulation time 131613111325 ps
CPU time 122.29 seconds
Started Jul 29 07:17:50 PM PDT 24
Finished Jul 29 07:19:52 PM PDT 24
Peak memory 199992 kb
Host smart-e2bd0dbe-b167-4d4c-95bd-e8336b505b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500782269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.1500782269
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.1205660790
Short name T46
Test name
Test status
Simulation time 93231351478 ps
CPU time 34.17 seconds
Started Jul 29 07:17:51 PM PDT 24
Finished Jul 29 07:18:25 PM PDT 24
Peak memory 199556 kb
Host smart-7a8dbffe-a6be-4a66-974e-7e495cd4fb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205660790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.1205660790
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.314704706
Short name T163
Test name
Test status
Simulation time 119476372588 ps
CPU time 46.27 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:44 PM PDT 24
Peak memory 199952 kb
Host smart-1d591025-03d1-4618-8158-6aca21cfcf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314704706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.314704706
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.1438351549
Short name T133
Test name
Test status
Simulation time 127709271901 ps
CPU time 178.92 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:20:56 PM PDT 24
Peak memory 199976 kb
Host smart-021af717-eb62-4b56-96e9-d8d88df6df0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438351549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.1438351549
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1378395961
Short name T1053
Test name
Test status
Simulation time 14867220557 ps
CPU time 21.57 seconds
Started Jul 29 07:17:59 PM PDT 24
Finished Jul 29 07:18:20 PM PDT 24
Peak memory 199536 kb
Host smart-6f67d1dd-70cb-4b98-972a-f745c81ba16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378395961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1378395961
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.248561199
Short name T217
Test name
Test status
Simulation time 37411904754 ps
CPU time 21.59 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:19 PM PDT 24
Peak memory 199788 kb
Host smart-d50ac5b6-4a66-475c-904f-98fa62b31d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248561199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.248561199
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2365506605
Short name T763
Test name
Test status
Simulation time 100788780280 ps
CPU time 103.88 seconds
Started Jul 29 07:18:02 PM PDT 24
Finished Jul 29 07:19:46 PM PDT 24
Peak memory 199916 kb
Host smart-fcb94cca-ae38-45d3-98ae-851b35ff1ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365506605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2365506605
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.2412695442
Short name T449
Test name
Test status
Simulation time 11234046 ps
CPU time 0.53 seconds
Started Jul 29 07:13:15 PM PDT 24
Finished Jul 29 07:13:16 PM PDT 24
Peak memory 195408 kb
Host smart-f3a0f0ed-0a70-4f49-bd8f-3225d00c2b9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412695442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.2412695442
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.4069968361
Short name T765
Test name
Test status
Simulation time 196558057044 ps
CPU time 88.53 seconds
Started Jul 29 07:13:18 PM PDT 24
Finished Jul 29 07:14:47 PM PDT 24
Peak memory 199968 kb
Host smart-bdead993-3645-453a-b29d-b5c88f1b564a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069968361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.4069968361
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3757703940
Short name T172
Test name
Test status
Simulation time 41959737736 ps
CPU time 91.64 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:14:44 PM PDT 24
Peak memory 199972 kb
Host smart-004e54e5-406e-44bb-8029-49dff7f6e410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757703940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3757703940
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.146665683
Short name T291
Test name
Test status
Simulation time 14174931592 ps
CPU time 15.73 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:28 PM PDT 24
Peak memory 199812 kb
Host smart-619e3904-86b0-4769-bc71-870b61260b6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146665683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.146665683
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2552152476
Short name T966
Test name
Test status
Simulation time 91346779365 ps
CPU time 532.87 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:22:06 PM PDT 24
Peak memory 199912 kb
Host smart-5eb08962-778d-4161-9b1a-723578f1bcbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552152476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2552152476
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2965630451
Short name T427
Test name
Test status
Simulation time 691355639 ps
CPU time 0.96 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:13 PM PDT 24
Peak memory 195996 kb
Host smart-b6b5759a-f0d6-4e81-8151-83b0a65ca8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965630451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2965630451
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3603891946
Short name T928
Test name
Test status
Simulation time 116009181387 ps
CPU time 46.34 seconds
Started Jul 29 07:13:14 PM PDT 24
Finished Jul 29 07:14:01 PM PDT 24
Peak memory 198844 kb
Host smart-b449e3c5-22b6-4c6c-ad2a-310eec8fc1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603891946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3603891946
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.4085078967
Short name T685
Test name
Test status
Simulation time 14777081585 ps
CPU time 116.27 seconds
Started Jul 29 07:13:14 PM PDT 24
Finished Jul 29 07:15:10 PM PDT 24
Peak memory 199916 kb
Host smart-ce28f463-386f-4a3c-bc60-f4bdc53fbb19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4085078967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4085078967
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.401119164
Short name T462
Test name
Test status
Simulation time 1666672300 ps
CPU time 8.55 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:21 PM PDT 24
Peak memory 198212 kb
Host smart-6e4feab7-926a-4691-9da4-b87b6b06a741
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=401119164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.401119164
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3547238260
Short name T1109
Test name
Test status
Simulation time 117256700345 ps
CPU time 82.82 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:14:35 PM PDT 24
Peak memory 199868 kb
Host smart-9d408ed4-453b-4297-86fc-1ea362fb51a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547238260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3547238260
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3102800512
Short name T289
Test name
Test status
Simulation time 4943063332 ps
CPU time 1.94 seconds
Started Jul 29 07:13:18 PM PDT 24
Finished Jul 29 07:13:20 PM PDT 24
Peak memory 196140 kb
Host smart-fcab9de1-57f8-4bd8-a77d-272f6a5e22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102800512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3102800512
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3334705378
Short name T662
Test name
Test status
Simulation time 5547356858 ps
CPU time 9.96 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:22 PM PDT 24
Peak memory 199976 kb
Host smart-7b4e32d3-3394-4d68-b1b4-099bc56d475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334705378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3334705378
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2120012557
Short name T1020
Test name
Test status
Simulation time 519028379128 ps
CPU time 806.52 seconds
Started Jul 29 07:13:15 PM PDT 24
Finished Jul 29 07:26:42 PM PDT 24
Peak memory 200024 kb
Host smart-37af0a97-9f18-4a28-a6d5-080e51d151aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120012557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2120012557
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1551835494
Short name T996
Test name
Test status
Simulation time 55543093278 ps
CPU time 553.54 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:22:27 PM PDT 24
Peak memory 216412 kb
Host smart-a5228254-fe26-46e3-b80c-172745e7d7c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551835494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1551835494
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.1907018751
Short name T1092
Test name
Test status
Simulation time 779521848 ps
CPU time 1.49 seconds
Started Jul 29 07:13:11 PM PDT 24
Finished Jul 29 07:13:13 PM PDT 24
Peak memory 197880 kb
Host smart-f1a93b0c-f616-4319-82ac-5912e825dc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907018751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.1907018751
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.957592198
Short name T575
Test name
Test status
Simulation time 81535337166 ps
CPU time 68.74 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:14:21 PM PDT 24
Peak memory 199968 kb
Host smart-ae51d3c4-5cf9-4fad-8aba-e91401736c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957592198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.957592198
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2574477365
Short name T791
Test name
Test status
Simulation time 81530834939 ps
CPU time 48.26 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:47 PM PDT 24
Peak memory 199936 kb
Host smart-6eb0288b-9f60-4e64-a3ab-a834853bb1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574477365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2574477365
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.603843048
Short name T1126
Test name
Test status
Simulation time 150872998803 ps
CPU time 28.53 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:18:26 PM PDT 24
Peak memory 199924 kb
Host smart-4c0f388c-9f99-46f0-b89e-69410846f663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603843048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.603843048
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1264206037
Short name T859
Test name
Test status
Simulation time 121254407903 ps
CPU time 178.41 seconds
Started Jul 29 07:17:59 PM PDT 24
Finished Jul 29 07:20:58 PM PDT 24
Peak memory 199980 kb
Host smart-5a75f54c-bf0e-4bb2-8053-8b722917dbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264206037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1264206037
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1341179841
Short name T1085
Test name
Test status
Simulation time 111691858933 ps
CPU time 47.99 seconds
Started Jul 29 07:18:02 PM PDT 24
Finished Jul 29 07:18:51 PM PDT 24
Peak memory 199968 kb
Host smart-a276958a-9c50-4df8-95c6-e2e001fcb0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341179841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1341179841
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3720760267
Short name T875
Test name
Test status
Simulation time 9455703935 ps
CPU time 18.4 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:17 PM PDT 24
Peak memory 199960 kb
Host smart-f0c8a16d-df3f-419e-b444-1a96fda387c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720760267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3720760267
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3845542683
Short name T214
Test name
Test status
Simulation time 75827072275 ps
CPU time 61.22 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:19:00 PM PDT 24
Peak memory 199908 kb
Host smart-aac86cee-b742-4e02-9985-a8bc7ea73ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845542683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3845542683
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3850262062
Short name T339
Test name
Test status
Simulation time 24005134048 ps
CPU time 10.49 seconds
Started Jul 29 07:18:00 PM PDT 24
Finished Jul 29 07:18:11 PM PDT 24
Peak memory 199904 kb
Host smart-64e98487-d551-4160-8223-4f1032ec86cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850262062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3850262062
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4225784668
Short name T534
Test name
Test status
Simulation time 203976259015 ps
CPU time 65.15 seconds
Started Jul 29 07:17:57 PM PDT 24
Finished Jul 29 07:19:03 PM PDT 24
Peak memory 199908 kb
Host smart-6c7d95db-42cc-4cd2-b2cd-4132d21569d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225784668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4225784668
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.438866165
Short name T63
Test name
Test status
Simulation time 15471409202 ps
CPU time 23.05 seconds
Started Jul 29 07:17:59 PM PDT 24
Finished Jul 29 07:18:23 PM PDT 24
Peak memory 199864 kb
Host smart-d4bbcff9-a683-48d3-86ea-1d2f8a853316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438866165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.438866165
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.2784969081
Short name T419
Test name
Test status
Simulation time 14098503 ps
CPU time 0.61 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 194596 kb
Host smart-9bde95d5-b48c-4a46-9b21-78b6156b3492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784969081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.2784969081
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3936398190
Short name T771
Test name
Test status
Simulation time 30215886795 ps
CPU time 16.18 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:12:44 PM PDT 24
Peak memory 199920 kb
Host smart-b86bf4a3-a24d-4033-b6b4-75fb481e14ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936398190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3936398190
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.394254590
Short name T175
Test name
Test status
Simulation time 81178493312 ps
CPU time 32.05 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:56 PM PDT 24
Peak memory 199836 kb
Host smart-c79a5e6d-9653-4e61-81b9-ba47c28b6b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394254590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.394254590
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_intr.1363712891
Short name T308
Test name
Test status
Simulation time 46440338863 ps
CPU time 77.23 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 199880 kb
Host smart-97881fd8-cbb9-4252-9574-c3fe052684d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363712891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.1363712891
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.399866951
Short name T313
Test name
Test status
Simulation time 133973797414 ps
CPU time 420.85 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:19:28 PM PDT 24
Peak memory 200080 kb
Host smart-92fad4d5-f2e4-4a6a-a65c-3d7322d5274b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=399866951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.399866951
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.2595392043
Short name T349
Test name
Test status
Simulation time 7641685956 ps
CPU time 6.96 seconds
Started Jul 29 07:12:22 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 199928 kb
Host smart-db262693-6a8a-4d3e-b6d9-8b6df453ea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595392043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.2595392043
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1030900584
Short name T473
Test name
Test status
Simulation time 323753103709 ps
CPU time 65.79 seconds
Started Jul 29 07:12:29 PM PDT 24
Finished Jul 29 07:13:35 PM PDT 24
Peak memory 208216 kb
Host smart-b205db35-ff4c-4986-b50b-ebf7f95a07bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030900584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1030900584
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.755254029
Short name T637
Test name
Test status
Simulation time 21699463138 ps
CPU time 273.11 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:16:58 PM PDT 24
Peak memory 199976 kb
Host smart-798ab8fe-cf05-4d38-a7a5-f3a1ef6cf307
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=755254029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.755254029
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3668914291
Short name T888
Test name
Test status
Simulation time 5594282135 ps
CPU time 13.79 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:40 PM PDT 24
Peak memory 198288 kb
Host smart-1428bee5-6877-4e65-afa1-3a3dadb9cdc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3668914291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3668914291
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3432707388
Short name T790
Test name
Test status
Simulation time 50990800734 ps
CPU time 76.43 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:13:42 PM PDT 24
Peak memory 199992 kb
Host smart-8ff61586-5f7b-42fd-bdc3-1a0aa8ed2507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432707388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3432707388
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.1616619090
Short name T727
Test name
Test status
Simulation time 6087859521 ps
CPU time 2.85 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:12:26 PM PDT 24
Peak memory 196096 kb
Host smart-85b27276-658a-409b-a3b7-3f28c7e1f174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616619090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1616619090
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_smoke.1592332574
Short name T39
Test name
Test status
Simulation time 695050054 ps
CPU time 3.3 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 199000 kb
Host smart-7e657476-21f0-4544-ac69-65d3f0551b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592332574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.1592332574
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1369057165
Short name T879
Test name
Test status
Simulation time 385003064020 ps
CPU time 412.44 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:19:17 PM PDT 24
Peak memory 210720 kb
Host smart-6546be57-4139-456c-894e-713fe57301d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369057165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1369057165
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.562877582
Short name T258
Test name
Test status
Simulation time 6402717009 ps
CPU time 1.63 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 199104 kb
Host smart-5437acc1-f08d-4638-9531-2869526ddd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562877582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.562877582
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3888036007
Short name T958
Test name
Test status
Simulation time 38139393354 ps
CPU time 58.75 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:13:23 PM PDT 24
Peak memory 199964 kb
Host smart-95d596be-b862-4a57-9f8e-9afdd9092eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888036007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3888036007
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2087839791
Short name T811
Test name
Test status
Simulation time 17995778 ps
CPU time 0.57 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 195640 kb
Host smart-cb270362-1835-468b-8839-d8e879c39fe6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087839791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2087839791
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.453303408
Short name T345
Test name
Test status
Simulation time 23931397202 ps
CPU time 38.72 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:52 PM PDT 24
Peak memory 199900 kb
Host smart-996254d2-5f15-4b8e-9f0e-368e0a2ce559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453303408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.453303408
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1393972186
Short name T1031
Test name
Test status
Simulation time 64743327737 ps
CPU time 23.28 seconds
Started Jul 29 07:13:16 PM PDT 24
Finished Jul 29 07:13:40 PM PDT 24
Peak memory 199904 kb
Host smart-f8830bf9-2f2a-465f-b26a-b803592e3671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393972186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1393972186
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3095027098
Short name T510
Test name
Test status
Simulation time 40925803183 ps
CPU time 32.96 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:46 PM PDT 24
Peak memory 199908 kb
Host smart-81f6ff7a-8663-4500-b42f-7bf72b44e7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095027098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3095027098
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.1348194630
Short name T732
Test name
Test status
Simulation time 14041761335 ps
CPU time 11.83 seconds
Started Jul 29 07:13:14 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 199852 kb
Host smart-de8d5dac-da5b-4324-813f-048627e99f19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348194630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.1348194630
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3691136568
Short name T425
Test name
Test status
Simulation time 139972472773 ps
CPU time 935.01 seconds
Started Jul 29 07:13:22 PM PDT 24
Finished Jul 29 07:28:57 PM PDT 24
Peak memory 199916 kb
Host smart-56183245-984c-4aac-a1e2-6dfdab2f0e6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691136568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3691136568
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.132024363
Short name T19
Test name
Test status
Simulation time 12823680550 ps
CPU time 18.46 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:31 PM PDT 24
Peak memory 198508 kb
Host smart-a4b97a9a-1d45-4f14-89b3-f32c78ccf647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132024363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.132024363
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.2905480238
Short name T1048
Test name
Test status
Simulation time 81675173290 ps
CPU time 25.6 seconds
Started Jul 29 07:13:17 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 198924 kb
Host smart-72b8a518-4dd5-4fe0-adac-400678b768f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905480238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2905480238
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.960967725
Short name T946
Test name
Test status
Simulation time 6355370532 ps
CPU time 370.33 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:19:23 PM PDT 24
Peak memory 199980 kb
Host smart-2a64825e-414e-4940-b77f-2c1677569417
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=960967725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.960967725
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.740897761
Short name T43
Test name
Test status
Simulation time 1172647644 ps
CPU time 1.58 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 195636 kb
Host smart-4075b982-8430-4ed4-a708-596d456459e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740897761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.740897761
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.1518516406
Short name T522
Test name
Test status
Simulation time 6044771104 ps
CPU time 12.56 seconds
Started Jul 29 07:13:18 PM PDT 24
Finished Jul 29 07:13:31 PM PDT 24
Peak memory 199928 kb
Host smart-a4f60b14-e80c-4cd0-bbdf-51146d23ea12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518516406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.1518516406
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.1545595372
Short name T585
Test name
Test status
Simulation time 2825952610 ps
CPU time 1.11 seconds
Started Jul 29 07:13:17 PM PDT 24
Finished Jul 29 07:13:18 PM PDT 24
Peak memory 196504 kb
Host smart-1f806a8a-b307-4229-af9c-3c719e2661a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545595372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1545595372
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.746777115
Short name T423
Test name
Test status
Simulation time 5964680270 ps
CPU time 16.81 seconds
Started Jul 29 07:13:11 PM PDT 24
Finished Jul 29 07:13:28 PM PDT 24
Peak memory 199888 kb
Host smart-764b4e7d-1686-4aa4-afcc-e7f1710e344e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746777115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.746777115
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.1677044198
Short name T955
Test name
Test status
Simulation time 59133143568 ps
CPU time 92.83 seconds
Started Jul 29 07:13:22 PM PDT 24
Finished Jul 29 07:14:55 PM PDT 24
Peak memory 199972 kb
Host smart-144cd349-b7e0-472c-bfa0-d8011ac96678
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677044198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.1677044198
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3234682108
Short name T487
Test name
Test status
Simulation time 52978308749 ps
CPU time 302.19 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:18:28 PM PDT 24
Peak memory 208312 kb
Host smart-318214c2-5aa1-4092-83ae-c9b7fed7f824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234682108 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3234682108
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.680011985
Short name T1003
Test name
Test status
Simulation time 1644494368 ps
CPU time 2.47 seconds
Started Jul 29 07:13:12 PM PDT 24
Finished Jul 29 07:13:15 PM PDT 24
Peak memory 198300 kb
Host smart-69705f5c-86dc-4059-8928-40a99d398468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680011985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.680011985
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.4123788976
Short name T702
Test name
Test status
Simulation time 29232530262 ps
CPU time 21.78 seconds
Started Jul 29 07:13:13 PM PDT 24
Finished Jul 29 07:13:35 PM PDT 24
Peak memory 199916 kb
Host smart-2cba8062-6129-4186-a2a2-d4a6d4c2cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123788976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.4123788976
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3854218797
Short name T243
Test name
Test status
Simulation time 187317075684 ps
CPU time 32.82 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:18:31 PM PDT 24
Peak memory 199840 kb
Host smart-0923ff99-2c92-4cf1-b976-c02183f0c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854218797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3854218797
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3094863035
Short name T45
Test name
Test status
Simulation time 9231147572 ps
CPU time 24.91 seconds
Started Jul 29 07:18:06 PM PDT 24
Finished Jul 29 07:18:31 PM PDT 24
Peak memory 199960 kb
Host smart-900c42f9-cdee-41e5-9d6c-9f0ecd547964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094863035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3094863035
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.682276590
Short name T990
Test name
Test status
Simulation time 48563458723 ps
CPU time 22.67 seconds
Started Jul 29 07:18:09 PM PDT 24
Finished Jul 29 07:18:32 PM PDT 24
Peak memory 199948 kb
Host smart-1b395afe-b0cd-4f92-b092-c9a7f7ac337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682276590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.682276590
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.541361410
Short name T903
Test name
Test status
Simulation time 56955986343 ps
CPU time 198.73 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:21:25 PM PDT 24
Peak memory 199952 kb
Host smart-b5e76698-cb22-4101-85e3-ff2e5e749166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541361410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.541361410
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3152700305
Short name T332
Test name
Test status
Simulation time 12341440686 ps
CPU time 20.55 seconds
Started Jul 29 07:18:08 PM PDT 24
Finished Jul 29 07:18:28 PM PDT 24
Peak memory 199896 kb
Host smart-54d69069-43c4-4301-a67b-78f75211858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152700305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3152700305
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.645768114
Short name T213
Test name
Test status
Simulation time 22086225924 ps
CPU time 32.28 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:39 PM PDT 24
Peak memory 199920 kb
Host smart-cc274ad4-8222-4b4e-a556-5df58e2874d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645768114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.645768114
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.385834755
Short name T756
Test name
Test status
Simulation time 329396237145 ps
CPU time 37.21 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:44 PM PDT 24
Peak memory 199956 kb
Host smart-8f318fad-270d-4492-9108-42cb9c94add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385834755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.385834755
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.1921086494
Short name T224
Test name
Test status
Simulation time 57804783437 ps
CPU time 26.03 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:33 PM PDT 24
Peak memory 199932 kb
Host smart-c26c1117-a718-4dca-88f4-0e5db226d0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921086494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.1921086494
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.206848215
Short name T867
Test name
Test status
Simulation time 158842806201 ps
CPU time 218.12 seconds
Started Jul 29 07:18:08 PM PDT 24
Finished Jul 29 07:21:46 PM PDT 24
Peak memory 199880 kb
Host smart-8297c7f0-203e-4c0e-ad46-ebf70a1b58fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206848215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.206848215
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.2128582132
Short name T23
Test name
Test status
Simulation time 14068802 ps
CPU time 0.55 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 194808 kb
Host smart-1a95e1ee-4f16-4962-bcc0-8e63de98c427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128582132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2128582132
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2002881767
Short name T1179
Test name
Test status
Simulation time 38296655607 ps
CPU time 35.58 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:59 PM PDT 24
Peak memory 199864 kb
Host smart-a10901b8-a95c-4ef9-bf05-6108859a51bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002881767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2002881767
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1322771973
Short name T1128
Test name
Test status
Simulation time 84670763578 ps
CPU time 43.33 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:14:08 PM PDT 24
Peak memory 199928 kb
Host smart-521801b1-74a3-4d17-bc32-cbb52ebc5a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322771973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1322771973
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_intr.2472200988
Short name T16
Test name
Test status
Simulation time 22901515179 ps
CPU time 40.39 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 199888 kb
Host smart-13f21b58-4d53-46c1-a421-b433e97045bd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472200988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.2472200988
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2661398179
Short name T385
Test name
Test status
Simulation time 175888203256 ps
CPU time 329.78 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:18:53 PM PDT 24
Peak memory 199876 kb
Host smart-7666a290-aaf9-4289-a7cc-0d1e5b5c20e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2661398179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2661398179
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.2518152631
Short name T344
Test name
Test status
Simulation time 10715097054 ps
CPU time 11.94 seconds
Started Jul 29 07:13:22 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 199976 kb
Host smart-12eb2655-2074-475c-b7c1-206a1f751d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518152631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.2518152631
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4249799051
Short name T1028
Test name
Test status
Simulation time 204258526710 ps
CPU time 173.83 seconds
Started Jul 29 07:13:27 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 200104 kb
Host smart-64018e4c-132b-45f5-bb2d-4762e3d1a168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249799051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4249799051
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.984466850
Short name T948
Test name
Test status
Simulation time 10052656558 ps
CPU time 479.29 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:21:25 PM PDT 24
Peak memory 199980 kb
Host smart-d167b345-fe00-46da-ac5e-6f5407fd8065
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=984466850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.984466850
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3589473505
Short name T838
Test name
Test status
Simulation time 4346520401 ps
CPU time 2.37 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:25 PM PDT 24
Peak memory 199108 kb
Host smart-af32c1b2-9001-4904-a62f-79f707a1d0a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3589473505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3589473505
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.811472899
Short name T1173
Test name
Test status
Simulation time 220504328231 ps
CPU time 383.37 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:19:49 PM PDT 24
Peak memory 199992 kb
Host smart-7089ff6a-9e7a-42d6-bb87-d9ebaf716dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811472899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.811472899
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3018151733
Short name T815
Test name
Test status
Simulation time 38285952666 ps
CPU time 15.94 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:13:42 PM PDT 24
Peak memory 196480 kb
Host smart-b55ac9a1-b4e0-4920-bd12-d2a1d86788dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018151733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3018151733
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.3338106053
Short name T579
Test name
Test status
Simulation time 5564112668 ps
CPU time 11.46 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 199168 kb
Host smart-8547bbb8-5957-46d0-8c79-93837693ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338106053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.3338106053
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.768204324
Short name T977
Test name
Test status
Simulation time 99786035712 ps
CPU time 1303.14 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:35:07 PM PDT 24
Peak memory 226412 kb
Host smart-6c68be60-3b28-48f3-9f80-c0a0fff18790
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768204324 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.768204324
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.1859044072
Short name T1046
Test name
Test status
Simulation time 875226202 ps
CPU time 4.33 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:28 PM PDT 24
Peak memory 198680 kb
Host smart-5ee33ee7-41d8-4ba0-97db-dd6fcb21bcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859044072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1859044072
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3786309508
Short name T793
Test name
Test status
Simulation time 78414351744 ps
CPU time 110.99 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:15:15 PM PDT 24
Peak memory 199916 kb
Host smart-6cc86233-8960-4cc1-8913-2f22808babd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786309508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3786309508
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.1954674569
Short name T193
Test name
Test status
Simulation time 21672079503 ps
CPU time 34.16 seconds
Started Jul 29 07:18:06 PM PDT 24
Finished Jul 29 07:18:40 PM PDT 24
Peak memory 199880 kb
Host smart-17ffd5e4-d012-49de-abac-7dcb6574d92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954674569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.1954674569
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.493209154
Short name T246
Test name
Test status
Simulation time 32803650458 ps
CPU time 17.77 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:25 PM PDT 24
Peak memory 199976 kb
Host smart-826b8dfa-29a5-44e0-9bf1-0c0bc647e7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493209154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.493209154
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.1384039624
Short name T985
Test name
Test status
Simulation time 398556016429 ps
CPU time 181.66 seconds
Started Jul 29 07:18:08 PM PDT 24
Finished Jul 29 07:21:10 PM PDT 24
Peak memory 200040 kb
Host smart-b91dc2ef-8d1f-401c-ad26-666bfad28c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384039624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.1384039624
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2192844790
Short name T185
Test name
Test status
Simulation time 20796932296 ps
CPU time 52.42 seconds
Started Jul 29 07:18:08 PM PDT 24
Finished Jul 29 07:19:01 PM PDT 24
Peak memory 200100 kb
Host smart-d4e7dfe5-4dcc-4876-8171-75e3c77855c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192844790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2192844790
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.3876465578
Short name T788
Test name
Test status
Simulation time 52378561884 ps
CPU time 17.1 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 199648 kb
Host smart-6c893158-fd16-4e22-a886-3f88a493bd55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876465578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.3876465578
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.4231212710
Short name T776
Test name
Test status
Simulation time 57716742596 ps
CPU time 24.44 seconds
Started Jul 29 07:18:07 PM PDT 24
Finished Jul 29 07:18:32 PM PDT 24
Peak memory 199840 kb
Host smart-a21261b3-f009-4376-8d07-38aa51c97dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231212710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.4231212710
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3253336242
Short name T593
Test name
Test status
Simulation time 42906349810 ps
CPU time 22.12 seconds
Started Jul 29 07:29:18 PM PDT 24
Finished Jul 29 07:29:40 PM PDT 24
Peak memory 199956 kb
Host smart-65c5b57f-28b3-42f3-934e-dabfa4f54ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253336242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3253336242
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2729258221
Short name T226
Test name
Test status
Simulation time 77022669550 ps
CPU time 132.8 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:31:36 PM PDT 24
Peak memory 199968 kb
Host smart-16025d06-84fe-4e28-bf62-a0170f173d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729258221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2729258221
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2075452668
Short name T714
Test name
Test status
Simulation time 43515382 ps
CPU time 0.56 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 194996 kb
Host smart-9644f9f9-742c-4db2-8b5f-11a38a253241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075452668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2075452668
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.943250698
Short name T681
Test name
Test status
Simulation time 30797329393 ps
CPU time 52.02 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:14:16 PM PDT 24
Peak memory 199896 kb
Host smart-333b22d7-9134-42b6-a34c-701e0a5b071a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943250698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.943250698
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.113152206
Short name T34
Test name
Test status
Simulation time 68187432545 ps
CPU time 28.02 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:13:52 PM PDT 24
Peak memory 199900 kb
Host smart-61480517-7b74-4535-a12e-38571b54d396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113152206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.113152206
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.4217413693
Short name T654
Test name
Test status
Simulation time 78844436160 ps
CPU time 52.79 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:14:18 PM PDT 24
Peak memory 199736 kb
Host smart-a782a7a6-bfa3-4e3f-b145-28db45ecb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217413693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.4217413693
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.647475130
Short name T883
Test name
Test status
Simulation time 20087710314 ps
CPU time 6.59 seconds
Started Jul 29 07:13:25 PM PDT 24
Finished Jul 29 07:13:32 PM PDT 24
Peak memory 199860 kb
Host smart-3125ba2f-f782-40a5-b7c4-95fa285cfafb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647475130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.647475130
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1973185020
Short name T1168
Test name
Test status
Simulation time 83596232921 ps
CPU time 593.02 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:23:27 PM PDT 24
Peak memory 199972 kb
Host smart-4e2025d7-c80f-46f6-a5f0-37deb2eb9da0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1973185020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1973185020
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1148645363
Short name T376
Test name
Test status
Simulation time 4558728666 ps
CPU time 5.26 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:13:41 PM PDT 24
Peak memory 199924 kb
Host smart-32a8a034-ad9c-4039-a069-b80e8927328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148645363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1148645363
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.315909335
Short name T451
Test name
Test status
Simulation time 50760139298 ps
CPU time 30.69 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:54 PM PDT 24
Peak memory 200080 kb
Host smart-0a403a5a-5a84-42ca-b74b-8cb43c521723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315909335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.315909335
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3658238998
Short name T261
Test name
Test status
Simulation time 21194161471 ps
CPU time 1079.51 seconds
Started Jul 29 07:13:37 PM PDT 24
Finished Jul 29 07:31:37 PM PDT 24
Peak memory 199984 kb
Host smart-0283241a-14a4-43ba-b431-69a890cb4045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658238998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3658238998
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1348158260
Short name T395
Test name
Test status
Simulation time 3396178287 ps
CPU time 10.22 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 197988 kb
Host smart-9a6bb459-6dc9-45c7-8b3b-7e123a654b0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348158260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1348158260
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.558938623
Short name T601
Test name
Test status
Simulation time 46973618469 ps
CPU time 21.61 seconds
Started Jul 29 07:13:23 PM PDT 24
Finished Jul 29 07:13:45 PM PDT 24
Peak memory 199948 kb
Host smart-a41e2adb-618c-4298-93d8-3e101b5d00f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558938623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.558938623
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.998801260
Short name T276
Test name
Test status
Simulation time 3566038010 ps
CPU time 6.37 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:13:30 PM PDT 24
Peak memory 196092 kb
Host smart-cbb09cca-6b7e-4cb4-90bb-f2fed4fa3c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998801260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.998801260
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1539357716
Short name T694
Test name
Test status
Simulation time 5754049899 ps
CPU time 20.06 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:13:44 PM PDT 24
Peak memory 199756 kb
Host smart-187b0b83-ca38-41e3-819f-ce382e3c5712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539357716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1539357716
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.140785223
Short name T309
Test name
Test status
Simulation time 6536095225 ps
CPU time 15.75 seconds
Started Jul 29 07:13:26 PM PDT 24
Finished Jul 29 07:13:41 PM PDT 24
Peak memory 199964 kb
Host smart-73d842e8-8b7f-4a98-bd97-a58bdcee652d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140785223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.140785223
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2225167818
Short name T461
Test name
Test status
Simulation time 19301590562 ps
CPU time 15.18 seconds
Started Jul 29 07:13:24 PM PDT 24
Finished Jul 29 07:13:39 PM PDT 24
Peak memory 199968 kb
Host smart-f8d9d330-5ccf-492b-bc05-c3c5b0bd413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225167818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2225167818
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2817102694
Short name T188
Test name
Test status
Simulation time 40911668281 ps
CPU time 82.78 seconds
Started Jul 29 07:29:18 PM PDT 24
Finished Jul 29 07:30:41 PM PDT 24
Peak memory 199896 kb
Host smart-33368662-ef83-448d-b178-0484bb42b3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817102694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2817102694
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.1806833215
Short name T1105
Test name
Test status
Simulation time 66360440731 ps
CPU time 171.73 seconds
Started Jul 29 07:29:19 PM PDT 24
Finished Jul 29 07:32:10 PM PDT 24
Peak memory 199956 kb
Host smart-96598da5-5fc8-4d58-93bc-43eb797764e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806833215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.1806833215
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.1376187841
Short name T324
Test name
Test status
Simulation time 16246848676 ps
CPU time 13.52 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:29:37 PM PDT 24
Peak memory 199856 kb
Host smart-99a447f3-ae8b-49bb-b6a2-c5b0a1b820f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376187841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.1376187841
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.2668351035
Short name T496
Test name
Test status
Simulation time 62986342359 ps
CPU time 26.33 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 200104 kb
Host smart-f05b1cfc-df1b-4380-a5f7-a894d21d229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668351035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2668351035
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4030434050
Short name T971
Test name
Test status
Simulation time 15878573242 ps
CPU time 27.07 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:29:51 PM PDT 24
Peak memory 199976 kb
Host smart-7f4ac0b7-0940-4c1f-b723-eed62ad6ca27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030434050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4030434050
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3296065454
Short name T1140
Test name
Test status
Simulation time 33767198082 ps
CPU time 8.77 seconds
Started Jul 29 07:29:28 PM PDT 24
Finished Jul 29 07:29:37 PM PDT 24
Peak memory 199880 kb
Host smart-882ae7ae-cc48-4401-a708-402c604575c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296065454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3296065454
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2858585634
Short name T204
Test name
Test status
Simulation time 26997060595 ps
CPU time 31.65 seconds
Started Jul 29 07:29:27 PM PDT 24
Finished Jul 29 07:29:58 PM PDT 24
Peak memory 199900 kb
Host smart-33d0494d-8d46-4844-bc4a-bd569532889e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858585634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2858585634
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.2755999897
Short name T148
Test name
Test status
Simulation time 13285921299 ps
CPU time 24.43 seconds
Started Jul 29 07:29:26 PM PDT 24
Finished Jul 29 07:29:50 PM PDT 24
Peak memory 199892 kb
Host smart-bb24afaf-f3cc-4f81-8160-9fe86608c833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755999897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.2755999897
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.865108338
Short name T184
Test name
Test status
Simulation time 206628697366 ps
CPU time 31.15 seconds
Started Jul 29 07:29:25 PM PDT 24
Finished Jul 29 07:29:56 PM PDT 24
Peak memory 199964 kb
Host smart-848fa0a8-95f0-4bf4-9d6b-8b2bdfca1998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865108338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.865108338
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3710831177
Short name T813
Test name
Test status
Simulation time 24764818 ps
CPU time 0.56 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:36 PM PDT 24
Peak memory 195368 kb
Host smart-67d5302d-94c5-4a16-bcd4-e3101e74108a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710831177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3710831177
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3797574213
Short name T1021
Test name
Test status
Simulation time 129555034509 ps
CPU time 207.51 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:17:01 PM PDT 24
Peak memory 200036 kb
Host smart-28deb1f7-08a7-4357-a973-7e293d3f52a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797574213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3797574213
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.265274711
Short name T600
Test name
Test status
Simulation time 52754672830 ps
CPU time 13.85 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:49 PM PDT 24
Peak memory 199976 kb
Host smart-208a6056-c933-4832-b5a3-a07fbe1341f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265274711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.265274711
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.3784033273
Short name T529
Test name
Test status
Simulation time 23069096011 ps
CPU time 32.51 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:14:08 PM PDT 24
Peak memory 199928 kb
Host smart-62b39df5-2dca-4f0e-b4e9-1b298ddb3992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784033273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.3784033273
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.701453150
Short name T507
Test name
Test status
Simulation time 17970456486 ps
CPU time 13.54 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:13:48 PM PDT 24
Peak memory 199920 kb
Host smart-dc20fa1a-3538-4059-8441-201f15fa4afa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701453150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.701453150
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1444345720
Short name T540
Test name
Test status
Simulation time 117741093908 ps
CPU time 878.02 seconds
Started Jul 29 07:13:32 PM PDT 24
Finished Jul 29 07:28:11 PM PDT 24
Peak memory 199808 kb
Host smart-1ac55a0f-3c66-4df5-9699-3a1bbf440769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444345720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1444345720
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.957584554
Short name T611
Test name
Test status
Simulation time 1324739646 ps
CPU time 2.84 seconds
Started Jul 29 07:13:37 PM PDT 24
Finished Jul 29 07:13:40 PM PDT 24
Peak memory 195456 kb
Host smart-943797e9-2f64-4ade-8ce0-f79dcd535cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957584554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.957584554
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.796643163
Short name T391
Test name
Test status
Simulation time 67339214207 ps
CPU time 25.63 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:13:59 PM PDT 24
Peak memory 198864 kb
Host smart-e05432d2-6bd2-4997-adc4-27af5f86b77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796643163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.796643163
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2070640801
Short name T411
Test name
Test status
Simulation time 13669501943 ps
CPU time 389.59 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:20:05 PM PDT 24
Peak memory 199916 kb
Host smart-2cd388db-4077-46a3-9a86-d236604d01bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2070640801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2070640801
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.2174590075
Short name T896
Test name
Test status
Simulation time 2119412893 ps
CPU time 4.49 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:13:38 PM PDT 24
Peak memory 198028 kb
Host smart-d6305839-863a-4306-b103-d07e47e849a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2174590075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2174590075
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.2391702750
Short name T434
Test name
Test status
Simulation time 24146794615 ps
CPU time 33.02 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:14:09 PM PDT 24
Peak memory 199952 kb
Host smart-bd2c39ca-9539-4e37-b78b-07188f9fea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391702750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.2391702750
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1556645728
Short name T812
Test name
Test status
Simulation time 41236032252 ps
CPU time 8.05 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:13:45 PM PDT 24
Peak memory 195876 kb
Host smart-30ef8002-2b15-407d-980f-451d8e5a9966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556645728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1556645728
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3615124839
Short name T1139
Test name
Test status
Simulation time 298237587 ps
CPU time 1.07 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:13:37 PM PDT 24
Peak memory 199876 kb
Host smart-c4c3f007-f195-4403-bd43-f5e231f58db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615124839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3615124839
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4056597819
Short name T1071
Test name
Test status
Simulation time 118925713586 ps
CPU time 158.29 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:16:13 PM PDT 24
Peak memory 199864 kb
Host smart-46e19c6f-0c62-49b7-8a57-83c4b390e40f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056597819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4056597819
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.813525566
Short name T545
Test name
Test status
Simulation time 34964251444 ps
CPU time 262.67 seconds
Started Jul 29 07:13:36 PM PDT 24
Finished Jul 29 07:17:59 PM PDT 24
Peak memory 216564 kb
Host smart-7d5d8f82-df6b-43a5-95d7-064a711043c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813525566 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.813525566
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.4135672898
Short name T486
Test name
Test status
Simulation time 5365941401 ps
CPU time 1.6 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:13:36 PM PDT 24
Peak memory 199944 kb
Host smart-b12082bb-845d-4178-98f1-d7d101701b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135672898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.4135672898
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.222025261
Short name T295
Test name
Test status
Simulation time 36619431095 ps
CPU time 30.85 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 199700 kb
Host smart-1b49d912-17c0-44fd-912b-fd8c6360eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222025261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.222025261
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1621931376
Short name T892
Test name
Test status
Simulation time 79128056226 ps
CPU time 39.03 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:30:03 PM PDT 24
Peak memory 199916 kb
Host smart-f3f5919d-69e1-4fd7-b312-0f8222a40d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621931376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1621931376
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.974419121
Short name T1124
Test name
Test status
Simulation time 46418020566 ps
CPU time 40.09 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:30:03 PM PDT 24
Peak memory 199976 kb
Host smart-9d7fab71-b55b-464c-b05f-4be661040bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974419121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.974419121
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.485695617
Short name T430
Test name
Test status
Simulation time 76088409572 ps
CPU time 30.69 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:29:52 PM PDT 24
Peak memory 200120 kb
Host smart-a375281e-7f91-48e6-bacb-ddc40bda9778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485695617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.485695617
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.3426313470
Short name T136
Test name
Test status
Simulation time 29363590185 ps
CPU time 44.09 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:30:07 PM PDT 24
Peak memory 199876 kb
Host smart-a27d90bf-7321-4c94-a580-b61e7eaae4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426313470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.3426313470
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1668768695
Short name T713
Test name
Test status
Simulation time 23816592227 ps
CPU time 38.6 seconds
Started Jul 29 07:29:24 PM PDT 24
Finished Jul 29 07:30:02 PM PDT 24
Peak memory 199916 kb
Host smart-2aa3d95c-4ab4-4ccc-87c0-6010e6e52fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668768695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1668768695
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.3208528966
Short name T340
Test name
Test status
Simulation time 30268557897 ps
CPU time 50.2 seconds
Started Jul 29 07:29:23 PM PDT 24
Finished Jul 29 07:30:14 PM PDT 24
Peak memory 199784 kb
Host smart-4987ccc8-8ed0-41f2-98c6-38af9f5e26bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208528966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.3208528966
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3951972903
Short name T414
Test name
Test status
Simulation time 22337805649 ps
CPU time 10.34 seconds
Started Jul 29 07:29:20 PM PDT 24
Finished Jul 29 07:29:30 PM PDT 24
Peak memory 199896 kb
Host smart-bbbd9522-2c98-47dc-b883-39952d9962c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951972903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3951972903
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1927121529
Short name T389
Test name
Test status
Simulation time 12838284 ps
CPU time 0.55 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:36 PM PDT 24
Peak memory 194328 kb
Host smart-def1b092-6a41-4d65-b1ba-84ffc1b791cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927121529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1927121529
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1982841093
Short name T794
Test name
Test status
Simulation time 23468500629 ps
CPU time 23.6 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:13:58 PM PDT 24
Peak memory 199900 kb
Host smart-ad7ba233-e1f9-4d2e-a497-b9b8deba6dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982841093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1982841093
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.1591932752
Short name T929
Test name
Test status
Simulation time 63922386635 ps
CPU time 82.82 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:14:56 PM PDT 24
Peak memory 199912 kb
Host smart-35b20bbf-9356-438f-9cf8-533c78144b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591932752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.1591932752
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1777497778
Short name T1144
Test name
Test status
Simulation time 103441452427 ps
CPU time 86.81 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:15:01 PM PDT 24
Peak memory 199908 kb
Host smart-3d8a371f-4024-4fd6-94c3-e61e0f2a5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777497778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1777497778
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.3800089230
Short name T287
Test name
Test status
Simulation time 400015028783 ps
CPU time 346.91 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:19:20 PM PDT 24
Peak memory 199868 kb
Host smart-7ebc05fd-75f8-495c-86a0-c8726254eeb2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800089230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.3800089230
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.2574925071
Short name T911
Test name
Test status
Simulation time 123073839016 ps
CPU time 230.35 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:17:25 PM PDT 24
Peak memory 199976 kb
Host smart-adaa85d1-b9a2-4261-bcc9-a9b5ef4100f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2574925071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.2574925071
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1886678765
Short name T709
Test name
Test status
Simulation time 6713108979 ps
CPU time 11.87 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:47 PM PDT 24
Peak memory 198636 kb
Host smart-67d1760f-8f23-43e2-890c-25f58cf1caec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886678765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1886678765
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2870496276
Short name T1145
Test name
Test status
Simulation time 71256127649 ps
CPU time 66.24 seconds
Started Jul 29 07:13:38 PM PDT 24
Finished Jul 29 07:14:44 PM PDT 24
Peak memory 198912 kb
Host smart-106e3b96-16e7-4239-811f-ed28138e3c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870496276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2870496276
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3963416067
Short name T1127
Test name
Test status
Simulation time 16519301717 ps
CPU time 139.39 seconds
Started Jul 29 07:13:39 PM PDT 24
Finished Jul 29 07:15:59 PM PDT 24
Peak memory 199908 kb
Host smart-c83b82ba-780f-4054-b107-dcb90eb707ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3963416067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3963416067
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3350937830
Short name T362
Test name
Test status
Simulation time 2766881273 ps
CPU time 4.41 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:13:37 PM PDT 24
Peak memory 198100 kb
Host smart-bea6043f-0701-4611-b3f8-31d282bd2014
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350937830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3350937830
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.872048815
Short name T932
Test name
Test status
Simulation time 68341423236 ps
CPU time 26.28 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:14:01 PM PDT 24
Peak memory 199352 kb
Host smart-71804f78-7ed4-4b22-93dc-33920396f4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872048815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.872048815
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3363060068
Short name T1134
Test name
Test status
Simulation time 4969747200 ps
CPU time 2.72 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:13:35 PM PDT 24
Peak memory 196292 kb
Host smart-cf1d9e12-69cb-40b6-ad5c-f4879d239e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363060068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3363060068
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3216070039
Short name T731
Test name
Test status
Simulation time 5822719367 ps
CPU time 10.57 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:46 PM PDT 24
Peak memory 199164 kb
Host smart-e6e03697-120e-4de3-9f72-fd552241c0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216070039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3216070039
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.3948755497
Short name T285
Test name
Test status
Simulation time 220872793819 ps
CPU time 123.72 seconds
Started Jul 29 07:13:33 PM PDT 24
Finished Jul 29 07:15:37 PM PDT 24
Peak memory 215568 kb
Host smart-2cf4bbce-c01b-4070-824a-ea67c45d2c02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948755497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3948755497
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1291169238
Short name T14
Test name
Test status
Simulation time 22898202984 ps
CPU time 566.27 seconds
Started Jul 29 07:13:34 PM PDT 24
Finished Jul 29 07:23:00 PM PDT 24
Peak memory 208260 kb
Host smart-88e2c7b6-d942-4ef4-80b9-9177e4801118
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291169238 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1291169238
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1533543766
Short name T319
Test name
Test status
Simulation time 12775191732 ps
CPU time 7.54 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 199872 kb
Host smart-285867ec-d697-4393-ac7f-a3ed28df31f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533543766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1533543766
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2025847488
Short name T405
Test name
Test status
Simulation time 11255148653 ps
CPU time 5.11 seconds
Started Jul 29 07:13:35 PM PDT 24
Finished Jul 29 07:13:40 PM PDT 24
Peak memory 199920 kb
Host smart-fd059ef6-11e7-4188-8d25-53ebf4f0006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025847488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2025847488
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2137514401
Short name T495
Test name
Test status
Simulation time 55299118375 ps
CPU time 75.7 seconds
Started Jul 29 07:29:26 PM PDT 24
Finished Jul 29 07:30:42 PM PDT 24
Peak memory 199900 kb
Host smart-e62e477b-5e43-401c-b878-29d68950734f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137514401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2137514401
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2246930073
Short name T741
Test name
Test status
Simulation time 36051035118 ps
CPU time 96.83 seconds
Started Jul 29 07:29:24 PM PDT 24
Finished Jul 29 07:31:01 PM PDT 24
Peak memory 199976 kb
Host smart-817af840-5181-416f-8ae8-4be2b435d447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246930073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2246930073
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2809142770
Short name T800
Test name
Test status
Simulation time 57034929295 ps
CPU time 103.15 seconds
Started Jul 29 07:29:24 PM PDT 24
Finished Jul 29 07:31:07 PM PDT 24
Peak memory 199976 kb
Host smart-bfc9e804-5041-495c-97aa-8390c891d8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809142770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2809142770
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3288305274
Short name T171
Test name
Test status
Simulation time 148458566121 ps
CPU time 49.36 seconds
Started Jul 29 07:29:22 PM PDT 24
Finished Jul 29 07:30:12 PM PDT 24
Peak memory 199980 kb
Host smart-60ddef35-f95d-46f5-9bdd-c6688d6b7751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288305274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3288305274
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.3596257169
Short name T196
Test name
Test status
Simulation time 61054609717 ps
CPU time 100.03 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:31:14 PM PDT 24
Peak memory 199848 kb
Host smart-d0d991c7-2318-46cb-ad33-d9282381d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596257169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3596257169
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.4204971789
Short name T1133
Test name
Test status
Simulation time 26303254166 ps
CPU time 20.8 seconds
Started Jul 29 07:29:26 PM PDT 24
Finished Jul 29 07:29:47 PM PDT 24
Peak memory 199916 kb
Host smart-a8bc4764-0b31-40c5-ab6c-f8cf2b6895fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204971789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.4204971789
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2278648898
Short name T202
Test name
Test status
Simulation time 14632602742 ps
CPU time 31.73 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:30:05 PM PDT 24
Peak memory 199980 kb
Host smart-3a383949-74bb-42cc-b569-5630f5b20350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278648898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2278648898
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.1444963234
Short name T863
Test name
Test status
Simulation time 74745081449 ps
CPU time 103.12 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:31:16 PM PDT 24
Peak memory 199908 kb
Host smart-2e0ea1b9-04c0-48f5-9a9f-9eb28aa90fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444963234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.1444963234
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.1110629795
Short name T1041
Test name
Test status
Simulation time 35889689753 ps
CPU time 27.28 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:30:02 PM PDT 24
Peak memory 199960 kb
Host smart-efb8ec58-0172-4d64-88ea-e030f2612d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110629795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.1110629795
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3016600711
Short name T785
Test name
Test status
Simulation time 18984643924 ps
CPU time 26.54 seconds
Started Jul 29 07:29:29 PM PDT 24
Finished Jul 29 07:29:56 PM PDT 24
Peak memory 199944 kb
Host smart-5597763b-590f-4a1b-b395-9ba4376e70c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016600711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3016600711
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2823553787
Short name T860
Test name
Test status
Simulation time 51036897 ps
CPU time 0.58 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:13:48 PM PDT 24
Peak memory 195580 kb
Host smart-97eb9bc8-405c-46b1-b57e-66d6d593b068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823553787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2823553787
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.201441414
Short name T718
Test name
Test status
Simulation time 141149049744 ps
CPU time 632.15 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:24:16 PM PDT 24
Peak memory 199800 kb
Host smart-76ef9fdd-bce3-48bb-95ed-1b63750dac43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201441414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.201441414
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.867627808
Short name T647
Test name
Test status
Simulation time 27914581936 ps
CPU time 24.06 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:14:12 PM PDT 24
Peak memory 199792 kb
Host smart-0bc952dd-c3e0-4382-8297-a0bf2800a07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867627808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.867627808
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1685829465
Short name T792
Test name
Test status
Simulation time 121507120778 ps
CPU time 183.59 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 200104 kb
Host smart-69a11344-6be2-4361-b67b-2d45971b32ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685829465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1685829465
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.264249658
Short name T758
Test name
Test status
Simulation time 54948081150 ps
CPU time 130.64 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:15:55 PM PDT 24
Peak memory 199916 kb
Host smart-685e9941-67c6-4769-b155-72fc968721b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264249658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.264249658
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.505203017
Short name T779
Test name
Test status
Simulation time 101195467607 ps
CPU time 127.4 seconds
Started Jul 29 07:13:49 PM PDT 24
Finished Jul 29 07:15:56 PM PDT 24
Peak memory 199956 kb
Host smart-bcf6d629-6c5f-4361-ba85-192a56383130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=505203017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.505203017
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.479101014
Short name T353
Test name
Test status
Simulation time 3756169966 ps
CPU time 4.71 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:13:53 PM PDT 24
Peak memory 198504 kb
Host smart-49e74c3e-4442-4593-b8a5-8a9cf630a967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479101014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.479101014
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2422904265
Short name T422
Test name
Test status
Simulation time 92147073844 ps
CPU time 88.79 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:15:13 PM PDT 24
Peak memory 200104 kb
Host smart-9036b666-0fc2-4e5e-b69c-d13d7c19a944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422904265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2422904265
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2131571297
Short name T924
Test name
Test status
Simulation time 12631299899 ps
CPU time 649.11 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:24:38 PM PDT 24
Peak memory 199956 kb
Host smart-bc67284c-ab4e-4556-9f43-74d1135a1f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2131571297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2131571297
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2100988970
Short name T698
Test name
Test status
Simulation time 2236728159 ps
CPU time 2.85 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:13:47 PM PDT 24
Peak memory 198236 kb
Host smart-95542d5a-85b0-47ca-880b-3da4e1bfa431
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2100988970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2100988970
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.289336723
Short name T549
Test name
Test status
Simulation time 207213521528 ps
CPU time 49.47 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:14:34 PM PDT 24
Peak memory 199920 kb
Host smart-481e0ba6-2d80-4212-9329-184d59359a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289336723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.289336723
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3418513763
Short name T648
Test name
Test status
Simulation time 3132181799 ps
CPU time 5.42 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:13:50 PM PDT 24
Peak memory 196572 kb
Host smart-3843ee0f-2e73-4a3c-b3c3-fa436fb8b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418513763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3418513763
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.975412401
Short name T409
Test name
Test status
Simulation time 6244353191 ps
CPU time 10.39 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:13:55 PM PDT 24
Peak memory 199720 kb
Host smart-e3b5b2ca-7514-4233-ae30-332ad5055683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975412401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.975412401
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1247504730
Short name T893
Test name
Test status
Simulation time 515760327558 ps
CPU time 161.43 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:16:29 PM PDT 24
Peak memory 200232 kb
Host smart-b8e63a99-696c-48aa-a022-65f155d3df53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247504730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1247504730
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1630961615
Short name T993
Test name
Test status
Simulation time 17012247729 ps
CPU time 191.97 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:16:57 PM PDT 24
Peak memory 216324 kb
Host smart-be755b5c-9b06-4788-aa8e-d56c9e02a74c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630961615 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1630961615
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1377625532
Short name T1007
Test name
Test status
Simulation time 732345034 ps
CPU time 2.95 seconds
Started Jul 29 07:13:43 PM PDT 24
Finished Jul 29 07:13:46 PM PDT 24
Peak memory 198860 kb
Host smart-c0715fcc-001c-4b6c-b554-45455aaf6c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377625532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1377625532
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.4287602282
Short name T661
Test name
Test status
Simulation time 100606071346 ps
CPU time 132.02 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:16:00 PM PDT 24
Peak memory 200100 kb
Host smart-d52f386d-70e5-4ee0-b869-06db14dcfa50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287602282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.4287602282
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.4187804449
Short name T1129
Test name
Test status
Simulation time 39242059559 ps
CPU time 61.49 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:30:34 PM PDT 24
Peak memory 199908 kb
Host smart-009cf845-0778-4e92-ad3b-cc6380d02dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187804449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.4187804449
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.3943282854
Short name T819
Test name
Test status
Simulation time 169717496391 ps
CPU time 69.89 seconds
Started Jul 29 07:29:32 PM PDT 24
Finished Jul 29 07:30:42 PM PDT 24
Peak memory 200076 kb
Host smart-7d16306f-49d4-471b-b112-e68cf1c1ac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943282854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.3943282854
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3125991409
Short name T149
Test name
Test status
Simulation time 18981828309 ps
CPU time 28.46 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:30:01 PM PDT 24
Peak memory 200032 kb
Host smart-0a6f8cdd-5e46-4a9c-873f-3d2338d5520f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125991409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3125991409
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.476782868
Short name T337
Test name
Test status
Simulation time 31238240098 ps
CPU time 14.48 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 199908 kb
Host smart-86060fc8-5158-4c94-9442-fea098df384a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476782868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.476782868
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.1278875657
Short name T341
Test name
Test status
Simulation time 9971074249 ps
CPU time 18.38 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:29:51 PM PDT 24
Peak memory 200088 kb
Host smart-4022922c-f85f-482e-8fda-6128601473da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278875657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.1278875657
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2630865385
Short name T440
Test name
Test status
Simulation time 19481912392 ps
CPU time 18.3 seconds
Started Jul 29 07:29:29 PM PDT 24
Finished Jul 29 07:29:47 PM PDT 24
Peak memory 199872 kb
Host smart-e0f0ed71-2789-4ac4-b23c-c443ff5f0998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630865385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2630865385
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2319828111
Short name T845
Test name
Test status
Simulation time 47052710603 ps
CPU time 119.45 seconds
Started Jul 29 07:29:27 PM PDT 24
Finished Jul 29 07:31:26 PM PDT 24
Peak memory 199908 kb
Host smart-5a9e8854-18d9-46fd-9992-8120d970c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319828111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2319828111
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.2530673597
Short name T1174
Test name
Test status
Simulation time 13805963544 ps
CPU time 13.73 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 199304 kb
Host smart-d018c1bd-460c-4294-af8c-1f8d8fe7b1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530673597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2530673597
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2506125223
Short name T445
Test name
Test status
Simulation time 16946622347 ps
CPU time 28.47 seconds
Started Jul 29 07:29:29 PM PDT 24
Finished Jul 29 07:29:58 PM PDT 24
Peak memory 199804 kb
Host smart-2c95aa56-9199-43a5-9bc3-e9e16f1f3f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506125223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2506125223
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.123404482
Short name T205
Test name
Test status
Simulation time 30847330408 ps
CPU time 13.01 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:29:47 PM PDT 24
Peak memory 199920 kb
Host smart-6cab93b8-1cfc-4262-90ac-c85a7df420c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123404482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.123404482
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2311070983
Short name T1096
Test name
Test status
Simulation time 15455034 ps
CPU time 0.6 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:13:48 PM PDT 24
Peak memory 195652 kb
Host smart-a32504d0-3693-4858-81b2-34d2e1c4671e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311070983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2311070983
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.3639975154
Short name T834
Test name
Test status
Simulation time 13834416874 ps
CPU time 20.36 seconds
Started Jul 29 07:13:46 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 199968 kb
Host smart-29e625b1-3e2f-411f-9885-fab5f39ed5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639975154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.3639975154
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.636787653
Short name T1098
Test name
Test status
Simulation time 152336693453 ps
CPU time 177.67 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:16:46 PM PDT 24
Peak memory 199940 kb
Host smart-9665f7db-d71f-48b2-956f-336b99d73f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636787653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.636787653
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1568721803
Short name T516
Test name
Test status
Simulation time 121713237843 ps
CPU time 134.32 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:16:02 PM PDT 24
Peak memory 200064 kb
Host smart-2e358e92-d07c-4c4a-bee8-88b45345854d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568721803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1568721803
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.130715008
Short name T270
Test name
Test status
Simulation time 22485353856 ps
CPU time 16.34 seconds
Started Jul 29 07:13:46 PM PDT 24
Finished Jul 29 07:14:03 PM PDT 24
Peak memory 199972 kb
Host smart-4e4a3a07-5f00-47cc-833e-9a1470a98dc7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130715008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.130715008
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4191449638
Short name T670
Test name
Test status
Simulation time 130987640960 ps
CPU time 637.34 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:24:25 PM PDT 24
Peak memory 199932 kb
Host smart-8015e3de-f30c-4d55-89ab-282b145595d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4191449638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4191449638
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1749933898
Short name T350
Test name
Test status
Simulation time 10503352704 ps
CPU time 23.14 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:14:10 PM PDT 24
Peak memory 199704 kb
Host smart-063cf758-970b-458a-a9cb-4b6a561f8bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749933898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1749933898
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.741559239
Short name T1091
Test name
Test status
Simulation time 176267444525 ps
CPU time 94.21 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:15:21 PM PDT 24
Peak memory 200016 kb
Host smart-5e3bef19-6c3d-4f58-90dc-120d71c6ad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741559239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.741559239
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.2239481648
Short name T548
Test name
Test status
Simulation time 35099940939 ps
CPU time 1881.43 seconds
Started Jul 29 07:13:46 PM PDT 24
Finished Jul 29 07:45:08 PM PDT 24
Peak memory 200032 kb
Host smart-8c4f9233-4a93-4b44-8250-90a4b772cb50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2239481648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2239481648
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.2788293280
Short name T560
Test name
Test status
Simulation time 6124803917 ps
CPU time 13.73 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:14:01 PM PDT 24
Peak memory 198984 kb
Host smart-65b5e592-3c6c-4851-a0f3-0f6e495edc39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2788293280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.2788293280
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.4121748107
Short name T584
Test name
Test status
Simulation time 262394315001 ps
CPU time 202.96 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:17:08 PM PDT 24
Peak memory 199908 kb
Host smart-3e2d2474-4099-4e09-b61c-eedab4d5c083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121748107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.4121748107
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.2658646528
Short name T481
Test name
Test status
Simulation time 3559980178 ps
CPU time 5.59 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:13:50 PM PDT 24
Peak memory 196812 kb
Host smart-9e4e9c4d-7ccd-4cce-b932-7f22bd0c13ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658646528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.2658646528
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.963192697
Short name T1080
Test name
Test status
Simulation time 5762109373 ps
CPU time 17.16 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:14:04 PM PDT 24
Peak memory 199232 kb
Host smart-913001b3-96d9-431c-9502-6c428cf8bd8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963192697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.963192697
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1158431132
Short name T544
Test name
Test status
Simulation time 106315217091 ps
CPU time 178.58 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:16:46 PM PDT 24
Peak memory 200172 kb
Host smart-738de1bc-863b-47be-bef4-0b31943d12c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158431132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1158431132
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.2966925219
Short name T1159
Test name
Test status
Simulation time 108432020820 ps
CPU time 1572.69 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:39:58 PM PDT 24
Peak memory 228744 kb
Host smart-84523cb9-c644-443c-bd50-3e70bbfb0272
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966925219 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.2966925219
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.3778918489
Short name T62
Test name
Test status
Simulation time 1221952804 ps
CPU time 2.01 seconds
Started Jul 29 07:13:44 PM PDT 24
Finished Jul 29 07:13:46 PM PDT 24
Peak memory 199416 kb
Host smart-f10cba4d-d850-4a9d-9ba3-58984a42001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778918489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.3778918489
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3143312188
Short name T1161
Test name
Test status
Simulation time 146222111337 ps
CPU time 83.93 seconds
Started Jul 29 07:13:46 PM PDT 24
Finished Jul 29 07:15:10 PM PDT 24
Peak memory 199936 kb
Host smart-1662995f-9514-4603-983d-a86c31167b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143312188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3143312188
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.3160892723
Short name T320
Test name
Test status
Simulation time 18828461024 ps
CPU time 14.29 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 199260 kb
Host smart-0ca3e1a7-aeb5-4790-9e3d-d9a069ede30d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160892723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.3160892723
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3265560172
Short name T244
Test name
Test status
Simulation time 14295809283 ps
CPU time 21.49 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:29:55 PM PDT 24
Peak memory 199960 kb
Host smart-442a064d-3988-4992-93af-e6c0bdf5d9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265560172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3265560172
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.2529490878
Short name T986
Test name
Test status
Simulation time 221621123094 ps
CPU time 78.26 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:30:52 PM PDT 24
Peak memory 199908 kb
Host smart-e66852be-9c3d-422d-91dc-f661a2a02cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529490878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.2529490878
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.1422482976
Short name T38
Test name
Test status
Simulation time 136164458606 ps
CPU time 14.77 seconds
Started Jul 29 07:29:34 PM PDT 24
Finished Jul 29 07:29:49 PM PDT 24
Peak memory 199876 kb
Host smart-ba1d95b4-a186-4eed-9ac3-802029fcc819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422482976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1422482976
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3190355227
Short name T889
Test name
Test status
Simulation time 132317150000 ps
CPU time 425.77 seconds
Started Jul 29 07:29:33 PM PDT 24
Finished Jul 29 07:36:39 PM PDT 24
Peak memory 199960 kb
Host smart-2b5bdfb2-b240-4e96-9557-422799517d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190355227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3190355227
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.788366110
Short name T854
Test name
Test status
Simulation time 41206404213 ps
CPU time 39.26 seconds
Started Jul 29 07:29:32 PM PDT 24
Finished Jul 29 07:30:11 PM PDT 24
Peak memory 200032 kb
Host smart-b0351203-9863-49d4-8ef6-00bf6ddb9b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788366110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.788366110
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.4134546488
Short name T233
Test name
Test status
Simulation time 48451155325 ps
CPU time 7.03 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:29:48 PM PDT 24
Peak memory 199924 kb
Host smart-e2a75523-419c-4dbe-aa24-d1176f4be420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134546488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4134546488
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2924996534
Short name T675
Test name
Test status
Simulation time 196853702616 ps
CPU time 51.85 seconds
Started Jul 29 07:29:36 PM PDT 24
Finished Jul 29 07:30:28 PM PDT 24
Peak memory 199980 kb
Host smart-075d0697-eb66-45f8-9ab3-d93b70eac8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924996534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2924996534
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.1379890188
Short name T772
Test name
Test status
Simulation time 11042662 ps
CPU time 0.56 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:13:59 PM PDT 24
Peak memory 195356 kb
Host smart-0777eba6-d8d9-4078-9b2c-c1b3d84102b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379890188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.1379890188
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.3854961390
Short name T622
Test name
Test status
Simulation time 143026274178 ps
CPU time 228.07 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:17:33 PM PDT 24
Peak memory 200020 kb
Host smart-393eb7d6-750c-4008-a293-fbab491e6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854961390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.3854961390
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.206158078
Short name T485
Test name
Test status
Simulation time 61223760403 ps
CPU time 48.15 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:14:35 PM PDT 24
Peak memory 199844 kb
Host smart-d279da2e-b99f-4561-a76b-1bc2e2d6621c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206158078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.206158078
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2393345002
Short name T750
Test name
Test status
Simulation time 99467065838 ps
CPU time 144.37 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:16:12 PM PDT 24
Peak memory 199912 kb
Host smart-8d5bf5e1-0fbc-49e4-8d04-c7f2e6046bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393345002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2393345002
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.4142313795
Short name T499
Test name
Test status
Simulation time 27265705446 ps
CPU time 48.37 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:14:36 PM PDT 24
Peak memory 199928 kb
Host smart-440a65e5-f1c5-46ac-9300-8a4124b60113
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142313795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.4142313795
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1466272606
Short name T1156
Test name
Test status
Simulation time 311911232169 ps
CPU time 228.41 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:17:45 PM PDT 24
Peak memory 199896 kb
Host smart-3ad5ad6f-31af-465a-b1b5-0cc4fd064461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1466272606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1466272606
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1016313730
Short name T628
Test name
Test status
Simulation time 5858231264 ps
CPU time 11.92 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:14:08 PM PDT 24
Peak memory 199660 kb
Host smart-bc14d2cd-2cdc-410f-8bb0-54c5333c22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016313730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1016313730
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.801532402
Short name T532
Test name
Test status
Simulation time 140825452789 ps
CPU time 59.38 seconds
Started Jul 29 07:13:47 PM PDT 24
Finished Jul 29 07:14:47 PM PDT 24
Peak memory 200060 kb
Host smart-0943ad15-c551-494c-b411-fe1a70f0929e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801532402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.801532402
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2968443989
Short name T621
Test name
Test status
Simulation time 22752502321 ps
CPU time 244.82 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:18:00 PM PDT 24
Peak memory 199968 kb
Host smart-f2d1c031-51f6-41b3-8ff2-6858762ba9af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968443989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2968443989
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.16216382
Short name T355
Test name
Test status
Simulation time 2010634160 ps
CPU time 9.6 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:13:54 PM PDT 24
Peak memory 197972 kb
Host smart-b77fb998-91d0-4891-921c-2e2e92086c80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=16216382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.16216382
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.830192900
Short name T907
Test name
Test status
Simulation time 21568539031 ps
CPU time 32.6 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:14:27 PM PDT 24
Peak memory 199988 kb
Host smart-b7a8f833-9c99-4469-879a-551c09266537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830192900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.830192900
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3926904108
Short name T1119
Test name
Test status
Simulation time 34828979704 ps
CPU time 8.91 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:13:57 PM PDT 24
Peak memory 196244 kb
Host smart-bb6fdb50-ea56-4be9-8a04-93de84499bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926904108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3926904108
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.3018793880
Short name T761
Test name
Test status
Simulation time 924681908 ps
CPU time 1.76 seconds
Started Jul 29 07:13:48 PM PDT 24
Finished Jul 29 07:13:50 PM PDT 24
Peak memory 199876 kb
Host smart-f640dff8-d779-4c55-bd46-96caa60c5dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018793880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.3018793880
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.4164335941
Short name T115
Test name
Test status
Simulation time 296638115824 ps
CPU time 361.38 seconds
Started Jul 29 07:13:54 PM PDT 24
Finished Jul 29 07:19:56 PM PDT 24
Peak memory 199972 kb
Host smart-22750b5b-10d5-4401-a0ef-ec2c8ef40a5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164335941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.4164335941
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.2403460300
Short name T475
Test name
Test status
Simulation time 758424205 ps
CPU time 4.1 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:14:02 PM PDT 24
Peak memory 198896 kb
Host smart-cd0fd579-e4e9-4262-8901-7f2565e4c72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403460300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.2403460300
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.2853092838
Short name T970
Test name
Test status
Simulation time 63552434828 ps
CPU time 13.15 seconds
Started Jul 29 07:13:45 PM PDT 24
Finished Jul 29 07:13:59 PM PDT 24
Peak memory 199892 kb
Host smart-099941da-ca9e-4190-a31b-a76b3a692050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853092838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.2853092838
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.1086220229
Short name T873
Test name
Test status
Simulation time 166881714450 ps
CPU time 221.92 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 199904 kb
Host smart-9eea411d-fa4f-47bb-8008-a29324648695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086220229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.1086220229
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1872139274
Short name T459
Test name
Test status
Simulation time 29263147891 ps
CPU time 36.3 seconds
Started Jul 29 07:29:39 PM PDT 24
Finished Jul 29 07:30:16 PM PDT 24
Peak memory 199880 kb
Host smart-935f1001-7b0a-42f6-bfb6-44178c046002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872139274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1872139274
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1933687164
Short name T1114
Test name
Test status
Simulation time 62057308758 ps
CPU time 13.56 seconds
Started Jul 29 07:29:38 PM PDT 24
Finished Jul 29 07:29:51 PM PDT 24
Peak memory 199952 kb
Host smart-ac76c5bc-1a96-4960-9cea-6ad2ceb28aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933687164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1933687164
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3871491701
Short name T766
Test name
Test status
Simulation time 19858411033 ps
CPU time 21.24 seconds
Started Jul 29 07:29:39 PM PDT 24
Finished Jul 29 07:30:00 PM PDT 24
Peak memory 199936 kb
Host smart-5dde7a72-eced-4882-8751-762676af6d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871491701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3871491701
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.939387646
Short name T566
Test name
Test status
Simulation time 308930169509 ps
CPU time 131.32 seconds
Started Jul 29 07:29:38 PM PDT 24
Finished Jul 29 07:31:49 PM PDT 24
Peak memory 199968 kb
Host smart-edea6e1f-eaee-4cbc-b321-e87c013b217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939387646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.939387646
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.713559720
Short name T673
Test name
Test status
Simulation time 164088792749 ps
CPU time 136.69 seconds
Started Jul 29 07:29:37 PM PDT 24
Finished Jul 29 07:31:53 PM PDT 24
Peak memory 199912 kb
Host smart-3ccacedd-f8e0-4896-b465-40af6ba687fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713559720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.713559720
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.3294912219
Short name T1077
Test name
Test status
Simulation time 26665665677 ps
CPU time 51.03 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:30:32 PM PDT 24
Peak memory 199912 kb
Host smart-11f23100-e7f9-4acc-a6fd-3c062f72a998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294912219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.3294912219
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.505718264
Short name T192
Test name
Test status
Simulation time 142056308654 ps
CPU time 22.75 seconds
Started Jul 29 07:29:36 PM PDT 24
Finished Jul 29 07:29:59 PM PDT 24
Peak memory 199852 kb
Host smart-7f93b80d-fe4f-4b33-b331-c0ab395d39d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505718264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.505718264
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3657658755
Short name T614
Test name
Test status
Simulation time 40422287 ps
CPU time 0.56 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:13:56 PM PDT 24
Peak memory 195308 kb
Host smart-d6cf4259-dee5-4086-b938-c24392507489
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657658755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3657658755
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3668441367
Short name T735
Test name
Test status
Simulation time 31449177053 ps
CPU time 40.56 seconds
Started Jul 29 07:13:54 PM PDT 24
Finished Jul 29 07:14:35 PM PDT 24
Peak memory 199740 kb
Host smart-a56d2df3-0d8d-4142-98fa-1cbc3eb4e404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668441367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3668441367
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2847163101
Short name T1177
Test name
Test status
Simulation time 24017552541 ps
CPU time 17.65 seconds
Started Jul 29 07:13:57 PM PDT 24
Finished Jul 29 07:14:15 PM PDT 24
Peak memory 199920 kb
Host smart-23cc1ac3-d3c2-4add-b49c-d6c0bf2ca140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847163101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2847163101
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.283333618
Short name T431
Test name
Test status
Simulation time 17787775616 ps
CPU time 11.38 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:14:10 PM PDT 24
Peak memory 199632 kb
Host smart-d484f67b-d4d2-41c4-8216-1e9be1ad3ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283333618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.283333618
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.4228364179
Short name T866
Test name
Test status
Simulation time 8798063893 ps
CPU time 5.1 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:14:00 PM PDT 24
Peak memory 199476 kb
Host smart-9df7ae3c-b1c3-4868-992f-246528912ba8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228364179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.4228364179
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2582937079
Short name T754
Test name
Test status
Simulation time 130108400815 ps
CPU time 624.51 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:24:20 PM PDT 24
Peak memory 199940 kb
Host smart-7079a078-5edc-47cb-8ceb-a5fee2827c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582937079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2582937079
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2494915857
Short name T672
Test name
Test status
Simulation time 11511390278 ps
CPU time 23.1 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:14:19 PM PDT 24
Peak memory 198920 kb
Host smart-71818be6-edf2-4509-a1e4-0415582fa8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494915857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2494915857
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.2612900853
Short name T652
Test name
Test status
Simulation time 8687619171 ps
CPU time 12.77 seconds
Started Jul 29 07:13:57 PM PDT 24
Finished Jul 29 07:14:10 PM PDT 24
Peak memory 199888 kb
Host smart-dc304064-e4e3-4615-8c7c-9ff9a26fe4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612900853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.2612900853
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.765320601
Short name T682
Test name
Test status
Simulation time 30967542418 ps
CPU time 186.39 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:17:03 PM PDT 24
Peak memory 199972 kb
Host smart-d9eed36e-d923-46a9-975c-e0997661ad96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=765320601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.765320601
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.656237687
Short name T460
Test name
Test status
Simulation time 2332425063 ps
CPU time 3.63 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:14:00 PM PDT 24
Peak memory 199008 kb
Host smart-722adf2d-75bf-48fb-a412-2981118239fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=656237687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.656237687
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1345348282
Short name T1131
Test name
Test status
Simulation time 97445806061 ps
CPU time 101.24 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:15:39 PM PDT 24
Peak memory 199904 kb
Host smart-21ae5ec6-ad36-44ed-9a4e-e775220d14e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345348282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1345348282
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2100930511
Short name T505
Test name
Test status
Simulation time 1893727519 ps
CPU time 2.11 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:13:57 PM PDT 24
Peak memory 195668 kb
Host smart-7cdb1f64-2988-4be5-9d2a-5808bb33852a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100930511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2100930511
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.3103654634
Short name T356
Test name
Test status
Simulation time 339793675 ps
CPU time 1.19 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:13:59 PM PDT 24
Peak memory 198384 kb
Host smart-ef9fd922-eaa7-4214-ac84-e027b1e023ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103654634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.3103654634
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2475400433
Short name T706
Test name
Test status
Simulation time 170925057151 ps
CPU time 81.59 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:15:19 PM PDT 24
Peak memory 199904 kb
Host smart-f6b552f7-5eba-4121-acec-9555e4a72658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475400433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2475400433
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.738856150
Short name T54
Test name
Test status
Simulation time 374744023022 ps
CPU time 1041.67 seconds
Started Jul 29 07:13:59 PM PDT 24
Finished Jul 29 07:31:21 PM PDT 24
Peak memory 216472 kb
Host smart-290715a4-5cd6-4e9b-b571-f241d067f116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738856150 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.738856150
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2313780825
Short name T920
Test name
Test status
Simulation time 6319393133 ps
CPU time 16.25 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:14:15 PM PDT 24
Peak memory 199752 kb
Host smart-0aeca7f9-f8d4-41fb-889c-bdf942f1b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313780825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2313780825
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2055738977
Short name T908
Test name
Test status
Simulation time 22390071448 ps
CPU time 32.59 seconds
Started Jul 29 07:13:59 PM PDT 24
Finished Jul 29 07:14:32 PM PDT 24
Peak memory 199956 kb
Host smart-ea9f3149-ce01-4d5a-9aea-dfc97e960a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055738977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2055738977
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3449607048
Short name T539
Test name
Test status
Simulation time 26445922971 ps
CPU time 21.66 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:30:03 PM PDT 24
Peak memory 199852 kb
Host smart-d64c7f60-1821-4fa6-8951-f07ab89a27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449607048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3449607048
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2440440764
Short name T852
Test name
Test status
Simulation time 24842517903 ps
CPU time 9.17 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:29:50 PM PDT 24
Peak memory 199124 kb
Host smart-9e51c34c-717d-4de6-bc3a-b55a6fa9b0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440440764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2440440764
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.980399452
Short name T965
Test name
Test status
Simulation time 12085605480 ps
CPU time 13.44 seconds
Started Jul 29 07:29:39 PM PDT 24
Finished Jul 29 07:29:52 PM PDT 24
Peak memory 199880 kb
Host smart-eff5c783-583b-4526-a889-cc4f356874c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980399452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.980399452
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2252922781
Short name T199
Test name
Test status
Simulation time 111876955232 ps
CPU time 156.18 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:32:17 PM PDT 24
Peak memory 199920 kb
Host smart-6a23a206-53b3-4b4f-a352-c6f5796a63b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252922781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2252922781
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.735808327
Short name T497
Test name
Test status
Simulation time 36130296996 ps
CPU time 56.56 seconds
Started Jul 29 07:29:37 PM PDT 24
Finished Jul 29 07:30:34 PM PDT 24
Peak memory 199912 kb
Host smart-f6dda798-7451-4435-b3fe-d2474534fe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735808327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.735808327
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.4031870963
Short name T830
Test name
Test status
Simulation time 12106581028 ps
CPU time 23.17 seconds
Started Jul 29 07:29:52 PM PDT 24
Finished Jul 29 07:30:16 PM PDT 24
Peak memory 199632 kb
Host smart-8ac5c523-d7ce-466f-9b5a-ae03541aea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031870963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.4031870963
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.898841814
Short name T1167
Test name
Test status
Simulation time 10219004456 ps
CPU time 9.05 seconds
Started Jul 29 07:29:42 PM PDT 24
Finished Jul 29 07:29:51 PM PDT 24
Peak memory 199892 kb
Host smart-c7715bf0-0c40-4eae-92a4-e4a7b9857e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898841814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.898841814
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.1647860511
Short name T1012
Test name
Test status
Simulation time 35889635835 ps
CPU time 30.46 seconds
Started Jul 29 07:29:49 PM PDT 24
Finished Jul 29 07:30:19 PM PDT 24
Peak memory 199976 kb
Host smart-60de993a-b293-4b64-bdfb-31db1876fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647860511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1647860511
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.1593723962
Short name T260
Test name
Test status
Simulation time 54713988591 ps
CPU time 39.08 seconds
Started Jul 29 07:29:52 PM PDT 24
Finished Jul 29 07:30:31 PM PDT 24
Peak memory 199512 kb
Host smart-e79b81de-1b7c-425d-b240-d6706011bfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593723962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1593723962
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3525731053
Short name T983
Test name
Test status
Simulation time 12450037 ps
CPU time 0.55 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 195800 kb
Host smart-650786e6-058a-497b-8a58-64ef7a39bc74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525731053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3525731053
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2602926927
Short name T803
Test name
Test status
Simulation time 23898430851 ps
CPU time 14.24 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:14:10 PM PDT 24
Peak memory 199868 kb
Host smart-69732ec4-96dd-4605-9bc7-1ff9d12be014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602926927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2602926927
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3472767242
Short name T147
Test name
Test status
Simulation time 199805101843 ps
CPU time 147.17 seconds
Started Jul 29 07:13:56 PM PDT 24
Finished Jul 29 07:16:23 PM PDT 24
Peak memory 199940 kb
Host smart-7aabf9f3-fa6a-46af-bc22-dddff233fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472767242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3472767242
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2355088265
Short name T155
Test name
Test status
Simulation time 96558748946 ps
CPU time 84.79 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:15:23 PM PDT 24
Peak memory 199932 kb
Host smart-e54aa8bb-ac7d-4e30-ad8d-6ff4dd370376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355088265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2355088265
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1220433234
Short name T885
Test name
Test status
Simulation time 247400300146 ps
CPU time 362.82 seconds
Started Jul 29 07:13:54 PM PDT 24
Finished Jul 29 07:19:57 PM PDT 24
Peak memory 199472 kb
Host smart-e378d86c-d0c3-4770-8274-10fb4efc7e2a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220433234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1220433234
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.2418791071
Short name T401
Test name
Test status
Simulation time 116875806519 ps
CPU time 125.9 seconds
Started Jul 29 07:14:07 PM PDT 24
Finished Jul 29 07:16:13 PM PDT 24
Peak memory 199992 kb
Host smart-9531e3d6-3094-4c96-b1c8-eb6147166348
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418791071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.2418791071
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.4185970071
Short name T1029
Test name
Test status
Simulation time 9730536637 ps
CPU time 30.53 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:36 PM PDT 24
Peak memory 199776 kb
Host smart-f645d38e-5683-4eb5-8986-b3eb3ab8dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185970071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.4185970071
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.342884330
Short name T403
Test name
Test status
Simulation time 325551699625 ps
CPU time 29.31 seconds
Started Jul 29 07:13:57 PM PDT 24
Finished Jul 29 07:14:27 PM PDT 24
Peak memory 200052 kb
Host smart-560d16cb-7d8a-4508-9d32-96d9fd46749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342884330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.342884330
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2453040116
Short name T513
Test name
Test status
Simulation time 14163085407 ps
CPU time 197.32 seconds
Started Jul 29 07:14:07 PM PDT 24
Finished Jul 29 07:17:24 PM PDT 24
Peak memory 199944 kb
Host smart-7cdf827b-eee3-427d-9c27-d476250aeb43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2453040116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2453040116
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.872106553
Short name T488
Test name
Test status
Simulation time 4920316167 ps
CPU time 40.16 seconds
Started Jul 29 07:13:57 PM PDT 24
Finished Jul 29 07:14:37 PM PDT 24
Peak memory 199128 kb
Host smart-2eca1d86-23c0-4ac6-bafa-57327d87d1cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872106553 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.872106553
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.1981444248
Short name T827
Test name
Test status
Simulation time 12469976067 ps
CPU time 20.58 seconds
Started Jul 29 07:14:04 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 199832 kb
Host smart-22dcf10d-7657-49db-8116-3dbb679201b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981444248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.1981444248
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.2031908717
Short name T607
Test name
Test status
Simulation time 40397817170 ps
CPU time 29.79 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:34 PM PDT 24
Peak memory 195820 kb
Host smart-ff1a6bff-4ba0-4be1-8137-079a6461504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031908717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.2031908717
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.469976583
Short name T818
Test name
Test status
Simulation time 295959900 ps
CPU time 1.48 seconds
Started Jul 29 07:13:58 PM PDT 24
Finished Jul 29 07:14:00 PM PDT 24
Peak memory 198168 kb
Host smart-5d1c54b9-ead9-4ce6-b227-b89da80e2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469976583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.469976583
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3416424077
Short name T909
Test name
Test status
Simulation time 319614053613 ps
CPU time 1314 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:35:59 PM PDT 24
Peak memory 199912 kb
Host smart-da93f871-169f-4059-9e63-49dbcd40fbfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416424077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3416424077
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.2325632638
Short name T212
Test name
Test status
Simulation time 43982163944 ps
CPU time 338.69 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:19:44 PM PDT 24
Peak memory 208720 kb
Host smart-2560220e-381a-4eb5-8027-a1dcd7d8d352
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325632638 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.2325632638
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.576293890
Short name T689
Test name
Test status
Simulation time 1583304420 ps
CPU time 2.25 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:07 PM PDT 24
Peak memory 198136 kb
Host smart-475d1ab9-1bec-49f4-817d-364fccda2463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576293890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.576293890
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1534110866
Short name T719
Test name
Test status
Simulation time 30765511865 ps
CPU time 45.19 seconds
Started Jul 29 07:13:55 PM PDT 24
Finished Jul 29 07:14:41 PM PDT 24
Peak memory 199980 kb
Host smart-a1ef0145-6e12-4fc2-987e-8b17b95f1959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534110866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1534110866
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1889946863
Short name T371
Test name
Test status
Simulation time 14496914866 ps
CPU time 28.74 seconds
Started Jul 29 07:29:49 PM PDT 24
Finished Jul 29 07:30:18 PM PDT 24
Peak memory 200036 kb
Host smart-93240a6f-3550-4481-88bd-711761694aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889946863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1889946863
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1035004585
Short name T1036
Test name
Test status
Simulation time 37935087694 ps
CPU time 52.14 seconds
Started Jul 29 07:29:41 PM PDT 24
Finished Jul 29 07:30:33 PM PDT 24
Peak memory 199884 kb
Host smart-d361726e-1ecd-4f3c-a9a1-5ac819df02e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035004585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1035004585
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2215528364
Short name T150
Test name
Test status
Simulation time 142792363672 ps
CPU time 61.89 seconds
Started Jul 29 07:29:43 PM PDT 24
Finished Jul 29 07:30:45 PM PDT 24
Peak memory 199976 kb
Host smart-0213ad89-4cfc-42f5-af8d-9943a6b137fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215528364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2215528364
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2803014041
Short name T139
Test name
Test status
Simulation time 18286404631 ps
CPU time 30.26 seconds
Started Jul 29 07:29:43 PM PDT 24
Finished Jul 29 07:30:13 PM PDT 24
Peak memory 199916 kb
Host smart-b63ad0ec-1255-4dbb-b391-9843f544885c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803014041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2803014041
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3050684361
Short name T273
Test name
Test status
Simulation time 43045940138 ps
CPU time 29.94 seconds
Started Jul 29 07:29:49 PM PDT 24
Finished Jul 29 07:30:19 PM PDT 24
Peak memory 200036 kb
Host smart-a8a31d8a-dba4-4ad9-84b8-b59d0f3fd37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050684361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3050684361
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1342815906
Short name T197
Test name
Test status
Simulation time 39845679806 ps
CPU time 29.31 seconds
Started Jul 29 07:29:42 PM PDT 24
Finished Jul 29 07:30:12 PM PDT 24
Peak memory 199916 kb
Host smart-9dd036d7-00d2-498c-af2b-0fc52b4511c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342815906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1342815906
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1429101305
Short name T862
Test name
Test status
Simulation time 29687659886 ps
CPU time 13.1 seconds
Started Jul 29 07:29:49 PM PDT 24
Finished Jul 29 07:30:02 PM PDT 24
Peak memory 199976 kb
Host smart-6ebe02ae-acad-42c1-805f-4e95ccb01324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429101305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1429101305
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.312875411
Short name T608
Test name
Test status
Simulation time 22073593350 ps
CPU time 8.37 seconds
Started Jul 29 07:29:45 PM PDT 24
Finished Jul 29 07:29:53 PM PDT 24
Peak memory 199860 kb
Host smart-c3f6b93e-0984-4230-811b-2bf04eebb465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312875411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.312875411
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.2894850349
Short name T457
Test name
Test status
Simulation time 18870686820 ps
CPU time 15.91 seconds
Started Jul 29 07:29:52 PM PDT 24
Finished Jul 29 07:30:08 PM PDT 24
Peak memory 199928 kb
Host smart-ee67b1c9-2f6e-44a5-9542-45c91adf6faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894850349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.2894850349
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.1192845980
Short name T973
Test name
Test status
Simulation time 20844234 ps
CPU time 0.61 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 194860 kb
Host smart-b3f84f65-3aef-47e7-aced-77aadb36bb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192845980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1192845980
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1363470840
Short name T298
Test name
Test status
Simulation time 66652465494 ps
CPU time 96.79 seconds
Started Jul 29 07:12:20 PM PDT 24
Finished Jul 29 07:13:57 PM PDT 24
Peak memory 199896 kb
Host smart-7570353d-6b5f-4ae7-a7f9-7c9ad6071afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363470840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1363470840
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.481860358
Short name T200
Test name
Test status
Simulation time 34572984973 ps
CPU time 29.82 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:12:58 PM PDT 24
Peak memory 199980 kb
Host smart-7a21bc0c-1c40-4366-a4b8-66e180bcc98f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481860358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.481860358
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.4149637194
Short name T468
Test name
Test status
Simulation time 20235302429 ps
CPU time 9.25 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:33 PM PDT 24
Peak memory 197484 kb
Host smart-391a2db2-36ed-4789-a644-3fb08b3beb08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149637194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4149637194
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1883886754
Short name T543
Test name
Test status
Simulation time 62080883583 ps
CPU time 357.36 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:18:22 PM PDT 24
Peak memory 199864 kb
Host smart-31285a22-6759-499d-9481-f8d49ae47692
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883886754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1883886754
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.2979778128
Short name T1101
Test name
Test status
Simulation time 3674358818 ps
CPU time 22.3 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:12:46 PM PDT 24
Peak memory 198672 kb
Host smart-668f5c72-392e-467a-96a8-cf8e86bd74cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979778128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.2979778128
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3253336842
Short name T786
Test name
Test status
Simulation time 92180875660 ps
CPU time 77.08 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 198680 kb
Host smart-0298cc30-ec96-4cd8-8b84-79149abe3711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253336842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3253336842
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.4269913710
Short name T1136
Test name
Test status
Simulation time 23005286987 ps
CPU time 161.18 seconds
Started Jul 29 07:12:41 PM PDT 24
Finished Jul 29 07:15:22 PM PDT 24
Peak memory 199928 kb
Host smart-5e5744ab-e12f-4b45-978a-9f331978c67b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4269913710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.4269913710
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3115362465
Short name T347
Test name
Test status
Simulation time 6241811679 ps
CPU time 16.11 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:41 PM PDT 24
Peak memory 198104 kb
Host smart-62726fe3-63c8-4344-a2ad-4090d7b330d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115362465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3115362465
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.3529110067
Short name T1000
Test name
Test status
Simulation time 42226360440 ps
CPU time 27.13 seconds
Started Jul 29 07:12:22 PM PDT 24
Finished Jul 29 07:12:50 PM PDT 24
Peak memory 199860 kb
Host smart-e96060a8-eeb1-480f-ad40-89cf7842d587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529110067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.3529110067
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3951217961
Short name T283
Test name
Test status
Simulation time 1433255897 ps
CPU time 1.65 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 195488 kb
Host smart-00ef2d69-5e2a-4323-b154-395a9786d358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951217961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3951217961
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2983627962
Short name T104
Test name
Test status
Simulation time 59144752 ps
CPU time 0.89 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 218464 kb
Host smart-7b32197b-ed39-43fc-948a-b7dae087a116
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983627962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2983627962
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1417774425
Short name T1075
Test name
Test status
Simulation time 565917850 ps
CPU time 0.95 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:12:24 PM PDT 24
Peak memory 198392 kb
Host smart-eddb7953-9604-4201-ae7c-d4d7f00ede37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417774425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1417774425
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3714966318
Short name T68
Test name
Test status
Simulation time 21410875186 ps
CPU time 259.88 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:16:45 PM PDT 24
Peak memory 215496 kb
Host smart-00116aa4-6f1a-413f-acbd-dfdd9fd43319
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714966318 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3714966318
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.155662435
Short name T1086
Test name
Test status
Simulation time 1132117453 ps
CPU time 2.13 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:26 PM PDT 24
Peak memory 198812 kb
Host smart-061cc4c4-304a-43e7-a113-3f54ae8f569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155662435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.155662435
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.112411226
Short name T373
Test name
Test status
Simulation time 22826680797 ps
CPU time 39.37 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:13:03 PM PDT 24
Peak memory 199932 kb
Host smart-d144c6a6-f23e-422d-aeef-96056adbf9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112411226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.112411226
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1068658126
Short name T705
Test name
Test status
Simulation time 38640792 ps
CPU time 0.56 seconds
Started Jul 29 07:14:04 PM PDT 24
Finished Jul 29 07:14:05 PM PDT 24
Peak memory 195296 kb
Host smart-db407f34-edc2-4e27-8085-adfb64aef1f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068658126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1068658126
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.1507422110
Short name T303
Test name
Test status
Simulation time 24349273208 ps
CPU time 40.37 seconds
Started Jul 29 07:14:06 PM PDT 24
Finished Jul 29 07:14:46 PM PDT 24
Peak memory 199900 kb
Host smart-982d75cc-7bfc-4de6-a34f-2c0145b03d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507422110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.1507422110
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.545607557
Short name T1072
Test name
Test status
Simulation time 182697014092 ps
CPU time 265.37 seconds
Started Jul 29 07:14:04 PM PDT 24
Finished Jul 29 07:18:30 PM PDT 24
Peak memory 199988 kb
Host smart-3223ff4d-e5aa-4aa2-bd8f-d59788cde4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545607557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.545607557
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1358455889
Short name T1038
Test name
Test status
Simulation time 74595104723 ps
CPU time 19.13 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 199668 kb
Host smart-7f2a873d-619e-4061-83ce-4e6500ffc435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358455889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1358455889
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.3074421204
Short name T957
Test name
Test status
Simulation time 246468593486 ps
CPU time 113.13 seconds
Started Jul 29 07:14:08 PM PDT 24
Finished Jul 29 07:16:01 PM PDT 24
Peak memory 199720 kb
Host smart-0e960537-7461-4f5f-b7e4-35e133411386
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074421204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3074421204
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.579216222
Short name T1014
Test name
Test status
Simulation time 114954955430 ps
CPU time 804.89 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:27:30 PM PDT 24
Peak memory 200000 kb
Host smart-f2947fe2-a4f3-4a2e-88dd-6c8939000d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=579216222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.579216222
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.3765565744
Short name T437
Test name
Test status
Simulation time 8516194424 ps
CPU time 12.92 seconds
Started Jul 29 07:14:09 PM PDT 24
Finished Jul 29 07:14:22 PM PDT 24
Peak memory 199908 kb
Host smart-6f864f1b-e0d1-4019-8a89-b7c54d4b172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765565744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.3765565744
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2038248877
Short name T808
Test name
Test status
Simulation time 65365377392 ps
CPU time 59.93 seconds
Started Jul 29 07:14:07 PM PDT 24
Finished Jul 29 07:15:07 PM PDT 24
Peak memory 208224 kb
Host smart-9ab0bc88-17ca-4374-8fea-6545d5e1488e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038248877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2038248877
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.1972082290
Short name T37
Test name
Test status
Simulation time 17465278558 ps
CPU time 486.97 seconds
Started Jul 29 07:14:06 PM PDT 24
Finished Jul 29 07:22:13 PM PDT 24
Peak memory 199920 kb
Host smart-77b68286-e267-41a8-8cfb-037af6c731a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972082290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.1972082290
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2759182319
Short name T979
Test name
Test status
Simulation time 3032701502 ps
CPU time 18.65 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 199840 kb
Host smart-2d8ee572-fe50-48d8-a794-7ff3e7949168
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2759182319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2759182319
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.1167738272
Short name T562
Test name
Test status
Simulation time 19655528114 ps
CPU time 14.32 seconds
Started Jul 29 07:14:04 PM PDT 24
Finished Jul 29 07:14:19 PM PDT 24
Peak memory 200060 kb
Host smart-9681712c-8a37-408f-8056-ab8dfd7933c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167738272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.1167738272
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.850987638
Short name T346
Test name
Test status
Simulation time 677000843 ps
CPU time 0.91 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:06 PM PDT 24
Peak memory 195456 kb
Host smart-6a32e990-db8a-4466-9282-f1c90aac408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850987638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.850987638
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.3247541854
Short name T302
Test name
Test status
Simulation time 840604941 ps
CPU time 2.83 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:08 PM PDT 24
Peak memory 199832 kb
Host smart-0ba28073-de89-4f48-8ebc-743cfb6683ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247541854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.3247541854
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3379999949
Short name T887
Test name
Test status
Simulation time 162496640789 ps
CPU time 503.92 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:22:29 PM PDT 24
Peak memory 199912 kb
Host smart-e7f3bea8-37d8-4832-a47c-a53bdcda3760
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379999949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3379999949
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2796336115
Short name T663
Test name
Test status
Simulation time 6721011165 ps
CPU time 24.26 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:30 PM PDT 24
Peak memory 199604 kb
Host smart-84a197ed-bd7a-409a-9d85-46d9c8066b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796336115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2796336115
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1932561631
Short name T479
Test name
Test status
Simulation time 43533660048 ps
CPU time 69.25 seconds
Started Jul 29 07:14:06 PM PDT 24
Finished Jul 29 07:15:16 PM PDT 24
Peak memory 200004 kb
Host smart-4e020831-1d1d-4341-a780-c0f95463b4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932561631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1932561631
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.2887639466
Short name T24
Test name
Test status
Simulation time 13338199 ps
CPU time 0.56 seconds
Started Jul 29 07:14:16 PM PDT 24
Finished Jul 29 07:14:17 PM PDT 24
Peak memory 194328 kb
Host smart-7f001d32-c979-4c2a-924f-d616127f048b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887639466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2887639466
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.2484521206
Short name T44
Test name
Test status
Simulation time 38736213039 ps
CPU time 39.62 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:45 PM PDT 24
Peak memory 199956 kb
Host smart-8666b7a4-45f9-4ca8-b9c5-f5e7b3f52c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484521206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.2484521206
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.732136943
Short name T612
Test name
Test status
Simulation time 18790334138 ps
CPU time 24.36 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:14:40 PM PDT 24
Peak memory 198952 kb
Host smart-7f568877-43a0-4af2-ae1c-7a1e427f03e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732136943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.732136943
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2816832227
Short name T561
Test name
Test status
Simulation time 33257550998 ps
CPU time 11.01 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 199960 kb
Host smart-c5e64341-9b4f-4482-9984-20d3ca18024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816832227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2816832227
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.2469283971
Short name T594
Test name
Test status
Simulation time 12047194165 ps
CPU time 5.44 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:14:20 PM PDT 24
Peak memory 198220 kb
Host smart-4f35eea3-a317-4e2b-912e-91db9472d7db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469283971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.2469283971
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2599359306
Short name T5
Test name
Test status
Simulation time 70302615440 ps
CPU time 245.54 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:18:18 PM PDT 24
Peak memory 199924 kb
Host smart-e7efcb54-ee2b-42d3-99b4-35a1ea298173
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2599359306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2599359306
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.3621260715
Short name T429
Test name
Test status
Simulation time 8046551666 ps
CPU time 7.77 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:14:21 PM PDT 24
Peak memory 199972 kb
Host smart-3adbc9c1-5eec-4b2b-9dc1-57ae5f808d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621260715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.3621260715
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2544179597
Short name T638
Test name
Test status
Simulation time 168535924169 ps
CPU time 110.88 seconds
Started Jul 29 07:14:16 PM PDT 24
Finished Jul 29 07:16:07 PM PDT 24
Peak memory 200084 kb
Host smart-08e72aa0-fdb4-498c-bb3b-05e2d185459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544179597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2544179597
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2877045203
Short name T701
Test name
Test status
Simulation time 6031296261 ps
CPU time 49.72 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:15:04 PM PDT 24
Peak memory 199920 kb
Host smart-95ab0e24-2528-4cf4-a98d-082bf06a03b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2877045203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2877045203
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2090852102
Short name T722
Test name
Test status
Simulation time 7200585583 ps
CPU time 63.71 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:15:18 PM PDT 24
Peak memory 198236 kb
Host smart-3e0c9738-1c2e-4de7-b388-782601863388
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090852102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2090852102
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3887120501
Short name T656
Test name
Test status
Simulation time 57097046673 ps
CPU time 70.2 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:15:24 PM PDT 24
Peak memory 199884 kb
Host smart-c261c7a5-9e9f-4800-ad20-f0de8a9d67c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887120501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3887120501
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.1371760207
Short name T616
Test name
Test status
Simulation time 21211383914 ps
CPU time 9.34 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 196212 kb
Host smart-9de88326-f9d9-4e73-af83-b7064d11b1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371760207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.1371760207
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.898987160
Short name T736
Test name
Test status
Simulation time 499387793 ps
CPU time 2.52 seconds
Started Jul 29 07:14:05 PM PDT 24
Finished Jul 29 07:14:08 PM PDT 24
Peak memory 198364 kb
Host smart-73e1c420-1857-4bea-a6b9-262dd33281ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898987160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.898987160
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2830423859
Short name T1037
Test name
Test status
Simulation time 95055680406 ps
CPU time 160.95 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:16:57 PM PDT 24
Peak memory 199972 kb
Host smart-afd8d00a-52ea-47b4-8310-08408df53fd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830423859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2830423859
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.3929238724
Short name T219
Test name
Test status
Simulation time 143449738993 ps
CPU time 671.17 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:25:24 PM PDT 24
Peak memory 224840 kb
Host smart-4cea0435-28f6-4ae9-ace2-0c89ada536c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929238724 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.3929238724
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.2878133200
Short name T848
Test name
Test status
Simulation time 7299411743 ps
CPU time 14.38 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:29 PM PDT 24
Peak memory 199980 kb
Host smart-960d0062-3c08-4288-874d-31d32d2bc191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878133200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2878133200
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3337674281
Short name T1122
Test name
Test status
Simulation time 95358928785 ps
CPU time 24.53 seconds
Started Jul 29 07:14:06 PM PDT 24
Finished Jul 29 07:14:30 PM PDT 24
Peak memory 199932 kb
Host smart-0d9f1004-cc8a-4278-bd3f-8b09a1da1f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337674281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3337674281
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3773098216
Short name T1083
Test name
Test status
Simulation time 35525786 ps
CPU time 0.57 seconds
Started Jul 29 07:14:16 PM PDT 24
Finished Jul 29 07:14:17 PM PDT 24
Peak memory 195644 kb
Host smart-b8fd1048-3766-4b5b-bc42-03a116323a2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773098216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3773098216
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.2172788975
Short name T165
Test name
Test status
Simulation time 30969598309 ps
CPU time 54.49 seconds
Started Jul 29 07:14:16 PM PDT 24
Finished Jul 29 07:15:10 PM PDT 24
Peak memory 199940 kb
Host smart-84a8884c-27ab-46a6-ac3d-e4291af9485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172788975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2172788975
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.802959456
Short name T377
Test name
Test status
Simulation time 26984035885 ps
CPU time 43.97 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:58 PM PDT 24
Peak memory 199952 kb
Host smart-54e89842-d93d-4c4b-9a22-d9729d8db42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802959456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.802959456
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3141957144
Short name T764
Test name
Test status
Simulation time 314785848650 ps
CPU time 199.05 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:17:33 PM PDT 24
Peak memory 199920 kb
Host smart-9764571f-17e7-4949-b501-76d507d9d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141957144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3141957144
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2279978209
Short name T352
Test name
Test status
Simulation time 12589355755 ps
CPU time 9.92 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:14:25 PM PDT 24
Peak memory 199968 kb
Host smart-82a960e1-3f16-4c23-98b9-53fc1d47595f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279978209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2279978209
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.263085970
Short name T259
Test name
Test status
Simulation time 164638444797 ps
CPU time 581.7 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:23:55 PM PDT 24
Peak memory 199972 kb
Host smart-db9087d5-b12d-4c6c-85b4-29afe8f1852a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=263085970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.263085970
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1367990899
Short name T1058
Test name
Test status
Simulation time 90460671 ps
CPU time 0.72 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:14:14 PM PDT 24
Peak memory 195868 kb
Host smart-c0c3731d-2e61-413c-abb2-cda3d9e926de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367990899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1367990899
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1304858371
Short name T550
Test name
Test status
Simulation time 77832327513 ps
CPU time 16.02 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:14:34 PM PDT 24
Peak memory 200104 kb
Host smart-27f7c46f-7793-4204-819d-8535c302046c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304858371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1304858371
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1335419915
Short name T387
Test name
Test status
Simulation time 21786760253 ps
CPU time 66.05 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:15:19 PM PDT 24
Peak memory 200112 kb
Host smart-7a29da04-43a3-4178-89ff-7bcb4a9aecec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335419915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1335419915
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.3552999393
Short name T1073
Test name
Test status
Simulation time 3570454216 ps
CPU time 10.37 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:14:24 PM PDT 24
Peak memory 198296 kb
Host smart-1c19a278-9d8b-4bd2-8942-8148f9c4a0a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3552999393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.3552999393
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1842216462
Short name T415
Test name
Test status
Simulation time 49201989096 ps
CPU time 78.72 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:15:36 PM PDT 24
Peak memory 199948 kb
Host smart-02775175-8228-4479-8e9d-8f13a951dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842216462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1842216462
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.593187471
Short name T696
Test name
Test status
Simulation time 2457541160 ps
CPU time 1.3 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:16 PM PDT 24
Peak memory 196012 kb
Host smart-adf78c56-e47d-46ee-bc60-39823888a069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593187471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.593187471
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.204982978
Short name T49
Test name
Test status
Simulation time 664724191 ps
CPU time 1.6 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:14:19 PM PDT 24
Peak memory 198704 kb
Host smart-f8ad43cf-8a31-4255-be5c-2a05cfec7332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204982978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.204982978
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1928218149
Short name T504
Test name
Test status
Simulation time 16170509256 ps
CPU time 196.53 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:17:34 PM PDT 24
Peak memory 215956 kb
Host smart-87899a0e-981c-4ba9-86f0-6cb99652f0f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928218149 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1928218149
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.826253650
Short name T782
Test name
Test status
Simulation time 3051646150 ps
CPU time 2.9 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:14:20 PM PDT 24
Peak memory 198916 kb
Host smart-cd1246f3-402e-4598-9a87-cd3287f843a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826253650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.826253650
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.4000010892
Short name T760
Test name
Test status
Simulation time 46611851279 ps
CPU time 90.43 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:15:43 PM PDT 24
Peak memory 199856 kb
Host smart-ce9c19c1-bfc5-4fb5-abf3-2b3dc47b767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000010892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.4000010892
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.526059978
Short name T583
Test name
Test status
Simulation time 15798897 ps
CPU time 0.59 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:29 PM PDT 24
Peak memory 195628 kb
Host smart-1d8fa0c1-4956-410e-9169-f1a877e79e88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526059978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.526059978
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.187070009
Short name T913
Test name
Test status
Simulation time 276411467451 ps
CPU time 163.3 seconds
Started Jul 29 07:14:17 PM PDT 24
Finished Jul 29 07:17:01 PM PDT 24
Peak memory 199944 kb
Host smart-76f5c2fa-14ef-451b-b296-c73679b269bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187070009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.187070009
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.4089584882
Short name T810
Test name
Test status
Simulation time 167464739806 ps
CPU time 32.71 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:47 PM PDT 24
Peak memory 199948 kb
Host smart-ec8ee44d-2cb4-4727-85d0-db564b67a69a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089584882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.4089584882
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2276579747
Short name T639
Test name
Test status
Simulation time 23692638823 ps
CPU time 17.55 seconds
Started Jul 29 07:14:16 PM PDT 24
Finished Jul 29 07:14:34 PM PDT 24
Peak memory 199852 kb
Host smart-6ce40e06-0272-445b-a537-5a7e5b07c4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276579747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2276579747
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2023649624
Short name T306
Test name
Test status
Simulation time 97178631328 ps
CPU time 269.55 seconds
Started Jul 29 07:14:13 PM PDT 24
Finished Jul 29 07:18:43 PM PDT 24
Peak memory 199888 kb
Host smart-592bcf9f-eff5-47c0-af3a-0b0b39b3a8b7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023649624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2023649624
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.1825583776
Short name T981
Test name
Test status
Simulation time 36368224388 ps
CPU time 227.77 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:18:17 PM PDT 24
Peak memory 200124 kb
Host smart-e29e6835-b5da-473c-ae5e-62769aac0387
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1825583776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.1825583776
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3456892094
Short name T624
Test name
Test status
Simulation time 8199717521 ps
CPU time 8.89 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:37 PM PDT 24
Peak memory 199660 kb
Host smart-3cbf2569-0290-416c-bcd5-7f00e410d452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456892094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3456892094
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4137115704
Short name T704
Test name
Test status
Simulation time 161132017134 ps
CPU time 84.15 seconds
Started Jul 29 07:14:30 PM PDT 24
Finished Jul 29 07:15:54 PM PDT 24
Peak memory 200112 kb
Host smart-84f6a404-847d-4b39-bd64-32248a280260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137115704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4137115704
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.2454565427
Short name T1004
Test name
Test status
Simulation time 16714609036 ps
CPU time 224.52 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:18:14 PM PDT 24
Peak memory 199972 kb
Host smart-4d0aa729-11aa-4380-b736-e45b9fcb7fd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2454565427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2454565427
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.441992633
Short name T864
Test name
Test status
Simulation time 2729225097 ps
CPU time 4.04 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:14:19 PM PDT 24
Peak memory 198100 kb
Host smart-71981cf7-0e20-44ab-8cb9-6a8ea90e0527
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=441992633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.441992633
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3549383371
Short name T753
Test name
Test status
Simulation time 125175748980 ps
CPU time 179.61 seconds
Started Jul 29 07:14:27 PM PDT 24
Finished Jul 29 07:17:27 PM PDT 24
Peak memory 199924 kb
Host smart-0f275a35-b91d-4e30-a9d4-93d412008a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549383371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3549383371
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2092623376
Short name T316
Test name
Test status
Simulation time 4148045145 ps
CPU time 1.13 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:14:30 PM PDT 24
Peak memory 196252 kb
Host smart-03f0b08d-f6e5-4159-802f-f26495a47b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092623376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2092623376
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2704503267
Short name T416
Test name
Test status
Simulation time 104602145 ps
CPU time 0.88 seconds
Started Jul 29 07:14:14 PM PDT 24
Finished Jul 29 07:14:15 PM PDT 24
Peak memory 196896 kb
Host smart-ba0332f2-65cd-436f-b028-33342cedc7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704503267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2704503267
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3181017688
Short name T1064
Test name
Test status
Simulation time 527499110234 ps
CPU time 218.92 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:18:07 PM PDT 24
Peak memory 216408 kb
Host smart-718b738c-58bf-46ff-9afc-36e89597d3d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181017688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3181017688
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.627672436
Short name T781
Test name
Test status
Simulation time 748241270 ps
CPU time 2.78 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:31 PM PDT 24
Peak memory 199696 kb
Host smart-19d2ed36-4683-43a9-8a69-88c02cfe4f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627672436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.627672436
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1531329780
Short name T257
Test name
Test status
Simulation time 130446928773 ps
CPU time 97.97 seconds
Started Jul 29 07:14:15 PM PDT 24
Finished Jul 29 07:15:53 PM PDT 24
Peak memory 199984 kb
Host smart-72739089-0f80-45a6-8fae-b2fe9535b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531329780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1531329780
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3500336633
Short name T527
Test name
Test status
Simulation time 14078278 ps
CPU time 0.57 seconds
Started Jul 29 07:14:27 PM PDT 24
Finished Jul 29 07:14:28 PM PDT 24
Peak memory 195632 kb
Host smart-e70b72cf-32ba-4bec-b349-dadb925d507e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500336633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3500336633
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.3975459385
Short name T336
Test name
Test status
Simulation time 107104309238 ps
CPU time 66.93 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:15:36 PM PDT 24
Peak memory 199976 kb
Host smart-36815a0d-bc79-4921-a5e9-b4813aa8227c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975459385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.3975459385
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.144109874
Short name T944
Test name
Test status
Simulation time 67161023130 ps
CPU time 55.93 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:15:25 PM PDT 24
Peak memory 199960 kb
Host smart-ea328bf0-4673-4ba1-98b0-cba3b6abcc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144109874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.144109874
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1064097584
Short name T201
Test name
Test status
Simulation time 22721507042 ps
CPU time 7.7 seconds
Started Jul 29 07:14:30 PM PDT 24
Finished Jul 29 07:14:38 PM PDT 24
Peak memory 199924 kb
Host smart-cc0433db-b263-4a71-9794-ffb4158f51f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064097584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1064097584
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1008417374
Short name T301
Test name
Test status
Simulation time 9042311595 ps
CPU time 16.61 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:14:45 PM PDT 24
Peak memory 199964 kb
Host smart-82b04de4-108f-48f2-9cd1-14f8308a6a5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008417374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1008417374
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.2039710230
Short name T964
Test name
Test status
Simulation time 96306159182 ps
CPU time 93.22 seconds
Started Jul 29 07:14:27 PM PDT 24
Finished Jul 29 07:16:01 PM PDT 24
Peak memory 199940 kb
Host smart-f208802d-7752-4238-ae62-74e29242a394
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2039710230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.2039710230
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3755256893
Short name T364
Test name
Test status
Simulation time 126895967 ps
CPU time 0.67 seconds
Started Jul 29 07:14:27 PM PDT 24
Finished Jul 29 07:14:28 PM PDT 24
Peak memory 196924 kb
Host smart-3b08d287-ae0a-41c6-a574-cb532b7f3a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755256893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3755256893
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3202434285
Short name T565
Test name
Test status
Simulation time 149129665759 ps
CPU time 46.51 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:15:16 PM PDT 24
Peak memory 208308 kb
Host smart-76c55f16-82ea-4364-bb3d-91d925b57355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202434285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3202434285
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3184752818
Short name T1019
Test name
Test status
Simulation time 14440109636 ps
CPU time 105.12 seconds
Started Jul 29 07:14:27 PM PDT 24
Finished Jul 29 07:16:12 PM PDT 24
Peak memory 199900 kb
Host smart-ec510ca4-b546-443f-8dea-864c5bc8ef3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3184752818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3184752818
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2051351112
Short name T490
Test name
Test status
Simulation time 7092501475 ps
CPU time 13.34 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:41 PM PDT 24
Peak memory 199660 kb
Host smart-c95bdb60-df08-49fa-b3e5-86d844c8dd04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2051351112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2051351112
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2466467936
Short name T931
Test name
Test status
Simulation time 32854264189 ps
CPU time 70.88 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:15:40 PM PDT 24
Peak memory 199924 kb
Host smart-593522ef-7e90-43c8-8342-623db3a34260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466467936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2466467936
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.248195804
Short name T599
Test name
Test status
Simulation time 6065476198 ps
CPU time 5.4 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:33 PM PDT 24
Peak memory 196080 kb
Host smart-925a2542-b8de-4760-ac29-5a6401359184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248195804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.248195804
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3791108888
Short name T413
Test name
Test status
Simulation time 11066920018 ps
CPU time 23.24 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:51 PM PDT 24
Peak memory 199860 kb
Host smart-926109f5-aee2-4769-bf2b-1ecdd2e3ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791108888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3791108888
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1446029130
Short name T125
Test name
Test status
Simulation time 75530351317 ps
CPU time 635.29 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:25:03 PM PDT 24
Peak memory 199980 kb
Host smart-01390fe8-8b30-4b33-baf2-a3502facd262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446029130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1446029130
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1962776344
Short name T842
Test name
Test status
Simulation time 46083085764 ps
CPU time 519.81 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:23:08 PM PDT 24
Peak memory 226476 kb
Host smart-aa70d1a1-4380-4940-b26b-b5191ff5d9e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962776344 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1962776344
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1434195561
Short name T407
Test name
Test status
Simulation time 7805795272 ps
CPU time 21.81 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:50 PM PDT 24
Peak memory 199880 kb
Host smart-81ee49b2-7253-41c9-9450-7c1a4fd0395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434195561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1434195561
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.444387250
Short name T333
Test name
Test status
Simulation time 6614074347 ps
CPU time 4.91 seconds
Started Jul 29 07:14:28 PM PDT 24
Finished Jul 29 07:14:33 PM PDT 24
Peak memory 197180 kb
Host smart-17142a70-1c75-41c9-ba16-38ce4cde55ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444387250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.444387250
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.1480807197
Short name T1024
Test name
Test status
Simulation time 54419268 ps
CPU time 0.58 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:48 PM PDT 24
Peak memory 195640 kb
Host smart-86026977-1ccd-4370-84fc-a09b1d066803
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480807197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.1480807197
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.1701175150
Short name T1170
Test name
Test status
Simulation time 70781515124 ps
CPU time 31.16 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:15:16 PM PDT 24
Peak memory 199848 kb
Host smart-3384513f-793c-4886-894d-d266a32ed4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701175150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1701175150
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4246449179
Short name T904
Test name
Test status
Simulation time 103777996738 ps
CPU time 726.96 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:26:52 PM PDT 24
Peak memory 200064 kb
Host smart-1ab05389-068e-4cc9-aa83-07eaac5e7adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246449179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4246449179
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1225030865
Short name T1026
Test name
Test status
Simulation time 114732035318 ps
CPU time 298.2 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:19:45 PM PDT 24
Peak memory 199920 kb
Host smart-d722c077-fcea-4174-b88f-0420ffbc8861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225030865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1225030865
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3567787491
Short name T1087
Test name
Test status
Simulation time 20265882526 ps
CPU time 14.5 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:15:02 PM PDT 24
Peak memory 199764 kb
Host smart-569a0537-a990-468c-8591-91b4ba87db41
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567787491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3567787491
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3708323641
Short name T749
Test name
Test status
Simulation time 77062391619 ps
CPU time 299.11 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:19:46 PM PDT 24
Peak memory 199896 kb
Host smart-0a9ed1eb-89b2-47f2-800b-fa962c5d3055
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3708323641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3708323641
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.392954587
Short name T952
Test name
Test status
Simulation time 5739530466 ps
CPU time 3.83 seconds
Started Jul 29 07:14:44 PM PDT 24
Finished Jul 29 07:14:48 PM PDT 24
Peak memory 198596 kb
Host smart-dbbd2c9d-2db3-40f4-86df-40b90a888f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392954587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.392954587
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3293068970
Short name T804
Test name
Test status
Simulation time 62014077135 ps
CPU time 34.87 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:15:22 PM PDT 24
Peak memory 208308 kb
Host smart-1b61dc3f-cd40-4198-a87c-719d6edb8776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293068970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3293068970
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3580157630
Short name T520
Test name
Test status
Simulation time 17814109404 ps
CPU time 108.7 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:16:34 PM PDT 24
Peak memory 199872 kb
Host smart-9b5ed2e8-4de9-46fc-87a1-edf65951fc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3580157630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3580157630
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4246413376
Short name T343
Test name
Test status
Simulation time 4236907771 ps
CPU time 9.09 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:56 PM PDT 24
Peak memory 197888 kb
Host smart-b9033fa5-2cb1-44d1-88c5-d7dae01b4d73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246413376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4246413376
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.4004267428
Short name T1112
Test name
Test status
Simulation time 89756580194 ps
CPU time 198.29 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:18:05 PM PDT 24
Peak memory 199944 kb
Host smart-911fad17-948e-4677-98f3-eccb81d6889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004267428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.4004267428
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.2971262437
Short name T294
Test name
Test status
Simulation time 37259878169 ps
CPU time 7.49 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:55 PM PDT 24
Peak memory 196312 kb
Host smart-fc9c26ee-e68d-4b32-9de0-5b7c73b85bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971262437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2971262437
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.309043200
Short name T323
Test name
Test status
Simulation time 501055495 ps
CPU time 2.08 seconds
Started Jul 29 07:14:29 PM PDT 24
Finished Jul 29 07:14:32 PM PDT 24
Peak memory 199624 kb
Host smart-3f1c38ae-e1ba-4c43-b46f-cdbea272a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309043200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.309043200
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.4293982196
Short name T1118
Test name
Test status
Simulation time 208107027617 ps
CPU time 436.84 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:22:02 PM PDT 24
Peak memory 199972 kb
Host smart-63da8764-e7c7-42b8-a3d8-79800e558976
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293982196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.4293982196
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.274862351
Short name T739
Test name
Test status
Simulation time 15610434317 ps
CPU time 175.44 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:17:42 PM PDT 24
Peak memory 216660 kb
Host smart-cf0800c9-b72d-4d95-be60-cfa8a9a37508
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274862351 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.274862351
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.408563756
Short name T978
Test name
Test status
Simulation time 501240784 ps
CPU time 2.16 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:50 PM PDT 24
Peak memory 198572 kb
Host smart-6dc5e380-6139-4c62-8b1e-f0475bc559f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408563756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.408563756
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3233087250
Short name T524
Test name
Test status
Simulation time 19179540566 ps
CPU time 16.63 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:15:05 PM PDT 24
Peak memory 199916 kb
Host smart-965869ce-e43f-4549-a2a0-acf611a42292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233087250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3233087250
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2890743476
Short name T1062
Test name
Test status
Simulation time 42411777 ps
CPU time 0.57 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:14:48 PM PDT 24
Peak memory 195356 kb
Host smart-5eeee3d8-af6e-4cd0-bf94-78f1d1f836b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890743476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2890743476
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2462434679
Short name T1165
Test name
Test status
Simulation time 75861973148 ps
CPU time 32.48 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:15:20 PM PDT 24
Peak memory 199960 kb
Host smart-3b5e62a1-f4d7-4a76-ba54-1be3fbef5884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462434679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2462434679
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3448821346
Short name T160
Test name
Test status
Simulation time 44668453814 ps
CPU time 69.4 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:15:55 PM PDT 24
Peak memory 199964 kb
Host smart-7dd71c48-d391-42dc-9d47-1b9a3d38853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448821346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3448821346
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.199296541
Short name T92
Test name
Test status
Simulation time 132437651256 ps
CPU time 235.09 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:18:41 PM PDT 24
Peak memory 200092 kb
Host smart-0be3f4f3-bd33-4b1f-b573-414cd2735865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199296541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.199296541
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.473937309
Short name T1100
Test name
Test status
Simulation time 13314178221 ps
CPU time 13.82 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:14:59 PM PDT 24
Peak memory 199432 kb
Host smart-e12f5a10-c1d4-4776-9bf8-3636c024735a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473937309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.473937309
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3508783991
Short name T865
Test name
Test status
Simulation time 70900885827 ps
CPU time 237.49 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:18:46 PM PDT 24
Peak memory 199944 kb
Host smart-1a1163a9-a949-48e7-86bc-a73d5a42bd2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508783991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3508783991
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3690398813
Short name T653
Test name
Test status
Simulation time 9265926658 ps
CPU time 16.28 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:15:02 PM PDT 24
Peak memory 198692 kb
Host smart-65322a49-1c6c-4723-892b-5e2264b3b14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690398813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3690398813
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3605629838
Short name T976
Test name
Test status
Simulation time 70155151207 ps
CPU time 100.13 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:16:25 PM PDT 24
Peak memory 199440 kb
Host smart-31e26c19-19fd-42c4-87b1-63c031d3021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605629838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3605629838
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.4005611932
Short name T480
Test name
Test status
Simulation time 2268035110 ps
CPU time 59.99 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:15:45 PM PDT 24
Peak memory 199908 kb
Host smart-8c398f7d-78e9-4a59-b61c-18d11bb19a45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4005611932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.4005611932
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3659634469
Short name T454
Test name
Test status
Simulation time 6631773322 ps
CPU time 54.33 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:15:41 PM PDT 24
Peak memory 198064 kb
Host smart-1077dec4-066c-47a4-a6d7-a4291a6e008b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3659634469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3659634469
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1319741445
Short name T551
Test name
Test status
Simulation time 182821789849 ps
CPU time 163.2 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:17:29 PM PDT 24
Peak memory 199940 kb
Host smart-7f39276c-b217-43bb-8515-ba0209c5c7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319741445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1319741445
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1602769745
Short name T849
Test name
Test status
Simulation time 2139661631 ps
CPU time 3.82 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:14:50 PM PDT 24
Peak memory 195652 kb
Host smart-c91ab78b-aefc-4663-b09c-483d53167e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602769745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1602769745
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3188880110
Short name T477
Test name
Test status
Simulation time 617179138 ps
CPU time 2.11 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:14:48 PM PDT 24
Peak memory 199796 kb
Host smart-e8f1a53a-a758-4859-8784-a4079a36d7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188880110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3188880110
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.387177019
Short name T933
Test name
Test status
Simulation time 342299387988 ps
CPU time 117.5 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:16:43 PM PDT 24
Peak memory 208284 kb
Host smart-9cef7ea6-7ff3-405a-8928-f23de249a4e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387177019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.387177019
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2593829745
Short name T1095
Test name
Test status
Simulation time 73947010074 ps
CPU time 204.78 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:18:13 PM PDT 24
Peak memory 216556 kb
Host smart-dac59c2f-093c-4c24-b9e1-98405b0a90d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593829745 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2593829745
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.449501171
Short name T325
Test name
Test status
Simulation time 731348106 ps
CPU time 3.18 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:14:49 PM PDT 24
Peak memory 198332 kb
Host smart-45e0d456-f9d7-403c-8fce-87a6a74ccc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449501171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.449501171
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1120653107
Short name T746
Test name
Test status
Simulation time 28874034332 ps
CPU time 46.91 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:15:35 PM PDT 24
Peak memory 199872 kb
Host smart-2f3ff174-2032-4163-9ed4-f73e0462c68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120653107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1120653107
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.795828757
Short name T435
Test name
Test status
Simulation time 32562539 ps
CPU time 0.55 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:14:59 PM PDT 24
Peak memory 194820 kb
Host smart-1714db98-d68a-430e-9838-77b2cbf1271e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795828757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.795828757
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.170198199
Short name T716
Test name
Test status
Simulation time 121026740038 ps
CPU time 52.89 seconds
Started Jul 29 07:14:45 PM PDT 24
Finished Jul 29 07:15:38 PM PDT 24
Peak memory 199928 kb
Host smart-5d1853c9-9d6b-4b94-808e-96796a2acaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170198199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.170198199
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2335352908
Short name T64
Test name
Test status
Simulation time 43559355447 ps
CPU time 77.25 seconds
Started Jul 29 07:14:44 PM PDT 24
Finished Jul 29 07:16:01 PM PDT 24
Peak memory 199860 kb
Host smart-250245c0-679f-46a7-bbec-ad9f5b67a1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335352908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2335352908
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.3725462677
Short name T961
Test name
Test status
Simulation time 132608277231 ps
CPU time 91.15 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:16:18 PM PDT 24
Peak memory 199968 kb
Host smart-e94eac96-0085-4a8e-b8c6-f32f8f86a54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725462677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3725462677
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.267983626
Short name T380
Test name
Test status
Simulation time 7546776595 ps
CPU time 3.63 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:14:52 PM PDT 24
Peak memory 199944 kb
Host smart-4a1f8167-b74c-4820-b134-86cbd1a59be5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267983626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.267983626
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2179155983
Short name T1097
Test name
Test status
Simulation time 96593704142 ps
CPU time 128.84 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:17:07 PM PDT 24
Peak memory 199956 kb
Host smart-a32259ad-3e1d-4be6-ab4b-0b0d8060d936
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179155983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2179155983
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2443332674
Short name T1155
Test name
Test status
Simulation time 6848344142 ps
CPU time 4 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:15:01 PM PDT 24
Peak memory 199884 kb
Host smart-02f027ab-6598-4113-a8b2-9caea51b54b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443332674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2443332674
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1486753792
Short name T590
Test name
Test status
Simulation time 181961795715 ps
CPU time 76.97 seconds
Started Jul 29 07:14:49 PM PDT 24
Finished Jul 29 07:16:06 PM PDT 24
Peak memory 199944 kb
Host smart-a4036298-88f2-483b-a159-c7b372ac6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486753792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1486753792
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.472940843
Short name T1074
Test name
Test status
Simulation time 13077447738 ps
CPU time 747.72 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:27:25 PM PDT 24
Peak memory 199980 kb
Host smart-bc1d062e-6c93-4954-abfb-3625fe29e303
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=472940843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.472940843
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2632712466
Short name T501
Test name
Test status
Simulation time 2452665595 ps
CPU time 3.81 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:51 PM PDT 24
Peak memory 198068 kb
Host smart-67da7536-f018-4135-8931-3e46464cac4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2632712466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2632712466
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.954558881
Short name T570
Test name
Test status
Simulation time 40977596215 ps
CPU time 36.78 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:15:35 PM PDT 24
Peak memory 199972 kb
Host smart-a462dda3-caf9-4036-8186-a663c2687bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954558881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.954558881
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3663532111
Short name T833
Test name
Test status
Simulation time 5037407155 ps
CPU time 2.44 seconds
Started Jul 29 07:14:48 PM PDT 24
Finished Jul 29 07:14:50 PM PDT 24
Peak memory 196440 kb
Host smart-ecf57dde-778b-4d2a-88bf-cbaa2af37184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663532111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3663532111
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.400173694
Short name T589
Test name
Test status
Simulation time 451084472 ps
CPU time 1.47 seconds
Started Jul 29 07:14:47 PM PDT 24
Finished Jul 29 07:14:48 PM PDT 24
Peak memory 198564 kb
Host smart-3e4be8fc-7b41-4b47-8c01-d5b8a422d13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400173694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.400173694
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.428740301
Short name T947
Test name
Test status
Simulation time 277731011309 ps
CPU time 206.91 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:18:24 PM PDT 24
Peak memory 216456 kb
Host smart-7c96b932-71db-4929-a63e-f28b6cec069c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428740301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.428740301
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2825170947
Short name T69
Test name
Test status
Simulation time 381006870326 ps
CPU time 606.91 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:25:05 PM PDT 24
Peak memory 224796 kb
Host smart-5ffa6bfb-e5b1-4b4b-8816-656369c97304
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825170947 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2825170947
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2685352069
Short name T840
Test name
Test status
Simulation time 1256350970 ps
CPU time 2.68 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:02 PM PDT 24
Peak memory 199864 kb
Host smart-cf31a662-35f1-4c85-b1cd-56762c791901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685352069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2685352069
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.603678021
Short name T720
Test name
Test status
Simulation time 7705396592 ps
CPU time 13.41 seconds
Started Jul 29 07:14:46 PM PDT 24
Finished Jul 29 07:14:59 PM PDT 24
Peak memory 199972 kb
Host smart-1b3df2ef-3163-48ba-97cc-75fe7cfcd9cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603678021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.603678021
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.1825577479
Short name T1147
Test name
Test status
Simulation time 141299429 ps
CPU time 0.57 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:01 PM PDT 24
Peak memory 195288 kb
Host smart-0a7a6c08-1fd9-477d-b592-c1b89824e8b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825577479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.1825577479
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.26341131
Short name T546
Test name
Test status
Simulation time 127779818376 ps
CPU time 343.7 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:20:42 PM PDT 24
Peak memory 199932 kb
Host smart-42d01fef-e192-4d06-a880-9871c553400e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26341131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.26341131
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2517983287
Short name T518
Test name
Test status
Simulation time 47830480975 ps
CPU time 73.08 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:16:12 PM PDT 24
Peak memory 199924 kb
Host smart-52766686-4cba-4588-b028-2edbf623c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517983287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2517983287
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.350545300
Short name T1069
Test name
Test status
Simulation time 306075092567 ps
CPU time 269.18 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:19:27 PM PDT 24
Peak memory 199892 kb
Host smart-526aba33-b50c-4079-b092-5ddf9a5df385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350545300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.350545300
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.310359273
Short name T354
Test name
Test status
Simulation time 12378052109 ps
CPU time 18.21 seconds
Started Jul 29 07:14:59 PM PDT 24
Finished Jul 29 07:15:17 PM PDT 24
Peak memory 197100 kb
Host smart-9ce08c79-c8a5-4112-a664-c65288ecfd15
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310359273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.310359273
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.902121572
Short name T61
Test name
Test status
Simulation time 86155212881 ps
CPU time 239.24 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:19:01 PM PDT 24
Peak memory 199976 kb
Host smart-56daeb6f-0cc4-423a-9509-d2227136a23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=902121572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.902121572
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.849848096
Short name T923
Test name
Test status
Simulation time 13896170848 ps
CPU time 7.01 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:15:09 PM PDT 24
Peak memory 198720 kb
Host smart-c3fb5879-fc46-4863-aa76-55eb9d924ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849848096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.849848096
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1797744406
Short name T399
Test name
Test status
Simulation time 97749199254 ps
CPU time 374.99 seconds
Started Jul 29 07:14:59 PM PDT 24
Finished Jul 29 07:21:14 PM PDT 24
Peak memory 200124 kb
Host smart-6e075302-1000-46a7-8c5c-db5b927f9a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797744406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1797744406
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.2686040095
Short name T664
Test name
Test status
Simulation time 14336684030 ps
CPU time 169.32 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:17:50 PM PDT 24
Peak memory 199912 kb
Host smart-d6771d79-35f5-4727-b5df-1bcaefb5073d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2686040095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.2686040095
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.432085819
Short name T938
Test name
Test status
Simulation time 3684628800 ps
CPU time 7.7 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:15:06 PM PDT 24
Peak memory 198024 kb
Host smart-224646e3-e9d5-4965-b477-20c8061490a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=432085819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.432085819
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1673878453
Short name T1175
Test name
Test status
Simulation time 211773027608 ps
CPU time 228.83 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:18:47 PM PDT 24
Peak memory 199860 kb
Host smart-a7f507aa-912e-441d-83e1-4b2cd96668b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673878453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1673878453
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1391111479
Short name T517
Test name
Test status
Simulation time 4458319737 ps
CPU time 2.35 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:15:00 PM PDT 24
Peak memory 196252 kb
Host smart-0f4dce44-6b39-4a05-853f-293b337da2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391111479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1391111479
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2947800883
Short name T317
Test name
Test status
Simulation time 822698756 ps
CPU time 1.3 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:14:58 PM PDT 24
Peak memory 199640 kb
Host smart-e8685025-f112-4912-979d-3c97d28098ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947800883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2947800883
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.4062063176
Short name T943
Test name
Test status
Simulation time 356587940296 ps
CPU time 158.33 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:17:40 PM PDT 24
Peak memory 199888 kb
Host smart-5a40b520-19c5-4c36-bf99-e11fe7fb1de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062063176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.4062063176
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2445141999
Short name T113
Test name
Test status
Simulation time 25590407036 ps
CPU time 218.12 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:18:40 PM PDT 24
Peak memory 216408 kb
Host smart-0703f732-3e55-4549-9909-e1c049dfb599
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445141999 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2445141999
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.3354502686
Short name T836
Test name
Test status
Simulation time 1533384414 ps
CPU time 2.27 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:03 PM PDT 24
Peak memory 199644 kb
Host smart-52e9aae6-d15b-430d-85e5-8028db79f159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354502686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.3354502686
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.1874747699
Short name T469
Test name
Test status
Simulation time 40254812821 ps
CPU time 33.31 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:33 PM PDT 24
Peak memory 199856 kb
Host smart-f5e70553-5220-4c25-8740-184809d03b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874747699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.1874747699
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1507418265
Short name T832
Test name
Test status
Simulation time 14972632 ps
CPU time 0.57 seconds
Started Jul 29 07:15:06 PM PDT 24
Finished Jul 29 07:15:07 PM PDT 24
Peak memory 195356 kb
Host smart-174f67ab-04ba-4c80-8919-c2550971e60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507418265 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1507418265
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3039237854
Short name T645
Test name
Test status
Simulation time 72975108315 ps
CPU time 205.91 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:18:26 PM PDT 24
Peak memory 200040 kb
Host smart-002cb074-2f4b-41c1-a40f-a612569bd551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039237854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3039237854
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.999101432
Short name T288
Test name
Test status
Simulation time 76844740687 ps
CPU time 28.46 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:29 PM PDT 24
Peak memory 199920 kb
Host smart-11bcec5b-37fe-4a54-9191-18e862f9960d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999101432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.999101432
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.907642591
Short name T402
Test name
Test status
Simulation time 21612149861 ps
CPU time 29.72 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:15:31 PM PDT 24
Peak memory 199960 kb
Host smart-e80a1eba-a381-4fe1-9c8a-c8fae8a5d16d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907642591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.907642591
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2401403412
Short name T300
Test name
Test status
Simulation time 54149112943 ps
CPU time 105.38 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 199984 kb
Host smart-49984143-65a0-4dde-ad3c-13d3598eb540
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401403412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2401403412
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2894389796
Short name T383
Test name
Test status
Simulation time 2798981469 ps
CPU time 5.24 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:15:06 PM PDT 24
Peak memory 197308 kb
Host smart-de3c560e-d022-40bc-8558-05ba6711aa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894389796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2894389796
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1908179824
Short name T605
Test name
Test status
Simulation time 111332606856 ps
CPU time 73.7 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:16:14 PM PDT 24
Peak memory 199408 kb
Host smart-e50bb90e-fd0f-4f6e-b658-261038e6c433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908179824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1908179824
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.54845444
Short name T312
Test name
Test status
Simulation time 23135047353 ps
CPU time 160.18 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:17:43 PM PDT 24
Peak memory 199932 kb
Host smart-9c2146e3-4690-4e94-941d-62dcd08507af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54845444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.54845444
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.3779184632
Short name T1050
Test name
Test status
Simulation time 6025520188 ps
CPU time 15.95 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:16 PM PDT 24
Peak memory 198052 kb
Host smart-03ebdf1e-5f40-43cc-9428-37a03822c54e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779184632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.3779184632
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3625538865
Short name T450
Test name
Test status
Simulation time 117409578982 ps
CPU time 149.55 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:17:29 PM PDT 24
Peak memory 200132 kb
Host smart-425bf701-2d5c-4aa9-97dd-236782f49ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625538865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3625538865
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.4113702841
Short name T370
Test name
Test status
Simulation time 5912451096 ps
CPU time 3.13 seconds
Started Jul 29 07:15:01 PM PDT 24
Finished Jul 29 07:15:04 PM PDT 24
Peak memory 196272 kb
Host smart-5fc4880a-8497-4c47-bd0b-a28727199ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113702841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.4113702841
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2877667786
Short name T778
Test name
Test status
Simulation time 760196611 ps
CPU time 1.62 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:15:04 PM PDT 24
Peak memory 198280 kb
Host smart-207d7e2f-93e6-4683-b397-07934ebc344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877667786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2877667786
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3275967952
Short name T1033
Test name
Test status
Simulation time 189394874839 ps
CPU time 78.71 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 208264 kb
Host smart-6f03ec2b-746b-4116-bb60-e01d3a0c6743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275967952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3275967952
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2913802227
Short name T57
Test name
Test status
Simulation time 539452281191 ps
CPU time 1140.76 seconds
Started Jul 29 07:15:06 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 226192 kb
Host smart-710020f1-5477-4cd7-9423-a84e5758e2a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913802227 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2913802227
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1207065997
Short name T492
Test name
Test status
Simulation time 7505864131 ps
CPU time 14.82 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:15:15 PM PDT 24
Peak memory 199856 kb
Host smart-0384a5c9-70c6-4010-830c-a6a3e3ef8e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207065997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1207065997
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.699210849
Short name T506
Test name
Test status
Simulation time 62943787670 ps
CPU time 59.7 seconds
Started Jul 29 07:15:00 PM PDT 24
Finished Jul 29 07:16:00 PM PDT 24
Peak memory 199856 kb
Host smart-c48c89e6-47bf-4076-807b-71c5d8eccd1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699210849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.699210849
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1262800428
Short name T452
Test name
Test status
Simulation time 19144517 ps
CPU time 0.61 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 195332 kb
Host smart-139cd9bb-9821-4cb2-9216-0ee17e7bb595
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262800428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1262800428
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.4276118292
Short name T284
Test name
Test status
Simulation time 161481559584 ps
CPU time 389.74 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:18:54 PM PDT 24
Peak memory 199976 kb
Host smart-e14bcfa0-aa1b-41c4-b96f-b5a09319ca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276118292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.4276118292
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3277986271
Short name T66
Test name
Test status
Simulation time 51375533819 ps
CPU time 40.99 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:13:06 PM PDT 24
Peak memory 199928 kb
Host smart-fdc46801-e889-491c-8cb8-bd498fa8eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277986271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3277986271
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.2751786207
Short name T969
Test name
Test status
Simulation time 9436619838 ps
CPU time 1.57 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:26 PM PDT 24
Peak memory 197824 kb
Host smart-7fea8866-2caf-4116-8370-07d9bf6d55fd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751786207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.2751786207
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.282175513
Short name T1107
Test name
Test status
Simulation time 111930938571 ps
CPU time 480.18 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:20:25 PM PDT 24
Peak memory 199736 kb
Host smart-a451d7f5-5489-4033-b146-7b7a974cdabf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282175513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.282175513
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1952450769
Short name T937
Test name
Test status
Simulation time 3229487606 ps
CPU time 3.34 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 198132 kb
Host smart-4e050d76-c879-46be-ba26-3f6bccede874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952450769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1952450769
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.1339598513
Short name T850
Test name
Test status
Simulation time 168013954765 ps
CPU time 55.8 seconds
Started Jul 29 07:12:29 PM PDT 24
Finished Jul 29 07:13:25 PM PDT 24
Peak memory 208284 kb
Host smart-b632de92-bb95-42f7-b7f5-9f8ba3b085ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339598513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.1339598513
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.2263000200
Short name T959
Test name
Test status
Simulation time 22061832924 ps
CPU time 140.09 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:14:43 PM PDT 24
Peak memory 199888 kb
Host smart-064c0863-9bc7-478e-ac8e-72a2c6762ce9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2263000200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.2263000200
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.145881186
Short name T502
Test name
Test status
Simulation time 2529620347 ps
CPU time 6.02 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:32 PM PDT 24
Peak memory 197504 kb
Host smart-1c6c3acb-43b5-45cb-8a2e-4272d3162ba5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=145881186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.145881186
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.243449689
Short name T433
Test name
Test status
Simulation time 43830632330 ps
CPU time 18.65 seconds
Started Jul 29 07:12:29 PM PDT 24
Finished Jul 29 07:12:48 PM PDT 24
Peak memory 199964 kb
Host smart-5e3baeaa-ad17-4fa8-8168-d2278a1f0bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243449689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.243449689
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3783613956
Short name T21
Test name
Test status
Simulation time 35575081195 ps
CPU time 40.01 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:13:03 PM PDT 24
Peak memory 195776 kb
Host smart-6d0fc8fb-2d40-4f69-ac28-236f79ae76fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783613956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3783613956
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.3100629465
Short name T27
Test name
Test status
Simulation time 39780326 ps
CPU time 0.79 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:12:29 PM PDT 24
Peak memory 218288 kb
Host smart-dd1414ff-a45f-408a-be90-1c789c1a4948
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100629465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.3100629465
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.4249119465
Short name T382
Test name
Test status
Simulation time 490864433 ps
CPU time 2.38 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:27 PM PDT 24
Peak memory 199384 kb
Host smart-5e8a485b-58f6-4dbc-985e-d92a7ef74de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249119465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.4249119465
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2481260246
Short name T483
Test name
Test status
Simulation time 150945220682 ps
CPU time 714.99 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:24:19 PM PDT 24
Peak memory 216512 kb
Host smart-74fd90cd-966d-43fc-8077-4536090d34b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481260246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2481260246
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.1200130462
Short name T995
Test name
Test status
Simulation time 3398422183 ps
CPU time 1.66 seconds
Started Jul 29 07:12:23 PM PDT 24
Finished Jul 29 07:12:25 PM PDT 24
Peak memory 199200 kb
Host smart-33b21cf8-a72d-48e5-ab6b-573ecc36a503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200130462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.1200130462
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1192012022
Short name T576
Test name
Test status
Simulation time 111029101313 ps
CPU time 61.38 seconds
Started Jul 29 07:12:24 PM PDT 24
Finished Jul 29 07:13:26 PM PDT 24
Peak memory 200064 kb
Host smart-e4b570cd-3f5e-459f-954b-ad3908c72bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192012022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1192012022
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.816380619
Short name T627
Test name
Test status
Simulation time 26064017 ps
CPU time 0.53 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:16:07 PM PDT 24
Peak memory 194228 kb
Host smart-9a9c7769-ffcd-40c0-bd36-9f4c8c5de241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816380619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.816380619
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2664080942
Short name T626
Test name
Test status
Simulation time 41262168968 ps
CPU time 55.41 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:15:57 PM PDT 24
Peak memory 199916 kb
Host smart-25c72283-a558-48b1-b987-be43f5ecd67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664080942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2664080942
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.698764302
Short name T269
Test name
Test status
Simulation time 143831809895 ps
CPU time 89.67 seconds
Started Jul 29 07:15:06 PM PDT 24
Finished Jul 29 07:16:36 PM PDT 24
Peak memory 199976 kb
Host smart-c85366a6-f0af-484b-bce1-6b44bb68142c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698764302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.698764302
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3132401861
Short name T245
Test name
Test status
Simulation time 125369017438 ps
CPU time 51.4 seconds
Started Jul 29 07:15:03 PM PDT 24
Finished Jul 29 07:15:55 PM PDT 24
Peak memory 199884 kb
Host smart-81f5801a-1b7d-44d4-b0be-70466be976e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132401861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3132401861
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1459497968
Short name T884
Test name
Test status
Simulation time 18915362951 ps
CPU time 12.48 seconds
Started Jul 29 07:15:03 PM PDT 24
Finished Jul 29 07:15:16 PM PDT 24
Peak memory 197108 kb
Host smart-c859d4f7-2d54-4832-b851-e87825af76eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459497968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1459497968
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.375771626
Short name T265
Test name
Test status
Simulation time 103192105770 ps
CPU time 403.36 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:22:50 PM PDT 24
Peak memory 199956 kb
Host smart-0e82cba2-d63e-48ab-a0c1-abaa3010be2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375771626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.375771626
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2699281571
Short name T841
Test name
Test status
Simulation time 6856862262 ps
CPU time 5.6 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:13 PM PDT 24
Peak memory 199800 kb
Host smart-a0b1be86-1e9c-4cd7-afb2-a7f9c814bb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699281571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2699281571
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1170851367
Short name T448
Test name
Test status
Simulation time 61533872149 ps
CPU time 100.24 seconds
Started Jul 29 07:14:58 PM PDT 24
Finished Jul 29 07:16:38 PM PDT 24
Peak memory 199560 kb
Host smart-b45a53a1-f1dc-4ad8-840e-c0b7bba42750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170851367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1170851367
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1591349735
Short name T366
Test name
Test status
Simulation time 24601527383 ps
CPU time 1291.23 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:37:40 PM PDT 24
Peak memory 199900 kb
Host smart-8d392827-4ec0-4506-b6be-3c739cc89626
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591349735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1591349735
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.2787997716
Short name T447
Test name
Test status
Simulation time 6731771558 ps
CPU time 14.41 seconds
Started Jul 29 07:15:04 PM PDT 24
Finished Jul 29 07:15:18 PM PDT 24
Peak memory 198168 kb
Host smart-64016c44-9a10-4f6c-9b3c-1985f046a88a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2787997716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2787997716
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2076785871
Short name T559
Test name
Test status
Simulation time 89466508687 ps
CPU time 150.94 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:18:37 PM PDT 24
Peak memory 199976 kb
Host smart-a70bda2a-ccf7-4396-8d4b-b65405d08612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076785871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2076785871
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.3064641984
Short name T1106
Test name
Test status
Simulation time 2136276427 ps
CPU time 1.37 seconds
Started Jul 29 07:14:57 PM PDT 24
Finished Jul 29 07:14:59 PM PDT 24
Peak memory 195724 kb
Host smart-d79af9bf-dcca-43d6-8cf6-f2cc9b85b936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064641984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.3064641984
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.689167365
Short name T1032
Test name
Test status
Simulation time 812856308 ps
CPU time 2.32 seconds
Started Jul 29 07:15:06 PM PDT 24
Finished Jul 29 07:15:09 PM PDT 24
Peak memory 198076 kb
Host smart-cf2b1179-b0cf-4c2d-9a33-7c998cc3f2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689167365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.689167365
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.2196531786
Short name T935
Test name
Test status
Simulation time 120592478352 ps
CPU time 197.31 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:19:23 PM PDT 24
Peak memory 208428 kb
Host smart-3e7aa9bc-bf30-4365-ad37-0f64ea5e3405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196531786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.2196531786
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.441290435
Short name T164
Test name
Test status
Simulation time 244485051941 ps
CPU time 730.4 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:28:19 PM PDT 24
Peak memory 216440 kb
Host smart-cb93f90d-60a1-46e5-b8a2-c8a352d79cd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441290435 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.441290435
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2459053856
Short name T939
Test name
Test status
Simulation time 12581430457 ps
CPU time 42.64 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 199680 kb
Host smart-a5f607f3-87d6-4de1-911d-2dd96fcd4737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459053856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2459053856
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.4171220364
Short name T784
Test name
Test status
Simulation time 66115603142 ps
CPU time 40.23 seconds
Started Jul 29 07:15:02 PM PDT 24
Finished Jul 29 07:15:43 PM PDT 24
Peak memory 199928 kb
Host smart-fcfbb078-a678-4182-8902-e2ccc1b302ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171220364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.4171220364
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4242698122
Short name T1089
Test name
Test status
Simulation time 32568377 ps
CPU time 0.55 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:08 PM PDT 24
Peak memory 195624 kb
Host smart-5027fdce-8f02-4949-bc43-f21f338d29a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242698122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4242698122
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.530444895
Short name T1027
Test name
Test status
Simulation time 125036842168 ps
CPU time 171.75 seconds
Started Jul 29 07:16:05 PM PDT 24
Finished Jul 29 07:18:57 PM PDT 24
Peak memory 199552 kb
Host smart-a954ed52-f1e1-4215-b8ca-9c84191a5f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530444895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.530444895
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.738579084
Short name T1130
Test name
Test status
Simulation time 103183100119 ps
CPU time 79.52 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:17:26 PM PDT 24
Peak memory 200128 kb
Host smart-56b2940c-ced8-42fb-9a3a-69a48327bf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738579084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.738579084
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.369791061
Short name T613
Test name
Test status
Simulation time 20211360071 ps
CPU time 27.56 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:35 PM PDT 24
Peak memory 199844 kb
Host smart-1e4097c1-0845-4b62-a297-b306d45835a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369791061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.369791061
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.333605992
Short name T421
Test name
Test status
Simulation time 20814784104 ps
CPU time 41.93 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:16:48 PM PDT 24
Peak memory 199628 kb
Host smart-321820f9-8de0-4bda-81aa-5cebc8c9018d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333605992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.333605992
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.3606459792
Short name T458
Test name
Test status
Simulation time 72998351629 ps
CPU time 151.37 seconds
Started Jul 29 07:16:11 PM PDT 24
Finished Jul 29 07:18:43 PM PDT 24
Peak memory 199920 kb
Host smart-4bde562d-793e-48be-b31c-d65512a5af8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3606459792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.3606459792
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1194325756
Short name T742
Test name
Test status
Simulation time 2005970877 ps
CPU time 2.24 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:09 PM PDT 24
Peak memory 195444 kb
Host smart-5953cd31-179b-436d-aead-b8295db494be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194325756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1194325756
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2689893992
Short name T708
Test name
Test status
Simulation time 243276343705 ps
CPU time 28.21 seconds
Started Jul 29 07:16:06 PM PDT 24
Finished Jul 29 07:16:35 PM PDT 24
Peak memory 208292 kb
Host smart-555e7558-dcdf-4bc4-9b7d-5af9ff17a3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689893992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2689893992
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.1726394998
Short name T256
Test name
Test status
Simulation time 6118703224 ps
CPU time 85.15 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:17:33 PM PDT 24
Peak memory 199972 kb
Host smart-4b351dc1-2e97-4553-a97a-fa9213f34ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1726394998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1726394998
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.131409467
Short name T951
Test name
Test status
Simulation time 5409383061 ps
CPU time 47.23 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:16:56 PM PDT 24
Peak memory 198872 kb
Host smart-4bed071d-098b-4598-a3dd-a793396c67d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131409467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.131409467
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.309643226
Short name T1093
Test name
Test status
Simulation time 247022651428 ps
CPU time 74.35 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:17:21 PM PDT 24
Peak memory 199980 kb
Host smart-ac686b0e-9133-4dbb-95a0-82b31e9fa8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309643226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.309643226
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.767718181
Short name T894
Test name
Test status
Simulation time 4617957350 ps
CPU time 3.65 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:11 PM PDT 24
Peak memory 196484 kb
Host smart-75a1279e-7743-47ff-a8eb-affeed374823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767718181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.767718181
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.1698387446
Short name T304
Test name
Test status
Simulation time 271574466 ps
CPU time 1.65 seconds
Started Jul 29 07:16:10 PM PDT 24
Finished Jul 29 07:16:11 PM PDT 24
Peak memory 199840 kb
Host smart-6db69e7b-d521-4bda-ad92-ca454a33533c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698387446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.1698387446
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.2688998256
Short name T286
Test name
Test status
Simulation time 190120833280 ps
CPU time 333.35 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:21:40 PM PDT 24
Peak memory 199888 kb
Host smart-886c88d0-dc9e-48a9-a297-7cb9991ab8e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688998256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.2688998256
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3277977982
Short name T577
Test name
Test status
Simulation time 120249898311 ps
CPU time 328.84 seconds
Started Jul 29 07:16:09 PM PDT 24
Finished Jul 29 07:21:38 PM PDT 24
Peak memory 216476 kb
Host smart-c79b8994-118b-4870-ac75-b92f519f52bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277977982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3277977982
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.3422887929
Short name T1017
Test name
Test status
Simulation time 1364019792 ps
CPU time 1.48 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:09 PM PDT 24
Peak memory 198624 kb
Host smart-344ab39a-ff4b-44c6-bd80-f11e25800936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422887929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.3422887929
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.4097037261
Short name T743
Test name
Test status
Simulation time 139574829988 ps
CPU time 229.73 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:20:06 PM PDT 24
Peak memory 199876 kb
Host smart-2afd2364-37cd-4db4-a321-549784448670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097037261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.4097037261
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3623513397
Short name T1039
Test name
Test status
Simulation time 14368245 ps
CPU time 0.57 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:20 PM PDT 24
Peak memory 195288 kb
Host smart-44b9f7c1-f9da-4253-835a-c7d88f7efa21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623513397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3623513397
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.2058345157
Short name T472
Test name
Test status
Simulation time 49261231020 ps
CPU time 81.22 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:17:30 PM PDT 24
Peak memory 199920 kb
Host smart-cbba9db6-e9b2-4bd1-ae4e-64c91a785e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058345157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.2058345157
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.468171606
Short name T456
Test name
Test status
Simulation time 13161933394 ps
CPU time 17.82 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:39 PM PDT 24
Peak memory 199968 kb
Host smart-ddbbf7c6-418b-492f-b3d8-04b7bb4a0458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468171606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.468171606
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_intr.3647944004
Short name T326
Test name
Test status
Simulation time 160430655969 ps
CPU time 242.01 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:20:21 PM PDT 24
Peak memory 196884 kb
Host smart-d198f34e-6104-4ba2-b0c5-cd5a732ba3b4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647944004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3647944004
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.415048569
Short name T926
Test name
Test status
Simulation time 83898576534 ps
CPU time 321.53 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:21:38 PM PDT 24
Peak memory 199840 kb
Host smart-e338a401-3c13-41ee-9cd6-91967f026fbd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=415048569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.415048569
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.31171859
Short name T598
Test name
Test status
Simulation time 4007616905 ps
CPU time 4.22 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:24 PM PDT 24
Peak memory 198788 kb
Host smart-cfb3c2eb-6662-4bdc-8068-60368e6e1d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31171859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.31171859
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1473422276
Short name T687
Test name
Test status
Simulation time 131041861681 ps
CPU time 38.48 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:57 PM PDT 24
Peak memory 200480 kb
Host smart-aa8eac10-ec80-4811-a4d4-05324296139a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473422276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1473422276
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3090341088
Short name T418
Test name
Test status
Simulation time 3569530055 ps
CPU time 24.04 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:43 PM PDT 24
Peak memory 199836 kb
Host smart-5e085e4c-5b98-42b7-9b38-d7d0d30c2241
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3090341088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3090341088
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.1754940986
Short name T752
Test name
Test status
Simulation time 2084464039 ps
CPU time 6.63 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:24 PM PDT 24
Peak memory 198564 kb
Host smart-ab824f20-d434-4478-bb59-ae9335e569e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1754940986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.1754940986
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1208954009
Short name T493
Test name
Test status
Simulation time 67879231688 ps
CPU time 55.45 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:17:13 PM PDT 24
Peak memory 199648 kb
Host smart-57243e3f-ac7f-4f99-b87f-128bbfef8dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208954009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1208954009
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.594368549
Short name T512
Test name
Test status
Simulation time 2099100097 ps
CPU time 3.98 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:16:24 PM PDT 24
Peak memory 195532 kb
Host smart-2eb0339d-bca0-4db7-9aff-560b397cbe7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594368549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.594368549
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3347612091
Short name T886
Test name
Test status
Simulation time 511959317 ps
CPU time 1.49 seconds
Started Jul 29 07:16:07 PM PDT 24
Finished Jul 29 07:16:09 PM PDT 24
Peak memory 198668 kb
Host smart-e13d6dcb-ce08-453e-ab86-8b02caa300c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347612091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3347612091
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.669449616
Short name T762
Test name
Test status
Simulation time 351004426091 ps
CPU time 1590.59 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:42:46 PM PDT 24
Peak memory 199884 kb
Host smart-7c7a7740-67bc-4117-b77a-461052303683
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669449616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.669449616
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3210617763
Short name T587
Test name
Test status
Simulation time 348149014184 ps
CPU time 1216.69 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:36:33 PM PDT 24
Peak memory 224744 kb
Host smart-c3957d31-27ee-4370-93ba-a15f0c489805
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210617763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3210617763
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3797953226
Short name T439
Test name
Test status
Simulation time 952379396 ps
CPU time 1.85 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:16:18 PM PDT 24
Peak memory 198760 kb
Host smart-4286d0b4-b99a-45e2-b961-e7e0fc833770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797953226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3797953226
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1328541037
Short name T262
Test name
Test status
Simulation time 197804150401 ps
CPU time 69.64 seconds
Started Jul 29 07:16:08 PM PDT 24
Finished Jul 29 07:17:18 PM PDT 24
Peak memory 199852 kb
Host smart-b343d61e-f788-4f70-aa15-ea17fe18f741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328541037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1328541037
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.902689530
Short name T1166
Test name
Test status
Simulation time 14603778 ps
CPU time 0.57 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:20 PM PDT 24
Peak memory 194768 kb
Host smart-335f11f2-af35-4848-bf58-aa9e3e5f8d45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902689530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.902689530
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1028245357
Short name T769
Test name
Test status
Simulation time 57431832233 ps
CPU time 47.48 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:17:08 PM PDT 24
Peak memory 199912 kb
Host smart-e4d2b293-a4ca-4c95-8343-0ed515fc3bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028245357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1028245357
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2506353655
Short name T950
Test name
Test status
Simulation time 40011825825 ps
CPU time 15.05 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:32 PM PDT 24
Peak memory 199560 kb
Host smart-c28a9eea-b86f-441e-8899-8d6e0a773af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506353655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2506353655
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.490964398
Short name T210
Test name
Test status
Simulation time 115233301910 ps
CPU time 54.51 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:17:12 PM PDT 24
Peak memory 200016 kb
Host smart-7b0dec4d-c008-4fb1-badf-e289a01980e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490964398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.490964398
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.3916229634
Short name T997
Test name
Test status
Simulation time 30858458669 ps
CPU time 7.14 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:25 PM PDT 24
Peak memory 199996 kb
Host smart-3a3f48c3-ea77-41db-89ea-7f8d85b69a30
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916229634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.3916229634
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1513524121
Short name T299
Test name
Test status
Simulation time 54522092173 ps
CPU time 367.1 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:22:24 PM PDT 24
Peak memory 200096 kb
Host smart-b53643c0-b68c-47ca-9600-7e784127411d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1513524121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1513524121
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2135270606
Short name T856
Test name
Test status
Simulation time 5085008635 ps
CPU time 1.32 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:16:22 PM PDT 24
Peak memory 197952 kb
Host smart-a77a63a7-f521-4341-ab8f-899e0aac1e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135270606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2135270606
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.2764972836
Short name T861
Test name
Test status
Simulation time 36403359836 ps
CPU time 60.03 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:17:18 PM PDT 24
Peak memory 200044 kb
Host smart-17921d9c-e3b0-4dfb-9da7-b7173221ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764972836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2764972836
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2106523094
Short name T290
Test name
Test status
Simulation time 15508218991 ps
CPU time 191.29 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:19:28 PM PDT 24
Peak memory 199916 kb
Host smart-3c7d0ece-c892-4ee3-b764-81232d39499d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2106523094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2106523094
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.704884628
Short name T693
Test name
Test status
Simulation time 3805533849 ps
CPU time 30.42 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 198032 kb
Host smart-bf6a2bc2-e913-4dc1-8744-3b3fef780332
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704884628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.704884628
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.3064654852
Short name T844
Test name
Test status
Simulation time 119312261715 ps
CPU time 179.9 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:19:16 PM PDT 24
Peak memory 199276 kb
Host smart-f07253d7-74a5-4f0a-9573-525dd9b455d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064654852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.3064654852
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.1797073568
Short name T881
Test name
Test status
Simulation time 38922744191 ps
CPU time 13.22 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:33 PM PDT 24
Peak memory 196236 kb
Host smart-3ed3982b-1e12-4866-b6ca-1dcbe4df9843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797073568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.1797073568
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.2159178015
Short name T536
Test name
Test status
Simulation time 252143890 ps
CPU time 1.46 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:18 PM PDT 24
Peak memory 198976 kb
Host smart-beff7f2f-a118-493f-b9f6-87381c093730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159178015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2159178015
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2906835918
Short name T989
Test name
Test status
Simulation time 451066904481 ps
CPU time 1240.19 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:37:00 PM PDT 24
Peak memory 208328 kb
Host smart-a7b3f663-132f-4c9e-adb5-7e91a3d65ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906835918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2906835918
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.1779568015
Short name T775
Test name
Test status
Simulation time 147660425238 ps
CPU time 541.5 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:25:19 PM PDT 24
Peak memory 216428 kb
Host smart-691c5124-6586-493f-9234-0ba362f50237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779568015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.1779568015
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2685453138
Short name T441
Test name
Test status
Simulation time 6916886321 ps
CPU time 20.57 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:41 PM PDT 24
Peak memory 199392 kb
Host smart-070dbbbc-a46a-4cb7-8d69-92042d451b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685453138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2685453138
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.840368602
Short name T975
Test name
Test status
Simulation time 76018374769 ps
CPU time 58.51 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:17:18 PM PDT 24
Peak memory 199976 kb
Host smart-6c092daf-549f-4264-8c8d-5e5f88966d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840368602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.840368602
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.3794424566
Short name T103
Test name
Test status
Simulation time 13472660 ps
CPU time 0.57 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 195348 kb
Host smart-8224a0fa-4645-49a3-9cb8-59d416b0170a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794424566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3794424566
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1238713290
Short name T467
Test name
Test status
Simulation time 66820222645 ps
CPU time 150.79 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:18:49 PM PDT 24
Peak memory 199968 kb
Host smart-812316c3-d380-4a2c-b29f-d567603bb66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238713290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1238713290
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3281780642
Short name T984
Test name
Test status
Simulation time 115429970196 ps
CPU time 13.02 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:31 PM PDT 24
Peak memory 199924 kb
Host smart-dda72cad-fe60-42f8-b1e0-874edeebffc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281780642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3281780642
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.2039161488
Short name T398
Test name
Test status
Simulation time 26285237835 ps
CPU time 10.86 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:29 PM PDT 24
Peak memory 199992 kb
Host smart-c5b9847e-a0aa-489e-aa03-f54ca60e4d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039161488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2039161488
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.1092560667
Short name T595
Test name
Test status
Simulation time 55796584775 ps
CPU time 78.22 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:17:35 PM PDT 24
Peak memory 199972 kb
Host smart-be0b8ff7-32c1-48b4-947c-d414a3913e07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092560667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.1092560667
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.69272534
Short name T1146
Test name
Test status
Simulation time 118148187383 ps
CPU time 940.77 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:32:00 PM PDT 24
Peak memory 199972 kb
Host smart-6452aa1e-4110-42b9-8f42-afbc14fc42b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=69272534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.69272534
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3848558908
Short name T404
Test name
Test status
Simulation time 1293800528 ps
CPU time 1.28 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 197448 kb
Host smart-391dfe17-3762-4fa2-b689-614f70d17cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848558908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3848558908
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.4239509299
Short name T426
Test name
Test status
Simulation time 27542305082 ps
CPU time 46.99 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:17:05 PM PDT 24
Peak memory 200104 kb
Host smart-3e1fa55c-43e3-4c98-b779-829845adc3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239509299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.4239509299
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.113948241
Short name T1135
Test name
Test status
Simulation time 3001648647 ps
CPU time 89.73 seconds
Started Jul 29 07:16:16 PM PDT 24
Finished Jul 29 07:17:46 PM PDT 24
Peak memory 199916 kb
Host smart-ae85ae46-4837-4a59-8f53-7f3fc8669ec4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113948241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.113948241
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.4182176300
Short name T914
Test name
Test status
Simulation time 5256876236 ps
CPU time 7.67 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:27 PM PDT 24
Peak memory 198832 kb
Host smart-a13dcbff-a0a7-4de2-9935-7cba959ad834
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182176300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.4182176300
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.3640398678
Short name T6
Test name
Test status
Simulation time 76938337066 ps
CPU time 24.53 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:41 PM PDT 24
Peak memory 198884 kb
Host smart-024d5644-92f2-4ab1-a9e5-ad04006b4e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640398678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.3640398678
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2378802702
Short name T940
Test name
Test status
Simulation time 568089415 ps
CPU time 1.4 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:22 PM PDT 24
Peak memory 195664 kb
Host smart-75775718-4ff8-46fa-b917-a388cb59f624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378802702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2378802702
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3510147522
Short name T1102
Test name
Test status
Simulation time 497800333 ps
CPU time 2.28 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:23 PM PDT 24
Peak memory 199448 kb
Host smart-31acd602-4165-4dfa-85c5-26751b6676f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510147522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3510147522
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.41456374
Short name T236
Test name
Test status
Simulation time 178691234264 ps
CPU time 598.88 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:26:18 PM PDT 24
Peak memory 199976 kb
Host smart-bd9875c2-8fa7-46be-8ddc-efa4a0c2400d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.41456374
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.2260236911
Short name T528
Test name
Test status
Simulation time 20632276946 ps
CPU time 302.93 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:21:23 PM PDT 24
Peak memory 216016 kb
Host smart-ce97826e-d8c4-460f-b911-f6935adc8c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260236911 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.2260236911
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1365108268
Short name T738
Test name
Test status
Simulation time 12588280114 ps
CPU time 54.04 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:17:14 PM PDT 24
Peak memory 199860 kb
Host smart-f4cb4dce-feec-47a2-91cf-914df26eea38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365108268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1365108268
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3106069994
Short name T476
Test name
Test status
Simulation time 143472587838 ps
CPU time 39.83 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:59 PM PDT 24
Peak memory 199992 kb
Host smart-c2c2716a-62cd-422d-ab86-fc0e2c52e888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106069994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3106069994
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.1240119612
Short name T515
Test name
Test status
Simulation time 37264716 ps
CPU time 0.54 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 195008 kb
Host smart-60a2585e-44a2-45e8-b186-68b1ae7f46f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240119612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1240119612
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3384832116
Short name T837
Test name
Test status
Simulation time 49690053845 ps
CPU time 18.58 seconds
Started Jul 29 07:16:18 PM PDT 24
Finished Jul 29 07:16:37 PM PDT 24
Peak memory 199884 kb
Host smart-1376e304-e955-45cd-9b58-1b532abfb508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384832116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3384832116
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.3363327809
Short name T138
Test name
Test status
Simulation time 18664568707 ps
CPU time 30.1 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 199900 kb
Host smart-5b4fb68b-feda-4689-97e6-1e915d83e827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363327809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.3363327809
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.4264826646
Short name T1152
Test name
Test status
Simulation time 158296276633 ps
CPU time 121.88 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:18:21 PM PDT 24
Peak memory 199824 kb
Host smart-e2833887-8b6a-4131-ab75-7b044b69c28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264826646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.4264826646
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.1050782951
Short name T780
Test name
Test status
Simulation time 24577123605 ps
CPU time 8.32 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:16:28 PM PDT 24
Peak memory 200036 kb
Host smart-6b30ca5a-ff92-4875-86d8-77620c264fde
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050782951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1050782951
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2006407195
Short name T470
Test name
Test status
Simulation time 141609713287 ps
CPU time 598.76 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:26:18 PM PDT 24
Peak memory 199992 kb
Host smart-58e253c6-4ac1-47c4-bedc-07a810612bd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006407195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2006407195
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2287812563
Short name T432
Test name
Test status
Simulation time 10672328729 ps
CPU time 23.2 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:43 PM PDT 24
Peak memory 198256 kb
Host smart-006d6ee5-5c64-419f-b307-016d4f83a4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287812563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2287812563
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.2450227307
Short name T1068
Test name
Test status
Simulation time 19905437717 ps
CPU time 16.57 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:34 PM PDT 24
Peak memory 199860 kb
Host smart-4280e64f-8fbf-406e-bf58-0d7205026a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450227307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.2450227307
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.451754165
Short name T1011
Test name
Test status
Simulation time 15969208870 ps
CPU time 954.56 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:32:15 PM PDT 24
Peak memory 199976 kb
Host smart-8cdaaa7b-0c6b-46c9-8fed-6566b92157ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451754165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.451754165
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1990366221
Short name T567
Test name
Test status
Simulation time 4517900991 ps
CPU time 3.23 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:24 PM PDT 24
Peak memory 198112 kb
Host smart-f1f1d1d5-b4f4-42d7-a97a-92c0256278dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1990366221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1990366221
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.4030659593
Short name T455
Test name
Test status
Simulation time 21966366329 ps
CPU time 30.87 seconds
Started Jul 29 07:16:17 PM PDT 24
Finished Jul 29 07:16:48 PM PDT 24
Peak memory 199916 kb
Host smart-dcf941d3-003a-4d22-ae34-e8bc16397bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030659593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.4030659593
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3661616111
Short name T692
Test name
Test status
Simulation time 33235605752 ps
CPU time 13.89 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:34 PM PDT 24
Peak memory 196104 kb
Host smart-e16519a3-2b21-42cd-902a-8eedafb62ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661616111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3661616111
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.952154534
Short name T394
Test name
Test status
Simulation time 142849037 ps
CPU time 0.84 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:22 PM PDT 24
Peak memory 197904 kb
Host smart-6d3b366e-8fdc-4d8c-8975-53ff1c2176f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952154534 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.952154534
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.3984610941
Short name T489
Test name
Test status
Simulation time 95008903465 ps
CPU time 33.83 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:55 PM PDT 24
Peak memory 199952 kb
Host smart-e56efeda-b459-4fdb-bdaa-e341218663e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984610941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.3984610941
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.4219378397
Short name T915
Test name
Test status
Simulation time 33002363744 ps
CPU time 361.62 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:22:23 PM PDT 24
Peak memory 209864 kb
Host smart-369579b4-5ed5-4aca-8687-32579b320571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219378397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.4219378397
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1745421574
Short name T942
Test name
Test status
Simulation time 8106686399 ps
CPU time 8.5 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:28 PM PDT 24
Peak memory 199996 kb
Host smart-85aa62ac-b7fa-4d6b-bbf9-7ecdd006c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745421574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1745421574
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.526186191
Short name T910
Test name
Test status
Simulation time 1398923290 ps
CPU time 2.88 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:16:23 PM PDT 24
Peak memory 197644 kb
Host smart-add3180a-a288-49b2-b355-347453c9a956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526186191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.526186191
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.714334149
Short name T740
Test name
Test status
Simulation time 34006163 ps
CPU time 0.56 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:16:45 PM PDT 24
Peak memory 195308 kb
Host smart-4d893a45-a79b-40f6-a63c-fc0f7703cc99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714334149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.714334149
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.473995611
Short name T658
Test name
Test status
Simulation time 228687163458 ps
CPU time 214.45 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:19:56 PM PDT 24
Peak memory 199980 kb
Host smart-7005c289-94f0-4219-9402-6585300c63c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473995611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.473995611
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.4117809465
Short name T134
Test name
Test status
Simulation time 13014623606 ps
CPU time 20.57 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:42 PM PDT 24
Peak memory 199988 kb
Host smart-c97b9a50-ea33-48e4-904b-17df8ad8eb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117809465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.4117809465
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.400274595
Short name T954
Test name
Test status
Simulation time 102948175898 ps
CPU time 38.3 seconds
Started Jul 29 07:16:19 PM PDT 24
Finished Jul 29 07:16:58 PM PDT 24
Peak memory 199908 kb
Host smart-cef9de53-069a-42d6-8538-6905d8652d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400274595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.400274595
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.2493221738
Short name T874
Test name
Test status
Simulation time 249344572055 ps
CPU time 164.87 seconds
Started Jul 29 07:16:48 PM PDT 24
Finished Jul 29 07:19:33 PM PDT 24
Peak memory 199580 kb
Host smart-46817e6f-026f-4f0e-a679-87425e66f76f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493221738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2493221738
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.513311756
Short name T35
Test name
Test status
Simulation time 164862234162 ps
CPU time 351.36 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:22:34 PM PDT 24
Peak memory 199956 kb
Host smart-7197f4e2-2bba-4788-95e1-b73d38837988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=513311756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.513311756
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2051197949
Short name T357
Test name
Test status
Simulation time 1264431638 ps
CPU time 3.75 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 197416 kb
Host smart-cf940327-3c0e-49f2-805e-a73d9da2a183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051197949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2051197949
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2478640799
Short name T953
Test name
Test status
Simulation time 169888212557 ps
CPU time 71.86 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:17:55 PM PDT 24
Peak memory 200028 kb
Host smart-63f57d6d-9a7b-4d85-8f84-ff65bdf91858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478640799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2478640799
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.171519153
Short name T795
Test name
Test status
Simulation time 5323510298 ps
CPU time 202.99 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:20:08 PM PDT 24
Peak memory 199664 kb
Host smart-e1cd352c-9a3f-4a83-8946-c78d832e3781
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=171519153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.171519153
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.289865253
Short name T767
Test name
Test status
Simulation time 5755512633 ps
CPU time 23.08 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:17:06 PM PDT 24
Peak memory 199904 kb
Host smart-06a3b4e0-0a3c-461c-a221-b4e004f0abaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=289865253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.289865253
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.561701542
Short name T1008
Test name
Test status
Simulation time 88129150236 ps
CPU time 66.39 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:17:52 PM PDT 24
Peak memory 199836 kb
Host smart-6fa8ea25-96a7-495c-a438-272f21637608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561701542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.561701542
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3426487804
Short name T1045
Test name
Test status
Simulation time 1888331141 ps
CPU time 3.63 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:16:47 PM PDT 24
Peak memory 195572 kb
Host smart-990b4b3a-df4c-47ea-95bc-7974aabe1eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426487804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3426487804
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.4139937966
Short name T1013
Test name
Test status
Simulation time 695590087 ps
CPU time 1.45 seconds
Started Jul 29 07:16:21 PM PDT 24
Finished Jul 29 07:16:23 PM PDT 24
Peak memory 198556 kb
Host smart-e7e9657a-2fe3-48da-b8d1-de47b2b7dc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139937966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.4139937966
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.1184592729
Short name T669
Test name
Test status
Simulation time 183485887376 ps
CPU time 88.44 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:18:14 PM PDT 24
Peak memory 199996 kb
Host smart-3a9b6b9a-3f9a-4da6-b546-d40028bcc29e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184592729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.1184592729
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.515087497
Short name T582
Test name
Test status
Simulation time 807523525 ps
CPU time 3.45 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 198596 kb
Host smart-16df09db-ac95-427b-b7e2-7d07ccaf7ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515087497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.515087497
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.208472737
Short name T392
Test name
Test status
Simulation time 34181402711 ps
CPU time 49.54 seconds
Started Jul 29 07:16:20 PM PDT 24
Finished Jul 29 07:17:10 PM PDT 24
Peak memory 199920 kb
Host smart-c4ec5491-06f4-48bc-b01e-c778ebff1658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208472737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.208472737
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.2388668653
Short name T1169
Test name
Test status
Simulation time 23884487 ps
CPU time 0.56 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:16:46 PM PDT 24
Peak memory 195160 kb
Host smart-9258dc77-c98b-4f5b-a183-cf80113f1b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388668653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2388668653
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.2131434417
Short name T1158
Test name
Test status
Simulation time 91019303294 ps
CPU time 40.34 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:17:23 PM PDT 24
Peak memory 199832 kb
Host smart-0922525b-66b6-4c9a-b751-0b2da71f93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131434417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2131434417
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.490548397
Short name T1063
Test name
Test status
Simulation time 143991952480 ps
CPU time 62.44 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:17:50 PM PDT 24
Peak memory 199968 kb
Host smart-8c09d61b-6ffc-4715-b42b-23053070e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490548397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.490548397
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2362330484
Short name T412
Test name
Test status
Simulation time 4669476896 ps
CPU time 8.21 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:16:53 PM PDT 24
Peak memory 199880 kb
Host smart-1af55d65-681b-4163-9479-10c9ffde3775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362330484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2362330484
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3095257336
Short name T991
Test name
Test status
Simulation time 218411931341 ps
CPU time 95.12 seconds
Started Jul 29 07:16:43 PM PDT 24
Finished Jul 29 07:18:19 PM PDT 24
Peak memory 199812 kb
Host smart-5be0276b-5e32-456b-9e7e-730c833b81f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095257336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3095257336
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2585642377
Short name T897
Test name
Test status
Simulation time 117874722815 ps
CPU time 300.33 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:21:45 PM PDT 24
Peak memory 199912 kb
Host smart-f4d19572-be03-4b9a-9c38-386a04c916ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2585642377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2585642377
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.1701775748
Short name T514
Test name
Test status
Simulation time 2608330643 ps
CPU time 2.45 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 197200 kb
Host smart-fd35495c-4039-4fb7-898d-6ca24a378dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701775748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.1701775748
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2243379188
Short name T725
Test name
Test status
Simulation time 9187086662 ps
CPU time 8.24 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:16:55 PM PDT 24
Peak memory 199948 kb
Host smart-3d667967-5caf-4211-b12c-14aa16b3d93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243379188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2243379188
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.3911224304
Short name T508
Test name
Test status
Simulation time 15968215531 ps
CPU time 199.33 seconds
Started Jul 29 07:16:49 PM PDT 24
Finished Jul 29 07:20:09 PM PDT 24
Peak memory 199896 kb
Host smart-d024fd21-7027-4fc3-84a1-68ed862a18aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911224304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.3911224304
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.3541524813
Short name T650
Test name
Test status
Simulation time 3553264188 ps
CPU time 22.91 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:17:09 PM PDT 24
Peak memory 198276 kb
Host smart-9c87fb98-4d28-49d5-90e0-4887b5b1aa87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3541524813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.3541524813
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2451809029
Short name T564
Test name
Test status
Simulation time 130206298408 ps
CPU time 107.5 seconds
Started Jul 29 07:16:42 PM PDT 24
Finished Jul 29 07:18:30 PM PDT 24
Peak memory 199988 kb
Host smart-c73d1ca4-c9e5-42a4-8e47-3b27d2ed4796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451809029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2451809029
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2102100139
Short name T980
Test name
Test status
Simulation time 3332742357 ps
CPU time 5.03 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:16:49 PM PDT 24
Peak memory 196580 kb
Host smart-c4317852-6b5f-4ca3-96ae-191306985989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102100139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2102100139
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2537815932
Short name T40
Test name
Test status
Simulation time 5690488302 ps
CPU time 9.33 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:16:53 PM PDT 24
Peak memory 199708 kb
Host smart-631e91f9-b9f8-40bf-859a-abefa7cd4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537815932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2537815932
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4257212877
Short name T801
Test name
Test status
Simulation time 9040495635 ps
CPU time 19.38 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:17:04 PM PDT 24
Peak memory 199880 kb
Host smart-f30b8c77-2135-4667-9294-4c6ee0c1be76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257212877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4257212877
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.1557688532
Short name T960
Test name
Test status
Simulation time 7921333718 ps
CPU time 64.07 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:17:50 PM PDT 24
Peak memory 215524 kb
Host smart-074c1f8f-6b61-4126-ad76-841c9d908a93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557688532 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.1557688532
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2720503535
Short name T877
Test name
Test status
Simulation time 1507772075 ps
CPU time 1.52 seconds
Started Jul 29 07:16:42 PM PDT 24
Finished Jul 29 07:16:44 PM PDT 24
Peak memory 198552 kb
Host smart-cf91fc54-8a65-49aa-8664-d17e95bb51aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720503535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2720503535
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.3173759905
Short name T1059
Test name
Test status
Simulation time 111876500392 ps
CPU time 60.96 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:17:45 PM PDT 24
Peak memory 199896 kb
Host smart-fe2acfe9-12aa-44d6-adac-1b01a5312fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173759905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.3173759905
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.952894562
Short name T424
Test name
Test status
Simulation time 15389327 ps
CPU time 0.53 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:16:46 PM PDT 24
Peak memory 195756 kb
Host smart-b775faf8-3c41-4376-9d84-5ce835b7520f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952894562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.952894562
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1327385370
Short name T446
Test name
Test status
Simulation time 135939834805 ps
CPU time 42.81 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:17:27 PM PDT 24
Peak memory 199960 kb
Host smart-23fbdc95-3d9a-4b91-8fde-5238efffd95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327385370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1327385370
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.2814807911
Short name T831
Test name
Test status
Simulation time 130044405093 ps
CPU time 462.5 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:24:28 PM PDT 24
Peak memory 200092 kb
Host smart-c7bf54b1-6b16-4bce-a58d-96ee95f5487a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814807911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.2814807911
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.2375942747
Short name T474
Test name
Test status
Simulation time 324662330684 ps
CPU time 24.69 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:17:12 PM PDT 24
Peak memory 199912 kb
Host smart-27d29fbf-6206-487b-928a-089b3aa9634c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375942747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2375942747
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.298300301
Short name T737
Test name
Test status
Simulation time 69103616150 ps
CPU time 27.68 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:17:14 PM PDT 24
Peak memory 199928 kb
Host smart-165005cf-7f04-4ec7-8650-cb0557313574
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298300301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.298300301
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.2857238433
Short name T774
Test name
Test status
Simulation time 128250998407 ps
CPU time 408.6 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:23:35 PM PDT 24
Peak memory 199924 kb
Host smart-b14e76a0-28a4-48d7-9b04-1628d4df6efc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2857238433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.2857238433
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.737188414
Short name T734
Test name
Test status
Simulation time 6186178817 ps
CPU time 11.31 seconds
Started Jul 29 07:16:48 PM PDT 24
Finished Jul 29 07:17:00 PM PDT 24
Peak memory 197892 kb
Host smart-45513bcf-56cb-4447-af09-3082f578a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737188414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.737188414
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1023232838
Short name T1120
Test name
Test status
Simulation time 120598208935 ps
CPU time 82.99 seconds
Started Jul 29 07:16:46 PM PDT 24
Finished Jul 29 07:18:09 PM PDT 24
Peak memory 199988 kb
Host smart-5b7bc125-7573-491e-8cf0-f038ecc7dac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023232838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1023232838
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.2979720353
Short name T417
Test name
Test status
Simulation time 12496313854 ps
CPU time 97.62 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:18:22 PM PDT 24
Peak memory 199980 kb
Host smart-24409466-9670-432f-a902-45d7a1a81194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979720353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2979720353
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1401574905
Short name T744
Test name
Test status
Simulation time 2135759432 ps
CPU time 3.1 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:16:48 PM PDT 24
Peak memory 198908 kb
Host smart-9010e257-6ce9-4ac8-acd2-7cfd51fb4e5a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1401574905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1401574905
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.1113831867
Short name T271
Test name
Test status
Simulation time 30852790803 ps
CPU time 35.28 seconds
Started Jul 29 07:16:45 PM PDT 24
Finished Jul 29 07:17:21 PM PDT 24
Peak memory 199944 kb
Host smart-df6ad6b0-1905-428a-9644-835856b4f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113831867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.1113831867
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2905081749
Short name T365
Test name
Test status
Simulation time 2834521131 ps
CPU time 2.76 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:16:50 PM PDT 24
Peak memory 195740 kb
Host smart-de26cec9-74e2-4762-a8dd-744756dc7932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905081749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2905081749
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.442631701
Short name T690
Test name
Test status
Simulation time 5459693584 ps
CPU time 9.43 seconds
Started Jul 29 07:16:49 PM PDT 24
Finished Jul 29 07:16:59 PM PDT 24
Peak memory 199740 kb
Host smart-0651ef48-0455-4a4b-add4-cd21c401eabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442631701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.442631701
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1445975633
Short name T797
Test name
Test status
Simulation time 233591587892 ps
CPU time 1456.23 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:41:04 PM PDT 24
Peak memory 208300 kb
Host smart-e8a4d9e2-3636-4a7d-a8b3-b300eac9fdc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445975633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1445975633
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.668381425
Short name T757
Test name
Test status
Simulation time 102696255425 ps
CPU time 258.61 seconds
Started Jul 29 07:16:48 PM PDT 24
Finished Jul 29 07:21:07 PM PDT 24
Peak memory 216508 kb
Host smart-d7554692-a9e4-42b2-89bf-154507861eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668381425 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.668381425
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2956709567
Short name T1116
Test name
Test status
Simulation time 952918721 ps
CPU time 2.44 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:16:50 PM PDT 24
Peak memory 198748 kb
Host smart-4ca5ca22-15a0-4195-8767-8a0f3c65e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956709567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2956709567
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.147596008
Short name T1103
Test name
Test status
Simulation time 36317590824 ps
CPU time 54.95 seconds
Started Jul 29 07:16:44 PM PDT 24
Finished Jul 29 07:17:39 PM PDT 24
Peak memory 199904 kb
Host smart-0b70b31a-4aa8-42ed-9e0a-de01f8fb4cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147596008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.147596008
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.114032331
Short name T22
Test name
Test status
Simulation time 24689536 ps
CPU time 0.56 seconds
Started Jul 29 07:17:05 PM PDT 24
Finished Jul 29 07:17:05 PM PDT 24
Peak memory 195340 kb
Host smart-c35dd0af-d4ff-4773-a1b5-2e6069a11a90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114032331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.114032331
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.824031002
Short name T1042
Test name
Test status
Simulation time 91549664878 ps
CPU time 131.01 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:19:15 PM PDT 24
Peak memory 199856 kb
Host smart-14f51347-f851-4b29-b6f9-58a4d872dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824031002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.824031002
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.4118661552
Short name T444
Test name
Test status
Simulation time 16079446293 ps
CPU time 22.82 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:17:34 PM PDT 24
Peak memory 199848 kb
Host smart-84f1b921-6c02-4211-8943-384f866fe046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118661552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4118661552
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2797272629
Short name T242
Test name
Test status
Simulation time 45232878547 ps
CPU time 17.07 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:17:26 PM PDT 24
Peak memory 199984 kb
Host smart-76eb7a76-4998-42c4-8f22-e80989866ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797272629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2797272629
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.2926010568
Short name T122
Test name
Test status
Simulation time 51241929166 ps
CPU time 55.94 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:18:01 PM PDT 24
Peak memory 199872 kb
Host smart-7301ef4d-141e-4bd5-93ab-b1ac504e9b0f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926010568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.2926010568
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2233915348
Short name T1143
Test name
Test status
Simulation time 20427581175 ps
CPU time 82.94 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:18:34 PM PDT 24
Peak memory 199908 kb
Host smart-54ee2b75-2581-4bd0-b3ad-4e070e926818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233915348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2233915348
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.128855631
Short name T47
Test name
Test status
Simulation time 8675935179 ps
CPU time 9.95 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:17:19 PM PDT 24
Peak memory 198816 kb
Host smart-82826a2e-763f-49f0-9d39-410a96ec9982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128855631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.128855631
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4157251799
Short name T825
Test name
Test status
Simulation time 70030376231 ps
CPU time 110.83 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:19:00 PM PDT 24
Peak memory 198868 kb
Host smart-2ac8de99-acdf-484f-a920-376e9e6c7951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157251799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4157251799
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.2781264002
Short name T484
Test name
Test status
Simulation time 20214779258 ps
CPU time 179.45 seconds
Started Jul 29 07:17:10 PM PDT 24
Finished Jul 29 07:20:10 PM PDT 24
Peak memory 199964 kb
Host smart-37c07cf7-948f-4ae2-b9f8-13d4bf49271f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2781264002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2781264002
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.4264338624
Short name T1043
Test name
Test status
Simulation time 4543507385 ps
CPU time 34.11 seconds
Started Jul 29 07:17:08 PM PDT 24
Finished Jul 29 07:17:42 PM PDT 24
Peak memory 198556 kb
Host smart-33f2d7e4-bc6e-4f6d-ab80-31b9ae59f60b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264338624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.4264338624
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.3914792609
Short name T770
Test name
Test status
Simulation time 165231909104 ps
CPU time 104.42 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:18:49 PM PDT 24
Peak memory 199924 kb
Host smart-f1ec7c5f-2c16-4dfa-b0ee-dbb397b9a5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914792609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.3914792609
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2977166369
Short name T1065
Test name
Test status
Simulation time 1148596024 ps
CPU time 2.43 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:17:14 PM PDT 24
Peak memory 195336 kb
Host smart-a7818549-fdc5-4fc1-aec4-5112393d2cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977166369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2977166369
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.1635205154
Short name T783
Test name
Test status
Simulation time 5382461057 ps
CPU time 9.64 seconds
Started Jul 29 07:16:48 PM PDT 24
Finished Jul 29 07:16:58 PM PDT 24
Peak memory 199344 kb
Host smart-6bce4997-9564-4f5f-a7e8-21b8b26108cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635205154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.1635205154
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2038436437
Short name T282
Test name
Test status
Simulation time 39312799306 ps
CPU time 152.16 seconds
Started Jul 29 07:17:10 PM PDT 24
Finished Jul 29 07:19:42 PM PDT 24
Peak memory 208316 kb
Host smart-dc6f39f3-9013-4428-9e59-a84283cd7dfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038436437 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2038436437
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2114909191
Short name T1117
Test name
Test status
Simulation time 7182609016 ps
CPU time 10.05 seconds
Started Jul 29 07:17:05 PM PDT 24
Finished Jul 29 07:17:16 PM PDT 24
Peak memory 199896 kb
Host smart-2f423d6a-3ce6-4c4c-bcb0-5094c4ac2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114909191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2114909191
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.529341496
Short name T821
Test name
Test status
Simulation time 74210097132 ps
CPU time 117.51 seconds
Started Jul 29 07:16:47 PM PDT 24
Finished Jul 29 07:18:45 PM PDT 24
Peak memory 199960 kb
Host smart-57e2820a-5ca0-44d8-96d7-9d5dc8969232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529341496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.529341496
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.3940001767
Short name T759
Test name
Test status
Simulation time 14615655 ps
CPU time 0.55 seconds
Started Jul 29 07:12:29 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 195356 kb
Host smart-d0bf7506-5055-42d2-ae8a-cd7cc6df159c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940001767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.3940001767
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.1525757259
Short name T876
Test name
Test status
Simulation time 170402244629 ps
CPU time 78.7 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:13:47 PM PDT 24
Peak memory 199928 kb
Host smart-b91413da-6d5b-4f1b-a9db-8477d5844e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525757259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.1525757259
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3772813536
Short name T471
Test name
Test status
Simulation time 161123697076 ps
CPU time 125.45 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:14:31 PM PDT 24
Peak memory 199976 kb
Host smart-0cc2d5bb-2653-44c0-b8ba-73c9ebb0223c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772813536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3772813536
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1869733340
Short name T676
Test name
Test status
Simulation time 32760438634 ps
CPU time 27.24 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:12:55 PM PDT 24
Peak memory 199904 kb
Host smart-93a30d60-0f34-4084-9a18-c58887516df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869733340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1869733340
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1125132859
Short name T751
Test name
Test status
Simulation time 43560777202 ps
CPU time 66.51 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:13:35 PM PDT 24
Peak memory 199872 kb
Host smart-0ba23779-9d95-47fe-b91a-f7303e988990
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125132859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1125132859
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3388569390
Short name T1002
Test name
Test status
Simulation time 73597529648 ps
CPU time 532.76 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:21:24 PM PDT 24
Peak memory 199856 kb
Host smart-ec2524bc-8d7c-4472-bf8e-769814fa0f38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3388569390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3388569390
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.1531781750
Short name T511
Test name
Test status
Simulation time 6245079009 ps
CPU time 15.96 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:12:44 PM PDT 24
Peak memory 198672 kb
Host smart-8335baa0-63e9-40e7-8cb8-33996bf4d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531781750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.1531781750
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.256211747
Short name T651
Test name
Test status
Simulation time 33858816735 ps
CPU time 119.43 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:14:28 PM PDT 24
Peak memory 200100 kb
Host smart-a168be31-0659-4cb1-b88c-d6a39f3bb6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256211747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.256211747
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.1734441842
Short name T36
Test name
Test status
Simulation time 3914046802 ps
CPU time 232.71 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:16:20 PM PDT 24
Peak memory 199972 kb
Host smart-a4c1b97c-335c-45ae-b4a8-367ff26abe99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734441842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.1734441842
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1692826767
Short name T420
Test name
Test status
Simulation time 4433254127 ps
CPU time 41.29 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:13:09 PM PDT 24
Peak memory 199236 kb
Host smart-2e88a913-9f77-4e41-b265-efbd7a01b7c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692826767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1692826767
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.888446557
Short name T580
Test name
Test status
Simulation time 158318732189 ps
CPU time 102.21 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:14:11 PM PDT 24
Peak memory 199980 kb
Host smart-8ee4dce4-b31c-4c5d-ae88-0faca2b7bba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888446557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.888446557
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.243939993
Short name T525
Test name
Test status
Simulation time 574957578 ps
CPU time 0.86 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:12:29 PM PDT 24
Peak memory 195472 kb
Host smart-9c3bde68-6d12-4cc7-b1db-1684caaf8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243939993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.243939993
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2046407267
Short name T267
Test name
Test status
Simulation time 496109662 ps
CPU time 1.77 seconds
Started Jul 29 07:12:28 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 198952 kb
Host smart-ceb1d0d7-cfd1-4e19-9853-8106399a9173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046407267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2046407267
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2554740188
Short name T264
Test name
Test status
Simulation time 38780520085 ps
CPU time 463.78 seconds
Started Jul 29 07:12:30 PM PDT 24
Finished Jul 29 07:20:14 PM PDT 24
Peak memory 199852 kb
Host smart-abb5f3e3-8392-4bde-9725-c1a8b3769248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554740188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2554740188
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.644975789
Short name T688
Test name
Test status
Simulation time 45633827625 ps
CPU time 244.41 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:16:31 PM PDT 24
Peak memory 215456 kb
Host smart-a5034c82-fcbb-4789-8b89-2a8d0e0a68bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644975789 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.644975789
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.1473344174
Short name T899
Test name
Test status
Simulation time 1940630139 ps
CPU time 2.72 seconds
Started Jul 29 07:12:25 PM PDT 24
Finished Jul 29 07:12:28 PM PDT 24
Peak memory 198332 kb
Host smart-05b3e708-d930-463f-98a5-545c351b2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473344174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1473344174
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2839056077
Short name T1104
Test name
Test status
Simulation time 19856467503 ps
CPU time 30.48 seconds
Started Jul 29 07:12:26 PM PDT 24
Finished Jul 29 07:12:57 PM PDT 24
Peak memory 199964 kb
Host smart-eb94956f-58d4-4f53-bb5a-120bfcdcce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839056077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2839056077
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2210740570
Short name T3
Test name
Test status
Simulation time 192392003388 ps
CPU time 79.43 seconds
Started Jul 29 07:17:14 PM PDT 24
Finished Jul 29 07:18:34 PM PDT 24
Peak memory 199884 kb
Host smart-59cf61db-a1d3-411f-99f9-1eeacdbd5d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210740570 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2210740570
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.139267938
Short name T634
Test name
Test status
Simulation time 154389321263 ps
CPU time 535.56 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:26:05 PM PDT 24
Peak memory 225832 kb
Host smart-d8574668-8a01-4d00-8e64-6c3c04210ff7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139267938 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.139267938
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2791953126
Short name T162
Test name
Test status
Simulation time 73638113287 ps
CPU time 120.78 seconds
Started Jul 29 07:17:14 PM PDT 24
Finished Jul 29 07:19:15 PM PDT 24
Peak memory 199964 kb
Host smart-1bd3f0dc-53ed-473c-8e01-b9f91661570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791953126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2791953126
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.2027737920
Short name T498
Test name
Test status
Simulation time 159124710496 ps
CPU time 458.43 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:24:43 PM PDT 24
Peak memory 216500 kb
Host smart-f1861b60-01d3-418a-9cd5-9bf2840f97bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027737920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.2027737920
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.1981529249
Short name T13
Test name
Test status
Simulation time 39382543440 ps
CPU time 129.19 seconds
Started Jul 29 07:17:13 PM PDT 24
Finished Jul 29 07:19:22 PM PDT 24
Peak memory 212088 kb
Host smart-1effba1d-a734-4233-80c3-20dd51f4bcfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981529249 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.1981529249
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3686816110
Short name T956
Test name
Test status
Simulation time 48120721915 ps
CPU time 380.51 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:23:30 PM PDT 24
Peak memory 209344 kb
Host smart-02b24551-1876-4f30-84d5-404a31267d45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686816110 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3686816110
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2709501671
Short name T194
Test name
Test status
Simulation time 77538366071 ps
CPU time 27.67 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:17:40 PM PDT 24
Peak memory 200008 kb
Host smart-b364e71c-fe77-40ba-8361-c759c5377877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709501671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2709501671
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.3808621434
Short name T1009
Test name
Test status
Simulation time 68052503222 ps
CPU time 212.84 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:20:42 PM PDT 24
Peak memory 216444 kb
Host smart-0396ad5f-65ce-4952-86d0-460e8909eeeb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808621434 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.3808621434
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1241124273
Short name T177
Test name
Test status
Simulation time 41807130274 ps
CPU time 70.43 seconds
Started Jul 29 07:17:07 PM PDT 24
Finished Jul 29 07:18:18 PM PDT 24
Peak memory 199932 kb
Host smart-28305f98-316e-444b-9a49-71975a1b3061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241124273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1241124273
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1236491128
Short name T186
Test name
Test status
Simulation time 235035335218 ps
CPU time 885.54 seconds
Started Jul 29 07:17:06 PM PDT 24
Finished Jul 29 07:31:52 PM PDT 24
Peak memory 226864 kb
Host smart-01ffe53b-ddfa-4114-9975-ab6c3c2da122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236491128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1236491128
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1796647622
Short name T683
Test name
Test status
Simulation time 25463994198 ps
CPU time 9.69 seconds
Started Jul 29 07:17:07 PM PDT 24
Finished Jul 29 07:17:17 PM PDT 24
Peak memory 199992 kb
Host smart-0d81b07b-7b29-4abf-8f4a-a29095964158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796647622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1796647622
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2522064944
Short name T1176
Test name
Test status
Simulation time 121073692744 ps
CPU time 814.3 seconds
Started Jul 29 07:17:10 PM PDT 24
Finished Jul 29 07:30:45 PM PDT 24
Peak memory 216504 kb
Host smart-68e4b86c-7e21-494e-8c8f-c5851a0f196d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522064944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2522064944
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3322115591
Short name T123
Test name
Test status
Simulation time 22705580242 ps
CPU time 34.46 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:17:43 PM PDT 24
Peak memory 199920 kb
Host smart-32c896ca-dd0b-418e-8e0c-945a4e8bf8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322115591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3322115591
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1027551712
Short name T798
Test name
Test status
Simulation time 11140846458 ps
CPU time 128.42 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:19:19 PM PDT 24
Peak memory 209508 kb
Host smart-f3c7347e-1411-48ae-8abd-abd123514931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027551712 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1027551712
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3455267031
Short name T1151
Test name
Test status
Simulation time 94340865901 ps
CPU time 43.67 seconds
Started Jul 29 07:17:13 PM PDT 24
Finished Jul 29 07:17:57 PM PDT 24
Peak memory 200036 kb
Host smart-bad1a1b4-7320-446c-a558-62919d98148e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455267031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3455267031
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.4002097212
Short name T1150
Test name
Test status
Simulation time 20284804487 ps
CPU time 172.48 seconds
Started Jul 29 07:17:14 PM PDT 24
Finished Jul 29 07:20:07 PM PDT 24
Peak memory 215420 kb
Host smart-bc0c09fc-a1c1-4d0c-8600-523137ce7e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002097212 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.4002097212
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.2781412608
Short name T641
Test name
Test status
Simulation time 20944607836 ps
CPU time 32.61 seconds
Started Jul 29 07:17:10 PM PDT 24
Finished Jul 29 07:17:43 PM PDT 24
Peak memory 199980 kb
Host smart-9c161fdf-9c5f-4b42-8ca8-afefe7f3a8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781412608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.2781412608
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.3637145538
Short name T1178
Test name
Test status
Simulation time 243845688295 ps
CPU time 397.59 seconds
Started Jul 29 07:17:08 PM PDT 24
Finished Jul 29 07:23:46 PM PDT 24
Peak memory 216644 kb
Host smart-4190621a-7487-4538-b28f-328a687c66b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637145538 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.3637145538
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1899853302
Short name T1115
Test name
Test status
Simulation time 18998350 ps
CPU time 0.55 seconds
Started Jul 29 07:12:30 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 195624 kb
Host smart-53a767ec-dd3a-4806-b68c-645865a6afcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899853302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1899853302
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3329863785
Short name T890
Test name
Test status
Simulation time 137100861395 ps
CPU time 50.91 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:13:22 PM PDT 24
Peak memory 199732 kb
Host smart-fc6b0913-664a-4c66-9b12-58093194ca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329863785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3329863785
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.1963920786
Short name T500
Test name
Test status
Simulation time 82176725558 ps
CPU time 34.32 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:13:05 PM PDT 24
Peak memory 199924 kb
Host smart-b0d09de3-0783-4eaa-a441-7ad1961e2e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963920786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.1963920786
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.3812804557
Short name T237
Test name
Test status
Simulation time 105542571158 ps
CPU time 92.1 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:14:03 PM PDT 24
Peak memory 199900 kb
Host smart-de80afa8-36e6-4422-bfa2-7f3f24e65f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812804557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3812804557
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1410550342
Short name T359
Test name
Test status
Simulation time 6774971318 ps
CPU time 2.01 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:12:33 PM PDT 24
Peak memory 196692 kb
Host smart-cb65909f-89b6-4c5f-abbf-d70671b9966d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410550342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1410550342
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1701898475
Short name T684
Test name
Test status
Simulation time 64232827343 ps
CPU time 270.45 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:16:58 PM PDT 24
Peak memory 199940 kb
Host smart-69d797d3-ded3-4e7b-8c92-d2f43ac9a518
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701898475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1701898475
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.4102185091
Short name T695
Test name
Test status
Simulation time 7099534971 ps
CPU time 4.12 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:12:35 PM PDT 24
Peak memory 198744 kb
Host smart-bacbd043-99dc-476a-afbb-1792cefb8ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102185091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.4102185091
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1919788868
Short name T642
Test name
Test status
Simulation time 194497058884 ps
CPU time 132.43 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:14:39 PM PDT 24
Peak memory 200072 kb
Host smart-8342431b-8c95-4991-aef9-6c1061aa98f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919788868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1919788868
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.4231350905
Short name T547
Test name
Test status
Simulation time 11761104134 ps
CPU time 697.34 seconds
Started Jul 29 07:12:30 PM PDT 24
Finished Jul 29 07:24:07 PM PDT 24
Peak memory 199964 kb
Host smart-28fb346e-63a4-49d6-8e06-1afea325eecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4231350905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.4231350905
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.3216233639
Short name T388
Test name
Test status
Simulation time 6736215562 ps
CPU time 17.56 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:12:48 PM PDT 24
Peak memory 199180 kb
Host smart-8c6f96a7-ad0e-4798-a9c9-3e903ac1d112
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3216233639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.3216233639
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.846611805
Short name T578
Test name
Test status
Simulation time 123280768583 ps
CPU time 276.87 seconds
Started Jul 29 07:12:29 PM PDT 24
Finished Jul 29 07:17:06 PM PDT 24
Peak memory 199972 kb
Host smart-5a29a965-6ced-4887-9da5-a8c1f538be84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846611805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.846611805
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.15371346
Short name T974
Test name
Test status
Simulation time 3279384019 ps
CPU time 2.01 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:12:30 PM PDT 24
Peak memory 196236 kb
Host smart-92129686-f638-477b-b8b2-1dc8b165b008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15371346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.15371346
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.2358324004
Short name T360
Test name
Test status
Simulation time 488093005 ps
CPU time 1.97 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:12:33 PM PDT 24
Peak memory 198568 kb
Host smart-e163498a-5f24-47d7-ba8c-2653da782afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358324004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.2358324004
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.483341441
Short name T280
Test name
Test status
Simulation time 166505241160 ps
CPU time 475.03 seconds
Started Jul 29 07:12:27 PM PDT 24
Finished Jul 29 07:20:22 PM PDT 24
Peak memory 199932 kb
Host smart-5c72ccdf-cda7-493e-9486-f06980175a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483341441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.483341441
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3131563745
Short name T773
Test name
Test status
Simulation time 839129364 ps
CPU time 2.56 seconds
Started Jul 29 07:12:30 PM PDT 24
Finished Jul 29 07:12:33 PM PDT 24
Peak memory 199148 kb
Host smart-da8b0fe0-a300-4e42-9811-02c78c21ff08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131563745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3131563745
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3404014275
Short name T878
Test name
Test status
Simulation time 81302402181 ps
CPU time 43.12 seconds
Started Jul 29 07:12:31 PM PDT 24
Finished Jul 29 07:13:14 PM PDT 24
Peak memory 199956 kb
Host smart-9a9d8044-5712-4dd7-8298-e8d42405fa86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404014275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3404014275
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1764827045
Short name T120
Test name
Test status
Simulation time 84522404605 ps
CPU time 43.43 seconds
Started Jul 29 07:17:03 PM PDT 24
Finished Jul 29 07:17:47 PM PDT 24
Peak memory 199964 kb
Host smart-b1216195-8353-4d84-a948-8c9e1578131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764827045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1764827045
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2363659993
Short name T930
Test name
Test status
Simulation time 57082225954 ps
CPU time 31.38 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:17:43 PM PDT 24
Peak memory 199904 kb
Host smart-351f02aa-09d3-438a-b7f3-9e9bfc917e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363659993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2363659993
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2549971610
Short name T10
Test name
Test status
Simulation time 28217862660 ps
CPU time 353.11 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:23:05 PM PDT 24
Peak memory 208292 kb
Host smart-b1007cf0-22fb-48f6-aef6-c6224d07c6b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549971610 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2549971610
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.669982365
Short name T554
Test name
Test status
Simulation time 24115957858 ps
CPU time 18.86 seconds
Started Jul 29 07:17:04 PM PDT 24
Finished Jul 29 07:17:24 PM PDT 24
Peak memory 199892 kb
Host smart-92223977-8af4-4612-851c-c7f5e993a5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669982365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.669982365
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.682266877
Short name T835
Test name
Test status
Simulation time 13114103204 ps
CPU time 21.47 seconds
Started Jul 29 07:17:06 PM PDT 24
Finished Jul 29 07:17:28 PM PDT 24
Peak memory 199972 kb
Host smart-3ba89d78-983e-4bac-bc82-089206b4ab56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682266877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.682266877
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.4267370207
Short name T110
Test name
Test status
Simulation time 46759441017 ps
CPU time 380.35 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:23:33 PM PDT 24
Peak memory 216440 kb
Host smart-5464aaf8-372c-4baa-a4ff-a4bfc9e1cd70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267370207 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.4267370207
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1647716951
Short name T644
Test name
Test status
Simulation time 120934941731 ps
CPU time 88.86 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:18:41 PM PDT 24
Peak memory 199972 kb
Host smart-2e811566-85f5-4517-ab42-14ae8c1dc79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647716951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1647716951
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2814332452
Short name T78
Test name
Test status
Simulation time 67142820755 ps
CPU time 476.98 seconds
Started Jul 29 07:17:07 PM PDT 24
Finished Jul 29 07:25:04 PM PDT 24
Peak memory 216468 kb
Host smart-0b4d79d5-a273-47b8-90e0-413554d6fe35
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814332452 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2814332452
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.637245637
Short name T216
Test name
Test status
Simulation time 201798954794 ps
CPU time 41.48 seconds
Started Jul 29 07:17:12 PM PDT 24
Finished Jul 29 07:17:54 PM PDT 24
Peak memory 200132 kb
Host smart-20390432-0686-4450-ae4b-33f524225eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637245637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.637245637
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1937888284
Short name T1060
Test name
Test status
Simulation time 893392383242 ps
CPU time 834.82 seconds
Started Jul 29 07:17:03 PM PDT 24
Finished Jul 29 07:30:58 PM PDT 24
Peak memory 216484 kb
Host smart-50ebde88-9f72-4935-b2d8-6c42a8d84c52
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937888284 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1937888284
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.204254165
Short name T523
Test name
Test status
Simulation time 71135120902 ps
CPU time 59.13 seconds
Started Jul 29 07:17:11 PM PDT 24
Finished Jul 29 07:18:10 PM PDT 24
Peak memory 199900 kb
Host smart-e26fb7e9-9ba1-43e6-82b3-bf6b508109d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204254165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.204254165
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.1003907809
Short name T618
Test name
Test status
Simulation time 39432979344 ps
CPU time 22.15 seconds
Started Jul 29 07:17:08 PM PDT 24
Finished Jul 29 07:17:30 PM PDT 24
Peak memory 199984 kb
Host smart-bc258313-0562-4c42-91d7-a102d3f924f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003907809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.1003907809
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.350316229
Short name T998
Test name
Test status
Simulation time 75508531712 ps
CPU time 30.92 seconds
Started Jul 29 07:17:03 PM PDT 24
Finished Jul 29 07:17:34 PM PDT 24
Peak memory 199924 kb
Host smart-d8b2b8fd-2045-468d-a561-fdb33e614b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350316229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.350316229
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2437523332
Short name T858
Test name
Test status
Simulation time 202775795750 ps
CPU time 596.22 seconds
Started Jul 29 07:17:09 PM PDT 24
Finished Jul 29 07:27:05 PM PDT 24
Peak memory 216448 kb
Host smart-12ebecdb-53ae-4ac6-8030-0c62f22573c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437523332 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2437523332
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.883716970
Short name T820
Test name
Test status
Simulation time 128106590235 ps
CPU time 209.58 seconds
Started Jul 29 07:17:03 PM PDT 24
Finished Jul 29 07:20:32 PM PDT 24
Peak memory 199972 kb
Host smart-b6efc0d6-0937-4bd7-bfae-5e967af9db0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883716970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.883716970
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1476521934
Short name T635
Test name
Test status
Simulation time 36431215 ps
CPU time 0.55 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:47 PM PDT 24
Peak memory 194800 kb
Host smart-0a2df4e6-b036-4d64-acb4-8170e339fbd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476521934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1476521934
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.2512548273
Short name T1141
Test name
Test status
Simulation time 209301167764 ps
CPU time 162.82 seconds
Started Jul 29 07:12:48 PM PDT 24
Finished Jul 29 07:15:31 PM PDT 24
Peak memory 199968 kb
Host smart-084152a6-e2cb-471c-9b4c-7534b50526c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512548273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.2512548273
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.1644033310
Short name T1123
Test name
Test status
Simulation time 21553651875 ps
CPU time 36.94 seconds
Started Jul 29 07:12:40 PM PDT 24
Finished Jul 29 07:13:17 PM PDT 24
Peak memory 199972 kb
Host smart-7468a124-f9f3-4ae8-aab5-9aa6dfe61218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644033310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.1644033310
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3260890103
Short name T1099
Test name
Test status
Simulation time 78637588152 ps
CPU time 123.1 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:14:47 PM PDT 24
Peak memory 199720 kb
Host smart-8eba8389-26ff-4ca1-a7d4-9f4d14e8d536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260890103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3260890103
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.666525091
Short name T119
Test name
Test status
Simulation time 71474987372 ps
CPU time 54.48 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:13:40 PM PDT 24
Peak memory 199916 kb
Host smart-81dfbb0f-3aca-4643-a7d7-a0b1fd752391
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666525091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.666525091
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_loopback.3477667582
Short name T671
Test name
Test status
Simulation time 1648071468 ps
CPU time 3.89 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 197448 kb
Host smart-9fcad465-ff15-4449-beee-7660dbfb08f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477667582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3477667582
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.2581978411
Short name T563
Test name
Test status
Simulation time 26824005564 ps
CPU time 40.58 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:13:30 PM PDT 24
Peak memory 200008 kb
Host smart-acfe535b-a34a-42fb-95e9-a4024f216a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581978411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.2581978411
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.547626495
Short name T1057
Test name
Test status
Simulation time 15810740550 ps
CPU time 57.37 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 199868 kb
Host smart-23ac465f-973a-4f82-94b0-d2fec299a984
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=547626495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.547626495
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3156146599
Short name T747
Test name
Test status
Simulation time 5473142283 ps
CPU time 13.86 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:13:04 PM PDT 24
Peak memory 198292 kb
Host smart-8d7d778a-4f91-4c6f-a6cf-7f3ab0c1342e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3156146599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3156146599
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1269126118
Short name T321
Test name
Test status
Simulation time 178100509014 ps
CPU time 75.96 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:14:02 PM PDT 24
Peak memory 200012 kb
Host smart-6e478c49-dcf8-4331-a94f-65a82bb660e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269126118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1269126118
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1514059890
Short name T553
Test name
Test status
Simulation time 65329459065 ps
CPU time 87.71 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:14:13 PM PDT 24
Peak memory 196112 kb
Host smart-f50ef234-0f1c-4929-aad0-160f42370451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514059890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1514059890
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1253247376
Short name T982
Test name
Test status
Simulation time 280735097 ps
CPU time 1.13 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:48 PM PDT 24
Peak memory 198132 kb
Host smart-b3205478-d251-4ddf-9dc5-ecbfd0da1408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253247376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1253247376
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.3952830187
Short name T941
Test name
Test status
Simulation time 389054661753 ps
CPU time 81.84 seconds
Started Jul 29 07:12:42 PM PDT 24
Finished Jul 29 07:14:04 PM PDT 24
Peak memory 208316 kb
Host smart-1c3b0a48-1e6a-4d12-87d1-b5c08ec8eac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952830187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.3952830187
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.831768408
Short name T157
Test name
Test status
Simulation time 29592294870 ps
CPU time 355.81 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:18:41 PM PDT 24
Peak memory 216644 kb
Host smart-480736fe-d6fe-4869-977c-b59b06fbc89d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831768408 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.831768408
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.3914773806
Short name T715
Test name
Test status
Simulation time 2118699335 ps
CPU time 2.27 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:12:48 PM PDT 24
Peak memory 198776 kb
Host smart-9be2220b-8431-41e8-99fb-29634a79b20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914773806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.3914773806
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2924840298
Short name T535
Test name
Test status
Simulation time 29604180538 ps
CPU time 50.23 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:36 PM PDT 24
Peak memory 199624 kb
Host smart-827ab790-12fb-479d-9ddd-a6b869e203f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924840298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2924840298
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.4055653524
Short name T666
Test name
Test status
Simulation time 184711118445 ps
CPU time 75.45 seconds
Started Jul 29 07:17:34 PM PDT 24
Finished Jul 29 07:18:49 PM PDT 24
Peak memory 199852 kb
Host smart-c31494cb-a5b7-46a3-88bc-9535dc6db1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055653524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.4055653524
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.774419561
Short name T478
Test name
Test status
Simulation time 91256587598 ps
CPU time 644.6 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:28:10 PM PDT 24
Peak memory 226740 kb
Host smart-cab79b9d-ae59-4a65-a7fd-67a02ae99eb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774419561 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.774419561
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.3269975927
Short name T255
Test name
Test status
Simulation time 47469100378 ps
CPU time 73.62 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:18:47 PM PDT 24
Peak memory 200044 kb
Host smart-c9485f04-8640-43f9-8d7a-d3d4082814be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269975927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.3269975927
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.210285249
Short name T668
Test name
Test status
Simulation time 132126347099 ps
CPU time 580.73 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:27:13 PM PDT 24
Peak memory 216568 kb
Host smart-8029aab5-2d85-4eac-b00e-beab136c74ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210285249 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.210285249
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1063066353
Short name T55
Test name
Test status
Simulation time 256225540901 ps
CPU time 2028.12 seconds
Started Jul 29 07:17:25 PM PDT 24
Finished Jul 29 07:51:14 PM PDT 24
Peak memory 225240 kb
Host smart-4e5c7432-3cbe-48d7-a5c6-7b5a030e07d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063066353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1063066353
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.3415732413
Short name T630
Test name
Test status
Simulation time 32640957896 ps
CPU time 24.07 seconds
Started Jul 29 07:17:23 PM PDT 24
Finished Jul 29 07:17:48 PM PDT 24
Peak memory 199824 kb
Host smart-ba58a443-9562-4388-a17e-a09453a599e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415732413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.3415732413
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.2995647358
Short name T962
Test name
Test status
Simulation time 250598645570 ps
CPU time 453.29 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:25:02 PM PDT 24
Peak memory 224832 kb
Host smart-2debf4e7-bb68-485f-88e2-de76b16afcdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995647358 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.2995647358
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.3709459490
Short name T114
Test name
Test status
Simulation time 63724790724 ps
CPU time 312.31 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:22:39 PM PDT 24
Peak memory 216468 kb
Host smart-1b8f1818-db32-4d1b-b08e-be6b8de3da7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709459490 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.3709459490
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.541516864
Short name T436
Test name
Test status
Simulation time 20202081376 ps
CPU time 33.96 seconds
Started Jul 29 07:17:33 PM PDT 24
Finished Jul 29 07:18:08 PM PDT 24
Peak memory 199908 kb
Host smart-38585a54-dbd7-4c4f-ac56-9a318782dcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541516864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.541516864
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.1761176595
Short name T11
Test name
Test status
Simulation time 101333269664 ps
CPU time 19.59 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:17:50 PM PDT 24
Peak memory 199976 kb
Host smart-f6e44578-026d-4b32-8204-a7d29cc6787d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761176595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1761176595
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3091406222
Short name T1055
Test name
Test status
Simulation time 36622148477 ps
CPU time 331.4 seconds
Started Jul 29 07:17:29 PM PDT 24
Finished Jul 29 07:23:00 PM PDT 24
Peak memory 216504 kb
Host smart-4b1af4a3-09c1-4309-a825-936880556e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091406222 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3091406222
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1409907150
Short name T572
Test name
Test status
Simulation time 17226540855 ps
CPU time 25.51 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:17:52 PM PDT 24
Peak memory 199980 kb
Host smart-c260c0e7-b455-4a98-99f6-30d6c793305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409907150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1409907150
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.2993334805
Short name T1121
Test name
Test status
Simulation time 71953097366 ps
CPU time 840.24 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:31:26 PM PDT 24
Peak memory 216568 kb
Host smart-6f5eed69-1b01-433d-8cd1-3bfd3ce3c1b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993334805 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.2993334805
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.25621234
Short name T632
Test name
Test status
Simulation time 40734090743 ps
CPU time 22.83 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:17:50 PM PDT 24
Peak memory 199904 kb
Host smart-aea13d02-95de-4d82-aa13-9664b96a88c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25621234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.25621234
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3728907777
Short name T542
Test name
Test status
Simulation time 302471973516 ps
CPU time 533.67 seconds
Started Jul 29 07:17:29 PM PDT 24
Finished Jul 29 07:26:23 PM PDT 24
Peak memory 216716 kb
Host smart-e0cf6352-75d3-4c3e-a599-1a4e6d6f3b8e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728907777 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3728907777
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.4281664713
Short name T239
Test name
Test status
Simulation time 63961802214 ps
CPU time 52.77 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:18:20 PM PDT 24
Peak memory 199860 kb
Host smart-e4ae6b55-649c-4db0-a681-52129808fb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281664713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.4281664713
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3557778916
Short name T1157
Test name
Test status
Simulation time 179463280491 ps
CPU time 465.24 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:25:13 PM PDT 24
Peak memory 224740 kb
Host smart-34b75a1c-6945-42ab-beaa-1e45ca493e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557778916 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3557778916
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.946902668
Short name T443
Test name
Test status
Simulation time 43969850 ps
CPU time 0.55 seconds
Started Jul 29 07:12:42 PM PDT 24
Finished Jul 29 07:12:43 PM PDT 24
Peak memory 195624 kb
Host smart-552928c4-a01f-449f-a870-fe8a9787de6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946902668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.946902668
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2571128796
Short name T307
Test name
Test status
Simulation time 252738611830 ps
CPU time 561.4 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:22:06 PM PDT 24
Peak memory 199920 kb
Host smart-fa740b5a-8889-4d29-8ff2-72d74b14fb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571128796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2571128796
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2794200977
Short name T602
Test name
Test status
Simulation time 78081306791 ps
CPU time 28.82 seconds
Started Jul 29 07:12:40 PM PDT 24
Finished Jul 29 07:13:09 PM PDT 24
Peak memory 199988 kb
Host smart-c8378f29-3097-49fe-b023-5c3bebfefa6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794200977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2794200977
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.2707234946
Short name T1125
Test name
Test status
Simulation time 168363090959 ps
CPU time 68.2 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:53 PM PDT 24
Peak memory 199920 kb
Host smart-e3a2371f-1343-4c08-8993-aa7b2902f67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707234946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.2707234946
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2970692772
Short name T604
Test name
Test status
Simulation time 14581408725 ps
CPU time 25.18 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:13:12 PM PDT 24
Peak memory 199864 kb
Host smart-7bfbf287-3dab-4731-9600-1e116f5e4159
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970692772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2970692772
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.1630467996
Short name T925
Test name
Test status
Simulation time 49103029567 ps
CPU time 246.09 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:16:52 PM PDT 24
Peak memory 199968 kb
Host smart-9fd98b4f-796e-40ba-b695-fc9f5b52d7bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1630467996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.1630467996
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.501637209
Short name T1006
Test name
Test status
Simulation time 3523659353 ps
CPU time 6.34 seconds
Started Jul 29 07:12:43 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 197712 kb
Host smart-966e77bd-c412-40ce-b9a3-d2f848a5ab6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501637209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.501637209
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.4280087318
Short name T297
Test name
Test status
Simulation time 3449021802 ps
CPU time 5.17 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:51 PM PDT 24
Peak memory 194564 kb
Host smart-365fbdce-531b-4858-9be0-439488096a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280087318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.4280087318
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.3190687584
Short name T393
Test name
Test status
Simulation time 15582767014 ps
CPU time 89.62 seconds
Started Jul 29 07:12:43 PM PDT 24
Finished Jul 29 07:14:13 PM PDT 24
Peak memory 199960 kb
Host smart-53cf1026-1452-452c-8165-e2785e021cd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3190687584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3190687584
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1834203476
Short name T60
Test name
Test status
Simulation time 5582404430 ps
CPU time 56.79 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:13:43 PM PDT 24
Peak memory 199536 kb
Host smart-a9b06b88-6f2b-4d1f-ba9c-460569550467
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1834203476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1834203476
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.857876197
Short name T275
Test name
Test status
Simulation time 26200307748 ps
CPU time 43.86 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:13:34 PM PDT 24
Peak memory 199928 kb
Host smart-dd10c2f6-ad40-4d51-a4b0-8a419041f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857876197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.857876197
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1174891623
Short name T318
Test name
Test status
Simulation time 6553187374 ps
CPU time 3.26 seconds
Started Jul 29 07:12:41 PM PDT 24
Finished Jul 29 07:12:44 PM PDT 24
Peak memory 196116 kb
Host smart-4f75ee05-bade-4800-8094-8ac0ebebf62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174891623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1174891623
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2091762788
Short name T726
Test name
Test status
Simulation time 146188307 ps
CPU time 0.85 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:47 PM PDT 24
Peak memory 198316 kb
Host smart-25a12486-c010-4070-abe7-1902edae685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091762788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2091762788
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.514037400
Short name T972
Test name
Test status
Simulation time 242164576422 ps
CPU time 380.89 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:19:06 PM PDT 24
Peak memory 199904 kb
Host smart-bd9d5af8-b87f-46be-ba5d-9a30dc9a6953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514037400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.514037400
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2726460966
Short name T4
Test name
Test status
Simulation time 28298497970 ps
CPU time 496.83 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:21:07 PM PDT 24
Peak memory 215900 kb
Host smart-d9c30557-5baf-459d-ae20-56e9f13cc88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726460966 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2726460966
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.2503455069
Short name T1067
Test name
Test status
Simulation time 1093512710 ps
CPU time 4.25 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:50 PM PDT 24
Peak memory 198416 kb
Host smart-17cc3c71-6c61-4711-851c-4aa20567eff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503455069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.2503455069
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1471826956
Short name T1162
Test name
Test status
Simulation time 5316823125 ps
CPU time 9.59 seconds
Started Jul 29 07:12:43 PM PDT 24
Finished Jul 29 07:12:53 PM PDT 24
Peak memory 197556 kb
Host smart-60fdab4a-c10e-4576-af5e-dd7f43a61d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471826956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1471826956
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.540555329
Short name T796
Test name
Test status
Simulation time 19725075792 ps
CPU time 13.84 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:17:42 PM PDT 24
Peak memory 198880 kb
Host smart-8b130c5c-dfb0-4deb-bb23-f08e87bc963e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540555329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.540555329
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.797406482
Short name T728
Test name
Test status
Simulation time 72795587538 ps
CPU time 427.14 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:24:34 PM PDT 24
Peak memory 214260 kb
Host smart-61aa32c9-79c6-4008-8822-44fed54d0620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797406482 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.797406482
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.3293082891
Short name T206
Test name
Test status
Simulation time 15482295636 ps
CPU time 21.89 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:17:53 PM PDT 24
Peak memory 199292 kb
Host smart-a50d9df9-7213-402f-b5f4-564d16a6afee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293082891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3293082891
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.766247564
Short name T52
Test name
Test status
Simulation time 333990513886 ps
CPU time 345.53 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:23:13 PM PDT 24
Peak memory 216436 kb
Host smart-9666f60a-30f5-47ec-a127-41d7cb169157
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766247564 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.766247564
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.763181934
Short name T222
Test name
Test status
Simulation time 12539519451 ps
CPU time 20.58 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:17:51 PM PDT 24
Peak memory 199908 kb
Host smart-618cf576-d83d-4c65-8495-033514508b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763181934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.763181934
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.2142210544
Short name T717
Test name
Test status
Simulation time 84878861589 ps
CPU time 32.29 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:17:59 PM PDT 24
Peak memory 199892 kb
Host smart-b965a425-c51c-424a-ab0b-6040ea0b4581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142210544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.2142210544
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2980811390
Short name T1108
Test name
Test status
Simulation time 78048437862 ps
CPU time 358.99 seconds
Started Jul 29 07:17:31 PM PDT 24
Finished Jul 29 07:23:30 PM PDT 24
Peak memory 216580 kb
Host smart-f1dc89e0-ffe3-4e78-9af6-0596f6a7674f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980811390 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2980811390
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2695196777
Short name T361
Test name
Test status
Simulation time 33955076482 ps
CPU time 15.51 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:17:44 PM PDT 24
Peak memory 199988 kb
Host smart-517a67c4-92ce-416c-8de8-b7ab6f52392f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695196777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2695196777
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1419728501
Short name T111
Test name
Test status
Simulation time 124896275078 ps
CPU time 286.31 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:22:14 PM PDT 24
Peak memory 212580 kb
Host smart-9ae6046c-a684-4286-a212-5e612f7557c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419728501 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1419728501
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3616912919
Short name T187
Test name
Test status
Simulation time 26421573544 ps
CPU time 42.88 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:18:10 PM PDT 24
Peak memory 199992 kb
Host smart-e66c7317-3bee-4ba8-8917-1e6e68073fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616912919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3616912919
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.398651177
Short name T329
Test name
Test status
Simulation time 68829568441 ps
CPU time 846.49 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:31:39 PM PDT 24
Peak memory 216376 kb
Host smart-4a359577-d5a9-4285-9af4-07170ed9b1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398651177 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.398651177
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.2449624313
Short name T220
Test name
Test status
Simulation time 55834453995 ps
CPU time 36.74 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:18:03 PM PDT 24
Peak memory 199884 kb
Host smart-3aa620b9-af6e-43d2-9470-e96102fbc2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449624313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.2449624313
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.1908231448
Short name T327
Test name
Test status
Simulation time 37617932801 ps
CPU time 1196.02 seconds
Started Jul 29 07:17:25 PM PDT 24
Finished Jul 29 07:37:22 PM PDT 24
Peak memory 216564 kb
Host smart-e5f6a8e3-1542-456f-ae55-7dd3c18d77d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908231448 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.1908231448
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.86362465
Short name T140
Test name
Test status
Simulation time 162154897679 ps
CPU time 19.44 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:17:49 PM PDT 24
Peak memory 199976 kb
Host smart-5aa0553a-a6ec-40cf-bb53-a2e44bf37cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86362465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.86362465
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1718558585
Short name T442
Test name
Test status
Simulation time 252984424943 ps
CPU time 725.08 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:29:32 PM PDT 24
Peak memory 216504 kb
Host smart-6abdd6fe-cc0e-463a-b765-908339da63f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718558585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1718558585
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.1190656388
Short name T1054
Test name
Test status
Simulation time 318857620513 ps
CPU time 196.41 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:20:48 PM PDT 24
Peak memory 199860 kb
Host smart-966d11dd-58f5-45e4-83e1-389b8d5db281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190656388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.1190656388
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1474203999
Short name T109
Test name
Test status
Simulation time 49919033058 ps
CPU time 144.54 seconds
Started Jul 29 07:17:58 PM PDT 24
Finished Jul 29 07:20:23 PM PDT 24
Peak memory 216468 kb
Host smart-4e0430dc-928e-4563-898f-5746991498e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474203999 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1474203999
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.217124108
Short name T342
Test name
Test status
Simulation time 15125709312 ps
CPU time 28.14 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:17:55 PM PDT 24
Peak memory 199940 kb
Host smart-7978246b-df51-4b9b-bb55-9ec94f271490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217124108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.217124108
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3899768706
Short name T697
Test name
Test status
Simulation time 27385995 ps
CPU time 0.54 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:47 PM PDT 24
Peak memory 195632 kb
Host smart-1131f255-cfe0-4fcd-b70d-95b64aa1b68f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899768706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3899768706
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3869670936
Short name T1180
Test name
Test status
Simulation time 144911022414 ps
CPU time 148.86 seconds
Started Jul 29 07:12:41 PM PDT 24
Finished Jul 29 07:15:10 PM PDT 24
Peak memory 199920 kb
Host smart-0d7e4924-98af-4c02-83c9-251e9fc50787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869670936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3869670936
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1895037340
Short name T131
Test name
Test status
Simulation time 261695122985 ps
CPU time 214.47 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:16:21 PM PDT 24
Peak memory 199908 kb
Host smart-0e3ffbcf-b783-48dc-9b39-511dbf999e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895037340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1895037340
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.3694696784
Short name T597
Test name
Test status
Simulation time 18801978106 ps
CPU time 19.63 seconds
Started Jul 29 07:12:49 PM PDT 24
Finished Jul 29 07:13:09 PM PDT 24
Peak memory 199900 kb
Host smart-f9507eec-e6ea-486a-a0b2-a3bed93b86d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694696784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3694696784
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3965896435
Short name T1142
Test name
Test status
Simulation time 24116360086 ps
CPU time 36.15 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:21 PM PDT 24
Peak memory 199128 kb
Host smart-c67fd694-51fe-43af-b1a2-b4da090cc106
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965896435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3965896435
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2007632767
Short name T968
Test name
Test status
Simulation time 149190294802 ps
CPU time 1049.46 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:30:16 PM PDT 24
Peak memory 200092 kb
Host smart-998e3715-98eb-4875-8a35-cd6429b991d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2007632767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2007632767
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.989760905
Short name T330
Test name
Test status
Simulation time 3041056858 ps
CPU time 2.77 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:12:47 PM PDT 24
Peak memory 199364 kb
Host smart-26689b34-c1df-46db-a4f7-dbde5fba4cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989760905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.989760905
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.2748576582
Short name T1078
Test name
Test status
Simulation time 123254779408 ps
CPU time 190.2 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:15:55 PM PDT 24
Peak memory 200024 kb
Host smart-17cba8f1-3e70-41d4-97e5-49c950b68563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748576582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.2748576582
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1359427271
Short name T900
Test name
Test status
Simulation time 6619583057 ps
CPU time 389.56 seconds
Started Jul 29 07:12:47 PM PDT 24
Finished Jul 29 07:19:17 PM PDT 24
Peak memory 199836 kb
Host smart-3d3ba409-aff7-4618-a540-93e07a6a32f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359427271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1359427271
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.113030970
Short name T378
Test name
Test status
Simulation time 1423536458 ps
CPU time 0.84 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:47 PM PDT 24
Peak memory 195608 kb
Host smart-3fd4f450-ab2a-4404-bf3b-dee63b2cf706
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113030970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.113030970
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.2608939771
Short name T531
Test name
Test status
Simulation time 15368380068 ps
CPU time 17.55 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:13:02 PM PDT 24
Peak memory 199896 kb
Host smart-910d2b09-c164-4f07-ba94-04c6c46db8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608939771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2608939771
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1590695243
Short name T379
Test name
Test status
Simulation time 1842747882 ps
CPU time 2.13 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:12:49 PM PDT 24
Peak memory 195620 kb
Host smart-7e4c9896-a1f7-4f75-ab94-a8d768e47f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590695243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1590695243
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.148651856
Short name T538
Test name
Test status
Simulation time 273649419 ps
CPU time 1.09 seconds
Started Jul 29 07:12:43 PM PDT 24
Finished Jul 29 07:12:44 PM PDT 24
Peak memory 198584 kb
Host smart-cf5eaf6a-7446-4f88-ba82-057fb3b1390a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148651856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.148651856
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4268312131
Short name T1153
Test name
Test status
Simulation time 345486494559 ps
CPU time 108.71 seconds
Started Jul 29 07:12:44 PM PDT 24
Finished Jul 29 07:14:33 PM PDT 24
Peak memory 199972 kb
Host smart-fc6283b3-44a3-43d9-ade6-30d754718835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268312131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4268312131
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.3500368937
Short name T1088
Test name
Test status
Simulation time 116232485116 ps
CPU time 1411.68 seconds
Started Jul 29 07:12:46 PM PDT 24
Finished Jul 29 07:36:18 PM PDT 24
Peak memory 224632 kb
Host smart-248e8f74-30e0-40a4-8594-2d4dcd2f3860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500368937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.3500368937
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2970083836
Short name T372
Test name
Test status
Simulation time 4081040727 ps
CPU time 2.61 seconds
Started Jul 29 07:12:50 PM PDT 24
Finished Jul 29 07:12:52 PM PDT 24
Peak memory 198900 kb
Host smart-952a95f0-b822-40fb-9ba9-6404b65834e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970083836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2970083836
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3067467407
Short name T390
Test name
Test status
Simulation time 11054816916 ps
CPU time 15.38 seconds
Started Jul 29 07:12:45 PM PDT 24
Finished Jul 29 07:13:01 PM PDT 24
Peak memory 199132 kb
Host smart-682e66af-ca26-436a-af70-b24e703f6d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067467407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3067467407
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1040860980
Short name T568
Test name
Test status
Simulation time 95143418735 ps
CPU time 137.6 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:19:47 PM PDT 24
Peak memory 200028 kb
Host smart-cea4f4ab-01dc-4d89-b31d-6b0daff4a0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040860980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1040860980
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2128100698
Short name T161
Test name
Test status
Simulation time 746780155104 ps
CPU time 807.91 seconds
Started Jul 29 07:17:29 PM PDT 24
Finished Jul 29 07:30:57 PM PDT 24
Peak memory 224936 kb
Host smart-7287c53d-2aec-490c-97e6-37eb76289b4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128100698 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2128100698
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.2729256235
Short name T106
Test name
Test status
Simulation time 20624238798 ps
CPU time 28.6 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:17:57 PM PDT 24
Peak memory 199012 kb
Host smart-6f26cceb-974f-47ea-a3bd-2b3d3a8979cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729256235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.2729256235
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.3440408022
Short name T112
Test name
Test status
Simulation time 76407488692 ps
CPU time 152.61 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:20:00 PM PDT 24
Peak memory 213548 kb
Host smart-7f0b0b41-181b-4c4f-be5c-e7044e23e86f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440408022 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.3440408022
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2261967261
Short name T1005
Test name
Test status
Simulation time 66163023118 ps
CPU time 96.09 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:19:08 PM PDT 24
Peak memory 199860 kb
Host smart-70689a32-aa83-4f58-bf27-6fb5bbf6c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261967261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2261967261
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.244696688
Short name T677
Test name
Test status
Simulation time 25560264857 ps
CPU time 538.13 seconds
Started Jul 29 07:17:34 PM PDT 24
Finished Jul 29 07:26:32 PM PDT 24
Peak memory 216672 kb
Host smart-3e9477fc-e63e-4e49-98c1-44af4b506a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244696688 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.244696688
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2537755223
Short name T799
Test name
Test status
Simulation time 71984483178 ps
CPU time 35.92 seconds
Started Jul 29 07:17:29 PM PDT 24
Finished Jul 29 07:18:05 PM PDT 24
Peak memory 199928 kb
Host smart-9116a429-1578-4be2-8ccb-0da71e94329d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537755223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2537755223
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3138238839
Short name T58
Test name
Test status
Simulation time 190288717806 ps
CPU time 775.09 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:30:22 PM PDT 24
Peak memory 216588 kb
Host smart-673353c8-5198-49c5-bb11-ff12d28aa3ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138238839 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3138238839
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2019577550
Short name T203
Test name
Test status
Simulation time 190629636897 ps
CPU time 409.53 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:24:20 PM PDT 24
Peak memory 199944 kb
Host smart-91f7ebc3-0b1c-4566-aa6d-0131660a0778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019577550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2019577550
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2772539196
Short name T1051
Test name
Test status
Simulation time 43590718308 ps
CPU time 71.5 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:18:44 PM PDT 24
Peak memory 199860 kb
Host smart-64afc4e9-37d5-4e7d-8615-4c9e505d5d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772539196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2772539196
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.638342699
Short name T56
Test name
Test status
Simulation time 707866564443 ps
CPU time 1042.18 seconds
Started Jul 29 07:17:36 PM PDT 24
Finished Jul 29 07:34:58 PM PDT 24
Peak memory 231932 kb
Host smart-8c631037-b675-46d4-a0a5-24f7aea1e40d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638342699 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.638342699
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.400713518
Short name T53
Test name
Test status
Simulation time 263523320271 ps
CPU time 737.31 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:29:44 PM PDT 24
Peak memory 216640 kb
Host smart-718788b3-4029-4ed8-93ee-7b9139232845
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400713518 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.400713518
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1497189780
Short name T229
Test name
Test status
Simulation time 48781285412 ps
CPU time 8.27 seconds
Started Jul 29 07:17:32 PM PDT 24
Finished Jul 29 07:17:40 PM PDT 24
Peak memory 199984 kb
Host smart-660840e9-3313-4a64-a873-dcb8819c7128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497189780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1497189780
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3194235579
Short name T30
Test name
Test status
Simulation time 52719761465 ps
CPU time 955.7 seconds
Started Jul 29 07:17:30 PM PDT 24
Finished Jul 29 07:33:26 PM PDT 24
Peak memory 216420 kb
Host smart-dcd9da3e-7782-419a-8ad6-b3bc13a65c05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194235579 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3194235579
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4174114643
Short name T180
Test name
Test status
Simulation time 80449399201 ps
CPU time 31.7 seconds
Started Jul 29 07:17:26 PM PDT 24
Finished Jul 29 07:17:58 PM PDT 24
Peak memory 199956 kb
Host smart-68c4e851-3f95-40e7-b8ba-2469cc6bb4b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174114643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4174114643
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1853189885
Short name T609
Test name
Test status
Simulation time 476104733481 ps
CPU time 995.67 seconds
Started Jul 29 07:17:28 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 224720 kb
Host smart-34d2f2da-b211-44d5-8e21-6d7e5cdc0369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853189885 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1853189885
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.2869122680
Short name T921
Test name
Test status
Simulation time 125158214982 ps
CPU time 52.64 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:18:20 PM PDT 24
Peak memory 200032 kb
Host smart-3437e3a0-3d50-4977-bf52-83acfe0c6beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869122680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.2869122680
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2383920052
Short name T1034
Test name
Test status
Simulation time 47962187523 ps
CPU time 1025.55 seconds
Started Jul 29 07:17:27 PM PDT 24
Finished Jul 29 07:34:33 PM PDT 24
Peak memory 216388 kb
Host smart-80eb5ea9-98a9-4c74-add7-49679ca22e4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383920052 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2383920052
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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