Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108344	1			T1	1		T2	26		T3	25
all_values[1]	108344	1			T1	1		T2	26		T3	25
all_values[2]	108344	1			T1	1		T2	26		T3	25
all_values[3]	108344	1			T1	1		T2	26		T3	25
all_values[4]	108344	1			T1	1		T2	26		T3	25
all_values[5]	108344	1			T1	1		T2	26		T3	25
all_values[6]	108344	1			T1	1		T2	26		T3	25
all_values[7]	108344	1			T1	1		T2	26		T3	25
all_values[8]	108344	1			T1	1		T2	26		T3	25

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

482929

1

T1

3

T2

108

T3

77

auto[1]

492167

1

T1

6

T2

126

T3

148

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

885169

1

T1

7

T2

193

T3

176

auto[1]

89927

1

T1

2

T2

41

T3

49

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29218	1			T3	3		T4	15		T6	47
all_values[0]	auto[0]	auto[1]	21829	1			T2	12		T3	7		T4	1
all_values[0]	auto[1]	auto[0]	33869	1			T2	6		T4	87		T9	9
all_values[0]	auto[1]	auto[1]	23428	1			T1	1		T2	8		T3	15
all_values[1]	auto[0]	auto[0]	50608	1			T2	10		T3	7		T4	88
all_values[1]	auto[0]	auto[1]	1625	1			T11	3		T41	13		T25	6
all_values[1]	auto[1]	auto[0]	54564	1			T1	1		T2	12		T3	16
all_values[1]	auto[1]	auto[1]	1547	1			T2	4		T3	2		T9	4
all_values[2]	auto[0]	auto[0]	53794	1			T1	1		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	2681	1			T2	2		T3	1		T4	1
all_values[2]	auto[1]	auto[0]	49478	1			T2	20		T3	16		T4	80
all_values[2]	auto[1]	auto[1]	2391	1			T2	2		T3	7		T4	1
all_values[3]	auto[0]	auto[0]	51975	1			T1	1		T2	14		T3	15
all_values[3]	auto[0]	auto[1]	291	1			T13	2		T14	2		T33	3
all_values[3]	auto[1]	auto[0]	55804	1			T2	11		T3	10		T4	14
all_values[3]	auto[1]	auto[1]	274	1			T2	1		T7	2		T11	5
all_values[4]	auto[0]	auto[0]	52507	1			T2	22		T3	8		T4	73
all_values[4]	auto[0]	auto[1]	354	1			T13	1		T16	2		T34	5
all_values[4]	auto[1]	auto[0]	55062	1			T1	1		T2	4		T3	17
all_values[4]	auto[1]	auto[1]	421	1			T11	3		T33	3		T34	4
all_values[5]	auto[0]	auto[0]	53496	1			T2	10		T3	14		T4	72
all_values[5]	auto[0]	auto[1]	166	1			T11	3		T13	4		T16	1
all_values[5]	auto[1]	auto[0]	54543	1			T1	1		T2	16		T3	11
all_values[5]	auto[1]	auto[1]	139	1			T16	3		T34	4		T66	1
all_values[6]	auto[0]	auto[0]	55327	1			T1	1		T2	18		T3	7
all_values[6]	auto[0]	auto[1]	164	1			T11	1		T16	1		T34	4
all_values[6]	auto[1]	auto[0]	52665	1			T2	8		T3	18		T4	14
all_values[6]	auto[1]	auto[1]	188	1			T13	1		T33	3		T34	5
all_values[7]	auto[0]	auto[0]	54957	1			T2	10		T3	11		T4	93
all_values[7]	auto[0]	auto[1]	334	1			T9	1		T25	1		T13	1
all_values[7]	auto[1]	auto[0]	52713	1			T1	1		T2	16		T3	14
all_values[7]	auto[1]	auto[1]	340	1			T25	1		T13	2		T16	3
all_values[8]	auto[0]	auto[0]	36784	1			T2	6		T3	3		T4	22
all_values[8]	auto[0]	auto[1]	16819	1			T2	2		T4	1		T5	2
all_values[8]	auto[1]	auto[0]	37805	1			T2	8		T3	5		T4	80
all_values[8]	auto[1]	auto[1]	16936	1			T1	1		T2	10		T3	17