Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg
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Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv



Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 34 0 34 100.00


Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_baud_rate 7 0 7 100.00 100 1 1 0
cp_clk_freq 5 0 5 100.00 100 1 1 0


Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
baud_rate_w_core_clk_cg_cc 34 0 34 100.00 100 1 1 0


Summary for Variable cp_baud_rate

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_baud_rate

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[BaudRate9600] 2217 1 T1 2 T2 1 T6 1
auto[BaudRate115200] 2059 1 T2 2 T3 2 T7 1
auto[BaudRate230400] 2006 1 T2 1 T5 1 T7 3
auto[BaudRate128Kbps] 2014 1 T5 1 T6 1 T7 3
auto[BaudRate256Kbps] 2319 1 T2 1 T3 1 T4 2
auto[BaudRate1Mbps] 1925 1 T3 1 T4 3 T6 1
auto[BaudRate1p5Mbps] 1318 1 T2 4 T3 1 T4 2



Summary for Variable cp_clk_freq

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for cp_clk_freq

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
freqs[24] 1407 1 T10 5 T43 5 T44 7
freqs[25] 1320 1 T40 5 T16 47 T19 2
freqs[48] 806 1 T42 2 T103 2 T315 27
freqs[50] 589 1 T9 9 T316 12 T317 45
freqs[100] 1189 1 T121 10 T31 12 T256 18



Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 34 0 34 100.00
Automatically Generated Cross Bins 34 0 34 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins
cp_baud_ratecp_clk_freqCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[BaudRate9600] freqs[24] 235 1 T13 6 T23 13 T291 2
auto[BaudRate9600] freqs[25] 174 1 T16 9 T107 1 T257 1
auto[BaudRate9600] freqs[48] 113 1 T315 6 T67 3 T273 1
auto[BaudRate9600] freqs[50] 62 1 T316 3 T317 3 T136 2
auto[BaudRate9600] freqs[100] 214 1 T121 2 T31 3 T256 3
auto[BaudRate115200] freqs[24] 207 1 T43 1 T44 3 T13 11
auto[BaudRate115200] freqs[25] 210 1 T40 2 T16 10 T19 1
auto[BaudRate115200] freqs[48] 119 1 T67 6 T318 1 T305 1
auto[BaudRate115200] freqs[50] 90 1 T9 1 T317 6 T319 1
auto[BaudRate115200] freqs[100] 138 1 T121 3 T256 3 T32 1
auto[BaudRate230400] freqs[24] 191 1 T43 2 T44 1 T13 15
auto[BaudRate230400] freqs[25] 166 1 T40 1 T16 5 T107 2
auto[BaudRate230400] freqs[48] 100 1 T103 1 T315 3 T67 3
auto[BaudRate230400] freqs[50] 97 1 T9 2 T316 3 T317 18
auto[BaudRate230400] freqs[100] 177 1 T256 1 T109 2 T32 2
auto[BaudRate128Kbps] freqs[24] 204 1 T43 1 T13 11 T96 4
auto[BaudRate128Kbps] freqs[25] 204 1 T40 1 T16 4 T107 1
auto[BaudRate128Kbps] freqs[48] 136 1 T315 9 T67 6 T310 1
auto[BaudRate128Kbps] freqs[50] 86 1 T9 3 T317 3 T136 1
auto[BaudRate128Kbps] freqs[100] 137 1 T121 2 T256 2 T320 3
auto[BaudRate256Kbps] freqs[24] 247 1 T44 1 T13 11 T102 2
auto[BaudRate256Kbps] freqs[25] 209 1 T16 5 T257 3 T35 5
auto[BaudRate256Kbps] freqs[48] 107 1 T315 6 T67 2 T273 1
auto[BaudRate256Kbps] freqs[50] 92 1 T317 6 T136 2 T275 1
auto[BaudRate256Kbps] freqs[100] 178 1 T31 4 T256 4 T109 2
auto[BaudRate1Mbps] freqs[24] 227 1 T10 4 T44 2 T13 25
auto[BaudRate1Mbps] freqs[25] 237 1 T16 10 T107 2 T257 3
auto[BaudRate1Mbps] freqs[48] 126 1 T42 1 T67 4 T318 2
auto[BaudRate1Mbps] freqs[50] 62 1 T316 3 T317 3 T136 3
auto[BaudRate1Mbps] freqs[100] 182 1 T121 3 T31 2 T109 2
auto[BaudRate1p5Mbps] freqs[25] 120 1 T40 1 T16 4 T19 1
auto[BaudRate1p5Mbps] freqs[48] 105 1 T42 1 T103 1 T315 3
auto[BaudRate1p5Mbps] freqs[50] 100 1 T9 3 T316 3 T317 6
auto[BaudRate1p5Mbps] freqs[100] 163 1 T31 3 T256 5 T32 2


User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
unsupported 0 Excluded

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