Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	9	121	93.08

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	9	121	93.08	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31279347	1			T1	1		T2	28		T3	199
all_levels[1]	191269	1			T2	2		T3	35		T4	3635
all_levels[2]	2409	1			T2	1		T3	4		T10	5
all_levels[3]	928	1			T2	1		T11	3		T38	7
all_levels[4]	690	1			T11	2		T38	2		T41	2
all_levels[5]	524	1			T7	1		T11	2		T41	1
all_levels[6]	380	1			T11	2		T38	2		T41	1
all_levels[7]	331	1			T38	1		T46	1		T48	1
all_levels[8]	244	1			T2	2		T9	1		T38	3
all_levels[9]	242	1			T6	1		T11	1		T38	1
all_levels[10]	213	1			T11	4		T13	1		T121	2
all_levels[11]	186	1			T2	2		T43	1		T13	1
all_levels[12]	164	1			T41	1		T13	1		T121	1
all_levels[13]	120	1			T7	1		T9	1		T43	1
all_levels[14]	144	1			T121	1		T31	1		T16	1
all_levels[15]	97	1			T48	1		T121	1		T109	1
all_levels[16]	95	1			T9	1		T44	1		T31	1
all_levels[17]	120	1			T41	1		T121	1		T31	1
all_levels[18]	110	1			T9	1		T44	1		T13	1
all_levels[19]	74	1			T2	1		T9	1		T121	1
all_levels[20]	94	1			T11	2		T109	1		T122	2
all_levels[21]	56	1			T7	2		T43	4		T110	1
all_levels[22]	81	1			T41	1		T32	1		T69	1
all_levels[23]	78	1			T25	1		T109	1		T110	1
all_levels[24]	54	1			T123	3		T31	1		T109	2
all_levels[25]	52	1			T7	1		T11	1		T109	1
all_levels[26]	64	1			T25	1		T13	1		T18	1
all_levels[27]	50	1			T111	1		T124	2		T125	1
all_levels[28]	56	1			T126	1		T35	1		T98	1
all_levels[29]	38	1			T13	1		T110	1		T127	1
all_levels[30]	47	1			T25	1		T70	1		T98	1
all_levels[31]	35	1			T31	1		T109	1		T110	1
all_levels[32]	29	1			T128	2		T129	1		T112	1
all_levels[33]	35	1			T44	1		T16	2		T130	1
all_levels[34]	27	1			T6	1		T70	1		T131	1
all_levels[35]	31	1			T113	1		T132	1		T133	2
all_levels[36]	24	1			T134	1		T135	1		T66	1
all_levels[37]	28	1			T134	1		T127	1		T136	2
all_levels[38]	23	1			T9	1		T25	1		T31	1
all_levels[39]	26	1			T7	1		T113	1		T137	1
all_levels[40]	21	1			T31	1		T135	1		T125	1
all_levels[41]	13	1			T138	1		T139	1		T140	1
all_levels[42]	12	1			T33	1		T125	1		T141	1
all_levels[43]	11	1			T109	1		T142	1		T133	2
all_levels[44]	30	1			T131	1		T143	2		T144	1
all_levels[45]	22	1			T135	1		T145	1		T66	1
all_levels[46]	14	1			T33	1		T98	1		T146	1
all_levels[47]	27	1			T7	1		T33	1		T113	1
all_levels[48]	14	1			T135	1		T33	1		T125	1
all_levels[49]	18	1			T145	1		T98	1		T113	3
all_levels[50]	8	1			T33	1		T110	1		T66	1
all_levels[51]	11	1			T147	2		T148	1		T149	1
all_levels[52]	11	1			T150	1		T151	1		T152	1
all_levels[53]	6	1			T137	1		T115	1		T153	1
all_levels[54]	14	1			T154	1		T155	4		T156	1
all_levels[55]	12	1			T52	1		T157	2		T158	1
all_levels[56]	9	1			T45	1		T159	1		T49	1
all_levels[57]	1	1			T160	1		-	-		-	-
all_levels[58]	15	1			T99	1		T140	1		T161	2
all_levels[59]	8	1			T162	1		T163	1		T164	1
all_levels[60]	9	1			T25	1		T153	1		T165	1
all_levels[61]	6	1			T166	1		T167	1		T168	1
all_levels[62]	9	1			T2	1		T134	1		T13	1
all_levels[63]	3	1			T169	1		T170	1		T171	1
all_levels[64]	97	1			T7	1		T13	1		T35	5

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474416

1

T2

30

T3

238

T4

161228

auto[1]

4600

1

T1

1

T2

8

T6

3

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	9	121	93.08	9

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[42] , all_levels[43]]	[auto[1]]	--	--	2
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[53]]	[auto[1]]	0	1	1
[all_levels[56] , all_levels[57]]	[auto[1]]	--	--	2
[all_levels[62] , all_levels[63]]	[auto[1]]	--	--	2

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31275254	1			T2	23		T3	199		T4	157593
all_levels[0]	auto[1]	4093	1			T1	1		T2	5		T8	2
all_levels[1]	auto[0]	191200	1			T2	1		T3	35		T4	3635
all_levels[1]	auto[1]	69	1			T2	1		T6	3		T172	2
all_levels[2]	auto[0]	2377	1			T2	1		T3	4		T10	5
all_levels[2]	auto[1]	32	1			T63	1		T173	1		T174	1
all_levels[3]	auto[0]	908	1			T2	1		T11	3		T38	7
all_levels[3]	auto[1]	20	1			T41	1		T131	2		T144	1
all_levels[4]	auto[0]	669	1			T11	2		T38	2		T41	2
all_levels[4]	auto[1]	21	1			T121	1		T31	1		T142	1
all_levels[5]	auto[0]	501	1			T7	1		T11	2		T41	1
all_levels[5]	auto[1]	23	1			T25	1		T33	3		T175	1
all_levels[6]	auto[0]	361	1			T11	1		T38	2		T41	1
all_levels[6]	auto[1]	19	1			T11	1		T147	2		T176	2
all_levels[7]	auto[0]	308	1			T38	1		T46	1		T48	1
all_levels[7]	auto[1]	23	1			T121	3		T177	1		T178	3
all_levels[8]	auto[0]	226	1			T2	1		T9	1		T38	3
all_levels[8]	auto[1]	18	1			T2	1		T147	1		T69	2
all_levels[9]	auto[0]	232	1			T6	1		T11	1		T38	1
all_levels[9]	auto[1]	10	1			T147	1		T152	1		T179	1
all_levels[10]	auto[0]	193	1			T11	3		T13	1		T121	2
all_levels[10]	auto[1]	20	1			T11	1		T180	3		T181	1
all_levels[11]	auto[0]	180	1			T2	1		T43	1		T13	1
all_levels[11]	auto[1]	6	1			T2	1		T182	1		T183	1
all_levels[12]	auto[0]	144	1			T41	1		T13	1		T121	1
all_levels[12]	auto[1]	20	1			T184	1		T185	4		T174	1
all_levels[13]	auto[0]	115	1			T7	1		T9	1		T43	1
all_levels[13]	auto[1]	5	1			T186	1		T187	1		T188	1
all_levels[14]	auto[0]	119	1			T121	1		T31	1		T16	1
all_levels[14]	auto[1]	25	1			T189	2		T190	4		T191	1
all_levels[15]	auto[0]	94	1			T48	1		T121	1		T109	1
all_levels[15]	auto[1]	3	1			T192	2		T193	1		-	-
all_levels[16]	auto[0]	82	1			T9	1		T44	1		T31	1
all_levels[16]	auto[1]	13	1			T176	1		T140	1		T194	4
all_levels[17]	auto[0]	102	1			T41	1		T121	1		T31	1
all_levels[17]	auto[1]	18	1			T137	1		T195	5		T125	1
all_levels[18]	auto[0]	95	1			T9	1		T44	1		T13	1
all_levels[18]	auto[1]	15	1			T69	2		T173	1		T196	2
all_levels[19]	auto[0]	69	1			T2	1		T9	1		T121	1
all_levels[19]	auto[1]	5	1			T197	1		T198	2		T199	1
all_levels[20]	auto[0]	84	1			T11	2		T109	1		T122	2
all_levels[20]	auto[1]	10	1			T173	2		T200	1		T201	2
all_levels[21]	auto[0]	48	1			T7	2		T43	2		T110	1
all_levels[21]	auto[1]	8	1			T43	2		T136	1		T202	1
all_levels[22]	auto[0]	75	1			T41	1		T32	1		T69	1
all_levels[22]	auto[1]	6	1			T180	1		T152	1		T203	1
all_levels[23]	auto[0]	72	1			T25	1		T109	1		T110	1
all_levels[23]	auto[1]	6	1			T112	4		T204	1		T205	1
all_levels[24]	auto[0]	48	1			T123	1		T31	1		T109	1
all_levels[24]	auto[1]	6	1			T123	2		T109	1		T206	2
all_levels[25]	auto[0]	47	1			T7	1		T11	1		T109	1
all_levels[25]	auto[1]	5	1			T207	1		T189	3		T208	1
all_levels[26]	auto[0]	56	1			T25	1		T13	1		T18	1
all_levels[26]	auto[1]	8	1			T143	1		T209	1		T210	1
all_levels[27]	auto[0]	46	1			T111	1		T124	1		T125	1
all_levels[27]	auto[1]	4	1			T124	1		T211	1		T212	2
all_levels[28]	auto[0]	52	1			T126	1		T35	1		T98	1
all_levels[28]	auto[1]	4	1			T213	2		T211	1		T214	1
all_levels[29]	auto[0]	35	1			T13	1		T110	1		T127	1
all_levels[29]	auto[1]	3	1			T215	1		T216	2		-	-
all_levels[30]	auto[0]	42	1			T25	1		T70	1		T98	1
all_levels[30]	auto[1]	5	1			T159	1		T167	1		T217	1
all_levels[31]	auto[0]	31	1			T31	1		T109	1		T110	1
all_levels[31]	auto[1]	4	1			T138	3		T218	1		-	-
all_levels[32]	auto[0]	27	1			T128	1		T129	1		T112	1
all_levels[32]	auto[1]	2	1			T128	1		T219	1		-	-
all_levels[33]	auto[0]	32	1			T44	1		T16	2		T130	1
all_levels[33]	auto[1]	3	1			T220	1		T221	1		T222	1
all_levels[34]	auto[0]	26	1			T6	1		T70	1		T131	1
all_levels[34]	auto[1]	1	1			T223	1		-	-		-	-
all_levels[35]	auto[0]	28	1			T113	1		T132	1		T133	1
all_levels[35]	auto[1]	3	1			T133	1		T224	1		T225	1
all_levels[36]	auto[0]	23	1			T134	1		T135	1		T66	1
all_levels[36]	auto[1]	1	1			T226	1		-	-		-	-
all_levels[37]	auto[0]	27	1			T134	1		T127	1		T136	2
all_levels[37]	auto[1]	1	1			T227	1		-	-		-	-
all_levels[38]	auto[0]	20	1			T9	1		T25	1		T31	1
all_levels[38]	auto[1]	3	1			T228	1		T229	2		-	-
all_levels[39]	auto[0]	23	1			T7	1		T113	1		T137	1
all_levels[39]	auto[1]	3	1			T230	1		T231	1		T232	1
all_levels[40]	auto[0]	21	1			T31	1		T135	1		T125	1
all_levels[41]	auto[0]	12	1			T138	1		T139	1		T140	1
all_levels[41]	auto[1]	1	1			T233	1		-	-		-	-
all_levels[42]	auto[0]	12	1			T33	1		T125	1		T141	1
all_levels[43]	auto[0]	11	1			T109	1		T142	1		T133	2
all_levels[44]	auto[0]	21	1			T131	1		T143	1		T144	1
all_levels[44]	auto[1]	9	1			T143	1		T234	2		T210	3
all_levels[45]	auto[0]	19	1			T135	1		T145	1		T66	1
all_levels[45]	auto[1]	3	1			T150	2		T235	1		-	-
all_levels[46]	auto[0]	13	1			T33	1		T98	1		T146	1
all_levels[46]	auto[1]	1	1			T236	1		-	-		-	-
all_levels[47]	auto[0]	22	1			T7	1		T33	1		T113	1
all_levels[47]	auto[1]	5	1			T195	2		T237	2		T238	1
all_levels[48]	auto[0]	12	1			T135	1		T33	1		T125	1
all_levels[48]	auto[1]	2	1			T239	1		T240	1		-	-
all_levels[49]	auto[0]	15	1			T145	1		T98	1		T113	1
all_levels[49]	auto[1]	3	1			T113	2		T241	1		-	-
all_levels[50]	auto[0]	8	1			T33	1		T110	1		T66	1
all_levels[51]	auto[0]	8	1			T147	1		T148	1		T149	1
all_levels[51]	auto[1]	3	1			T147	1		T242	1		T243	1
all_levels[52]	auto[0]	9	1			T150	1		T151	1		T152	1
all_levels[52]	auto[1]	2	1			T244	2		-	-		-	-
all_levels[53]	auto[0]	6	1			T137	1		T115	1		T153	1
all_levels[54]	auto[0]	11	1			T154	1		T155	1		T156	1
all_levels[54]	auto[1]	3	1			T155	3		-	-		-	-
all_levels[55]	auto[0]	11	1			T52	1		T157	2		T158	1
all_levels[55]	auto[1]	1	1			T245	1		-	-		-	-
all_levels[56]	auto[0]	9	1			T45	1		T159	1		T49	1
all_levels[57]	auto[0]	1	1			T160	1		-	-		-	-
all_levels[58]	auto[0]	11	1			T99	1		T140	1		T161	1
all_levels[58]	auto[1]	4	1			T161	1		T211	1		T246	2
all_levels[59]	auto[0]	7	1			T162	1		T163	1		T164	1
all_levels[59]	auto[1]	1	1			T247	1		-	-		-	-
all_levels[60]	auto[0]	5	1			T25	1		T153	1		T165	1
all_levels[60]	auto[1]	4	1			T248	2		T249	2		-	-
all_levels[61]	auto[0]	5	1			T166	1		T167	1		T168	1
all_levels[61]	auto[1]	1	1			T250	1		-	-		-	-
all_levels[62]	auto[0]	9	1			T2	1		T134	1		T13	1
all_levels[63]	auto[0]	3	1			T169	1		T170	1		T171	1
all_levels[64]	auto[0]	84	1			T7	1		T13	1		T35	1
all_levels[64]	auto[1]	13	1			T35	4		T70	1		T251	2