Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108344	1			T1	1		T2	26		T3	25
all_pins[1]	108344	1			T1	1		T2	26		T3	25
all_pins[2]	108344	1			T1	1		T2	26		T3	25
all_pins[3]	108344	1			T1	1		T2	26		T3	25
all_pins[4]	108344	1			T1	1		T2	26		T3	25
all_pins[5]	108344	1			T1	1		T2	26		T3	25
all_pins[6]	108344	1			T1	1		T2	26		T3	25
all_pins[7]	108344	1			T1	1		T2	26		T3	25
all_pins[8]	108344	1			T1	1		T2	26		T3	25

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	928545	1			T1	7		T2	209		T3	184
values[0x1]	46551	1			T1	2		T2	25		T3	41
transitions[0x0=>0x1]	35462	1			T1	1		T2	19		T3	25
transitions[0x1=>0x0]	35235	1			T1	1		T2	20		T3	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84839	1			T2	18		T3	10		T4	103
all_pins[0]	values[0x1]	23505	1			T1	1		T2	8		T3	15
all_pins[0]	transitions[0x0=>0x1]	22909	1			T1	1		T2	4		T3	13
all_pins[0]	transitions[0x1=>0x0]	946	1			T9	4		T11	1		T44	3
all_pins[1]	values[0x0]	106802	1			T1	1		T2	22		T3	23
all_pins[1]	values[0x1]	1542	1			T2	4		T3	2		T9	4
all_pins[1]	transitions[0x0=>0x1]	1399	1			T2	4		T3	2		T11	1
all_pins[1]	transitions[0x1=>0x0]	2298	1			T2	2		T3	7		T4	1
all_pins[2]	values[0x0]	105903	1			T1	1		T2	24		T3	18
all_pins[2]	values[0x1]	2441	1			T2	2		T3	7		T4	1
all_pins[2]	transitions[0x0=>0x1]	2381	1			T2	2		T3	7		T4	1
all_pins[2]	transitions[0x1=>0x0]	214	1			T2	1		T11	5		T13	1
all_pins[3]	values[0x0]	108070	1			T1	1		T2	25		T3	25
all_pins[3]	values[0x1]	274	1			T2	1		T7	2		T11	5
all_pins[3]	transitions[0x0=>0x1]	243	1			T2	1		T7	2		T11	4
all_pins[3]	transitions[0x1=>0x0]	390	1			T11	2		T33	3		T34	4
all_pins[4]	values[0x0]	107923	1			T1	1		T2	26		T3	25
all_pins[4]	values[0x1]	421	1			T11	3		T33	3		T34	4
all_pins[4]	transitions[0x0=>0x1]	357	1			T11	3		T33	3		T34	3
all_pins[4]	transitions[0x1=>0x0]	108	1			T16	3		T34	3		T66	1
all_pins[5]	values[0x0]	108172	1			T1	1		T2	26		T3	25
all_pins[5]	values[0x1]	172	1			T16	3		T34	4		T66	1
all_pins[5]	transitions[0x0=>0x1]	144	1			T16	3		T34	1		T66	1
all_pins[5]	transitions[0x1=>0x0]	828	1			T6	1		T7	2		T39	1
all_pins[6]	values[0x0]	107488	1			T1	1		T2	26		T3	25
all_pins[6]	values[0x1]	856	1			T6	1		T7	2		T39	1
all_pins[6]	transitions[0x0=>0x1]	798	1			T6	1		T7	2		T39	1
all_pins[6]	transitions[0x1=>0x0]	282	1			T25	1		T13	2		T16	3
all_pins[7]	values[0x0]	108004	1			T1	1		T2	26		T3	25
all_pins[7]	values[0x1]	340	1			T25	1		T13	2		T16	3
all_pins[7]	transitions[0x0=>0x1]	197	1			T25	1		T13	2		T34	3
all_pins[7]	transitions[0x1=>0x0]	16857	1			T1	1		T2	10		T3	17
all_pins[8]	values[0x0]	91344	1			T2	16		T3	8		T4	103
all_pins[8]	values[0x1]	17000	1			T1	1		T2	10		T3	17
all_pins[8]	transitions[0x0=>0x1]	7034	1			T2	8		T3	3		T6	1
all_pins[8]	transitions[0x1=>0x0]	13312	1			T2	7		T3	1		T7	3