Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7886211	1			T2	6		T3	133		T4	1725
all_levels[1]	1873517	1			T3	4		T4	45		T7	1
all_levels[2]	581232	1			T2	3		T3	5		T4	55
all_levels[3]	298352	1			T4	46		T9	2		T10	8
all_levels[4]	366291	1			T2	2		T3	4		T4	50
all_levels[5]	264479	1			T3	4		T4	50		T9	1
all_levels[6]	245382	1			T3	2		T4	50		T9	3
all_levels[7]	287395	1			T2	2		T3	2		T4	57
all_levels[8]	335989	1			T4	49		T9	2		T10	9
all_levels[9]	310881	1			T3	1		T4	51		T7	1
all_levels[10]	222075	1			T4	51		T10	12		T11	18
all_levels[11]	528045	1			T3	83		T4	54		T7	2
all_levels[12]	223937	1			T4	53		T10	11		T11	15
all_levels[13]	249989	1			T4	58		T10	6		T11	1
all_levels[14]	205095	1			T4	60		T9	1		T10	10
all_levels[15]	249947	1			T4	53		T9	2		T10	12
all_levels[16]	351720	1			T4	55		T10	6		T11	3
all_levels[17]	369281	1			T4	51		T9	3		T10	18
all_levels[18]	204354	1			T2	2		T4	49		T9	2
all_levels[19]	195373	1			T2	1		T4	52		T9	1
all_levels[20]	215864	1			T4	48		T10	9		T11	5
all_levels[21]	331194	1			T4	49		T10	9		T37	193
all_levels[22]	215447	1			T4	59		T9	3		T10	8
all_levels[23]	191365	1			T4	53		T10	12		T11	1
all_levels[24]	515129	1			T4	61		T10	7		T37	193
all_levels[25]	401110	1			T4	54		T9	1		T10	11
all_levels[26]	233117	1			T4	45		T10	12		T11	2
all_levels[27]	309896	1			T4	44		T10	11		T37	194
all_levels[28]	256277	1			T4	55		T10	9		T11	5
all_levels[29]	158130	1			T4	52		T10	7		T11	8
all_levels[30]	200296	1			T4	52		T10	7		T11	2
all_levels[31]	521540	1			T2	2		T4	2565		T9	4
all_levels[32]	12679745	1			T2	22		T4	155377		T7	7

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31474416

1

T2

30

T3

238

T4

161228

auto[1]

4239

1

T2

10

T6

5

T11

13

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7883818	1			T2	2		T3	133		T4	1725
all_levels[0]	auto[1]	2393	1			T2	4		T6	5		T11	6
all_levels[1]	auto[0]	1873241	1			T3	4		T4	45		T7	1
all_levels[1]	auto[1]	276	1			T45	3		T123	1		T14	2
all_levels[2]	auto[0]	581204	1			T2	2		T3	5		T4	55
all_levels[2]	auto[1]	28	1			T2	1		T20	1		T124	1
all_levels[3]	auto[0]	298263	1			T4	46		T9	2		T10	8
all_levels[3]	auto[1]	89	1			T109	1		T108	1		T69	1
all_levels[4]	auto[0]	366275	1			T2	2		T3	4		T4	50
all_levels[4]	auto[1]	16	1			T33	1		T323	1		T324	5
all_levels[5]	auto[0]	264447	1			T3	4		T4	50		T9	1
all_levels[5]	auto[1]	32	1			T135	1		T172	2		T176	2
all_levels[6]	auto[0]	245353	1			T3	2		T4	50		T9	3
all_levels[6]	auto[1]	29	1			T41	3		T137	1		T195	5
all_levels[7]	auto[0]	287297	1			T2	2		T3	2		T4	57
all_levels[7]	auto[1]	98	1			T11	1		T16	1		T262	2
all_levels[8]	auto[0]	335957	1			T4	49		T9	2		T10	9
all_levels[8]	auto[1]	32	1			T40	3		T25	2		T230	4
all_levels[9]	auto[0]	310849	1			T3	1		T4	51		T7	1
all_levels[9]	auto[1]	32	1			T121	1		T293	1		T177	1
all_levels[10]	auto[0]	222056	1			T4	51		T10	12		T11	18
all_levels[10]	auto[1]	19	1			T291	2		T262	1		T189	2
all_levels[11]	auto[0]	528015	1			T3	83		T4	54		T7	2
all_levels[11]	auto[1]	30	1			T25	1		T34	1		T127	1
all_levels[12]	auto[0]	223917	1			T4	53		T10	11		T11	15
all_levels[12]	auto[1]	20	1			T213	2		T175	1		T325	1
all_levels[13]	auto[0]	249966	1			T4	58		T10	6		T11	1
all_levels[13]	auto[1]	23	1			T289	1		T264	1		T177	2
all_levels[14]	auto[0]	205072	1			T4	60		T9	1		T10	10
all_levels[14]	auto[1]	23	1			T135	3		T33	1		T128	1
all_levels[15]	auto[0]	249736	1			T4	53		T9	2		T10	12
all_levels[15]	auto[1]	211	1			T11	2		T38	1		T39	1
all_levels[16]	auto[0]	351689	1			T4	55		T10	6		T11	3
all_levels[16]	auto[1]	31	1			T262	2		T289	2		T325	1
all_levels[17]	auto[0]	369258	1			T4	51		T9	3		T10	18
all_levels[17]	auto[1]	23	1			T25	1		T311	1		T201	1
all_levels[18]	auto[0]	204315	1			T2	1		T4	49		T9	2
all_levels[18]	auto[1]	39	1			T2	1		T173	2		T318	1
all_levels[19]	auto[0]	195355	1			T2	1		T4	52		T9	1
all_levels[19]	auto[1]	18	1			T70	1		T133	1		T326	1
all_levels[20]	auto[0]	215833	1			T4	48		T10	9		T11	5
all_levels[20]	auto[1]	31	1			T134	1		T70	1		T71	1
all_levels[21]	auto[0]	331159	1			T4	49		T10	9		T37	193
all_levels[21]	auto[1]	35	1			T142	1		T191	3		T327	1
all_levels[22]	auto[0]	215419	1			T4	59		T9	3		T10	8
all_levels[22]	auto[1]	28	1			T123	2		T147	1		T142	1
all_levels[23]	auto[0]	191358	1			T4	53		T10	12		T11	1
all_levels[23]	auto[1]	7	1			T218	1		T325	1		T143	1
all_levels[24]	auto[0]	515094	1			T4	61		T10	7		T37	193
all_levels[24]	auto[1]	35	1			T118	1		T136	1		T115	7
all_levels[25]	auto[0]	401093	1			T4	54		T9	1		T10	11
all_levels[25]	auto[1]	17	1			T46	1		T70	3		T293	1
all_levels[26]	auto[0]	233101	1			T4	45		T10	12		T11	2
all_levels[26]	auto[1]	16	1			T230	1		T179	1		T181	1
all_levels[27]	auto[0]	309875	1			T4	44		T10	11		T37	194
all_levels[27]	auto[1]	21	1			T66	1		T174	1		T284	1
all_levels[28]	auto[0]	256254	1			T4	55		T10	9		T11	5
all_levels[28]	auto[1]	23	1			T185	4		T328	2		T329	1
all_levels[29]	auto[0]	158112	1			T4	52		T10	7		T11	8
all_levels[29]	auto[1]	18	1			T121	2		T123	1		T64	2
all_levels[30]	auto[0]	200272	1			T4	52		T10	7		T11	2
all_levels[30]	auto[1]	24	1			T147	2		T133	1		T330	1
all_levels[31]	auto[0]	521520	1			T2	1		T4	2565		T9	4
all_levels[31]	auto[1]	20	1			T2	1		T11	1		T173	1
all_levels[32]	auto[0]	12679243	1			T2	19		T4	155377		T7	7
all_levels[32]	auto[1]	502	1			T2	3		T11	3		T39	2