Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	756	1			T11	8		T13	7		T16	4
all_values[1]	756	1			T11	8		T13	7		T16	4
all_values[2]	756	1			T11	8		T13	7		T16	4
all_values[3]	756	1			T11	8		T13	7		T16	4
all_values[4]	756	1			T11	8		T13	7		T16	4
all_values[5]	756	1			T11	8		T13	7		T16	4
all_values[6]	756	1			T11	8		T13	7		T16	4
all_values[7]	756	1			T11	8		T13	7		T16	4
all_values[8]	756	1			T11	8		T13	7		T16	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3627

1

T11

45

T13

32

T16

12

auto[1]

3177

1

T11

27

T13

31

T16

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2278

1

T11

23

T13

20

T16

17

auto[1]

4526

1

T11

49

T13

43

T16

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4039

1

T11

42

T13

32

T16

25

auto[1]

2765

1

T11

30

T13

31

T16

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	241	1			T11	3		T13	1		T16	2
all_values[0]	auto[0]	auto[1]	auto[1]	203	1			T11	1		T13	1		T33	1
all_values[0]	auto[1]	auto[0]	auto[1]	185	1			T11	1		T13	2		T33	1
all_values[0]	auto[1]	auto[1]	auto[1]	127	1			T11	3		T13	3		T16	2
all_values[1]	auto[0]	auto[0]	auto[0]	227	1			T11	3		T13	1		T16	2
all_values[1]	auto[0]	auto[1]	auto[0]	214	1			T11	1		T13	2		T16	2
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T11	4		T13	2		T33	3
all_values[1]	auto[1]	auto[1]	auto[1]	145	1			T13	2		T34	3		T108	3
all_values[2]	auto[0]	auto[0]	auto[0]	166	1			T11	2		T13	1		T33	1
all_values[2]	auto[0]	auto[0]	auto[1]	91	1			T11	1		T34	1		T108	2
all_values[2]	auto[0]	auto[1]	auto[0]	141	1			T13	1		T16	4		T34	5
all_values[2]	auto[0]	auto[1]	auto[1]	61	1			T11	1		T13	1		T33	1
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T11	3		T13	2		T34	3
all_values[2]	auto[1]	auto[1]	auto[1]	135	1			T11	1		T13	2		T33	2
all_values[3]	auto[0]	auto[0]	auto[0]	154	1			T11	2		T13	1		T16	2
all_values[3]	auto[0]	auto[0]	auto[1]	71	1			T33	1		T34	2		T108	2
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T16	2		T34	5		T108	1
all_values[3]	auto[0]	auto[1]	auto[1]	63	1			T11	3		T13	4		T66	1
all_values[3]	auto[1]	auto[0]	auto[1]	187	1			T11	1		T13	2		T33	3
all_values[3]	auto[1]	auto[1]	auto[1]	130	1			T11	2		T34	1		T108	2
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T11	3		T13	3		T33	1
all_values[4]	auto[0]	auto[0]	auto[1]	66	1			T16	1		T34	2		T118	1
all_values[4]	auto[0]	auto[1]	auto[0]	122	1			T13	3		T16	2		T34	2
all_values[4]	auto[0]	auto[1]	auto[1]	92	1			T11	1		T33	1		T34	2
all_values[4]	auto[1]	auto[0]	auto[1]	144	1			T11	2		T13	1		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	171	1			T11	2		T33	1		T34	3
all_values[5]	auto[0]	auto[0]	auto[0]	192	1			T11	2		T13	1		T33	1
all_values[5]	auto[0]	auto[0]	auto[1]	67	1			T11	2		T13	2		T34	1
all_values[5]	auto[0]	auto[1]	auto[0]	145	1			T11	1		T33	1		T34	1
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T16	2		T33	1		T34	3
all_values[5]	auto[1]	auto[0]	auto[1]	153	1			T11	2		T13	4		T33	1
all_values[5]	auto[1]	auto[1]	auto[1]	129	1			T11	1		T16	2		T34	3
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T11	2		T13	2		T16	2
all_values[6]	auto[0]	auto[0]	auto[1]	73	1			T11	1		T34	4		T108	1
all_values[6]	auto[0]	auto[1]	auto[0]	125	1			T11	2		T13	2		T34	2
all_values[6]	auto[0]	auto[1]	auto[1]	77	1			T33	2		T34	2		T108	1
all_values[6]	auto[1]	auto[0]	auto[1]	179	1			T11	2		T13	1		T16	2
all_values[6]	auto[1]	auto[1]	auto[1]	144	1			T11	1		T13	2		T34	3
all_values[7]	auto[0]	auto[0]	auto[0]	148	1			T11	3		T13	2		T34	2
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T33	2		T34	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[0]	174	1			T11	2		T13	1		T16	1
all_values[7]	auto[0]	auto[1]	auto[1]	71	1			T13	1		T16	1		T34	1
all_values[7]	auto[1]	auto[0]	auto[1]	157	1			T11	1		T13	2		T33	2
all_values[7]	auto[1]	auto[1]	auto[1]	136	1			T11	2		T13	1		T16	2
all_values[8]	auto[0]	auto[0]	auto[1]	247	1			T11	4		T33	3		T34	4
all_values[8]	auto[0]	auto[1]	auto[1]	198	1			T11	2		T13	2		T16	2
all_values[8]	auto[1]	auto[0]	auto[1]	158	1			T11	1		T13	2		T33	1
all_values[8]	auto[1]	auto[1]	auto[1]	153	1			T11	1		T13	3		T16	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal