Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.12 99.10 97.65 100.00 98.38 100.00 99.57


Total test records in report: 1313
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T1259 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.484446165 Jul 30 06:27:10 PM PDT 24 Jul 30 06:27:11 PM PDT 24 40608723 ps
T1260 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3099000049 Jul 30 06:27:11 PM PDT 24 Jul 30 06:27:12 PM PDT 24 99364594 ps
T1261 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3967828627 Jul 30 06:27:06 PM PDT 24 Jul 30 06:27:07 PM PDT 24 55152786 ps
T1262 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1220832960 Jul 30 06:26:42 PM PDT 24 Jul 30 06:26:43 PM PDT 24 12701326 ps
T1263 /workspace/coverage/cover_reg_top/1.uart_csr_rw.1287670183 Jul 30 06:26:35 PM PDT 24 Jul 30 06:26:36 PM PDT 24 15741193 ps
T1264 /workspace/coverage/cover_reg_top/7.uart_csr_rw.3025077557 Jul 30 06:26:50 PM PDT 24 Jul 30 06:26:51 PM PDT 24 21361514 ps
T92 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4160714678 Jul 30 06:27:04 PM PDT 24 Jul 30 06:27:05 PM PDT 24 41412161 ps
T1265 /workspace/coverage/cover_reg_top/36.uart_intr_test.234801952 Jul 30 06:27:05 PM PDT 24 Jul 30 06:27:06 PM PDT 24 51467400 ps
T1266 /workspace/coverage/cover_reg_top/5.uart_intr_test.145830271 Jul 30 06:26:42 PM PDT 24 Jul 30 06:26:42 PM PDT 24 12934673 ps
T1267 /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1259191197 Jul 30 06:26:37 PM PDT 24 Jul 30 06:26:38 PM PDT 24 17267575 ps
T119 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.691278621 Jul 30 06:26:53 PM PDT 24 Jul 30 06:26:54 PM PDT 24 86235259 ps
T1268 /workspace/coverage/cover_reg_top/3.uart_intr_test.519436519 Jul 30 06:26:38 PM PDT 24 Jul 30 06:26:39 PM PDT 24 15204585 ps
T1269 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3002665847 Jul 30 06:26:32 PM PDT 24 Jul 30 06:26:33 PM PDT 24 74357690 ps
T1270 /workspace/coverage/cover_reg_top/31.uart_intr_test.2954324374 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:13 PM PDT 24 24637616 ps
T1271 /workspace/coverage/cover_reg_top/21.uart_intr_test.1275470383 Jul 30 06:27:11 PM PDT 24 Jul 30 06:27:12 PM PDT 24 29169870 ps
T58 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.988693879 Jul 30 06:26:44 PM PDT 24 Jul 30 06:26:45 PM PDT 24 21528017 ps
T1272 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1322353007 Jul 30 06:27:08 PM PDT 24 Jul 30 06:27:09 PM PDT 24 245731598 ps
T1273 /workspace/coverage/cover_reg_top/18.uart_tl_errors.594174366 Jul 30 06:27:22 PM PDT 24 Jul 30 06:27:23 PM PDT 24 259681467 ps
T1274 /workspace/coverage/cover_reg_top/15.uart_tl_errors.1918383412 Jul 30 06:27:02 PM PDT 24 Jul 30 06:27:04 PM PDT 24 366243431 ps
T93 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2852110991 Jul 30 06:26:36 PM PDT 24 Jul 30 06:26:37 PM PDT 24 240551350 ps
T1275 /workspace/coverage/cover_reg_top/37.uart_intr_test.1177104480 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:13 PM PDT 24 46147428 ps
T1276 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3747798873 Jul 30 06:26:33 PM PDT 24 Jul 30 06:26:35 PM PDT 24 747320015 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1554670964 Jul 30 06:26:36 PM PDT 24 Jul 30 06:26:37 PM PDT 24 575749952 ps
T1278 /workspace/coverage/cover_reg_top/22.uart_intr_test.1010380169 Jul 30 06:27:18 PM PDT 24 Jul 30 06:27:18 PM PDT 24 20542231 ps
T1279 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.981731813 Jul 30 06:27:06 PM PDT 24 Jul 30 06:27:07 PM PDT 24 111139778 ps
T59 /workspace/coverage/cover_reg_top/4.uart_csr_rw.711534255 Jul 30 06:26:46 PM PDT 24 Jul 30 06:26:46 PM PDT 24 12060561 ps
T1280 /workspace/coverage/cover_reg_top/7.uart_tl_errors.473727681 Jul 30 06:26:53 PM PDT 24 Jul 30 06:26:55 PM PDT 24 59564681 ps
T1281 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2753625240 Jul 30 06:26:34 PM PDT 24 Jul 30 06:26:37 PM PDT 24 67795600 ps
T1282 /workspace/coverage/cover_reg_top/12.uart_intr_test.1794649647 Jul 30 06:27:07 PM PDT 24 Jul 30 06:27:08 PM PDT 24 13977508 ps
T1283 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3676870991 Jul 30 06:27:11 PM PDT 24 Jul 30 06:27:12 PM PDT 24 18324297 ps
T60 /workspace/coverage/cover_reg_top/17.uart_csr_rw.2032119495 Jul 30 06:27:08 PM PDT 24 Jul 30 06:27:09 PM PDT 24 10650466 ps
T1284 /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.983816157 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:13 PM PDT 24 35247442 ps
T1285 /workspace/coverage/cover_reg_top/39.uart_intr_test.1937457309 Jul 30 06:27:04 PM PDT 24 Jul 30 06:27:04 PM PDT 24 37947972 ps
T1286 /workspace/coverage/cover_reg_top/33.uart_intr_test.1296807025 Jul 30 06:27:19 PM PDT 24 Jul 30 06:27:20 PM PDT 24 10877527 ps
T120 /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1626625705 Jul 30 06:27:11 PM PDT 24 Jul 30 06:27:12 PM PDT 24 203019839 ps
T1287 /workspace/coverage/cover_reg_top/17.uart_intr_test.1084856886 Jul 30 06:27:16 PM PDT 24 Jul 30 06:27:17 PM PDT 24 13270436 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_tl_errors.2099140999 Jul 30 06:27:01 PM PDT 24 Jul 30 06:27:02 PM PDT 24 134815233 ps
T1289 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2231599683 Jul 30 06:27:04 PM PDT 24 Jul 30 06:27:05 PM PDT 24 32314059 ps
T1290 /workspace/coverage/cover_reg_top/11.uart_intr_test.2053272095 Jul 30 06:26:51 PM PDT 24 Jul 30 06:26:52 PM PDT 24 13612632 ps
T1291 /workspace/coverage/cover_reg_top/25.uart_intr_test.2501921507 Jul 30 06:27:13 PM PDT 24 Jul 30 06:27:14 PM PDT 24 14037323 ps
T1292 /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.495773099 Jul 30 06:27:00 PM PDT 24 Jul 30 06:27:01 PM PDT 24 57202199 ps
T1293 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1423870336 Jul 30 06:27:03 PM PDT 24 Jul 30 06:27:05 PM PDT 24 234670729 ps
T1294 /workspace/coverage/cover_reg_top/16.uart_tl_errors.3735959691 Jul 30 06:27:17 PM PDT 24 Jul 30 06:27:19 PM PDT 24 1287793074 ps
T1295 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1761983673 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:13 PM PDT 24 90684851 ps
T1296 /workspace/coverage/cover_reg_top/15.uart_csr_rw.2115033312 Jul 30 06:27:11 PM PDT 24 Jul 30 06:27:12 PM PDT 24 24691452 ps
T1297 /workspace/coverage/cover_reg_top/42.uart_intr_test.2237007926 Jul 30 06:27:13 PM PDT 24 Jul 30 06:27:14 PM PDT 24 35560923 ps
T1298 /workspace/coverage/cover_reg_top/12.uart_tl_errors.3684500155 Jul 30 06:27:08 PM PDT 24 Jul 30 06:27:10 PM PDT 24 65317997 ps
T1299 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4095873373 Jul 30 06:26:45 PM PDT 24 Jul 30 06:26:46 PM PDT 24 142940365 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_intr_test.3047117635 Jul 30 06:26:56 PM PDT 24 Jul 30 06:26:57 PM PDT 24 67415493 ps
T1301 /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1746444000 Jul 30 06:26:39 PM PDT 24 Jul 30 06:26:40 PM PDT 24 23005803 ps
T1302 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.333258819 Jul 30 06:27:08 PM PDT 24 Jul 30 06:27:09 PM PDT 24 144119659 ps
T1303 /workspace/coverage/cover_reg_top/6.uart_tl_errors.1079736166 Jul 30 06:26:43 PM PDT 24 Jul 30 06:26:46 PM PDT 24 169627794 ps
T1304 /workspace/coverage/cover_reg_top/3.uart_csr_rw.3080277048 Jul 30 06:26:39 PM PDT 24 Jul 30 06:26:40 PM PDT 24 40270872 ps
T1305 /workspace/coverage/cover_reg_top/3.uart_tl_errors.1494384371 Jul 30 06:26:39 PM PDT 24 Jul 30 06:26:41 PM PDT 24 32228006 ps
T1306 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.151358614 Jul 30 06:26:38 PM PDT 24 Jul 30 06:26:39 PM PDT 24 68951242 ps
T1307 /workspace/coverage/cover_reg_top/5.uart_tl_errors.3250184556 Jul 30 06:26:43 PM PDT 24 Jul 30 06:26:46 PM PDT 24 132021264 ps
T1308 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3722237209 Jul 30 06:26:40 PM PDT 24 Jul 30 06:26:40 PM PDT 24 21520020 ps
T1309 /workspace/coverage/cover_reg_top/19.uart_intr_test.1601761872 Jul 30 06:27:03 PM PDT 24 Jul 30 06:27:03 PM PDT 24 21464766 ps
T1310 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2034705726 Jul 30 06:26:42 PM PDT 24 Jul 30 06:26:43 PM PDT 24 88250542 ps
T1311 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4243623639 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:14 PM PDT 24 83980104 ps
T1312 /workspace/coverage/cover_reg_top/11.uart_csr_rw.1859530617 Jul 30 06:27:05 PM PDT 24 Jul 30 06:27:05 PM PDT 24 43080404 ps
T61 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3910209447 Jul 30 06:27:12 PM PDT 24 Jul 30 06:27:13 PM PDT 24 49394654 ps
T1313 /workspace/coverage/cover_reg_top/13.uart_csr_rw.1582359810 Jul 30 06:27:06 PM PDT 24 Jul 30 06:27:07 PM PDT 24 31771782 ps

Test location /workspace/coverage/default/0.uart_noise_filter.3802673939
Short name T3
Test name
Test status
Simulation time 28106620304 ps
CPU time 42.56 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:37:16 PM PDT 24
Peak memory 200108 kb
Host smart-bb9f2e5f-c98b-4551-b239-0916129c0b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802673939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.3802673939
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.432383440
Short name T13
Test name
Test status
Simulation time 245851805687 ps
CPU time 913.8 seconds
Started Jul 30 07:41:04 PM PDT 24
Finished Jul 30 07:56:18 PM PDT 24
Peak memory 216512 kb
Host smart-75ff8c8a-8120-46e8-8dbc-2cec12a70ee2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432383440 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.432383440
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.503342719
Short name T11
Test name
Test status
Simulation time 136671506937 ps
CPU time 569.06 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:46:55 PM PDT 24
Peak memory 224792 kb
Host smart-113ef3c1-1b03-4e13-b118-85615cf23461
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503342719 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.503342719
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_stress_all.3247495728
Short name T110
Test name
Test status
Simulation time 409435870523 ps
CPU time 568.36 seconds
Started Jul 30 07:37:51 PM PDT 24
Finished Jul 30 07:47:19 PM PDT 24
Peak memory 199932 kb
Host smart-82051eca-1682-4933-b8a8-174491b20701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247495728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.3247495728
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all.584931651
Short name T67
Test name
Test status
Simulation time 149338891402 ps
CPU time 266.98 seconds
Started Jul 30 07:38:25 PM PDT 24
Finished Jul 30 07:42:52 PM PDT 24
Peak memory 200000 kb
Host smart-847482f4-4a8c-4f19-b620-1a26c525617f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584931651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.584931651
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.3809017739
Short name T66
Test name
Test status
Simulation time 395678534993 ps
CPU time 344.81 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:42:31 PM PDT 24
Peak memory 199952 kb
Host smart-0d73f07c-55fd-4fd5-8b9e-78eef746d36b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809017739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3809017739
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.4015270533
Short name T25
Test name
Test status
Simulation time 194245462611 ps
CPU time 695.19 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:48:17 PM PDT 24
Peak memory 216504 kb
Host smart-d88a0437-81d1-40cd-a10d-2211b18ea5d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015270533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4015270533
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.298035248
Short name T20
Test name
Test status
Simulation time 33189594969 ps
CPU time 425.23 seconds
Started Jul 30 07:41:16 PM PDT 24
Finished Jul 30 07:48:21 PM PDT 24
Peak memory 215644 kb
Host smart-3002a256-535f-41dd-ac65-91236ada386b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298035248 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.298035248
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_stress_all.3045392579
Short name T16
Test name
Test status
Simulation time 464685985125 ps
CPU time 235.32 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:43:05 PM PDT 24
Peak memory 208300 kb
Host smart-8ede1c9e-f08b-45e3-806e-b5af37dd4143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045392579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3045392579
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.2579468272
Short name T29
Test name
Test status
Simulation time 67308094 ps
CPU time 0.95 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:36:32 PM PDT 24
Peak memory 218440 kb
Host smart-375b4845-4595-45aa-8135-deb9d66af36c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579468272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.2579468272
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/14.uart_stress_all.4001406172
Short name T108
Test name
Test status
Simulation time 220529451153 ps
CPU time 471.48 seconds
Started Jul 30 07:37:15 PM PDT 24
Finished Jul 30 07:45:07 PM PDT 24
Peak memory 199904 kb
Host smart-1ee3c7a1-8be3-4c14-a989-4f937d84efcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001406172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.4001406172
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.4056264669
Short name T9
Test name
Test status
Simulation time 41925603276 ps
CPU time 42.39 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:31 PM PDT 24
Peak memory 199876 kb
Host smart-033e675f-55b2-4849-9779-a8d34354d503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056264669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.4056264669
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3742673243
Short name T99
Test name
Test status
Simulation time 53056241561 ps
CPU time 458.24 seconds
Started Jul 30 07:41:28 PM PDT 24
Finished Jul 30 07:49:06 PM PDT 24
Peak memory 216548 kb
Host smart-82b9fb01-f0ff-4ab4-89b9-c6e42ec8cc38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742673243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3742673243
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_stress_all.724593120
Short name T127
Test name
Test status
Simulation time 505699320602 ps
CPU time 955.07 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:52:33 PM PDT 24
Peak memory 199872 kb
Host smart-60af5cc4-a0d8-47be-8fb4-9b5124d652d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724593120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.724593120
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all.1213833108
Short name T270
Test name
Test status
Simulation time 351570959109 ps
CPU time 379.27 seconds
Started Jul 30 07:37:08 PM PDT 24
Finished Jul 30 07:43:28 PM PDT 24
Peak memory 199956 kb
Host smart-16448fea-2ae5-41bb-983e-4dfcd2e7b777
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213833108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1213833108
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.1352233931
Short name T33
Test name
Test status
Simulation time 99935862736 ps
CPU time 249.39 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:41:05 PM PDT 24
Peak memory 216464 kb
Host smart-38599500-3c21-477d-9e5e-46ef5e50ccc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352233931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.1352233931
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1600223482
Short name T89
Test name
Test status
Simulation time 93158022 ps
CPU time 1.33 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 199668 kb
Host smart-1ad41ba0-5c60-44cb-9990-8d691d1346df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600223482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1600223482
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2210160025
Short name T49
Test name
Test status
Simulation time 294794718173 ps
CPU time 665.02 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:51:34 PM PDT 24
Peak memory 224780 kb
Host smart-793c2142-1437-4a7f-be7f-3313c0e742d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210160025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2210160025
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2104055477
Short name T134
Test name
Test status
Simulation time 263404793889 ps
CPU time 30.47 seconds
Started Jul 30 07:38:14 PM PDT 24
Finished Jul 30 07:38:45 PM PDT 24
Peak memory 199852 kb
Host smart-4afa4657-5783-40e9-9af0-b3754b1383c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104055477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2104055477
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_alert_test.1771738190
Short name T339
Test name
Test status
Simulation time 50430239 ps
CPU time 0.57 seconds
Started Jul 30 07:37:34 PM PDT 24
Finished Jul 30 07:37:34 PM PDT 24
Peak memory 195300 kb
Host smart-04d4dc39-288d-42e4-85ee-51eb770a9231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771738190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1771738190
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.837832760
Short name T114
Test name
Test status
Simulation time 54288798728 ps
CPU time 1831.91 seconds
Started Jul 30 07:40:58 PM PDT 24
Finished Jul 30 08:11:30 PM PDT 24
Peak memory 216420 kb
Host smart-b51b57ca-2226-4370-a572-d2505b97224f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837832760 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.837832760
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all.3220334999
Short name T262
Test name
Test status
Simulation time 300852836410 ps
CPU time 1317.61 seconds
Started Jul 30 07:38:15 PM PDT 24
Finished Jul 30 08:00:13 PM PDT 24
Peak memory 199920 kb
Host smart-4bcf99c7-fb39-44e2-85ba-e887e688c87a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220334999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3220334999
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2544211686
Short name T150
Test name
Test status
Simulation time 102921969115 ps
CPU time 153.08 seconds
Started Jul 30 07:42:27 PM PDT 24
Finished Jul 30 07:45:00 PM PDT 24
Peak memory 199996 kb
Host smart-734fcd4f-f861-4072-bc5a-3f6c5aeb69b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544211686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2544211686
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.3902863025
Short name T140
Test name
Test status
Simulation time 423646904360 ps
CPU time 1104.74 seconds
Started Jul 30 07:41:12 PM PDT 24
Finished Jul 30 07:59:37 PM PDT 24
Peak memory 224740 kb
Host smart-1db65aa7-81a8-47a4-be2c-3dfbecbc2533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902863025 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.3902863025
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_stress_all.2091794192
Short name T115
Test name
Test status
Simulation time 383103593829 ps
CPU time 971.65 seconds
Started Jul 30 07:40:02 PM PDT 24
Finished Jul 30 07:56:14 PM PDT 24
Peak memory 199868 kb
Host smart-63b8d2a4-3c37-446d-b9d7-de3be0a4fb70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091794192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2091794192
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2866825323
Short name T69
Test name
Test status
Simulation time 53004578784 ps
CPU time 149.38 seconds
Started Jul 30 07:42:19 PM PDT 24
Finished Jul 30 07:44:49 PM PDT 24
Peak memory 199932 kb
Host smart-2f48fcb9-322a-43b3-8de3-9f202ab755af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866825323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2866825323
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.1268531686
Short name T80
Test name
Test status
Simulation time 108186809 ps
CPU time 0.71 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 196268 kb
Host smart-0474df2b-95e0-42b0-9056-221f232a5119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268531686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.1268531686
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1602353893
Short name T57
Test name
Test status
Simulation time 118017605 ps
CPU time 2.28 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 198380 kb
Host smart-f257b173-e4a2-487b-a070-896701c3070e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602353893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1602353893
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2891219080
Short name T113
Test name
Test status
Simulation time 134887822233 ps
CPU time 62.1 seconds
Started Jul 30 07:37:09 PM PDT 24
Finished Jul 30 07:38:11 PM PDT 24
Peak memory 199916 kb
Host smart-94d6ded7-6a44-453f-bcbc-565660a0deab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891219080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2891219080
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3140212954
Short name T52
Test name
Test status
Simulation time 1184611572692 ps
CPU time 1118.55 seconds
Started Jul 30 07:37:38 PM PDT 24
Finished Jul 30 07:56:17 PM PDT 24
Peak memory 232668 kb
Host smart-6072c7ed-410f-4573-8498-736a2835b44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140212954 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3140212954
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.1228046951
Short name T142
Test name
Test status
Simulation time 42456461712 ps
CPU time 71.05 seconds
Started Jul 30 07:43:08 PM PDT 24
Finished Jul 30 07:44:19 PM PDT 24
Peak memory 199948 kb
Host smart-28012d91-fee4-4347-a840-33446a10be45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228046951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.1228046951
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.765541948
Short name T149
Test name
Test status
Simulation time 590667538198 ps
CPU time 290.63 seconds
Started Jul 30 07:38:12 PM PDT 24
Finished Jul 30 07:43:03 PM PDT 24
Peak memory 199896 kb
Host smart-b1f6b960-1013-4026-b07b-fb7159640ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765541948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.765541948
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2278989246
Short name T314
Test name
Test status
Simulation time 70703196515 ps
CPU time 1010.59 seconds
Started Jul 30 07:41:20 PM PDT 24
Finished Jul 30 07:58:11 PM PDT 24
Peak memory 224652 kb
Host smart-44d358c0-ad98-4c9b-afa4-2be35e702006
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278989246 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2278989246
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3104903206
Short name T244
Test name
Test status
Simulation time 74134700470 ps
CPU time 59.15 seconds
Started Jul 30 07:43:15 PM PDT 24
Finished Jul 30 07:44:14 PM PDT 24
Peak memory 199816 kb
Host smart-53059ee5-cadf-4e94-9e73-c8d82f881f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104903206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3104903206
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3735703233
Short name T178
Test name
Test status
Simulation time 246767502744 ps
CPU time 262.24 seconds
Started Jul 30 07:41:16 PM PDT 24
Finished Jul 30 07:45:38 PM PDT 24
Peak memory 199964 kb
Host smart-bae403b9-eea6-4359-9f89-3775e553b3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735703233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3735703233
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.4004369037
Short name T112
Test name
Test status
Simulation time 96861217228 ps
CPU time 42.43 seconds
Started Jul 30 07:41:52 PM PDT 24
Finished Jul 30 07:42:35 PM PDT 24
Peak memory 199992 kb
Host smart-08e7c580-75e1-4752-abd3-5030c1974769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004369037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.4004369037
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_fifo_full.2314785651
Short name T169
Test name
Test status
Simulation time 153531596627 ps
CPU time 35.03 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 199868 kb
Host smart-f45c127c-93d7-4352-bbc1-66d8016c95b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314785651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2314785651
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3930015331
Short name T88
Test name
Test status
Simulation time 133616979 ps
CPU time 1.35 seconds
Started Jul 30 06:26:52 PM PDT 24
Finished Jul 30 06:26:53 PM PDT 24
Peak memory 199692 kb
Host smart-59c353e6-f28a-4b87-a46d-1f8f18c70e57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930015331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3930015331
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1559099908
Short name T211
Test name
Test status
Simulation time 32044994747 ps
CPU time 26.77 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:42:29 PM PDT 24
Peak memory 199936 kb
Host smart-41f16674-040f-4492-8196-0198a985aee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559099908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1559099908
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.2111590482
Short name T151
Test name
Test status
Simulation time 124446033553 ps
CPU time 123.12 seconds
Started Jul 30 07:37:40 PM PDT 24
Finished Jul 30 07:39:43 PM PDT 24
Peak memory 208288 kb
Host smart-b9e4c2b6-a1ae-4741-be45-2d3d4df4f205
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111590482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.2111590482
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.265007700
Short name T825
Test name
Test status
Simulation time 65446966562 ps
CPU time 99.68 seconds
Started Jul 30 07:42:49 PM PDT 24
Finished Jul 30 07:44:29 PM PDT 24
Peak memory 200004 kb
Host smart-69a8adde-e5a6-4979-8c5f-c9c094a13e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265007700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.265007700
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1428143637
Short name T136
Test name
Test status
Simulation time 164516042237 ps
CPU time 134.73 seconds
Started Jul 30 07:38:08 PM PDT 24
Finished Jul 30 07:40:23 PM PDT 24
Peak memory 199788 kb
Host smart-bb50cf75-fe9d-410b-b788-c9aae0ba94eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428143637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1428143637
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.1031860606
Short name T167
Test name
Test status
Simulation time 206053746603 ps
CPU time 89.6 seconds
Started Jul 30 07:41:36 PM PDT 24
Finished Jul 30 07:43:06 PM PDT 24
Peak memory 199948 kb
Host smart-2bd26945-17c4-48ce-aa97-937f74fb6275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031860606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.1031860606
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1020496567
Short name T325
Test name
Test status
Simulation time 17044798892 ps
CPU time 29.74 seconds
Started Jul 30 07:41:56 PM PDT 24
Finished Jul 30 07:42:26 PM PDT 24
Peak memory 199980 kb
Host smart-ccf2ccc0-a5c3-42d4-bdb2-63069c146baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020496567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1020496567
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3207941541
Short name T195
Test name
Test status
Simulation time 16141911256 ps
CPU time 13 seconds
Started Jul 30 07:42:19 PM PDT 24
Finished Jul 30 07:42:32 PM PDT 24
Peak memory 199936 kb
Host smart-500a61e8-a25d-4a54-bf15-dec980c96e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207941541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3207941541
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3353944639
Short name T172
Test name
Test status
Simulation time 190460861987 ps
CPU time 145.49 seconds
Started Jul 30 07:42:30 PM PDT 24
Finished Jul 30 07:44:55 PM PDT 24
Peak memory 199920 kb
Host smart-22b4046b-b1b2-4fc8-a053-6460f4688b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353944639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3353944639
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1978972857
Short name T210
Test name
Test status
Simulation time 55973095102 ps
CPU time 113.52 seconds
Started Jul 30 07:42:52 PM PDT 24
Finished Jul 30 07:44:46 PM PDT 24
Peak memory 199888 kb
Host smart-b9f08d3c-a00b-43c7-ace2-2c05cdba168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978972857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1978972857
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.18672001
Short name T231
Test name
Test status
Simulation time 21767564635 ps
CPU time 34.66 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 199956 kb
Host smart-89af125c-e520-42aa-8994-84c9cb196be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18672001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.18672001
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.2409534213
Short name T219
Test name
Test status
Simulation time 125842889079 ps
CPU time 52.03 seconds
Started Jul 30 07:41:43 PM PDT 24
Finished Jul 30 07:42:36 PM PDT 24
Peak memory 199932 kb
Host smart-806f39c5-c4b6-491e-ac66-8fb360b40400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409534213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.2409534213
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.1678152586
Short name T236
Test name
Test status
Simulation time 391743161454 ps
CPU time 36.58 seconds
Started Jul 30 07:41:49 PM PDT 24
Finished Jul 30 07:42:25 PM PDT 24
Peak memory 199996 kb
Host smart-4292cd4e-8180-49fa-bd97-f73174a3ec21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678152586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.1678152586
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.406952211
Short name T189
Test name
Test status
Simulation time 16717825529 ps
CPU time 31.87 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:35 PM PDT 24
Peak memory 199752 kb
Host smart-07061cfd-202e-47e7-bc35-0afb93adeb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406952211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.406952211
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.2544930478
Short name T2
Test name
Test status
Simulation time 30289225135 ps
CPU time 44.06 seconds
Started Jul 30 07:42:18 PM PDT 24
Finished Jul 30 07:43:02 PM PDT 24
Peak memory 199896 kb
Host smart-e0fd9efd-8315-4669-bafa-8878973d1b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544930478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.2544930478
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.2565006290
Short name T160
Test name
Test status
Simulation time 94172591392 ps
CPU time 39.68 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:43:17 PM PDT 24
Peak memory 199984 kb
Host smart-9ec6ba3b-e36e-41a0-9084-281e859ffb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565006290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.2565006290
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.1210061138
Short name T758
Test name
Test status
Simulation time 41022112805 ps
CPU time 26.02 seconds
Started Jul 30 07:38:07 PM PDT 24
Finished Jul 30 07:38:33 PM PDT 24
Peak memory 199896 kb
Host smart-fe8d0d45-a7b7-42e9-9251-4e0ea0c9dabc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210061138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.1210061138
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.942958280
Short name T224
Test name
Test status
Simulation time 38998135183 ps
CPU time 42.92 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:41:46 PM PDT 24
Peak memory 199952 kb
Host smart-81770673-9e0f-473c-9fca-581361eaa66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942958280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.942958280
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.1182220629
Short name T216
Test name
Test status
Simulation time 66058417661 ps
CPU time 50.46 seconds
Started Jul 30 07:36:25 PM PDT 24
Finished Jul 30 07:37:15 PM PDT 24
Peak memory 199872 kb
Host smart-49bff5be-c82d-471c-8804-d55d51fef98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182220629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.1182220629
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_smoke.3679053922
Short name T392
Test name
Test status
Simulation time 663179239 ps
CPU time 3.18 seconds
Started Jul 30 07:36:25 PM PDT 24
Finished Jul 30 07:36:29 PM PDT 24
Peak memory 198948 kb
Host smart-a6b6416a-100b-4e92-8daa-b827e28ca623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679053922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3679053922
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.1201678452
Short name T226
Test name
Test status
Simulation time 9915553014 ps
CPU time 30.44 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:42:33 PM PDT 24
Peak memory 199940 kb
Host smart-8aca4321-35f9-42b0-9f2b-68bd2bc82864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201678452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.1201678452
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.897266082
Short name T239
Test name
Test status
Simulation time 40001849201 ps
CPU time 17.76 seconds
Started Jul 30 07:41:55 PM PDT 24
Finished Jul 30 07:42:13 PM PDT 24
Peak memory 199860 kb
Host smart-823f2d11-1926-4a82-875b-cf78121a16b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897266082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.897266082
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2355817054
Short name T223
Test name
Test status
Simulation time 134135287188 ps
CPU time 226.01 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:45:46 PM PDT 24
Peak memory 199972 kb
Host smart-d9492599-7dd8-4b82-9ea2-212bda7da939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355817054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2355817054
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3439628015
Short name T218
Test name
Test status
Simulation time 26194628219 ps
CPU time 40.58 seconds
Started Jul 30 07:42:01 PM PDT 24
Finished Jul 30 07:42:42 PM PDT 24
Peak memory 199964 kb
Host smart-e5a18d89-9993-4035-8b26-33093ae995ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439628015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3439628015
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.1839305023
Short name T229
Test name
Test status
Simulation time 75133184346 ps
CPU time 71.84 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:43:14 PM PDT 24
Peak memory 200000 kb
Host smart-83e36135-973b-4cc6-af63-521ca35f4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839305023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.1839305023
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3952874484
Short name T248
Test name
Test status
Simulation time 79881184532 ps
CPU time 29.53 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:33 PM PDT 24
Peak memory 199956 kb
Host smart-aebb8658-2605-49f7-81c2-ed1bfc236faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952874484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3952874484
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.213916155
Short name T198
Test name
Test status
Simulation time 37861867243 ps
CPU time 27.73 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:31 PM PDT 24
Peak memory 199932 kb
Host smart-582639a6-9f62-48d6-89f3-25c0c02c2558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213916155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.213916155
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.2485297676
Short name T233
Test name
Test status
Simulation time 48810167568 ps
CPU time 67.46 seconds
Started Jul 30 07:42:07 PM PDT 24
Finished Jul 30 07:43:14 PM PDT 24
Peak memory 199972 kb
Host smart-2678f358-af51-489a-bc11-e02e3c9067f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485297676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.2485297676
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.133026179
Short name T188
Test name
Test status
Simulation time 20523707359 ps
CPU time 14.85 seconds
Started Jul 30 07:42:06 PM PDT 24
Finished Jul 30 07:42:22 PM PDT 24
Peak memory 199308 kb
Host smart-2278da95-4cdb-4d12-8e1b-4ddeb01f3604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133026179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.133026179
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.407297429
Short name T203
Test name
Test status
Simulation time 88551206050 ps
CPU time 36.99 seconds
Started Jul 30 07:42:18 PM PDT 24
Finished Jul 30 07:42:55 PM PDT 24
Peak memory 198972 kb
Host smart-08bc4bbc-ec39-42aa-a4ef-a3ca8e248271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407297429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.407297429
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.2380704120
Short name T250
Test name
Test status
Simulation time 73695806066 ps
CPU time 409.43 seconds
Started Jul 30 07:37:44 PM PDT 24
Finished Jul 30 07:44:34 PM PDT 24
Peak memory 199856 kb
Host smart-355fb0c0-1eb0-4a07-bab6-9c56deb42c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380704120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.2380704120
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.371970096
Short name T147
Test name
Test status
Simulation time 23736440961 ps
CPU time 43.07 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:43:22 PM PDT 24
Peak memory 199912 kb
Host smart-b9993841-279b-4cc9-b55d-e311ffa5db93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371970096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.371970096
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2473611547
Short name T109
Test name
Test status
Simulation time 25189388530 ps
CPU time 42.81 seconds
Started Jul 30 07:42:52 PM PDT 24
Finished Jul 30 07:43:35 PM PDT 24
Peak memory 199924 kb
Host smart-9e433208-7afb-4983-9605-b63d74dd82e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473611547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2473611547
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.2363267326
Short name T155
Test name
Test status
Simulation time 243438701155 ps
CPU time 22.19 seconds
Started Jul 30 07:43:03 PM PDT 24
Finished Jul 30 07:43:25 PM PDT 24
Peak memory 199924 kb
Host smart-475ff3ed-32ce-4bc3-b425-00d6ec7771d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363267326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.2363267326
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.2735787640
Short name T221
Test name
Test status
Simulation time 45319235517 ps
CPU time 48.79 seconds
Started Jul 30 07:43:06 PM PDT 24
Finished Jul 30 07:43:55 PM PDT 24
Peak memory 200008 kb
Host smart-db6888a5-5e83-4601-aad8-b8ae2b2fe477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735787640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.2735787640
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.1741186832
Short name T192
Test name
Test status
Simulation time 46789493223 ps
CPU time 67.28 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:44:19 PM PDT 24
Peak memory 199900 kb
Host smart-45483898-74c2-46df-ab04-7779692c5aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741186832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.1741186832
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.2737267488
Short name T245
Test name
Test status
Simulation time 85602876629 ps
CPU time 45.49 seconds
Started Jul 30 07:43:15 PM PDT 24
Finished Jul 30 07:44:01 PM PDT 24
Peak memory 199876 kb
Host smart-f13e0e0b-485f-4e05-be7b-51d613339cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737267488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2737267488
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.95586761
Short name T227
Test name
Test status
Simulation time 28052772910 ps
CPU time 22.16 seconds
Started Jul 30 07:41:04 PM PDT 24
Finished Jul 30 07:41:26 PM PDT 24
Peak memory 199868 kb
Host smart-029c5bde-8770-4829-b185-64a9580c9eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95586761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.95586761
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2920644089
Short name T247
Test name
Test status
Simulation time 194822804273 ps
CPU time 1391.19 seconds
Started Jul 30 07:41:21 PM PDT 24
Finished Jul 30 08:04:32 PM PDT 24
Peak memory 224804 kb
Host smart-719895b0-b03c-4a4f-acd9-2ba0e8559825
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920644089 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2920644089
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3002665847
Short name T1269
Test name
Test status
Simulation time 74357690 ps
CPU time 0.7 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 195216 kb
Host smart-b0d53378-3a0f-4068-9afd-65db8c43cde4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002665847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3002665847
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3747798873
Short name T1276
Test name
Test status
Simulation time 747320015 ps
CPU time 1.52 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 198248 kb
Host smart-cc6e0fb5-1adc-4a99-b406-ab294978c952
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747798873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3747798873
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3544072269
Short name T1197
Test name
Test status
Simulation time 180004575 ps
CPU time 0.58 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 195720 kb
Host smart-8fe6702d-88e9-44bb-adfd-ce282aacb480
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544072269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3544072269
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.3883246520
Short name T1208
Test name
Test status
Simulation time 68396750 ps
CPU time 0.78 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 198720 kb
Host smart-6f8224df-edbe-4eb5-aec2-0cbeb0f4f4f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883246520 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.3883246520
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1733216950
Short name T73
Test name
Test status
Simulation time 17554873 ps
CPU time 0.58 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 195896 kb
Host smart-93034e92-3d08-4841-9851-ac1c65b13152
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733216950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1733216950
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.2168324803
Short name T1245
Test name
Test status
Simulation time 28362711 ps
CPU time 0.55 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 194804 kb
Host smart-81ebecad-d8be-4343-a8a5-b56c01b98e20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168324803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.2168324803
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3499172703
Short name T1201
Test name
Test status
Simulation time 191793254 ps
CPU time 1.21 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 200408 kb
Host smart-62859039-ea9e-4595-86a0-3be26121b146
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499172703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3499172703
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1402994874
Short name T85
Test name
Test status
Simulation time 146801452 ps
CPU time 0.91 seconds
Started Jul 30 06:26:34 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 199212 kb
Host smart-e49fa49d-e184-461e-8824-5e44c28a51c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402994874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1402994874
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.951973053
Short name T74
Test name
Test status
Simulation time 50019648 ps
CPU time 0.77 seconds
Started Jul 30 06:26:35 PM PDT 24
Finished Jul 30 06:26:36 PM PDT 24
Peak memory 196768 kb
Host smart-3cadcc0a-48a7-408e-9911-01929dd2a98d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951973053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.951973053
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1280021749
Short name T1221
Test name
Test status
Simulation time 14651816 ps
CPU time 0.59 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 195852 kb
Host smart-a6deb0cf-99ee-4b1b-87c0-a7bd1eb17a22
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280021749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1280021749
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2753625240
Short name T1281
Test name
Test status
Simulation time 67795600 ps
CPU time 0.68 seconds
Started Jul 30 06:26:34 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 197908 kb
Host smart-8495a0b5-3958-406c-adc3-1ee9a5df5171
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753625240 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2753625240
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.1287670183
Short name T1263
Test name
Test status
Simulation time 15741193 ps
CPU time 0.57 seconds
Started Jul 30 06:26:35 PM PDT 24
Finished Jul 30 06:26:36 PM PDT 24
Peak memory 195832 kb
Host smart-1e8daf9b-7b76-45e9-8b8a-ff6fcf4d20a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287670183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.1287670183
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.3192644711
Short name T1182
Test name
Test status
Simulation time 40430974 ps
CPU time 0.62 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 194784 kb
Host smart-e3797ddc-64e5-4030-8ca2-8954cfdffb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192644711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3192644711
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.2231599683
Short name T1289
Test name
Test status
Simulation time 32314059 ps
CPU time 0.81 seconds
Started Jul 30 06:27:04 PM PDT 24
Finished Jul 30 06:27:05 PM PDT 24
Peak memory 196264 kb
Host smart-01d33c92-0799-4c9c-a33e-313c3987b35e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231599683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.2231599683
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2717101077
Short name T1247
Test name
Test status
Simulation time 35843181 ps
CPU time 1.76 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 200424 kb
Host smart-43e954ba-6413-4783-8e64-d3a063348ff9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717101077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2717101077
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.1554670964
Short name T1277
Test name
Test status
Simulation time 575749952 ps
CPU time 1.23 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 199896 kb
Host smart-02025019-2d14-4b79-af48-389b0a4fc798
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554670964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.1554670964
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4189631840
Short name T1240
Test name
Test status
Simulation time 17059016 ps
CPU time 0.76 seconds
Started Jul 30 06:27:10 PM PDT 24
Finished Jul 30 06:27:11 PM PDT 24
Peak memory 200192 kb
Host smart-f100d057-6685-4a1e-8f71-4c23f3b4ffb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189631840 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4189631840
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2745614995
Short name T1216
Test name
Test status
Simulation time 45381446 ps
CPU time 0.6 seconds
Started Jul 30 06:26:53 PM PDT 24
Finished Jul 30 06:26:54 PM PDT 24
Peak memory 195796 kb
Host smart-b33161f6-ce90-464c-9814-c3d79e7e004d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745614995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2745614995
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.1345343438
Short name T1231
Test name
Test status
Simulation time 38171896 ps
CPU time 0.57 seconds
Started Jul 30 06:26:58 PM PDT 24
Finished Jul 30 06:26:59 PM PDT 24
Peak memory 194796 kb
Host smart-136574b4-b33a-4db0-a2b4-0645d2638c73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345343438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.1345343438
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2692858722
Short name T79
Test name
Test status
Simulation time 68023382 ps
CPU time 0.66 seconds
Started Jul 30 06:27:04 PM PDT 24
Finished Jul 30 06:27:04 PM PDT 24
Peak memory 195912 kb
Host smart-3a2eb20f-de56-457d-bbc3-e14163402948
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692858722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2692858722
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3050286276
Short name T1181
Test name
Test status
Simulation time 270414609 ps
CPU time 1.69 seconds
Started Jul 30 06:26:50 PM PDT 24
Finished Jul 30 06:26:52 PM PDT 24
Peak memory 200464 kb
Host smart-3be4cf5b-603f-4987-b75b-eb4beb0955bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050286276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3050286276
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.4160714678
Short name T92
Test name
Test status
Simulation time 41412161 ps
CPU time 0.87 seconds
Started Jul 30 06:27:04 PM PDT 24
Finished Jul 30 06:27:05 PM PDT 24
Peak memory 199104 kb
Host smart-aeb1370d-6b1f-40f4-aa64-8fe6fa339dd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160714678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.4160714678
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2446224458
Short name T1218
Test name
Test status
Simulation time 79712578 ps
CPU time 0.67 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 198632 kb
Host smart-3ac57111-2cc6-45e4-995b-0a1c715c8e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446224458 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2446224458
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.1859530617
Short name T1312
Test name
Test status
Simulation time 43080404 ps
CPU time 0.58 seconds
Started Jul 30 06:27:05 PM PDT 24
Finished Jul 30 06:27:05 PM PDT 24
Peak memory 195768 kb
Host smart-212edd8e-3d25-4750-a545-ea29f37ebb32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859530617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1859530617
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2053272095
Short name T1290
Test name
Test status
Simulation time 13612632 ps
CPU time 0.56 seconds
Started Jul 30 06:26:51 PM PDT 24
Finished Jul 30 06:26:52 PM PDT 24
Peak memory 194756 kb
Host smart-8ed75a9c-e5dd-4fc7-a404-a8391129627f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053272095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2053272095
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.495773099
Short name T1292
Test name
Test status
Simulation time 57202199 ps
CPU time 0.75 seconds
Started Jul 30 06:27:00 PM PDT 24
Finished Jul 30 06:27:01 PM PDT 24
Peak memory 196440 kb
Host smart-4af09ce8-cc53-4f51-9e45-c2fa145cd086
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495773099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_csr
_outstanding.495773099
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.2099140999
Short name T1288
Test name
Test status
Simulation time 134815233 ps
CPU time 1.41 seconds
Started Jul 30 06:27:01 PM PDT 24
Finished Jul 30 06:27:02 PM PDT 24
Peak memory 200468 kb
Host smart-8aef21df-cc3a-4a90-ac81-eeb9559739f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099140999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2099140999
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1104280599
Short name T84
Test name
Test status
Simulation time 51515660 ps
CPU time 0.99 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 199408 kb
Host smart-2db899ff-5b9e-4331-9cab-3b22e5b86e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104280599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1104280599
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.981731813
Short name T1279
Test name
Test status
Simulation time 111139778 ps
CPU time 1.16 seconds
Started Jul 30 06:27:06 PM PDT 24
Finished Jul 30 06:27:07 PM PDT 24
Peak memory 200424 kb
Host smart-a8adcfa0-c69d-4561-91ee-d73d0f05f125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981731813 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.981731813
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.2397337742
Short name T72
Test name
Test status
Simulation time 36375983 ps
CPU time 0.61 seconds
Started Jul 30 06:27:03 PM PDT 24
Finished Jul 30 06:27:03 PM PDT 24
Peak memory 195872 kb
Host smart-60d90039-6052-4595-ba0a-c6282a247d34
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397337742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.2397337742
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.1794649647
Short name T1282
Test name
Test status
Simulation time 13977508 ps
CPU time 0.55 seconds
Started Jul 30 06:27:07 PM PDT 24
Finished Jul 30 06:27:08 PM PDT 24
Peak memory 194768 kb
Host smart-32fbb478-549f-474c-85c2-bec61c6c6778
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794649647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.1794649647
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3099000049
Short name T1260
Test name
Test status
Simulation time 99364594 ps
CPU time 0.69 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 196120 kb
Host smart-e40cddf6-56ab-4079-be3f-dfc4707ae0af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099000049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3099000049
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.3684500155
Short name T1298
Test name
Test status
Simulation time 65317997 ps
CPU time 1.47 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 200496 kb
Host smart-f481455f-1b22-4d7a-996f-d873f63cc739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684500155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.3684500155
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.333258819
Short name T1302
Test name
Test status
Simulation time 144119659 ps
CPU time 0.91 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 199364 kb
Host smart-2b308571-ebf4-433b-a8fe-e7e45daf8f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333258819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.333258819
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2272732054
Short name T1183
Test name
Test status
Simulation time 18421405 ps
CPU time 0.68 seconds
Started Jul 30 06:27:07 PM PDT 24
Finished Jul 30 06:27:08 PM PDT 24
Peak memory 198040 kb
Host smart-c1a1434a-6b77-4873-8c41-9f9f9f347b07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272732054 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2272732054
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.1582359810
Short name T1313
Test name
Test status
Simulation time 31771782 ps
CPU time 0.58 seconds
Started Jul 30 06:27:06 PM PDT 24
Finished Jul 30 06:27:07 PM PDT 24
Peak memory 195784 kb
Host smart-31f8b729-a069-4b27-bfb5-3d6e136da038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582359810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.1582359810
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3047117635
Short name T1300
Test name
Test status
Simulation time 67415493 ps
CPU time 0.57 seconds
Started Jul 30 06:26:56 PM PDT 24
Finished Jul 30 06:26:57 PM PDT 24
Peak memory 194784 kb
Host smart-8bab6623-361c-4b13-b48f-21a50aeafeff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047117635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3047117635
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3982571689
Short name T1236
Test name
Test status
Simulation time 211143439 ps
CPU time 0.63 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 196048 kb
Host smart-d5769ff2-ab58-4cb9-a5ab-9031b17384b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982571689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3982571689
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1733075501
Short name T1190
Test name
Test status
Simulation time 117409966 ps
CPU time 1.71 seconds
Started Jul 30 06:27:04 PM PDT 24
Finished Jul 30 06:27:06 PM PDT 24
Peak memory 200460 kb
Host smart-4f73b6c6-5c0e-4859-ac4b-df7325373ec8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733075501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1733075501
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.99197890
Short name T86
Test name
Test status
Simulation time 704136387 ps
CPU time 1.33 seconds
Started Jul 30 06:26:58 PM PDT 24
Finished Jul 30 06:27:00 PM PDT 24
Peak memory 199776 kb
Host smart-8efa09d5-d3ac-4b30-99f2-7c5fac30058c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99197890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.99197890
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.1322353007
Short name T1272
Test name
Test status
Simulation time 245731598 ps
CPU time 0.77 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 198432 kb
Host smart-67f2d9cf-39dc-4e4b-8da1-c7e088d3ee8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322353007 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.1322353007
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1584427702
Short name T1203
Test name
Test status
Simulation time 14705528 ps
CPU time 0.56 seconds
Started Jul 30 06:26:54 PM PDT 24
Finished Jul 30 06:26:55 PM PDT 24
Peak memory 195912 kb
Host smart-6e364387-a27e-4a94-a943-3cfd7e8cd858
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584427702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1584427702
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.4123496408
Short name T1202
Test name
Test status
Simulation time 41305392 ps
CPU time 0.56 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 194712 kb
Host smart-a4d64f1d-0948-498e-9d66-f0826a943c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123496408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.4123496408
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2812085089
Short name T1222
Test name
Test status
Simulation time 76429437 ps
CPU time 0.7 seconds
Started Jul 30 06:27:05 PM PDT 24
Finished Jul 30 06:27:06 PM PDT 24
Peak memory 194956 kb
Host smart-14d5d49b-b3a1-43c3-88ea-0bbf8f9ed597
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812085089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2812085089
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1477738482
Short name T1250
Test name
Test status
Simulation time 36498890 ps
CPU time 1.8 seconds
Started Jul 30 06:27:03 PM PDT 24
Finished Jul 30 06:27:05 PM PDT 24
Peak memory 200492 kb
Host smart-adcefaa3-1e67-4208-afd4-0eca67350ad7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477738482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1477738482
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3501671671
Short name T1256
Test name
Test status
Simulation time 72849293 ps
CPU time 1.25 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 199836 kb
Host smart-83e9130d-aa1a-4d72-9bd9-b4bd5a4389cb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501671671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3501671671
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.4101819219
Short name T1241
Test name
Test status
Simulation time 21048179 ps
CPU time 1.12 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 200476 kb
Host smart-680cafdb-1300-4946-b1c1-5339c38234ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101819219 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.4101819219
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2115033312
Short name T1296
Test name
Test status
Simulation time 24691452 ps
CPU time 0.58 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 195800 kb
Host smart-8cba8593-832b-4f3a-b54a-3736233b3dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115033312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2115033312
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3308034275
Short name T1220
Test name
Test status
Simulation time 20928007 ps
CPU time 0.58 seconds
Started Jul 30 06:27:01 PM PDT 24
Finished Jul 30 06:27:02 PM PDT 24
Peak memory 194784 kb
Host smart-7f06fd08-2376-48eb-a7c7-74e6b83b35d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308034275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3308034275
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4206871092
Short name T1226
Test name
Test status
Simulation time 24501182 ps
CPU time 0.75 seconds
Started Jul 30 06:26:59 PM PDT 24
Finished Jul 30 06:26:59 PM PDT 24
Peak memory 198300 kb
Host smart-7cd7aa8d-5ab8-4851-8ec0-e5987b571bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206871092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4206871092
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.1918383412
Short name T1274
Test name
Test status
Simulation time 366243431 ps
CPU time 1.91 seconds
Started Jul 30 06:27:02 PM PDT 24
Finished Jul 30 06:27:04 PM PDT 24
Peak memory 200444 kb
Host smart-e34b801a-dae0-41b5-9bcb-9f2ee60d08bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918383412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1918383412
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.3967828627
Short name T1261
Test name
Test status
Simulation time 55152786 ps
CPU time 0.95 seconds
Started Jul 30 06:27:06 PM PDT 24
Finished Jul 30 06:27:07 PM PDT 24
Peak memory 199060 kb
Host smart-04bca6ae-89ef-4e89-b321-bd8e37de5126
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967828627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.3967828627
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.983816157
Short name T1284
Test name
Test status
Simulation time 35247442 ps
CPU time 0.69 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 198716 kb
Host smart-547f27e0-7141-44ff-8c2d-ac21ab9728cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983816157 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.983816157
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2428719585
Short name T1212
Test name
Test status
Simulation time 25689018 ps
CPU time 0.62 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 196248 kb
Host smart-bf3517aa-6055-483c-9f0f-254b2be47a4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428719585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2428719585
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4007678360
Short name T1251
Test name
Test status
Simulation time 57995164 ps
CPU time 0.55 seconds
Started Jul 30 06:27:06 PM PDT 24
Finished Jul 30 06:27:07 PM PDT 24
Peak memory 194828 kb
Host smart-f179a575-a6f3-4f57-9eb9-cc4885f786eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007678360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4007678360
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1255147441
Short name T77
Test name
Test status
Simulation time 68668202 ps
CPU time 0.7 seconds
Started Jul 30 06:27:00 PM PDT 24
Finished Jul 30 06:27:01 PM PDT 24
Peak memory 197244 kb
Host smart-3c75dcf5-c840-48d4-a03c-ca86a4859cb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255147441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1255147441
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.3735959691
Short name T1294
Test name
Test status
Simulation time 1287793074 ps
CPU time 1.77 seconds
Started Jul 30 06:27:17 PM PDT 24
Finished Jul 30 06:27:19 PM PDT 24
Peak memory 200328 kb
Host smart-42ffcb50-bfe7-4d57-85ad-00ef7d9cf85c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735959691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.3735959691
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3257362701
Short name T87
Test name
Test status
Simulation time 41740149 ps
CPU time 0.99 seconds
Started Jul 30 06:27:13 PM PDT 24
Finished Jul 30 06:27:14 PM PDT 24
Peak memory 199192 kb
Host smart-c11c2abe-0dab-4c20-a1e2-18ff6d7bbc58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257362701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3257362701
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.484446165
Short name T1259
Test name
Test status
Simulation time 40608723 ps
CPU time 0.7 seconds
Started Jul 30 06:27:10 PM PDT 24
Finished Jul 30 06:27:11 PM PDT 24
Peak memory 198276 kb
Host smart-5f0260b9-3a75-4c91-b518-a98fde9e0d40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484446165 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.484446165
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.2032119495
Short name T60
Test name
Test status
Simulation time 10650466 ps
CPU time 0.58 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 195776 kb
Host smart-d595f029-0680-436d-ad6a-02d97d50b442
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032119495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.2032119495
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1084856886
Short name T1287
Test name
Test status
Simulation time 13270436 ps
CPU time 0.59 seconds
Started Jul 30 06:27:16 PM PDT 24
Finished Jul 30 06:27:17 PM PDT 24
Peak memory 194828 kb
Host smart-82433ec7-5afe-42a2-b2c0-fa829ef45c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084856886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1084856886
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.3564361790
Short name T1200
Test name
Test status
Simulation time 19278117 ps
CPU time 0.8 seconds
Started Jul 30 06:26:52 PM PDT 24
Finished Jul 30 06:26:53 PM PDT 24
Peak memory 196656 kb
Host smart-3be8aea8-ddb8-48bb-8b6f-3abb8b8150af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564361790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.3564361790
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.625054010
Short name T1196
Test name
Test status
Simulation time 56544013 ps
CPU time 1.42 seconds
Started Jul 30 06:27:10 PM PDT 24
Finished Jul 30 06:27:11 PM PDT 24
Peak memory 200544 kb
Host smart-96faaf7c-150c-4fcc-925c-b85f806d7228
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625054010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.625054010
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3648228889
Short name T1234
Test name
Test status
Simulation time 66660830 ps
CPU time 0.65 seconds
Started Jul 30 06:27:16 PM PDT 24
Finished Jul 30 06:27:17 PM PDT 24
Peak memory 198028 kb
Host smart-f7efe93e-9a2c-427e-9a69-82b71c83b78d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648228889 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3648228889
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3910209447
Short name T61
Test name
Test status
Simulation time 49394654 ps
CPU time 0.6 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 195792 kb
Host smart-a6c17066-e8ba-4bcd-bf77-ecf0224597f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910209447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3910209447
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.3402175180
Short name T1193
Test name
Test status
Simulation time 28589186 ps
CPU time 0.57 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 194780 kb
Host smart-7baa2a9b-7d32-4366-a727-532338a9c53c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402175180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.3402175180
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.1948544338
Short name T1215
Test name
Test status
Simulation time 60742931 ps
CPU time 0.65 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 195884 kb
Host smart-93bd963b-5b9b-43b2-8744-499f0f187b56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948544338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.1948544338
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.594174366
Short name T1273
Test name
Test status
Simulation time 259681467 ps
CPU time 1.49 seconds
Started Jul 30 06:27:22 PM PDT 24
Finished Jul 30 06:27:23 PM PDT 24
Peak memory 200484 kb
Host smart-54726122-4426-4eb5-9e7f-8ddca556c5a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594174366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.594174366
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1761983673
Short name T1295
Test name
Test status
Simulation time 90684851 ps
CPU time 1.38 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 199640 kb
Host smart-40d3d94d-eb84-45cd-a12b-075e829d62a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761983673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1761983673
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.3676870991
Short name T1283
Test name
Test status
Simulation time 18324297 ps
CPU time 0.87 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 200172 kb
Host smart-7e26cba2-6825-408a-974e-df2290903e3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676870991 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.3676870991
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.1871323394
Short name T54
Test name
Test status
Simulation time 41716262 ps
CPU time 0.58 seconds
Started Jul 30 06:27:15 PM PDT 24
Finished Jul 30 06:27:16 PM PDT 24
Peak memory 195792 kb
Host smart-02dff121-c0d0-465a-9e81-fd52b00fa97e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871323394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.1871323394
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.1601761872
Short name T1309
Test name
Test status
Simulation time 21464766 ps
CPU time 0.57 seconds
Started Jul 30 06:27:03 PM PDT 24
Finished Jul 30 06:27:03 PM PDT 24
Peak memory 194812 kb
Host smart-e176f752-453a-490d-a906-0c52d31b3430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601761872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.1601761872
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2646058011
Short name T1258
Test name
Test status
Simulation time 28665711 ps
CPU time 0.61 seconds
Started Jul 30 06:27:19 PM PDT 24
Finished Jul 30 06:27:19 PM PDT 24
Peak memory 194816 kb
Host smart-17cc09d9-af04-42e7-9e68-5bc1e404c0e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646058011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2646058011
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.3512730078
Short name T1209
Test name
Test status
Simulation time 341222864 ps
CPU time 2.24 seconds
Started Jul 30 06:27:06 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 200440 kb
Host smart-a1e93124-4440-4afe-88be-7fa31f172540
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512730078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3512730078
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1626625705
Short name T120
Test name
Test status
Simulation time 203019839 ps
CPU time 0.98 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 199616 kb
Host smart-01ef28f0-f37e-4ba4-b23d-ede14e2a6d65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626625705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1626625705
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3007230607
Short name T1187
Test name
Test status
Simulation time 71128337 ps
CPU time 0.64 seconds
Started Jul 30 06:26:40 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 195192 kb
Host smart-503b2094-b904-49aa-b94e-bd5f7860c3d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007230607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3007230607
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.1401079228
Short name T1206
Test name
Test status
Simulation time 36396570 ps
CPU time 1.41 seconds
Started Jul 30 06:26:45 PM PDT 24
Finished Jul 30 06:26:47 PM PDT 24
Peak memory 198092 kb
Host smart-bfd434f2-27f1-44ba-ac0a-dc51a5f0a7b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401079228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.1401079228
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1656700147
Short name T1185
Test name
Test status
Simulation time 13891239 ps
CPU time 0.59 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:44 PM PDT 24
Peak memory 195812 kb
Host smart-d52a617e-d937-439f-b80c-83c93fe61c89
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656700147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1656700147
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1259191197
Short name T1267
Test name
Test status
Simulation time 17267575 ps
CPU time 0.8 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:38 PM PDT 24
Peak memory 199200 kb
Host smart-b2228820-0910-467f-89e6-f662b814a933
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259191197 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1259191197
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4175104974
Short name T56
Test name
Test status
Simulation time 48264592 ps
CPU time 0.6 seconds
Started Jul 30 06:26:40 PM PDT 24
Finished Jul 30 06:26:41 PM PDT 24
Peak memory 195884 kb
Host smart-79c7b403-d893-460f-9969-bbd37831530d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175104974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4175104974
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.3743013019
Short name T1198
Test name
Test status
Simulation time 11281175 ps
CPU time 0.57 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 194840 kb
Host smart-4102686f-e921-4235-9571-63bab321e445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743013019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3743013019
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3722237209
Short name T1308
Test name
Test status
Simulation time 21520020 ps
CPU time 0.69 seconds
Started Jul 30 06:26:40 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 196372 kb
Host smart-d9127f4d-6ba1-4106-ba7f-51ca5469a420
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722237209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3722237209
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.561653090
Short name T1188
Test name
Test status
Simulation time 35815587 ps
CPU time 1.79 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 200440 kb
Host smart-88684b91-bcaf-481e-a344-35d8b1f7a294
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561653090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.561653090
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.2852110991
Short name T93
Test name
Test status
Simulation time 240551350 ps
CPU time 0.94 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 199236 kb
Host smart-83193fdc-51e2-477e-bd94-74b9875dab18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852110991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.2852110991
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1310923468
Short name T1189
Test name
Test status
Simulation time 14789461 ps
CPU time 0.55 seconds
Started Jul 30 06:27:13 PM PDT 24
Finished Jul 30 06:27:14 PM PDT 24
Peak memory 194780 kb
Host smart-eb21ae67-7024-4829-aa35-9dca9731275c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310923468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1310923468
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1275470383
Short name T1271
Test name
Test status
Simulation time 29169870 ps
CPU time 0.61 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 194756 kb
Host smart-e46a650c-81ce-4d5f-ad85-e0aeb0680d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275470383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1275470383
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.1010380169
Short name T1278
Test name
Test status
Simulation time 20542231 ps
CPU time 0.57 seconds
Started Jul 30 06:27:18 PM PDT 24
Finished Jul 30 06:27:18 PM PDT 24
Peak memory 194748 kb
Host smart-fd3ac3ec-4363-420c-b664-5a04dda61138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010380169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.1010380169
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3603955949
Short name T1257
Test name
Test status
Simulation time 17232549 ps
CPU time 0.58 seconds
Started Jul 30 06:27:16 PM PDT 24
Finished Jul 30 06:27:16 PM PDT 24
Peak memory 194736 kb
Host smart-f1521362-f359-49c0-a366-3ac19b0d7df2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603955949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3603955949
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2854592796
Short name T1213
Test name
Test status
Simulation time 38647968 ps
CPU time 0.58 seconds
Started Jul 30 06:27:19 PM PDT 24
Finished Jul 30 06:27:19 PM PDT 24
Peak memory 194756 kb
Host smart-1af4dae0-0256-4f81-9534-d880308b230a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854592796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2854592796
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2501921507
Short name T1291
Test name
Test status
Simulation time 14037323 ps
CPU time 0.56 seconds
Started Jul 30 06:27:13 PM PDT 24
Finished Jul 30 06:27:14 PM PDT 24
Peak memory 194724 kb
Host smart-276b27d1-fae6-4c8c-becc-2dbcaa4eeee1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501921507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2501921507
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1882705917
Short name T1253
Test name
Test status
Simulation time 51079018 ps
CPU time 0.61 seconds
Started Jul 30 06:27:18 PM PDT 24
Finished Jul 30 06:27:19 PM PDT 24
Peak memory 194796 kb
Host smart-ddb65e51-67d4-4e86-adf4-b94b81e5ed69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882705917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1882705917
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1748266124
Short name T1229
Test name
Test status
Simulation time 50857262 ps
CPU time 0.55 seconds
Started Jul 30 06:27:15 PM PDT 24
Finished Jul 30 06:27:16 PM PDT 24
Peak memory 194792 kb
Host smart-cfcc5e36-0f17-4d51-b011-9fca87fc1adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748266124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1748266124
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3038581654
Short name T1246
Test name
Test status
Simulation time 26086766 ps
CPU time 0.57 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 194748 kb
Host smart-8b2bc187-2dc4-4f8b-a879-f57d64fad1c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038581654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3038581654
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.2737594163
Short name T1239
Test name
Test status
Simulation time 30122548 ps
CPU time 0.57 seconds
Started Jul 30 06:27:23 PM PDT 24
Finished Jul 30 06:27:24 PM PDT 24
Peak memory 194820 kb
Host smart-ef561ec9-a041-44ce-8999-87f029d7199e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737594163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.2737594163
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.4021483715
Short name T1219
Test name
Test status
Simulation time 149871159 ps
CPU time 0.8 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 196752 kb
Host smart-574fc5bb-2835-4581-92d0-1e51b7d2918f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021483715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.4021483715
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.3698050301
Short name T55
Test name
Test status
Simulation time 66733947 ps
CPU time 1.43 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 197960 kb
Host smart-7196eb5b-d1f9-4190-b4cf-b72eff17e8f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698050301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.3698050301
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.527940748
Short name T1248
Test name
Test status
Simulation time 23312181 ps
CPU time 0.58 seconds
Started Jul 30 06:26:40 PM PDT 24
Finished Jul 30 06:26:41 PM PDT 24
Peak memory 195808 kb
Host smart-1794f54c-efb9-4f19-bc93-c0b3abcaff4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527940748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.527940748
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3135228331
Short name T1186
Test name
Test status
Simulation time 95866879 ps
CPU time 1.18 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 200480 kb
Host smart-9afee862-d228-44ea-82d3-c37983bd1683
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135228331 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3135228331
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3080277048
Short name T1304
Test name
Test status
Simulation time 40270872 ps
CPU time 0.64 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 195856 kb
Host smart-1c6f4f28-4350-4c65-9590-bfccd59ab06a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080277048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3080277048
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.519436519
Short name T1268
Test name
Test status
Simulation time 15204585 ps
CPU time 0.58 seconds
Started Jul 30 06:26:38 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 194784 kb
Host smart-d7bd6fa9-de5b-4f59-9622-7432985bc520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519436519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.519436519
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1746444000
Short name T1301
Test name
Test status
Simulation time 23005803 ps
CPU time 0.69 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 196208 kb
Host smart-bb43a029-1b0a-45d5-9ae2-12a92eeb948c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746444000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1746444000
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1494384371
Short name T1305
Test name
Test status
Simulation time 32228006 ps
CPU time 1.67 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:41 PM PDT 24
Peak memory 200508 kb
Host smart-0acc9325-04cb-45b4-b1a0-d44fb77f41b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494384371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1494384371
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.151358614
Short name T1306
Test name
Test status
Simulation time 68951242 ps
CPU time 0.93 seconds
Started Jul 30 06:26:38 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 199028 kb
Host smart-a62cefd5-b2ae-403a-99ed-2e4d4931c791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151358614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.151358614
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2853442809
Short name T1225
Test name
Test status
Simulation time 11826623 ps
CPU time 0.55 seconds
Started Jul 30 06:27:07 PM PDT 24
Finished Jul 30 06:27:08 PM PDT 24
Peak memory 194796 kb
Host smart-99fe748b-2609-43c8-8d46-e3bd7f32e932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853442809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2853442809
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.2954324374
Short name T1270
Test name
Test status
Simulation time 24637616 ps
CPU time 0.54 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 194788 kb
Host smart-6d117457-5ccb-4051-82db-4e6994fae1c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954324374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.2954324374
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.943067683
Short name T1244
Test name
Test status
Simulation time 16564251 ps
CPU time 0.58 seconds
Started Jul 30 06:27:24 PM PDT 24
Finished Jul 30 06:27:25 PM PDT 24
Peak memory 194812 kb
Host smart-f7f339d3-b056-4ee2-8bec-a61401e8266e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943067683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.943067683
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1296807025
Short name T1286
Test name
Test status
Simulation time 10877527 ps
CPU time 0.6 seconds
Started Jul 30 06:27:19 PM PDT 24
Finished Jul 30 06:27:20 PM PDT 24
Peak memory 194796 kb
Host smart-ab932ef0-377c-4d72-bc52-34838bff179b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296807025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1296807025
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.451615740
Short name T1195
Test name
Test status
Simulation time 39285780 ps
CPU time 0.57 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 194792 kb
Host smart-0f9eedee-b64f-4d7f-b66c-0d59a561751d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451615740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.451615740
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.3355736255
Short name T1192
Test name
Test status
Simulation time 24897681 ps
CPU time 0.57 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 194804 kb
Host smart-b866ce76-443a-4ae8-9981-a5791aab877a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355736255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3355736255
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.234801952
Short name T1265
Test name
Test status
Simulation time 51467400 ps
CPU time 0.57 seconds
Started Jul 30 06:27:05 PM PDT 24
Finished Jul 30 06:27:06 PM PDT 24
Peak memory 194772 kb
Host smart-a7f39390-b4ce-4afb-8094-994e7babda3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234801952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.234801952
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.1177104480
Short name T1275
Test name
Test status
Simulation time 46147428 ps
CPU time 0.57 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:13 PM PDT 24
Peak memory 194780 kb
Host smart-00a1a52a-3231-4d41-8a51-3c2a7a919d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177104480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.1177104480
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3464680015
Short name T1214
Test name
Test status
Simulation time 29655378 ps
CPU time 0.56 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 194788 kb
Host smart-6d924119-76bd-4924-9dff-66c424b32b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464680015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3464680015
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.1937457309
Short name T1285
Test name
Test status
Simulation time 37947972 ps
CPU time 0.54 seconds
Started Jul 30 06:27:04 PM PDT 24
Finished Jul 30 06:27:04 PM PDT 24
Peak memory 194728 kb
Host smart-78369751-72e7-4f73-a310-4cc1fc08866d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937457309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.1937457309
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.988693879
Short name T58
Test name
Test status
Simulation time 21528017 ps
CPU time 0.67 seconds
Started Jul 30 06:26:44 PM PDT 24
Finished Jul 30 06:26:45 PM PDT 24
Peak memory 195376 kb
Host smart-19f7b894-8e57-4e27-99b0-9c450f3173e4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988693879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.988693879
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.2919992019
Short name T1237
Test name
Test status
Simulation time 66139245 ps
CPU time 1.4 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:45 PM PDT 24
Peak memory 198076 kb
Host smart-4769aa5a-9c28-4fcd-a457-4b3b94487d95
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919992019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.2919992019
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3030392144
Short name T1228
Test name
Test status
Simulation time 58060448 ps
CPU time 0.59 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:44 PM PDT 24
Peak memory 195816 kb
Host smart-76ccba09-fb91-479f-9001-82efdc1627ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030392144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3030392144
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.669318539
Short name T1207
Test name
Test status
Simulation time 131025403 ps
CPU time 1.02 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:44 PM PDT 24
Peak memory 200200 kb
Host smart-84258a62-1688-44a7-8c92-befa416dde5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669318539 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.669318539
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.711534255
Short name T59
Test name
Test status
Simulation time 12060561 ps
CPU time 0.59 seconds
Started Jul 30 06:26:46 PM PDT 24
Finished Jul 30 06:26:46 PM PDT 24
Peak memory 195812 kb
Host smart-c0213b90-2131-4df6-ae8a-f5afb3e5ce70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711534255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.711534255
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.3221379302
Short name T1184
Test name
Test status
Simulation time 33908822 ps
CPU time 0.57 seconds
Started Jul 30 06:26:42 PM PDT 24
Finished Jul 30 06:26:43 PM PDT 24
Peak memory 194780 kb
Host smart-1b1c76f3-7f32-4c29-aa7b-479a88ca3a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221379302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.3221379302
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4095873373
Short name T1299
Test name
Test status
Simulation time 142940365 ps
CPU time 0.76 seconds
Started Jul 30 06:26:45 PM PDT 24
Finished Jul 30 06:26:46 PM PDT 24
Peak memory 196436 kb
Host smart-de7e465a-4810-4a4f-b8d9-e53c7562c912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095873373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4095873373
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.37120058
Short name T1235
Test name
Test status
Simulation time 371000870 ps
CPU time 1.7 seconds
Started Jul 30 06:26:40 PM PDT 24
Finished Jul 30 06:26:42 PM PDT 24
Peak memory 200444 kb
Host smart-93a70eac-9c54-47a1-a318-f78d12c8e84b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37120058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.37120058
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1494516109
Short name T91
Test name
Test status
Simulation time 94096665 ps
CPU time 0.97 seconds
Started Jul 30 06:26:38 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 199520 kb
Host smart-b3ebe975-2913-4bf7-82fb-f4cca3676e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494516109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1494516109
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2460694500
Short name T1249
Test name
Test status
Simulation time 45208157 ps
CPU time 0.61 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 194836 kb
Host smart-bb488696-c2d1-493b-a8b5-86beb5fb1a7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460694500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2460694500
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3722777568
Short name T1223
Test name
Test status
Simulation time 14921620 ps
CPU time 0.58 seconds
Started Jul 30 06:27:10 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 194828 kb
Host smart-e662ea56-fc06-4d90-8eeb-71c8ab8f408f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722777568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3722777568
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.2237007926
Short name T1297
Test name
Test status
Simulation time 35560923 ps
CPU time 0.57 seconds
Started Jul 30 06:27:13 PM PDT 24
Finished Jul 30 06:27:14 PM PDT 24
Peak memory 194824 kb
Host smart-d9fbe119-313b-4ee3-9761-bc54a8fd9639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237007926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.2237007926
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1373951302
Short name T1194
Test name
Test status
Simulation time 32018676 ps
CPU time 0.6 seconds
Started Jul 30 06:27:11 PM PDT 24
Finished Jul 30 06:27:12 PM PDT 24
Peak memory 194776 kb
Host smart-25236ba8-ba43-4449-bd95-910ddebdd6f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373951302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1373951302
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3584176202
Short name T1224
Test name
Test status
Simulation time 14918878 ps
CPU time 0.58 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 194804 kb
Host smart-35008291-126c-4ddb-9372-e4c6ac68f343
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584176202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3584176202
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.1216289796
Short name T1255
Test name
Test status
Simulation time 39040888 ps
CPU time 0.57 seconds
Started Jul 30 06:27:08 PM PDT 24
Finished Jul 30 06:27:09 PM PDT 24
Peak memory 194792 kb
Host smart-86147a81-e0d2-4bc6-aabd-41b6cab09d96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216289796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1216289796
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1806545753
Short name T1242
Test name
Test status
Simulation time 10627210 ps
CPU time 0.55 seconds
Started Jul 30 06:27:09 PM PDT 24
Finished Jul 30 06:27:10 PM PDT 24
Peak memory 194788 kb
Host smart-0b87b42b-fd6a-4509-86ee-4abea15720e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806545753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1806545753
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.630464639
Short name T1233
Test name
Test status
Simulation time 22453431 ps
CPU time 0.57 seconds
Started Jul 30 06:27:14 PM PDT 24
Finished Jul 30 06:27:15 PM PDT 24
Peak memory 194788 kb
Host smart-5e5439f4-bc3d-40f2-a3a7-d5aca316b191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630464639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.630464639
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.3919953162
Short name T1191
Test name
Test status
Simulation time 50225298 ps
CPU time 0.55 seconds
Started Jul 30 06:27:16 PM PDT 24
Finished Jul 30 06:27:17 PM PDT 24
Peak memory 194784 kb
Host smart-6e786a7c-2404-4c29-b98c-03ebd70f4f8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919953162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.3919953162
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.952983842
Short name T1204
Test name
Test status
Simulation time 58370219 ps
CPU time 0.57 seconds
Started Jul 30 06:27:16 PM PDT 24
Finished Jul 30 06:27:17 PM PDT 24
Peak memory 194852 kb
Host smart-67e3a778-490e-4305-b04d-20a066ba33b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952983842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.952983842
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.882421403
Short name T1211
Test name
Test status
Simulation time 236832473 ps
CPU time 1.11 seconds
Started Jul 30 06:26:41 PM PDT 24
Finished Jul 30 06:26:42 PM PDT 24
Peak memory 200508 kb
Host smart-5a5d69f9-262d-491f-87d8-eda8904fd2bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882421403 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.882421403
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1220832960
Short name T1262
Test name
Test status
Simulation time 12701326 ps
CPU time 0.61 seconds
Started Jul 30 06:26:42 PM PDT 24
Finished Jul 30 06:26:43 PM PDT 24
Peak memory 195960 kb
Host smart-881f618b-6f29-4f40-a12d-36019eabc821
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220832960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1220832960
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.145830271
Short name T1266
Test name
Test status
Simulation time 12934673 ps
CPU time 0.57 seconds
Started Jul 30 06:26:42 PM PDT 24
Finished Jul 30 06:26:42 PM PDT 24
Peak memory 194684 kb
Host smart-0a8d461d-a1a9-4f43-b8f7-52a293da9276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145830271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.145830271
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.2083566107
Short name T81
Test name
Test status
Simulation time 37675095 ps
CPU time 0.72 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:43 PM PDT 24
Peak memory 197512 kb
Host smart-9565f6c5-dbb0-4269-9a74-44a6c6dc6a9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083566107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.2083566107
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.3250184556
Short name T1307
Test name
Test status
Simulation time 132021264 ps
CPU time 2.27 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:46 PM PDT 24
Peak memory 200460 kb
Host smart-6148dd31-bca7-4c7c-a767-922b1151ab30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250184556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.3250184556
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2034705726
Short name T1310
Test name
Test status
Simulation time 88250542 ps
CPU time 1.24 seconds
Started Jul 30 06:26:42 PM PDT 24
Finished Jul 30 06:26:43 PM PDT 24
Peak memory 199580 kb
Host smart-43672096-2ce9-496c-83dd-c75df337e883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034705726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2034705726
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.238244225
Short name T1254
Test name
Test status
Simulation time 21420548 ps
CPU time 0.68 seconds
Started Jul 30 06:26:50 PM PDT 24
Finished Jul 30 06:26:50 PM PDT 24
Peak memory 198660 kb
Host smart-1c36be98-d142-4024-902e-cdd4252f5fdc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238244225 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.238244225
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.1273005118
Short name T1252
Test name
Test status
Simulation time 36014517 ps
CPU time 0.59 seconds
Started Jul 30 06:26:55 PM PDT 24
Finished Jul 30 06:26:56 PM PDT 24
Peak memory 195832 kb
Host smart-f28c4583-f0d0-4c5e-9a13-b27dc9984346
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273005118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.1273005118
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.1645365436
Short name T1227
Test name
Test status
Simulation time 19828361 ps
CPU time 0.56 seconds
Started Jul 30 06:26:54 PM PDT 24
Finished Jul 30 06:26:54 PM PDT 24
Peak memory 194828 kb
Host smart-396dc0b4-de67-4c0d-94eb-336f67dceb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645365436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.1645365436
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1326298587
Short name T78
Test name
Test status
Simulation time 15241600 ps
CPU time 0.65 seconds
Started Jul 30 06:26:46 PM PDT 24
Finished Jul 30 06:26:47 PM PDT 24
Peak memory 196352 kb
Host smart-31dbc746-0164-419c-b471-7c93938e6766
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326298587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1326298587
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1079736166
Short name T1303
Test name
Test status
Simulation time 169627794 ps
CPU time 2.23 seconds
Started Jul 30 06:26:43 PM PDT 24
Finished Jul 30 06:26:46 PM PDT 24
Peak memory 200360 kb
Host smart-4428d417-9ed6-45d6-b91a-5c7a6c7cc74e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079736166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1079736166
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.777363261
Short name T90
Test name
Test status
Simulation time 45587634 ps
CPU time 0.9 seconds
Started Jul 30 06:26:47 PM PDT 24
Finished Jul 30 06:26:49 PM PDT 24
Peak memory 199384 kb
Host smart-5c259a8b-9ced-4401-b28d-0a55ca82a459
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777363261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.777363261
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.2245732475
Short name T1232
Test name
Test status
Simulation time 39594131 ps
CPU time 0.74 seconds
Started Jul 30 06:26:50 PM PDT 24
Finished Jul 30 06:26:51 PM PDT 24
Peak memory 198644 kb
Host smart-e0f82c22-d13d-4cb1-b1f4-648b949ce8c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245732475 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.2245732475
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.3025077557
Short name T1264
Test name
Test status
Simulation time 21361514 ps
CPU time 0.64 seconds
Started Jul 30 06:26:50 PM PDT 24
Finished Jul 30 06:26:51 PM PDT 24
Peak memory 195880 kb
Host smart-475855a2-9ef6-4fa2-9a5c-71ba2ae0cada
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025077557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.3025077557
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1154561899
Short name T1238
Test name
Test status
Simulation time 14498922 ps
CPU time 0.58 seconds
Started Jul 30 06:27:03 PM PDT 24
Finished Jul 30 06:27:04 PM PDT 24
Peak memory 194852 kb
Host smart-a259b85a-8e54-4a35-89d7-70969fa35e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154561899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1154561899
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2084220572
Short name T76
Test name
Test status
Simulation time 37586986 ps
CPU time 0.66 seconds
Started Jul 30 06:26:46 PM PDT 24
Finished Jul 30 06:26:47 PM PDT 24
Peak memory 196024 kb
Host smart-883cf894-4353-45e9-bea4-12d774440363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084220572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2084220572
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.473727681
Short name T1280
Test name
Test status
Simulation time 59564681 ps
CPU time 1.42 seconds
Started Jul 30 06:26:53 PM PDT 24
Finished Jul 30 06:26:55 PM PDT 24
Peak memory 200448 kb
Host smart-4f934457-5994-4730-810c-265a5d72d521
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473727681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.473727681
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.691278621
Short name T119
Test name
Test status
Simulation time 86235259 ps
CPU time 1.29 seconds
Started Jul 30 06:26:53 PM PDT 24
Finished Jul 30 06:26:54 PM PDT 24
Peak memory 199808 kb
Host smart-c2c33f77-5eb6-45af-8f11-3a3ed08491f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691278621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.691278621
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3775966971
Short name T1230
Test name
Test status
Simulation time 33356212 ps
CPU time 0.93 seconds
Started Jul 30 06:26:50 PM PDT 24
Finished Jul 30 06:26:51 PM PDT 24
Peak memory 200292 kb
Host smart-00c5f0b3-1e0f-428e-9ea9-97f5f0479e8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775966971 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3775966971
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1396542239
Short name T83
Test name
Test status
Simulation time 34404541 ps
CPU time 0.62 seconds
Started Jul 30 06:26:48 PM PDT 24
Finished Jul 30 06:26:48 PM PDT 24
Peak memory 195856 kb
Host smart-ca41e93d-1070-4439-b583-ba06167bb7b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396542239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1396542239
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.400110972
Short name T1217
Test name
Test status
Simulation time 19935691 ps
CPU time 0.57 seconds
Started Jul 30 06:26:46 PM PDT 24
Finished Jul 30 06:26:47 PM PDT 24
Peak memory 194728 kb
Host smart-85f440f7-c618-4108-8ad5-e5403c5baa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400110972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.400110972
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.2577175717
Short name T1210
Test name
Test status
Simulation time 90778029 ps
CPU time 0.67 seconds
Started Jul 30 06:26:57 PM PDT 24
Finished Jul 30 06:26:58 PM PDT 24
Peak memory 196244 kb
Host smart-00c03a30-be2d-49e1-ad24-6ed8ef2549e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577175717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.2577175717
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.786236062
Short name T1199
Test name
Test status
Simulation time 37751253 ps
CPU time 1.94 seconds
Started Jul 30 06:26:46 PM PDT 24
Finished Jul 30 06:26:48 PM PDT 24
Peak memory 200468 kb
Host smart-e3b9d5ff-05e8-4f03-8fa2-75bb81ca3a41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786236062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.786236062
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.2922007372
Short name T1205
Test name
Test status
Simulation time 37119742 ps
CPU time 0.91 seconds
Started Jul 30 06:26:49 PM PDT 24
Finished Jul 30 06:26:50 PM PDT 24
Peak memory 200204 kb
Host smart-8bc6fc3a-728a-41ff-8bb8-ad47f46b1902
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922007372 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.2922007372
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.475659930
Short name T82
Test name
Test status
Simulation time 78316414 ps
CPU time 0.59 seconds
Started Jul 30 06:26:49 PM PDT 24
Finished Jul 30 06:26:50 PM PDT 24
Peak memory 196208 kb
Host smart-851c9fa9-9f41-480a-9e44-0c5bda78bc71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475659930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.475659930
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1639763067
Short name T1243
Test name
Test status
Simulation time 16207069 ps
CPU time 0.56 seconds
Started Jul 30 06:26:48 PM PDT 24
Finished Jul 30 06:26:48 PM PDT 24
Peak memory 194828 kb
Host smart-c4740074-4dff-4599-9f91-187b69609a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639763067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1639763067
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3261110688
Short name T75
Test name
Test status
Simulation time 199425988 ps
CPU time 0.65 seconds
Started Jul 30 06:26:48 PM PDT 24
Finished Jul 30 06:26:49 PM PDT 24
Peak memory 196016 kb
Host smart-cb649d8f-f6f7-40ff-b1f8-ac06c4be9dea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261110688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.3261110688
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1423870336
Short name T1293
Test name
Test status
Simulation time 234670729 ps
CPU time 2.16 seconds
Started Jul 30 06:27:03 PM PDT 24
Finished Jul 30 06:27:05 PM PDT 24
Peak memory 200448 kb
Host smart-566e7670-0322-4ff0-b8ee-09edf48bef5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423870336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1423870336
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4243623639
Short name T1311
Test name
Test status
Simulation time 83980104 ps
CPU time 0.99 seconds
Started Jul 30 06:27:12 PM PDT 24
Finished Jul 30 06:27:14 PM PDT 24
Peak memory 199368 kb
Host smart-d6b9a031-10a6-4f52-a341-de55a45bf85d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243623639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4243623639
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.1732150815
Short name T449
Test name
Test status
Simulation time 48207574 ps
CPU time 0.56 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:36:31 PM PDT 24
Peak memory 195620 kb
Host smart-7fbcb92a-7106-4a81-867d-3a74911c3958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732150815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.1732150815
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3318540958
Short name T145
Test name
Test status
Simulation time 22134502239 ps
CPU time 7.49 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:36:33 PM PDT 24
Peak memory 199912 kb
Host smart-5d670409-31e8-4a5f-b95c-e56407b5cf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318540958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3318540958
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3245096510
Short name T718
Test name
Test status
Simulation time 140972678249 ps
CPU time 60.48 seconds
Started Jul 30 07:36:25 PM PDT 24
Finished Jul 30 07:37:26 PM PDT 24
Peak memory 199888 kb
Host smart-29668d5d-6de7-48f4-8955-011df146f006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245096510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3245096510
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.1692084720
Short name T1038
Test name
Test status
Simulation time 5966775802 ps
CPU time 4.89 seconds
Started Jul 30 07:36:29 PM PDT 24
Finished Jul 30 07:36:34 PM PDT 24
Peak memory 196216 kb
Host smart-9f0b9040-64b2-414b-a057-abd916807b45
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692084720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1692084720
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.138910177
Short name T37
Test name
Test status
Simulation time 84465306622 ps
CPU time 837.09 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:50:24 PM PDT 24
Peak memory 199952 kb
Host smart-c0b98ee9-6c4d-4661-b836-bae1e72d0199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138910177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.138910177
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1080893480
Short name T1001
Test name
Test status
Simulation time 8484301974 ps
CPU time 9.48 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 200052 kb
Host smart-023d1428-5dd9-4070-89e6-4ce506ccbbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080893480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1080893480
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.4156727498
Short name T337
Test name
Test status
Simulation time 10626744945 ps
CPU time 607.09 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:46:33 PM PDT 24
Peak memory 199944 kb
Host smart-c91582cf-9a92-4a95-8cc0-6abf58e0f22b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156727498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.4156727498
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.4223573097
Short name T686
Test name
Test status
Simulation time 2426386878 ps
CPU time 7.89 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:36:34 PM PDT 24
Peak memory 198160 kb
Host smart-8808c18c-508e-4dc2-91a9-652a688c7800
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4223573097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.4223573097
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2212177360
Short name T1095
Test name
Test status
Simulation time 64489772929 ps
CPU time 90.11 seconds
Started Jul 30 07:36:25 PM PDT 24
Finished Jul 30 07:37:55 PM PDT 24
Peak memory 199888 kb
Host smart-6d6de7a6-6c2d-4ef2-839c-bb929cf88fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212177360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2212177360
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.3019463481
Short name T1059
Test name
Test status
Simulation time 3216091858 ps
CPU time 1.94 seconds
Started Jul 30 07:36:26 PM PDT 24
Finished Jul 30 07:36:28 PM PDT 24
Peak memory 196128 kb
Host smart-101d1b85-3165-4853-baba-10ecd6c69de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019463481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3019463481
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_stress_all.1422200236
Short name T1179
Test name
Test status
Simulation time 68111631895 ps
CPU time 2033.94 seconds
Started Jul 30 07:36:29 PM PDT 24
Finished Jul 30 08:10:23 PM PDT 24
Peak memory 208288 kb
Host smart-cbc70a78-2112-46aa-8617-f9d2e1d21968
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422200236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1422200236
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.1648053109
Short name T118
Test name
Test status
Simulation time 59607608491 ps
CPU time 336.57 seconds
Started Jul 30 07:36:28 PM PDT 24
Finished Jul 30 07:42:05 PM PDT 24
Peak memory 216080 kb
Host smart-c01999f6-b410-4e20-a162-71571c7a663d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648053109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.1648053109
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1632784544
Short name T19
Test name
Test status
Simulation time 1316043761 ps
CPU time 1.66 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:36:32 PM PDT 24
Peak memory 199888 kb
Host smart-ab371334-392d-4a18-8ede-4b8e3501b2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632784544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1632784544
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.3007488581
Short name T915
Test name
Test status
Simulation time 111372647319 ps
CPU time 37.45 seconds
Started Jul 30 07:36:23 PM PDT 24
Finished Jul 30 07:37:01 PM PDT 24
Peak memory 199996 kb
Host smart-4df1207b-a7e8-42c1-a3f6-3ac4b31f4812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007488581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3007488581
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4022876772
Short name T1040
Test name
Test status
Simulation time 32494403 ps
CPU time 0.56 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:36:38 PM PDT 24
Peak memory 195336 kb
Host smart-68f0ce00-8a12-4d57-a7c8-cf84eec478aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022876772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4022876772
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.1376109099
Short name T833
Test name
Test status
Simulation time 41162974998 ps
CPU time 14.04 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:36:45 PM PDT 24
Peak memory 199972 kb
Host smart-ac7eec53-30c3-4266-aa1e-4f562b9202df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376109099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.1376109099
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.2862601774
Short name T1140
Test name
Test status
Simulation time 18726502693 ps
CPU time 27.47 seconds
Started Jul 30 07:36:32 PM PDT 24
Finished Jul 30 07:37:00 PM PDT 24
Peak memory 199284 kb
Host smart-7d839eee-1680-475b-9d46-96e90cdf5af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862601774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.2862601774
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.3288048917
Short name T190
Test name
Test status
Simulation time 64807061770 ps
CPU time 82.09 seconds
Started Jul 30 07:36:32 PM PDT 24
Finished Jul 30 07:37:54 PM PDT 24
Peak memory 199764 kb
Host smart-313077d4-9ae1-4626-844f-74ed9e29ad03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288048917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.3288048917
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.362258613
Short name T474
Test name
Test status
Simulation time 55274969441 ps
CPU time 55.04 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:37:28 PM PDT 24
Peak memory 199536 kb
Host smart-6ddabb77-1c3b-467e-91c6-a71d8a8cba68
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362258613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.362258613
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1359457554
Short name T383
Test name
Test status
Simulation time 86823879511 ps
CPU time 650.6 seconds
Started Jul 30 07:36:29 PM PDT 24
Finished Jul 30 07:47:20 PM PDT 24
Peak memory 199868 kb
Host smart-823ea116-363f-4066-902e-8e4f02e4b336
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1359457554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1359457554
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.293331053
Short name T461
Test name
Test status
Simulation time 1162371761 ps
CPU time 3.23 seconds
Started Jul 30 07:36:32 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 198600 kb
Host smart-7d6db4f7-1e56-416a-998f-252023b3a638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293331053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.293331053
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.3930161165
Short name T529
Test name
Test status
Simulation time 273160054173 ps
CPU time 45.8 seconds
Started Jul 30 07:36:32 PM PDT 24
Finished Jul 30 07:37:18 PM PDT 24
Peak memory 200080 kb
Host smart-410de8a6-2c81-4d2b-9eee-e02a63b142c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930161165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3930161165
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2317474093
Short name T924
Test name
Test status
Simulation time 12225904374 ps
CPU time 561.79 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:45:52 PM PDT 24
Peak memory 199940 kb
Host smart-c0c5216f-3157-4a7b-a0d0-56d437376e9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317474093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2317474093
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2776903275
Short name T341
Test name
Test status
Simulation time 6130115608 ps
CPU time 57.49 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:37:28 PM PDT 24
Peak memory 198124 kb
Host smart-b88c6e62-d5b0-4884-a922-9d28a4c9efcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2776903275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2776903275
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2631478626
Short name T558
Test name
Test status
Simulation time 122037760219 ps
CPU time 165.71 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:39:19 PM PDT 24
Peak memory 199992 kb
Host smart-5df905c7-04e4-4647-9cb7-a105b325c7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631478626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2631478626
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.2321424136
Short name T650
Test name
Test status
Simulation time 4766215464 ps
CPU time 7.49 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:36:41 PM PDT 24
Peak memory 196276 kb
Host smart-fe8f931a-87fc-4b93-870c-e16df8108ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321424136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.2321424136
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1565465055
Short name T12
Test name
Test status
Simulation time 141643053 ps
CPU time 0.82 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 218416 kb
Host smart-46e48445-de99-496d-895a-2592c1110bfc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565465055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1565465055
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.6450706
Short name T919
Test name
Test status
Simulation time 5465257835 ps
CPU time 12.47 seconds
Started Jul 30 07:36:29 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 199956 kb
Host smart-803f02b6-5478-41c7-b79d-2cdfa6bf2fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6450706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.6450706
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.3392461627
Short name T864
Test name
Test status
Simulation time 87910317977 ps
CPU time 164.17 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:39:19 PM PDT 24
Peak memory 199900 kb
Host smart-4a9920ec-7b48-4656-8bed-5a193bdc2354
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392461627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.3392461627
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.1172797996
Short name T1153
Test name
Test status
Simulation time 142312731889 ps
CPU time 610.11 seconds
Started Jul 30 07:36:30 PM PDT 24
Finished Jul 30 07:46:40 PM PDT 24
Peak memory 216204 kb
Host smart-bb58fd24-f085-4a32-899b-c23ec6f2edd8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172797996 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.1172797996
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.4200896766
Short name T1090
Test name
Test status
Simulation time 1117360066 ps
CPU time 3.5 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:36:37 PM PDT 24
Peak memory 198924 kb
Host smart-d3cdec28-8bb2-4125-9f0f-01f08dedccb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200896766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.4200896766
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1830118623
Short name T974
Test name
Test status
Simulation time 10867669676 ps
CPU time 8.92 seconds
Started Jul 30 07:36:27 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 197160 kb
Host smart-ea4b87d5-ea1c-4449-a55b-50d500966bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830118623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1830118623
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.3241881058
Short name T613
Test name
Test status
Simulation time 41254051 ps
CPU time 0.56 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:36:56 PM PDT 24
Peak memory 195380 kb
Host smart-922b0625-8e2d-4a38-8f50-3f9a5fdbe67f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241881058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3241881058
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.1717443463
Short name T407
Test name
Test status
Simulation time 236990524689 ps
CPU time 96.05 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:38:33 PM PDT 24
Peak memory 199896 kb
Host smart-927372d6-66a5-4d6e-bd97-3476acc6b0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717443463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.1717443463
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.2015400329
Short name T330
Test name
Test status
Simulation time 47843439645 ps
CPU time 18.22 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:37:13 PM PDT 24
Peak memory 199944 kb
Host smart-db35c46e-531a-43e6-8868-0c3716902eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015400329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.2015400329
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.1072279696
Short name T684
Test name
Test status
Simulation time 50677876440 ps
CPU time 85.8 seconds
Started Jul 30 07:36:56 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 200000 kb
Host smart-36c2f760-014b-430c-b76b-a6791d4945de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072279696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.1072279696
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1149105746
Short name T705
Test name
Test status
Simulation time 35394927340 ps
CPU time 47.68 seconds
Started Jul 30 07:36:56 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 198488 kb
Host smart-471d2d76-08c7-48da-8b48-981ee8f501f6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149105746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1149105746
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.2906063562
Short name T261
Test name
Test status
Simulation time 106129850658 ps
CPU time 468.26 seconds
Started Jul 30 07:37:00 PM PDT 24
Finished Jul 30 07:44:48 PM PDT 24
Peak memory 199876 kb
Host smart-23d15c5f-5153-4a39-92da-c163334f50d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2906063562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2906063562
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2901854010
Short name T8
Test name
Test status
Simulation time 1278395776 ps
CPU time 1.61 seconds
Started Jul 30 07:36:58 PM PDT 24
Finished Jul 30 07:36:59 PM PDT 24
Peak memory 196316 kb
Host smart-7516466b-3a4f-400d-affc-84c2c4e59951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901854010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2901854010
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.296547693
Short name T271
Test name
Test status
Simulation time 23280459573 ps
CPU time 39.58 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:37:36 PM PDT 24
Peak memory 198556 kb
Host smart-491bafba-ab95-4b61-b61c-3e9365cbee6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296547693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.296547693
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2013944216
Short name T843
Test name
Test status
Simulation time 15385323910 ps
CPU time 236.7 seconds
Started Jul 30 07:36:59 PM PDT 24
Finished Jul 30 07:40:56 PM PDT 24
Peak memory 199892 kb
Host smart-0331c6cd-d0b7-4a2b-8575-31707d378da8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2013944216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2013944216
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.1815545562
Short name T1125
Test name
Test status
Simulation time 1802599864 ps
CPU time 8.34 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:37:04 PM PDT 24
Peak memory 197944 kb
Host smart-9d6a3a48-ea74-4692-8b83-fbc59787243b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815545562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1815545562
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1181100215
Short name T846
Test name
Test status
Simulation time 22554429501 ps
CPU time 19.15 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:37:16 PM PDT 24
Peak memory 199844 kb
Host smart-65bed23c-f29d-4705-99af-d8563d08bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181100215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1181100215
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.1954662284
Short name T356
Test name
Test status
Simulation time 40634358435 ps
CPU time 3.88 seconds
Started Jul 30 07:36:56 PM PDT 24
Finished Jul 30 07:37:00 PM PDT 24
Peak memory 196036 kb
Host smart-ea8b3695-15b6-4b53-a716-47b3c8e766cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954662284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.1954662284
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1682451356
Short name T1024
Test name
Test status
Simulation time 248471686 ps
CPU time 1.23 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:36:53 PM PDT 24
Peak memory 198388 kb
Host smart-6905b467-3dc3-4313-b372-3891163f115e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682451356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1682451356
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.928726863
Short name T447
Test name
Test status
Simulation time 293097984088 ps
CPU time 528.05 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:45:45 PM PDT 24
Peak memory 199968 kb
Host smart-c9d8afcc-9f8e-4469-8020-58691f97cfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928726863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.928726863
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1308887363
Short name T1124
Test name
Test status
Simulation time 139971215842 ps
CPU time 774.88 seconds
Started Jul 30 07:36:56 PM PDT 24
Finished Jul 30 07:49:51 PM PDT 24
Peak memory 216456 kb
Host smart-87d1dfc6-99bc-4413-b24f-9f30b893ec4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308887363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1308887363
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.1584313595
Short name T854
Test name
Test status
Simulation time 5063114367 ps
CPU time 1.68 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:36:59 PM PDT 24
Peak memory 199028 kb
Host smart-4ba42242-356f-47c7-92d0-61ca1bb3a003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584313595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.1584313595
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.1482950864
Short name T1105
Test name
Test status
Simulation time 6809250131 ps
CPU time 3.48 seconds
Started Jul 30 07:36:57 PM PDT 24
Finished Jul 30 07:37:01 PM PDT 24
Peak memory 199940 kb
Host smart-0adb74bb-06bf-4dbc-b752-4dc6e24016a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482950864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1482950864
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.2334754002
Short name T473
Test name
Test status
Simulation time 18571627875 ps
CPU time 26.67 seconds
Started Jul 30 07:41:32 PM PDT 24
Finished Jul 30 07:41:58 PM PDT 24
Peak memory 199696 kb
Host smart-01dd8d82-3cf0-423f-99ba-372c59c09bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334754002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.2334754002
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.4264769314
Short name T1098
Test name
Test status
Simulation time 24766759716 ps
CPU time 23.14 seconds
Started Jul 30 07:41:32 PM PDT 24
Finished Jul 30 07:41:55 PM PDT 24
Peak memory 199964 kb
Host smart-b712918f-a314-4878-82d9-71ab67d07b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264769314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.4264769314
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.3944294369
Short name T1036
Test name
Test status
Simulation time 327065280060 ps
CPU time 44.21 seconds
Started Jul 30 07:41:34 PM PDT 24
Finished Jul 30 07:42:18 PM PDT 24
Peak memory 199912 kb
Host smart-74a00049-b93c-4379-969b-dacf9dd0edae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944294369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3944294369
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.894206422
Short name T987
Test name
Test status
Simulation time 18277258358 ps
CPU time 17.23 seconds
Started Jul 30 07:41:35 PM PDT 24
Finished Jul 30 07:41:52 PM PDT 24
Peak memory 199992 kb
Host smart-bcd5ecf2-0ed1-4401-96c5-3bc5d9bf0f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894206422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.894206422
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.2455343493
Short name T1165
Test name
Test status
Simulation time 8407572207 ps
CPU time 22.75 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:42:03 PM PDT 24
Peak memory 200048 kb
Host smart-2a5d92c0-2691-4d69-8ae9-123a6c99bf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455343493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.2455343493
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2357734036
Short name T653
Test name
Test status
Simulation time 157313650397 ps
CPU time 73.98 seconds
Started Jul 30 07:41:41 PM PDT 24
Finished Jul 30 07:42:55 PM PDT 24
Peak memory 199984 kb
Host smart-a1a23734-3283-471e-8dcd-26299865eebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357734036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2357734036
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.2192757122
Short name T456
Test name
Test status
Simulation time 76390512795 ps
CPU time 40.83 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:42:21 PM PDT 24
Peak memory 199968 kb
Host smart-080498ff-9970-4a15-9b56-569b5b4dc47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192757122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2192757122
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2547793613
Short name T559
Test name
Test status
Simulation time 25151317638 ps
CPU time 38.77 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:42:19 PM PDT 24
Peak memory 199872 kb
Host smart-1225b3a1-df0c-4799-a115-24c2f6c07e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547793613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2547793613
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.2563828959
Short name T384
Test name
Test status
Simulation time 32045259 ps
CPU time 0.55 seconds
Started Jul 30 07:37:06 PM PDT 24
Finished Jul 30 07:37:06 PM PDT 24
Peak memory 195348 kb
Host smart-0883846b-561b-4bd6-a3f3-334d4c497afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563828959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.2563828959
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.1747987671
Short name T1111
Test name
Test status
Simulation time 105028890225 ps
CPU time 27.26 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:37:29 PM PDT 24
Peak memory 199972 kb
Host smart-cdfd5ed1-4c45-4d53-ad25-f3246a2a17ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747987671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1747987671
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3696303219
Short name T648
Test name
Test status
Simulation time 116830362445 ps
CPU time 152.5 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:39:34 PM PDT 24
Peak memory 199836 kb
Host smart-e9835034-8f75-4136-8745-caad8c81bd1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696303219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3696303219
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.2793571400
Short name T185
Test name
Test status
Simulation time 83098742750 ps
CPU time 57.72 seconds
Started Jul 30 07:36:59 PM PDT 24
Finished Jul 30 07:37:56 PM PDT 24
Peak memory 199980 kb
Host smart-f78b8b01-a7a4-40e6-917e-5e887cd074f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793571400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.2793571400
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.2485844350
Short name T1070
Test name
Test status
Simulation time 59623071944 ps
CPU time 48.28 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:37:50 PM PDT 24
Peak memory 198536 kb
Host smart-1a5b404e-b690-4a95-bd13-9d6690c89ebf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485844350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.2485844350
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.957429081
Short name T1071
Test name
Test status
Simulation time 123654098752 ps
CPU time 864.03 seconds
Started Jul 30 07:37:00 PM PDT 24
Finished Jul 30 07:51:24 PM PDT 24
Peak memory 199884 kb
Host smart-ccd15e5f-56c4-45dd-99f7-058a67505597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957429081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.957429081
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2905020836
Short name T593
Test name
Test status
Simulation time 8319335296 ps
CPU time 27.75 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:37:28 PM PDT 24
Peak memory 199868 kb
Host smart-323e2a7c-3f59-4a3e-9360-6b14f3edeace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905020836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2905020836
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.3666583369
Short name T708
Test name
Test status
Simulation time 122590219913 ps
CPU time 128.91 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:39:10 PM PDT 24
Peak memory 200140 kb
Host smart-dcaa979c-6597-45e7-adff-b9b9bb407e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666583369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.3666583369
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.2111634424
Short name T294
Test name
Test status
Simulation time 21215466687 ps
CPU time 1217.15 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:57:18 PM PDT 24
Peak memory 199976 kb
Host smart-d1486272-25f8-4902-a0a4-b288e0d1aa20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2111634424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.2111634424
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.1216632380
Short name T23
Test name
Test status
Simulation time 5145666354 ps
CPU time 11.87 seconds
Started Jul 30 07:37:00 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 198132 kb
Host smart-92dd60b9-4477-4484-8b12-0798ef142520
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216632380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.1216632380
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.4289538298
Short name T129
Test name
Test status
Simulation time 17578229311 ps
CPU time 14.29 seconds
Started Jul 30 07:36:59 PM PDT 24
Finished Jul 30 07:37:13 PM PDT 24
Peak memory 200024 kb
Host smart-d7e93b23-6da5-4cea-98e7-2b5227ca8aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289538298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.4289538298
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.2246040050
Short name T395
Test name
Test status
Simulation time 33947739356 ps
CPU time 25.82 seconds
Started Jul 30 07:36:58 PM PDT 24
Finished Jul 30 07:37:24 PM PDT 24
Peak memory 196796 kb
Host smart-d791538e-28d5-4992-84c8-5cbe7b4b456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246040050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.2246040050
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.2752116883
Short name T1086
Test name
Test status
Simulation time 560485404 ps
CPU time 1.87 seconds
Started Jul 30 07:37:01 PM PDT 24
Finished Jul 30 07:37:03 PM PDT 24
Peak memory 199848 kb
Host smart-c667c73e-d1f7-4dea-864f-e83140414b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752116883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.2752116883
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3692688778
Short name T818
Test name
Test status
Simulation time 150441069358 ps
CPU time 236.4 seconds
Started Jul 30 07:37:02 PM PDT 24
Finished Jul 30 07:40:58 PM PDT 24
Peak memory 200244 kb
Host smart-6ed45f97-c238-49c8-b690-5ba0f36def16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692688778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3692688778
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2477375364
Short name T975
Test name
Test status
Simulation time 37838572680 ps
CPU time 169.94 seconds
Started Jul 30 07:37:03 PM PDT 24
Finished Jul 30 07:39:53 PM PDT 24
Peak memory 215788 kb
Host smart-046bf6a7-7e74-4c9b-adc8-e489658ec67b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477375364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2477375364
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3727320679
Short name T710
Test name
Test status
Simulation time 1719829648 ps
CPU time 1.87 seconds
Started Jul 30 07:37:00 PM PDT 24
Finished Jul 30 07:37:02 PM PDT 24
Peak memory 198912 kb
Host smart-af0c5ecf-cf49-4fcd-9992-c1073e17759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727320679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3727320679
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.3172204331
Short name T1076
Test name
Test status
Simulation time 55165039900 ps
CPU time 41.19 seconds
Started Jul 30 07:36:59 PM PDT 24
Finished Jul 30 07:37:40 PM PDT 24
Peak memory 199936 kb
Host smart-944da421-f57a-4c40-a6ab-1f415b65c182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172204331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.3172204331
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.755759486
Short name T1002
Test name
Test status
Simulation time 35159083440 ps
CPU time 54.13 seconds
Started Jul 30 07:41:41 PM PDT 24
Finished Jul 30 07:42:35 PM PDT 24
Peak memory 199996 kb
Host smart-77802606-accf-4d3e-b8cf-abb3c525d74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755759486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.755759486
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.2170635123
Short name T124
Test name
Test status
Simulation time 96609272750 ps
CPU time 155.65 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:44:16 PM PDT 24
Peak memory 199944 kb
Host smart-651eee8f-fdb0-4bad-9dcb-7f58acec9046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170635123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2170635123
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2862005505
Short name T798
Test name
Test status
Simulation time 93497436194 ps
CPU time 96.27 seconds
Started Jul 30 07:41:40 PM PDT 24
Finished Jul 30 07:43:16 PM PDT 24
Peak memory 199936 kb
Host smart-10f9b07f-d0ab-400f-99e3-1dad844a896b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862005505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2862005505
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.456648672
Short name T1081
Test name
Test status
Simulation time 308467360684 ps
CPU time 55.3 seconds
Started Jul 30 07:41:41 PM PDT 24
Finished Jul 30 07:42:36 PM PDT 24
Peak memory 199876 kb
Host smart-5465320e-af48-4bb4-9d98-d9d252100210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456648672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.456648672
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.3329246754
Short name T1008
Test name
Test status
Simulation time 18493500729 ps
CPU time 27.21 seconds
Started Jul 30 07:41:45 PM PDT 24
Finished Jul 30 07:42:12 PM PDT 24
Peak memory 199888 kb
Host smart-4c3a6907-0de0-4957-9573-b3ad3af84ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329246754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3329246754
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3765069900
Short name T912
Test name
Test status
Simulation time 99336257913 ps
CPU time 100.87 seconds
Started Jul 30 07:41:46 PM PDT 24
Finished Jul 30 07:43:27 PM PDT 24
Peak memory 199912 kb
Host smart-9bf18871-e758-44f7-86d1-647a1fffc366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765069900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3765069900
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1055642747
Short name T125
Test name
Test status
Simulation time 84542900384 ps
CPU time 19.97 seconds
Started Jul 30 07:41:45 PM PDT 24
Finished Jul 30 07:42:05 PM PDT 24
Peak memory 199948 kb
Host smart-f33c8a74-ed77-439e-9ae2-7da436f20946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055642747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1055642747
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.426663726
Short name T563
Test name
Test status
Simulation time 138882933075 ps
CPU time 49.91 seconds
Started Jul 30 07:41:44 PM PDT 24
Finished Jul 30 07:42:34 PM PDT 24
Peak memory 199960 kb
Host smart-e647345b-e583-4109-abd6-7fdf2db69d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426663726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.426663726
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.2860364045
Short name T706
Test name
Test status
Simulation time 33276330304 ps
CPU time 34.14 seconds
Started Jul 30 07:41:45 PM PDT 24
Finished Jul 30 07:42:19 PM PDT 24
Peak memory 199740 kb
Host smart-c0815a58-f677-4a31-ae73-605589425918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860364045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2860364045
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4249684030
Short name T413
Test name
Test status
Simulation time 106596175 ps
CPU time 0.56 seconds
Started Jul 30 07:37:10 PM PDT 24
Finished Jul 30 07:37:10 PM PDT 24
Peak memory 194356 kb
Host smart-33f9ec9f-f071-44ec-a870-d4ad9eef8e6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249684030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4249684030
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.748184192
Short name T420
Test name
Test status
Simulation time 34953273697 ps
CPU time 29.88 seconds
Started Jul 30 07:37:05 PM PDT 24
Finished Jul 30 07:37:35 PM PDT 24
Peak memory 199896 kb
Host smart-ee6080c9-e90a-409c-b9bc-81051c2626fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748184192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.748184192
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.791459821
Short name T282
Test name
Test status
Simulation time 44420854250 ps
CPU time 41.42 seconds
Started Jul 30 07:37:05 PM PDT 24
Finished Jul 30 07:37:47 PM PDT 24
Peak memory 199948 kb
Host smart-1d626d36-031e-4e60-98ca-688ef902d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791459821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.791459821
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.4209393270
Short name T174
Test name
Test status
Simulation time 56156761124 ps
CPU time 42.34 seconds
Started Jul 30 07:37:09 PM PDT 24
Finished Jul 30 07:37:51 PM PDT 24
Peak memory 200000 kb
Host smart-342ca040-0f77-4b1f-a5e8-dc2607953733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209393270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.4209393270
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3141165835
Short name T1122
Test name
Test status
Simulation time 21603621678 ps
CPU time 24.97 seconds
Started Jul 30 07:37:04 PM PDT 24
Finished Jul 30 07:37:29 PM PDT 24
Peak memory 197648 kb
Host smart-9c0dd72c-93eb-481f-bc1c-e59b66246865
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141165835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3141165835
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.3362212810
Short name T562
Test name
Test status
Simulation time 199962556518 ps
CPU time 255.9 seconds
Started Jul 30 07:37:07 PM PDT 24
Finished Jul 30 07:41:23 PM PDT 24
Peak memory 199948 kb
Host smart-95101cfe-0a3f-4618-a6f6-7056fc1835cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362212810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3362212810
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4039451109
Short name T435
Test name
Test status
Simulation time 5256763552 ps
CPU time 3.19 seconds
Started Jul 30 07:37:04 PM PDT 24
Finished Jul 30 07:37:07 PM PDT 24
Peak memory 197820 kb
Host smart-4884db3c-a18c-47af-ac1a-e412d6d4aaf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039451109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4039451109
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.2194818519
Short name T914
Test name
Test status
Simulation time 13803042065 ps
CPU time 9.71 seconds
Started Jul 30 07:37:04 PM PDT 24
Finished Jul 30 07:37:14 PM PDT 24
Peak memory 198488 kb
Host smart-7abbc960-367a-4f18-9abd-ec57a71953e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194818519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.2194818519
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1923988507
Short name T1078
Test name
Test status
Simulation time 11420675670 ps
CPU time 736.14 seconds
Started Jul 30 07:37:06 PM PDT 24
Finished Jul 30 07:49:22 PM PDT 24
Peak memory 199952 kb
Host smart-3c867638-ca62-4ed4-915c-f5eba163a663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1923988507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1923988507
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3897309849
Short name T517
Test name
Test status
Simulation time 4223367390 ps
CPU time 35.19 seconds
Started Jul 30 07:37:04 PM PDT 24
Finished Jul 30 07:37:40 PM PDT 24
Peak memory 199952 kb
Host smart-d000dde4-1434-4691-a489-4b2f434282a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3897309849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3897309849
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2814955925
Short name T874
Test name
Test status
Simulation time 31300775562 ps
CPU time 31.88 seconds
Started Jul 30 07:37:05 PM PDT 24
Finished Jul 30 07:37:37 PM PDT 24
Peak memory 199956 kb
Host smart-fc11be2f-313f-4416-9976-cf23da1b424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814955925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2814955925
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.3684043472
Short name T735
Test name
Test status
Simulation time 6947734071 ps
CPU time 2.04 seconds
Started Jul 30 07:37:03 PM PDT 24
Finished Jul 30 07:37:05 PM PDT 24
Peak memory 196224 kb
Host smart-74ed9da9-aba6-4488-a0e7-923400699a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684043472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.3684043472
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.1096873236
Short name T475
Test name
Test status
Simulation time 850286396 ps
CPU time 2.98 seconds
Started Jul 30 07:37:09 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 198560 kb
Host smart-eece46ff-b310-40b6-b5b6-9496e7e8d426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096873236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.1096873236
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.1444407691
Short name T1100
Test name
Test status
Simulation time 128726371752 ps
CPU time 471.93 seconds
Started Jul 30 07:37:09 PM PDT 24
Finished Jul 30 07:45:01 PM PDT 24
Peak memory 224740 kb
Host smart-2cb1bbc4-5729-4253-8b53-1d0039cadf00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444407691 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.1444407691
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.651289190
Short name T414
Test name
Test status
Simulation time 7305295402 ps
CPU time 8.77 seconds
Started Jul 30 07:37:05 PM PDT 24
Finished Jul 30 07:37:14 PM PDT 24
Peak memory 199976 kb
Host smart-41c8efe4-4fce-4a86-9f9a-697e6b65cfde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651289190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.651289190
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2860149059
Short name T521
Test name
Test status
Simulation time 764557853 ps
CPU time 1.85 seconds
Started Jul 30 07:37:03 PM PDT 24
Finished Jul 30 07:37:05 PM PDT 24
Peak memory 197272 kb
Host smart-600c1982-7038-4502-9ef0-98e3f4df5e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860149059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2860149059
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.1455352081
Short name T232
Test name
Test status
Simulation time 198401047832 ps
CPU time 28.52 seconds
Started Jul 30 07:41:44 PM PDT 24
Finished Jul 30 07:42:13 PM PDT 24
Peak memory 200004 kb
Host smart-6ba4caa3-15af-46f8-bc7c-a3a167fa81b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455352081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.1455352081
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.4228371173
Short name T629
Test name
Test status
Simulation time 34219768133 ps
CPU time 57.2 seconds
Started Jul 30 07:41:44 PM PDT 24
Finished Jul 30 07:42:41 PM PDT 24
Peak memory 199912 kb
Host smart-7fb2eb51-cfd2-4c53-a940-f060c1e77285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228371173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.4228371173
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.3853949952
Short name T657
Test name
Test status
Simulation time 109977815010 ps
CPU time 146.34 seconds
Started Jul 30 07:41:46 PM PDT 24
Finished Jul 30 07:44:12 PM PDT 24
Peak memory 199916 kb
Host smart-2c81661c-9410-446c-9ada-cc2d602879dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853949952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.3853949952
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.2998384349
Short name T168
Test name
Test status
Simulation time 54850884167 ps
CPU time 23.02 seconds
Started Jul 30 07:41:48 PM PDT 24
Finished Jul 30 07:42:11 PM PDT 24
Peak memory 199964 kb
Host smart-6c8f6f19-620f-416b-8272-f4d05f91d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998384349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.2998384349
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.1402503783
Short name T598
Test name
Test status
Simulation time 71016275996 ps
CPU time 38.2 seconds
Started Jul 30 07:41:48 PM PDT 24
Finished Jul 30 07:42:26 PM PDT 24
Peak memory 199948 kb
Host smart-2dd5c43f-93bb-4e7a-970c-7d975de76cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402503783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.1402503783
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1552345214
Short name T196
Test name
Test status
Simulation time 73050977241 ps
CPU time 9.15 seconds
Started Jul 30 07:41:52 PM PDT 24
Finished Jul 30 07:42:01 PM PDT 24
Peak memory 199984 kb
Host smart-415cea69-3720-4324-80d6-2c8deafdff6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552345214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1552345214
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.41936792
Short name T283
Test name
Test status
Simulation time 68331772647 ps
CPU time 100.04 seconds
Started Jul 30 07:41:50 PM PDT 24
Finished Jul 30 07:43:31 PM PDT 24
Peak memory 199880 kb
Host smart-6e9cf633-f70e-4047-94ba-622708368fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41936792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.41936792
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.219072811
Short name T1062
Test name
Test status
Simulation time 44767326730 ps
CPU time 50.47 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 199940 kb
Host smart-c4d2f671-f1e2-4ade-95e9-fc462d96d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219072811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.219072811
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3003009302
Short name T936
Test name
Test status
Simulation time 26040255667 ps
CPU time 39.02 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:42 PM PDT 24
Peak memory 199840 kb
Host smart-6651220d-4018-45be-a052-2bf0806fbbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003009302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3003009302
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1098696103
Short name T496
Test name
Test status
Simulation time 12087502 ps
CPU time 0.56 seconds
Started Jul 30 07:37:13 PM PDT 24
Finished Jul 30 07:37:14 PM PDT 24
Peak memory 195360 kb
Host smart-d05c8042-1e4f-4cd1-a874-02d8e297c0b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098696103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1098696103
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3867499931
Short name T1109
Test name
Test status
Simulation time 90089623218 ps
CPU time 33.74 seconds
Started Jul 30 07:37:07 PM PDT 24
Finished Jul 30 07:37:41 PM PDT 24
Peak memory 199924 kb
Host smart-6c4cb712-f738-475c-b4cb-19c07a895be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867499931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3867499931
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1565939538
Short name T801
Test name
Test status
Simulation time 247151229101 ps
CPU time 38.59 seconds
Started Jul 30 07:37:09 PM PDT 24
Finished Jul 30 07:37:47 PM PDT 24
Peak memory 199620 kb
Host smart-d85a6627-4b93-44eb-beec-7e33eb9fa616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565939538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1565939538
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_intr.791345072
Short name T1065
Test name
Test status
Simulation time 216682484210 ps
CPU time 316.62 seconds
Started Jul 30 07:37:10 PM PDT 24
Finished Jul 30 07:42:27 PM PDT 24
Peak memory 196800 kb
Host smart-c11f8bed-ca50-4010-ab9e-dfbfef8e0001
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791345072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.791345072
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.3625879420
Short name T396
Test name
Test status
Simulation time 115579042840 ps
CPU time 51.83 seconds
Started Jul 30 07:37:12 PM PDT 24
Finished Jul 30 07:38:03 PM PDT 24
Peak memory 199828 kb
Host smart-9b369473-6e33-4eea-8041-c8d9a2c2c2e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625879420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.3625879420
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1091524352
Short name T377
Test name
Test status
Simulation time 14265730908 ps
CPU time 8.03 seconds
Started Jul 30 07:37:17 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 199896 kb
Host smart-66b80009-6f53-4c57-af5f-e9844b28e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091524352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1091524352
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.351748286
Short name T690
Test name
Test status
Simulation time 91027286279 ps
CPU time 74.85 seconds
Started Jul 30 07:37:17 PM PDT 24
Finished Jul 30 07:38:32 PM PDT 24
Peak memory 208248 kb
Host smart-5878e353-94f4-4360-a9f4-30aee7adeab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351748286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.351748286
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.2183521441
Short name T817
Test name
Test status
Simulation time 10830748144 ps
CPU time 565.08 seconds
Started Jul 30 07:37:16 PM PDT 24
Finished Jul 30 07:46:42 PM PDT 24
Peak memory 200000 kb
Host smart-e1fdd28b-8266-4a7a-8ea7-d620d9a00103
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183521441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.2183521441
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.1737944005
Short name T836
Test name
Test status
Simulation time 7245664929 ps
CPU time 63.72 seconds
Started Jul 30 07:37:06 PM PDT 24
Finished Jul 30 07:38:10 PM PDT 24
Peak memory 199160 kb
Host smart-ba9367d3-f792-4a1b-9fdc-1624feea0ddf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737944005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.1737944005
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3211738712
Short name T931
Test name
Test status
Simulation time 143553439209 ps
CPU time 136.61 seconds
Started Jul 30 07:37:11 PM PDT 24
Finished Jul 30 07:39:28 PM PDT 24
Peak memory 199932 kb
Host smart-2a2bc642-295f-43d3-b860-971581a3ae9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211738712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3211738712
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1149106388
Short name T482
Test name
Test status
Simulation time 1670522581 ps
CPU time 1.14 seconds
Started Jul 30 07:37:11 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 195536 kb
Host smart-f96cb370-65cf-4a26-906f-68b3f73003c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149106388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1149106388
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.2952671525
Short name T514
Test name
Test status
Simulation time 125502304 ps
CPU time 1.05 seconds
Started Jul 30 07:37:07 PM PDT 24
Finished Jul 30 07:37:08 PM PDT 24
Peak memory 198588 kb
Host smart-2ea35afc-e89e-47d3-92f1-3f8827367901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952671525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.2952671525
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.1655462142
Short name T743
Test name
Test status
Simulation time 202836981996 ps
CPU time 920.99 seconds
Started Jul 30 07:37:13 PM PDT 24
Finished Jul 30 07:52:34 PM PDT 24
Peak memory 199972 kb
Host smart-7549732f-df27-4e5d-ab62-b4b303c9dabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655462142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.1655462142
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2791767847
Short name T950
Test name
Test status
Simulation time 97558155650 ps
CPU time 350.92 seconds
Started Jul 30 07:37:11 PM PDT 24
Finished Jul 30 07:43:02 PM PDT 24
Peak memory 216552 kb
Host smart-ba8659b4-1ec7-4205-a390-2539e4e13755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791767847 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2791767847
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.3317074126
Short name T756
Test name
Test status
Simulation time 6808514964 ps
CPU time 18.8 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:37:37 PM PDT 24
Peak memory 199940 kb
Host smart-bef3e122-3b6e-4825-9b94-559c7e661f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317074126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.3317074126
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2503560176
Short name T523
Test name
Test status
Simulation time 248567318616 ps
CPU time 122.78 seconds
Started Jul 30 07:37:07 PM PDT 24
Finished Jul 30 07:39:09 PM PDT 24
Peak memory 199968 kb
Host smart-cd634faa-f83f-43ca-9b37-91151422adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503560176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2503560176
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2099540803
Short name T560
Test name
Test status
Simulation time 30507251965 ps
CPU time 36.53 seconds
Started Jul 30 07:41:52 PM PDT 24
Finished Jul 30 07:42:29 PM PDT 24
Peak memory 199972 kb
Host smart-e6df4f3e-5282-41ff-8edb-273bddd839aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099540803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2099540803
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.1428680294
Short name T868
Test name
Test status
Simulation time 43744979330 ps
CPU time 20.52 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:24 PM PDT 24
Peak memory 199940 kb
Host smart-f792137b-4a14-4cac-92f8-4c6a5b416b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428680294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1428680294
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.1251452854
Short name T1010
Test name
Test status
Simulation time 12572370150 ps
CPU time 24.65 seconds
Started Jul 30 07:41:52 PM PDT 24
Finished Jul 30 07:42:17 PM PDT 24
Peak memory 199940 kb
Host smart-54ede519-05f1-4fa5-95be-9d551053a5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251452854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.1251452854
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.3819687036
Short name T490
Test name
Test status
Simulation time 74498830924 ps
CPU time 19.81 seconds
Started Jul 30 07:41:52 PM PDT 24
Finished Jul 30 07:42:12 PM PDT 24
Peak memory 198924 kb
Host smart-c8c5aaf1-4f0b-4290-9939-096bf63108dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819687036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.3819687036
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3035939193
Short name T862
Test name
Test status
Simulation time 63189987387 ps
CPU time 24.68 seconds
Started Jul 30 07:41:58 PM PDT 24
Finished Jul 30 07:42:22 PM PDT 24
Peak memory 199576 kb
Host smart-11b21d8f-d735-4814-b20c-6e3073fe4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035939193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3035939193
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2324630191
Short name T640
Test name
Test status
Simulation time 94997702304 ps
CPU time 141.36 seconds
Started Jul 30 07:41:56 PM PDT 24
Finished Jul 30 07:44:18 PM PDT 24
Peak memory 199872 kb
Host smart-8eef0ff5-ded3-40b6-abee-d9155375fdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324630191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2324630191
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2481521642
Short name T438
Test name
Test status
Simulation time 171029065 ps
CPU time 0.62 seconds
Started Jul 30 07:37:19 PM PDT 24
Finished Jul 30 07:37:20 PM PDT 24
Peak memory 195316 kb
Host smart-f8a7bf26-ed0e-4b4c-80e6-9f15ffb0dd1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481521642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2481521642
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.2091940645
Short name T375
Test name
Test status
Simulation time 15797257189 ps
CPU time 13.43 seconds
Started Jul 30 07:37:15 PM PDT 24
Finished Jul 30 07:37:29 PM PDT 24
Peak memory 199948 kb
Host smart-5bd45901-a169-4bcd-8e13-1f9435b08be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091940645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2091940645
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2491673379
Short name T387
Test name
Test status
Simulation time 42193656136 ps
CPU time 17.83 seconds
Started Jul 30 07:37:10 PM PDT 24
Finished Jul 30 07:37:28 PM PDT 24
Peak memory 199960 kb
Host smart-fa15b167-c4df-4dd5-ba4a-f8b833271628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491673379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2491673379
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.112455647
Short name T1141
Test name
Test status
Simulation time 57883961536 ps
CPU time 23.49 seconds
Started Jul 30 07:37:14 PM PDT 24
Finished Jul 30 07:37:37 PM PDT 24
Peak memory 199896 kb
Host smart-ebbe454b-974b-4066-8cdf-7389944eb14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112455647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.112455647
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.1738262710
Short name T980
Test name
Test status
Simulation time 42089926945 ps
CPU time 44.44 seconds
Started Jul 30 07:37:23 PM PDT 24
Finished Jul 30 07:38:07 PM PDT 24
Peak memory 197724 kb
Host smart-5f74b7a4-0be4-4b27-9abb-ac70b9798b07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738262710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.1738262710
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.3801905925
Short name T985
Test name
Test status
Simulation time 153120726765 ps
CPU time 213.23 seconds
Started Jul 30 07:37:15 PM PDT 24
Finished Jul 30 07:40:48 PM PDT 24
Peak memory 199920 kb
Host smart-990d3b27-408d-40aa-b0cc-4e6da6d51c4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801905925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3801905925
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.3927906079
Short name T345
Test name
Test status
Simulation time 5294702376 ps
CPU time 8.75 seconds
Started Jul 30 07:37:16 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 198712 kb
Host smart-51ede1c2-5549-4689-8fc7-f7d6c7a26421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927906079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3927906079
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.3537857313
Short name T1160
Test name
Test status
Simulation time 28867894961 ps
CPU time 21.74 seconds
Started Jul 30 07:37:16 PM PDT 24
Finished Jul 30 07:37:38 PM PDT 24
Peak memory 198400 kb
Host smart-e0a19c3f-fe59-4306-b93d-20e63ef447ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537857313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.3537857313
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1319427765
Short name T378
Test name
Test status
Simulation time 18039907801 ps
CPU time 240.51 seconds
Started Jul 30 07:37:15 PM PDT 24
Finished Jul 30 07:41:15 PM PDT 24
Peak memory 199884 kb
Host smart-68c7763a-5f76-4f92-9e57-d095279da895
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1319427765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1319427765
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2827068557
Short name T596
Test name
Test status
Simulation time 5875489991 ps
CPU time 53.11 seconds
Started Jul 30 07:37:13 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 198872 kb
Host smart-37e25685-efc9-437d-bd51-5985bbf4e40e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827068557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2827068557
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.2732155270
Short name T1031
Test name
Test status
Simulation time 20758252917 ps
CPU time 28.96 seconds
Started Jul 30 07:37:17 PM PDT 24
Finished Jul 30 07:37:46 PM PDT 24
Peak memory 199860 kb
Host smart-d451649a-e8f4-4c30-8d59-896209efdee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732155270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.2732155270
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3626942187
Short name T621
Test name
Test status
Simulation time 4874039116 ps
CPU time 8.56 seconds
Started Jul 30 07:37:17 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 196120 kb
Host smart-1a74455b-9486-462e-b5bf-f7ce4f44bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626942187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3626942187
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3583558727
Short name T410
Test name
Test status
Simulation time 906784968 ps
CPU time 1.7 seconds
Started Jul 30 07:37:10 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 198668 kb
Host smart-b73079e0-1ac9-4f07-a8e3-e685775c7ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583558727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3583558727
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1225449137
Short name T432
Test name
Test status
Simulation time 22079008621 ps
CPU time 249.36 seconds
Started Jul 30 07:37:16 PM PDT 24
Finished Jul 30 07:41:25 PM PDT 24
Peak memory 215844 kb
Host smart-45df142f-db5f-46f5-9802-104757a254dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225449137 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1225449137
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.3670677463
Short name T68
Test name
Test status
Simulation time 7322742284 ps
CPU time 18.2 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:37:36 PM PDT 24
Peak memory 199876 kb
Host smart-44990b1b-b1fb-49b2-b121-2d788177cc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670677463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3670677463
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1306786153
Short name T277
Test name
Test status
Simulation time 133445491794 ps
CPU time 116.84 seconds
Started Jul 30 07:37:12 PM PDT 24
Finished Jul 30 07:39:09 PM PDT 24
Peak memory 199892 kb
Host smart-a222e226-e949-4cbe-94db-0981b0eaf6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306786153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1306786153
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1603497650
Short name T606
Test name
Test status
Simulation time 100474842051 ps
CPU time 77.84 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:43:20 PM PDT 24
Peak memory 199880 kb
Host smart-320e2cef-98e4-40ba-a49c-daed1b7ae16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603497650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1603497650
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3449183811
Short name T181
Test name
Test status
Simulation time 100505733015 ps
CPU time 81.8 seconds
Started Jul 30 07:41:58 PM PDT 24
Finished Jul 30 07:43:19 PM PDT 24
Peak memory 199884 kb
Host smart-73342de9-d6b5-4924-9bcc-985928db2f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449183811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3449183811
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.3941734480
Short name T734
Test name
Test status
Simulation time 18274602419 ps
CPU time 19.19 seconds
Started Jul 30 07:41:56 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 200000 kb
Host smart-51e6a29b-99f6-4755-88b1-b0ee93b86476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941734480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.3941734480
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.1000918041
Short name T1159
Test name
Test status
Simulation time 30566169436 ps
CPU time 28.54 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:42:28 PM PDT 24
Peak memory 199932 kb
Host smart-09ef7b74-3b4c-4e67-b957-1661878ba17e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000918041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1000918041
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.420816271
Short name T720
Test name
Test status
Simulation time 10112809018 ps
CPU time 14.42 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:42:14 PM PDT 24
Peak memory 200000 kb
Host smart-5b6ec749-3c89-4b88-90f7-84ac2a5b41bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420816271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.420816271
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.1696427740
Short name T235
Test name
Test status
Simulation time 46182623282 ps
CPU time 67.66 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:43:07 PM PDT 24
Peak memory 199916 kb
Host smart-118a37c9-ffaf-444e-bba9-b6bb5315001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696427740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.1696427740
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.4190793366
Short name T144
Test name
Test status
Simulation time 10981419611 ps
CPU time 20.77 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:42:20 PM PDT 24
Peak memory 199976 kb
Host smart-5ffc997e-5dfb-4a87-b43a-178d65433f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190793366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.4190793366
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.4252528052
Short name T402
Test name
Test status
Simulation time 33956175 ps
CPU time 0.54 seconds
Started Jul 30 07:37:25 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 194792 kb
Host smart-eeaa7de8-2c02-4e43-aec4-1d15436e3f26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252528052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4252528052
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.681431400
Short name T916
Test name
Test status
Simulation time 82845755419 ps
CPU time 34.67 seconds
Started Jul 30 07:37:15 PM PDT 24
Finished Jul 30 07:37:50 PM PDT 24
Peak memory 199912 kb
Host smart-5c7add3a-8669-494b-a361-6157d0993d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681431400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.681431400
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.4041745037
Short name T633
Test name
Test status
Simulation time 9581920152 ps
CPU time 8.32 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:37:26 PM PDT 24
Peak memory 199904 kb
Host smart-8be3c0f5-e544-492b-817f-989442a3ff04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041745037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.4041745037
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.781547935
Short name T883
Test name
Test status
Simulation time 95081713427 ps
CPU time 67.08 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:38:26 PM PDT 24
Peak memory 199996 kb
Host smart-56971a5b-3c19-4827-8ff7-d4873b24527a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781547935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.781547935
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2103624594
Short name T970
Test name
Test status
Simulation time 52275337906 ps
CPU time 20.7 seconds
Started Jul 30 07:37:19 PM PDT 24
Finished Jul 30 07:37:40 PM PDT 24
Peak memory 199916 kb
Host smart-2b4b30c1-d804-47d5-acb4-61d51b48537f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103624594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2103624594
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2097657783
Short name T458
Test name
Test status
Simulation time 110272769312 ps
CPU time 185.28 seconds
Started Jul 30 07:37:22 PM PDT 24
Finished Jul 30 07:40:28 PM PDT 24
Peak memory 199956 kb
Host smart-950d3137-726d-4fcb-b6c9-3464cfe6b2fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2097657783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2097657783
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.4192057491
Short name T954
Test name
Test status
Simulation time 3506940672 ps
CPU time 1.95 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:37:28 PM PDT 24
Peak memory 198940 kb
Host smart-b55a7384-8d92-4182-8eb7-5dda0f980cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192057491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.4192057491
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3736724980
Short name T925
Test name
Test status
Simulation time 35156326866 ps
CPU time 32.91 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:37:51 PM PDT 24
Peak memory 199548 kb
Host smart-e8fa1666-e76d-4df3-99ed-9546c7360bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736724980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3736724980
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.3440283961
Short name T865
Test name
Test status
Simulation time 16567476694 ps
CPU time 278 seconds
Started Jul 30 07:37:23 PM PDT 24
Finished Jul 30 07:42:01 PM PDT 24
Peak memory 199928 kb
Host smart-967ed607-4030-499e-9808-07cf0a000c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440283961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.3440283961
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3611304635
Short name T545
Test name
Test status
Simulation time 4450970827 ps
CPU time 35.65 seconds
Started Jul 30 07:37:19 PM PDT 24
Finished Jul 30 07:37:55 PM PDT 24
Peak memory 199028 kb
Host smart-cc24a6d5-8330-4216-8c6f-ba2f1508d9cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3611304635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3611304635
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.618034422
Short name T588
Test name
Test status
Simulation time 81676639483 ps
CPU time 89.3 seconds
Started Jul 30 07:37:20 PM PDT 24
Finished Jul 30 07:38:50 PM PDT 24
Peak memory 199860 kb
Host smart-f48d840a-9d79-4bb6-9528-f296c6a4a5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618034422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.618034422
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3014256731
Short name T1161
Test name
Test status
Simulation time 1768700227 ps
CPU time 3.37 seconds
Started Jul 30 07:37:19 PM PDT 24
Finished Jul 30 07:37:22 PM PDT 24
Peak memory 195540 kb
Host smart-574de5c6-0915-4099-9ed9-3025ddbc0c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014256731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3014256731
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.99831562
Short name T641
Test name
Test status
Simulation time 150039940 ps
CPU time 0.72 seconds
Started Jul 30 07:37:16 PM PDT 24
Finished Jul 30 07:37:17 PM PDT 24
Peak memory 197252 kb
Host smart-cda78934-7976-4add-9295-76f29646b4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99831562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.99831562
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.2775550843
Short name T116
Test name
Test status
Simulation time 73623901724 ps
CPU time 61.73 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:38:28 PM PDT 24
Peak memory 199772 kb
Host smart-4b679b5c-8438-4431-bac0-d1968156db49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775550843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2775550843
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1037253143
Short name T96
Test name
Test status
Simulation time 86508713375 ps
CPU time 182.35 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:40:28 PM PDT 24
Peak memory 216452 kb
Host smart-c13b331d-272c-48a7-bf96-0b5c1848fb33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037253143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1037253143
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.257727709
Short name T565
Test name
Test status
Simulation time 12628745032 ps
CPU time 16.64 seconds
Started Jul 30 07:37:18 PM PDT 24
Finished Jul 30 07:37:35 PM PDT 24
Peak memory 199688 kb
Host smart-2dbf1f3e-2602-4820-afbd-3cfc2312a696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257727709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.257727709
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2321298918
Short name T923
Test name
Test status
Simulation time 94230104804 ps
CPU time 54.64 seconds
Started Jul 30 07:37:14 PM PDT 24
Finished Jul 30 07:38:08 PM PDT 24
Peak memory 199948 kb
Host smart-35c3b3a1-69b4-4192-9229-3f62970f3b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321298918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2321298918
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.86840710
Short name T627
Test name
Test status
Simulation time 104333615399 ps
CPU time 37.95 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:42:37 PM PDT 24
Peak memory 199472 kb
Host smart-4851fc45-47ab-47e0-9d22-9070c0d10a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86840710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.86840710
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.1413143557
Short name T479
Test name
Test status
Simulation time 168481809454 ps
CPU time 122.54 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:44:02 PM PDT 24
Peak memory 199956 kb
Host smart-ae1645ec-a246-4e55-837e-876a3531d54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413143557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1413143557
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.2244432325
Short name T892
Test name
Test status
Simulation time 21512952987 ps
CPU time 13.26 seconds
Started Jul 30 07:42:02 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 199964 kb
Host smart-44648c8d-9c25-47e4-b850-ecfa24aa23ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244432325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2244432325
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2665284981
Short name T128
Test name
Test status
Simulation time 44864077742 ps
CPU time 49.59 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 199940 kb
Host smart-7ee62875-6f72-407a-95cf-05668dfd2222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665284981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2665284981
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.1757296783
Short name T959
Test name
Test status
Simulation time 28420033282 ps
CPU time 37.21 seconds
Started Jul 30 07:41:59 PM PDT 24
Finished Jul 30 07:42:37 PM PDT 24
Peak memory 199848 kb
Host smart-307c5626-4b8a-415a-b598-cdc3f722fc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757296783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.1757296783
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.2066849799
Short name T45
Test name
Test status
Simulation time 205881239569 ps
CPU time 34.11 seconds
Started Jul 30 07:42:03 PM PDT 24
Finished Jul 30 07:42:38 PM PDT 24
Peak memory 199892 kb
Host smart-3347093a-9793-47fd-84c3-747306f54fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066849799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.2066849799
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3737798619
Short name T594
Test name
Test status
Simulation time 11316744 ps
CPU time 0.58 seconds
Started Jul 30 07:37:30 PM PDT 24
Finished Jul 30 07:37:31 PM PDT 24
Peak memory 195308 kb
Host smart-8c7ec5b9-b30a-494d-9062-8ab9142f77cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737798619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3737798619
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.4042470341
Short name T1178
Test name
Test status
Simulation time 57033169211 ps
CPU time 20.59 seconds
Started Jul 30 07:37:25 PM PDT 24
Finished Jul 30 07:37:46 PM PDT 24
Peak memory 199604 kb
Host smart-341da113-9ad2-477e-ba6c-95e4bc7d25d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042470341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.4042470341
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3030763370
Short name T503
Test name
Test status
Simulation time 80913820368 ps
CPU time 134.67 seconds
Started Jul 30 07:37:28 PM PDT 24
Finished Jul 30 07:39:43 PM PDT 24
Peak memory 200044 kb
Host smart-0422830b-f82c-43ec-b5e4-917219634f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030763370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3030763370
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.831746648
Short name T590
Test name
Test status
Simulation time 33938863486 ps
CPU time 29.2 seconds
Started Jul 30 07:37:28 PM PDT 24
Finished Jul 30 07:37:57 PM PDT 24
Peak memory 199936 kb
Host smart-bf3ac001-d0ff-4914-bfbb-0e6fa3327568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831746648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.831746648
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.194397080
Short name T424
Test name
Test status
Simulation time 6327399422 ps
CPU time 10.27 seconds
Started Jul 30 07:37:25 PM PDT 24
Finished Jul 30 07:37:36 PM PDT 24
Peak memory 199868 kb
Host smart-1eeb2a1e-c63a-41b3-bc52-fa4854c8aa8c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194397080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.194397080
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1775856628
Short name T567
Test name
Test status
Simulation time 186043132219 ps
CPU time 1383.8 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 08:00:30 PM PDT 24
Peak memory 199916 kb
Host smart-efd69f38-88b6-4035-9750-f5c5682484c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775856628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1775856628
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.3385283608
Short name T422
Test name
Test status
Simulation time 3416518773 ps
CPU time 2.66 seconds
Started Jul 30 07:37:28 PM PDT 24
Finished Jul 30 07:37:31 PM PDT 24
Peak memory 199960 kb
Host smart-a243e345-bb5e-4889-ab1e-3accf62434c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385283608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.3385283608
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.676926738
Short name T992
Test name
Test status
Simulation time 60659818725 ps
CPU time 22.3 seconds
Started Jul 30 07:37:27 PM PDT 24
Finished Jul 30 07:37:50 PM PDT 24
Peak memory 197556 kb
Host smart-d5c4d4c3-06d1-4f25-bd24-9522e2264531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676926738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.676926738
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2975516924
Short name T754
Test name
Test status
Simulation time 28801366660 ps
CPU time 389.77 seconds
Started Jul 30 07:37:27 PM PDT 24
Finished Jul 30 07:43:57 PM PDT 24
Peak memory 199932 kb
Host smart-983997e5-32ca-4c53-9188-16508994ce83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975516924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2975516924
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.436284596
Short name T794
Test name
Test status
Simulation time 7245756626 ps
CPU time 15.76 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:37:42 PM PDT 24
Peak memory 198144 kb
Host smart-80f7ae19-2125-4e59-a2d8-25b5593f9194
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=436284596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.436284596
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2043266414
Short name T898
Test name
Test status
Simulation time 103076366125 ps
CPU time 224.72 seconds
Started Jul 30 07:37:29 PM PDT 24
Finished Jul 30 07:41:14 PM PDT 24
Peak memory 199840 kb
Host smart-5622ccea-461c-4457-ae26-baa2cff9e382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043266414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2043266414
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.2485382880
Short name T497
Test name
Test status
Simulation time 30845743843 ps
CPU time 12.57 seconds
Started Jul 30 07:37:26 PM PDT 24
Finished Jul 30 07:37:39 PM PDT 24
Peak memory 196232 kb
Host smart-748074bd-a217-448f-81b1-52669df18b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485382880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.2485382880
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.211982049
Short name T682
Test name
Test status
Simulation time 454198321 ps
CPU time 1.5 seconds
Started Jul 30 07:37:24 PM PDT 24
Finished Jul 30 07:37:26 PM PDT 24
Peak memory 199708 kb
Host smart-56be817f-e108-410d-9f00-80fd9ea5ad2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211982049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.211982049
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.3782788905
Short name T299
Test name
Test status
Simulation time 982226858 ps
CPU time 3.32 seconds
Started Jul 30 07:37:27 PM PDT 24
Finished Jul 30 07:37:31 PM PDT 24
Peak memory 198800 kb
Host smart-e34a986d-8c01-46d1-ad2b-21728ec90885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782788905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3782788905
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1252671140
Short name T278
Test name
Test status
Simulation time 92995550501 ps
CPU time 445.78 seconds
Started Jul 30 07:37:22 PM PDT 24
Finished Jul 30 07:44:48 PM PDT 24
Peak memory 199984 kb
Host smart-79be90e6-b6cd-44aa-98f2-02a95d98c0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252671140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1252671140
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.1114708740
Short name T611
Test name
Test status
Simulation time 59369150592 ps
CPU time 7.31 seconds
Started Jul 30 07:42:07 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 200012 kb
Host smart-a52501fb-9815-4e0a-b431-ef952ebc493c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114708740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.1114708740
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.53855699
Short name T861
Test name
Test status
Simulation time 17247700753 ps
CPU time 25.08 seconds
Started Jul 30 07:42:09 PM PDT 24
Finished Jul 30 07:42:34 PM PDT 24
Peak memory 199876 kb
Host smart-93f443eb-4b01-40fc-9197-565d3efef6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53855699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.53855699
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.265405543
Short name T572
Test name
Test status
Simulation time 103896509619 ps
CPU time 15.97 seconds
Started Jul 30 07:42:12 PM PDT 24
Finished Jul 30 07:42:29 PM PDT 24
Peak memory 199872 kb
Host smart-a678e9b6-0aef-42f6-a997-c40a7a552596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265405543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.265405543
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.1715450069
Short name T467
Test name
Test status
Simulation time 79331566021 ps
CPU time 57.64 seconds
Started Jul 30 07:42:10 PM PDT 24
Finished Jul 30 07:43:08 PM PDT 24
Peak memory 199536 kb
Host smart-f7bb0751-8cd3-4c72-8c33-ce6e9b472458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715450069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.1715450069
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1998598138
Short name T907
Test name
Test status
Simulation time 29480860839 ps
CPU time 30.77 seconds
Started Jul 30 07:42:17 PM PDT 24
Finished Jul 30 07:42:48 PM PDT 24
Peak memory 199876 kb
Host smart-f8e9e43e-c1ff-4aeb-bcbc-739117a748ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998598138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1998598138
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.2521282242
Short name T389
Test name
Test status
Simulation time 38791922908 ps
CPU time 65.08 seconds
Started Jul 30 07:42:11 PM PDT 24
Finished Jul 30 07:43:16 PM PDT 24
Peak memory 199788 kb
Host smart-937e9bf7-ede5-40ee-bf17-80d0cc89b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521282242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.2521282242
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.1012642804
Short name T731
Test name
Test status
Simulation time 29749037160 ps
CPU time 13.92 seconds
Started Jul 30 07:42:12 PM PDT 24
Finished Jul 30 07:42:26 PM PDT 24
Peak memory 199976 kb
Host smart-4c88e242-1244-4c5a-b3f8-cd5a254f0cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012642804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.1012642804
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.284607735
Short name T161
Test name
Test status
Simulation time 41884519060 ps
CPU time 47.96 seconds
Started Jul 30 07:42:14 PM PDT 24
Finished Jul 30 07:43:02 PM PDT 24
Peak memory 200012 kb
Host smart-e0ea5e5b-f44c-497f-9422-db6ad36867c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284607735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.284607735
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3613592755
Short name T1061
Test name
Test status
Simulation time 28384817067 ps
CPU time 50.96 seconds
Started Jul 30 07:37:31 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 199976 kb
Host smart-04652fa5-8a10-4f91-8682-83047807270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613592755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3613592755
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2462046656
Short name T380
Test name
Test status
Simulation time 13073074019 ps
CPU time 16.61 seconds
Started Jul 30 07:37:30 PM PDT 24
Finished Jul 30 07:37:47 PM PDT 24
Peak memory 199256 kb
Host smart-100ca25c-465e-45eb-9628-31f24375308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462046656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2462046656
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3137104733
Short name T202
Test name
Test status
Simulation time 127980444353 ps
CPU time 69.6 seconds
Started Jul 30 07:37:32 PM PDT 24
Finished Jul 30 07:38:41 PM PDT 24
Peak memory 199760 kb
Host smart-fa11a412-3cf9-499d-920e-e8b3f65cc3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137104733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3137104733
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2361574891
Short name T895
Test name
Test status
Simulation time 61270837486 ps
CPU time 36.15 seconds
Started Jul 30 07:37:30 PM PDT 24
Finished Jul 30 07:38:07 PM PDT 24
Peak memory 200056 kb
Host smart-424bea7e-eb2e-477d-88e9-5f0c070f22ae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361574891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2361574891
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.889587344
Short name T104
Test name
Test status
Simulation time 326568307556 ps
CPU time 433.46 seconds
Started Jul 30 07:37:34 PM PDT 24
Finished Jul 30 07:44:48 PM PDT 24
Peak memory 199872 kb
Host smart-cad970ea-bed6-4d54-9182-4418b2fd181d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=889587344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.889587344
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.2372798973
Short name T587
Test name
Test status
Simulation time 5045442252 ps
CPU time 9.15 seconds
Started Jul 30 07:37:35 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 198636 kb
Host smart-40539026-aa03-4076-99ec-b339f0613feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372798973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.2372798973
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.2472634371
Short name T486
Test name
Test status
Simulation time 77198672976 ps
CPU time 35.61 seconds
Started Jul 30 07:37:31 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 200088 kb
Host smart-e2794572-0360-4e56-8a06-40187989ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472634371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.2472634371
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1307376013
Short name T1049
Test name
Test status
Simulation time 14332933156 ps
CPU time 866.48 seconds
Started Jul 30 07:37:35 PM PDT 24
Finished Jul 30 07:52:02 PM PDT 24
Peak memory 200000 kb
Host smart-3bd77618-63da-4c80-abc6-5f0952cfc8b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307376013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1307376013
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.487967616
Short name T488
Test name
Test status
Simulation time 4862971940 ps
CPU time 7.28 seconds
Started Jul 30 07:37:31 PM PDT 24
Finished Jul 30 07:37:39 PM PDT 24
Peak memory 199464 kb
Host smart-b6376a3a-090a-4071-b6ee-c0dbb5a480aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=487967616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.487967616
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3272742988
Short name T963
Test name
Test status
Simulation time 35252209170 ps
CPU time 14.45 seconds
Started Jul 30 07:37:32 PM PDT 24
Finished Jul 30 07:37:46 PM PDT 24
Peak memory 199736 kb
Host smart-28460a12-c459-4d00-9d45-f3c040a05c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272742988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3272742988
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3826901629
Short name T342
Test name
Test status
Simulation time 3740670885 ps
CPU time 2.03 seconds
Started Jul 30 07:37:33 PM PDT 24
Finished Jul 30 07:37:35 PM PDT 24
Peak memory 196272 kb
Host smart-8be7e7b8-5ffb-4587-b2df-469f7de5873d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826901629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3826901629
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.86970859
Short name T254
Test name
Test status
Simulation time 817450774 ps
CPU time 2.52 seconds
Started Jul 30 07:37:32 PM PDT 24
Finished Jul 30 07:37:35 PM PDT 24
Peak memory 199012 kb
Host smart-9cd195d5-8046-4a04-a3e6-640e5607a6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86970859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.86970859
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.321832203
Short name T164
Test name
Test status
Simulation time 157468957287 ps
CPU time 724.82 seconds
Started Jul 30 07:37:33 PM PDT 24
Finished Jul 30 07:49:38 PM PDT 24
Peak memory 199992 kb
Host smart-41335a15-a1e4-4815-8c63-60c454ab0f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321832203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.321832203
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1733923225
Short name T272
Test name
Test status
Simulation time 190528319711 ps
CPU time 841.31 seconds
Started Jul 30 07:37:34 PM PDT 24
Finished Jul 30 07:51:35 PM PDT 24
Peak memory 216432 kb
Host smart-e72bdb56-2629-4d96-8842-785b77f199fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733923225 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1733923225
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1551844408
Short name T574
Test name
Test status
Simulation time 2321938862 ps
CPU time 2.31 seconds
Started Jul 30 07:37:35 PM PDT 24
Finished Jul 30 07:37:37 PM PDT 24
Peak memory 200004 kb
Host smart-3c1c947d-7b6c-4cde-b184-7e3cc1579221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551844408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1551844408
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.2261375984
Short name T38
Test name
Test status
Simulation time 179177989285 ps
CPU time 35.31 seconds
Started Jul 30 07:37:30 PM PDT 24
Finished Jul 30 07:38:05 PM PDT 24
Peak memory 199908 kb
Host smart-bdb3dd48-a393-448a-9aa7-500358e5337f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261375984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2261375984
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1760289071
Short name T927
Test name
Test status
Simulation time 125233178764 ps
CPU time 187.43 seconds
Started Jul 30 07:42:17 PM PDT 24
Finished Jul 30 07:45:24 PM PDT 24
Peak memory 199972 kb
Host smart-424054a2-af4d-4f63-82c8-bc1fe88351be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760289071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1760289071
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.2140014237
Short name T63
Test name
Test status
Simulation time 92150137624 ps
CPU time 13.64 seconds
Started Jul 30 07:42:14 PM PDT 24
Finished Jul 30 07:42:27 PM PDT 24
Peak memory 199788 kb
Host smart-81e349ea-d740-49e3-a184-ace2227635bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140014237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.2140014237
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.1160528122
Short name T494
Test name
Test status
Simulation time 98859324535 ps
CPU time 132.84 seconds
Started Jul 30 07:42:16 PM PDT 24
Finished Jul 30 07:44:28 PM PDT 24
Peak memory 199964 kb
Host smart-abed14a3-3e17-4fa2-9578-187e81c5f036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160528122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.1160528122
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2758310545
Short name T290
Test name
Test status
Simulation time 35410071781 ps
CPU time 8.15 seconds
Started Jul 30 07:42:15 PM PDT 24
Finished Jul 30 07:42:23 PM PDT 24
Peak memory 199616 kb
Host smart-74f760c2-8625-496a-813f-25bdf9cc27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758310545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2758310545
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.861295160
Short name T918
Test name
Test status
Simulation time 250270513858 ps
CPU time 140.79 seconds
Started Jul 30 07:42:17 PM PDT 24
Finished Jul 30 07:44:38 PM PDT 24
Peak memory 199904 kb
Host smart-cd4ddbcb-30c7-4333-bee3-dc7526c60345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861295160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.861295160
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1583757353
Short name T14
Test name
Test status
Simulation time 29919308324 ps
CPU time 16.66 seconds
Started Jul 30 07:42:17 PM PDT 24
Finished Jul 30 07:42:34 PM PDT 24
Peak memory 199904 kb
Host smart-f7f07743-41dd-4e7a-84a9-ce14fe8353d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583757353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1583757353
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3138596064
Short name T940
Test name
Test status
Simulation time 10917182046 ps
CPU time 31.62 seconds
Started Jul 30 07:42:21 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 199964 kb
Host smart-cb30f933-5a14-4e0e-947d-f3906dd797d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138596064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3138596064
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.162044571
Short name T240
Test name
Test status
Simulation time 87125190122 ps
CPU time 142.68 seconds
Started Jul 30 07:42:19 PM PDT 24
Finished Jul 30 07:44:42 PM PDT 24
Peak memory 199880 kb
Host smart-524565d5-0457-4a48-b17b-01ee187e5832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162044571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.162044571
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.1256434692
Short name T159
Test name
Test status
Simulation time 140669590755 ps
CPU time 225.4 seconds
Started Jul 30 07:42:20 PM PDT 24
Finished Jul 30 07:46:05 PM PDT 24
Peak memory 199936 kb
Host smart-c63b25a3-4ef2-429f-a723-eced17cbda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256434692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.1256434692
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.887023022
Short name T576
Test name
Test status
Simulation time 14459223 ps
CPU time 0.57 seconds
Started Jul 30 07:37:38 PM PDT 24
Finished Jul 30 07:37:39 PM PDT 24
Peak memory 195364 kb
Host smart-23bb6942-d0dc-47ac-bd90-c031fec79dfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887023022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.887023022
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.1882339296
Short name T917
Test name
Test status
Simulation time 127865792492 ps
CPU time 308.46 seconds
Started Jul 30 07:37:35 PM PDT 24
Finished Jul 30 07:42:44 PM PDT 24
Peak memory 199948 kb
Host smart-6daa746b-f0b9-43a0-a0cd-7de2a001c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882339296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1882339296
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1282472148
Short name T1170
Test name
Test status
Simulation time 34219035638 ps
CPU time 58.61 seconds
Started Jul 30 07:37:33 PM PDT 24
Finished Jul 30 07:38:32 PM PDT 24
Peak memory 199896 kb
Host smart-e356255a-2aff-48bb-9bbd-582097bf03ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282472148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1282472148
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3113106966
Short name T505
Test name
Test status
Simulation time 24358293011 ps
CPU time 35.92 seconds
Started Jul 30 07:37:32 PM PDT 24
Finished Jul 30 07:38:09 PM PDT 24
Peak memory 200000 kb
Host smart-54d6648c-0b24-4495-871e-29f0abea1c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113106966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3113106966
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.1360865523
Short name T873
Test name
Test status
Simulation time 355220827404 ps
CPU time 527.93 seconds
Started Jul 30 07:37:33 PM PDT 24
Finished Jul 30 07:46:21 PM PDT 24
Peak memory 198060 kb
Host smart-dc20f37f-5414-410a-80ab-9594d208646d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360865523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.1360865523
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3487123786
Short name T382
Test name
Test status
Simulation time 249426904082 ps
CPU time 265.86 seconds
Started Jul 30 07:37:38 PM PDT 24
Finished Jul 30 07:42:04 PM PDT 24
Peak memory 199948 kb
Host smart-3630a9ff-d5ed-4d83-ade6-19d4fa0d4cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3487123786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3487123786
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.969861652
Short name T320
Test name
Test status
Simulation time 6466565344 ps
CPU time 13.4 seconds
Started Jul 30 07:37:39 PM PDT 24
Finished Jul 30 07:37:52 PM PDT 24
Peak memory 199948 kb
Host smart-7bf745a8-3d6a-4b8f-bad6-dfbc74111cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969861652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.969861652
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.398058369
Short name T312
Test name
Test status
Simulation time 69685281597 ps
CPU time 26.98 seconds
Started Jul 30 07:37:37 PM PDT 24
Finished Jul 30 07:38:05 PM PDT 24
Peak memory 198480 kb
Host smart-97733120-bef0-4092-91bd-09a2092bc0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398058369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.398058369
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2964015869
Short name T809
Test name
Test status
Simulation time 42071002069 ps
CPU time 607.47 seconds
Started Jul 30 07:37:41 PM PDT 24
Finished Jul 30 07:47:48 PM PDT 24
Peak memory 199872 kb
Host smart-1351dd1e-06b7-4d98-a838-000599e110f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964015869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2964015869
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.295441755
Short name T1130
Test name
Test status
Simulation time 1918212533 ps
CPU time 3.27 seconds
Started Jul 30 07:37:35 PM PDT 24
Finished Jul 30 07:37:38 PM PDT 24
Peak memory 197716 kb
Host smart-db9790f8-3c52-42fd-b809-dd6c01fafac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=295441755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.295441755
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1594165913
Short name T757
Test name
Test status
Simulation time 113808715502 ps
CPU time 64.91 seconds
Started Jul 30 07:37:37 PM PDT 24
Finished Jul 30 07:38:42 PM PDT 24
Peak memory 199932 kb
Host smart-5e3f9dbf-738b-48ca-91c3-9fec3b1c30b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594165913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1594165913
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2164147427
Short name T884
Test name
Test status
Simulation time 38057450708 ps
CPU time 35.76 seconds
Started Jul 30 07:37:39 PM PDT 24
Finished Jul 30 07:38:15 PM PDT 24
Peak memory 196808 kb
Host smart-b400ba99-5bd8-49a0-bd7d-9b928455b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164147427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2164147427
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2226984717
Short name T295
Test name
Test status
Simulation time 5714560433 ps
CPU time 9.6 seconds
Started Jul 30 07:37:34 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 199844 kb
Host smart-af7c2bdf-fcce-49c7-9158-64c47a0efff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226984717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2226984717
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1780559032
Short name T292
Test name
Test status
Simulation time 6817687096 ps
CPU time 22.19 seconds
Started Jul 30 07:37:39 PM PDT 24
Finished Jul 30 07:38:01 PM PDT 24
Peak memory 199864 kb
Host smart-cefb494f-cd7f-4e7b-bc4a-71a6ba9cd2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780559032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1780559032
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.2547695349
Short name T1026
Test name
Test status
Simulation time 11277090634 ps
CPU time 16.29 seconds
Started Jul 30 07:37:34 PM PDT 24
Finished Jul 30 07:37:50 PM PDT 24
Peak memory 199876 kb
Host smart-5c11b7c1-d697-495f-bbc4-81ac9a5f1261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547695349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.2547695349
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1666272624
Short name T328
Test name
Test status
Simulation time 115599150884 ps
CPU time 155.41 seconds
Started Jul 30 07:42:21 PM PDT 24
Finished Jul 30 07:44:56 PM PDT 24
Peak memory 199872 kb
Host smart-f5e9839d-c634-4e7f-b706-95ea278de300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666272624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1666272624
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.2087772205
Short name T135
Test name
Test status
Simulation time 68795572531 ps
CPU time 52.23 seconds
Started Jul 30 07:42:17 PM PDT 24
Finished Jul 30 07:43:10 PM PDT 24
Peak memory 200008 kb
Host smart-2bc2fb9d-4298-4205-ace9-7ab60051853b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087772205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.2087772205
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2805972747
Short name T1147
Test name
Test status
Simulation time 60893948346 ps
CPU time 75.96 seconds
Started Jul 30 07:42:21 PM PDT 24
Finished Jul 30 07:43:37 PM PDT 24
Peak memory 199980 kb
Host smart-d73eebed-74ad-4cc1-91d2-c37958118628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805972747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2805972747
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3119287706
Short name T969
Test name
Test status
Simulation time 97847489619 ps
CPU time 170.55 seconds
Started Jul 30 07:42:20 PM PDT 24
Finished Jul 30 07:45:11 PM PDT 24
Peak memory 199912 kb
Host smart-9eb35a01-527a-41e6-b641-6b2c35b2bafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119287706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3119287706
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2779949497
Short name T713
Test name
Test status
Simulation time 45955404778 ps
CPU time 29.92 seconds
Started Jul 30 07:42:23 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 199984 kb
Host smart-86e97817-18ce-4946-9052-305e8cd9465b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779949497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2779949497
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.2006277894
Short name T39
Test name
Test status
Simulation time 34144182895 ps
CPU time 20.05 seconds
Started Jul 30 07:42:23 PM PDT 24
Finished Jul 30 07:42:43 PM PDT 24
Peak memory 199920 kb
Host smart-5c590f9c-d950-46c3-a4cf-67ae5285e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006277894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.2006277894
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.3770343330
Short name T872
Test name
Test status
Simulation time 272453898414 ps
CPU time 28.09 seconds
Started Jul 30 07:42:23 PM PDT 24
Finished Jul 30 07:42:51 PM PDT 24
Peak memory 199940 kb
Host smart-23123f83-46ba-4500-b725-1e46f34d12af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770343330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3770343330
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3310906919
Short name T334
Test name
Test status
Simulation time 11174861 ps
CPU time 0.56 seconds
Started Jul 30 07:37:44 PM PDT 24
Finished Jul 30 07:37:45 PM PDT 24
Peak memory 195340 kb
Host smart-2ed9c989-7bee-4868-83ad-acc8e5539931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310906919 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3310906919
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.3611456339
Short name T797
Test name
Test status
Simulation time 81022634199 ps
CPU time 29.78 seconds
Started Jul 30 07:37:41 PM PDT 24
Finished Jul 30 07:38:11 PM PDT 24
Peak memory 199984 kb
Host smart-cad8d059-599b-4e05-a5e4-c6e7127f4e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611456339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.3611456339
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3047911077
Short name T858
Test name
Test status
Simulation time 63565955469 ps
CPU time 54.62 seconds
Started Jul 30 07:37:42 PM PDT 24
Finished Jul 30 07:38:37 PM PDT 24
Peak memory 199964 kb
Host smart-5c6cba61-5ce6-4d88-b881-3efac2d24286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047911077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3047911077
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.2638532623
Short name T1143
Test name
Test status
Simulation time 131517745823 ps
CPU time 69.81 seconds
Started Jul 30 07:37:42 PM PDT 24
Finished Jul 30 07:38:52 PM PDT 24
Peak memory 199928 kb
Host smart-8e59b48a-9eb8-4368-8fbf-0d4082780d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638532623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2638532623
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.682252467
Short name T783
Test name
Test status
Simulation time 19448915426 ps
CPU time 35.22 seconds
Started Jul 30 07:37:43 PM PDT 24
Finished Jul 30 07:38:19 PM PDT 24
Peak memory 199916 kb
Host smart-63baa2c4-7a37-4bb3-9427-0a81176baa81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682252467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.682252467
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.2291937625
Short name T376
Test name
Test status
Simulation time 143534598410 ps
CPU time 1491.82 seconds
Started Jul 30 07:37:47 PM PDT 24
Finished Jul 30 08:02:39 PM PDT 24
Peak memory 199920 kb
Host smart-41db152f-3bf6-43b8-a07a-4f837f85437c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2291937625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.2291937625
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.887794572
Short name T552
Test name
Test status
Simulation time 155549678 ps
CPU time 1.35 seconds
Started Jul 30 07:37:46 PM PDT 24
Finished Jul 30 07:37:48 PM PDT 24
Peak memory 198708 kb
Host smart-93454eb1-6767-446f-8457-46018f3150a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887794572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.887794572
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1595848020
Short name T582
Test name
Test status
Simulation time 49155641163 ps
CPU time 19.26 seconds
Started Jul 30 07:37:42 PM PDT 24
Finished Jul 30 07:38:01 PM PDT 24
Peak memory 199016 kb
Host smart-2d5d9125-6c73-413f-842e-7aa4fee02de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595848020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1595848020
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.4044679184
Short name T889
Test name
Test status
Simulation time 6959872796 ps
CPU time 310.86 seconds
Started Jul 30 07:37:46 PM PDT 24
Finished Jul 30 07:42:57 PM PDT 24
Peak memory 199996 kb
Host smart-9dee0cfc-e999-477a-8a8d-33ea71204e98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044679184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4044679184
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.699537744
Short name T1115
Test name
Test status
Simulation time 7380023660 ps
CPU time 67.98 seconds
Started Jul 30 07:37:41 PM PDT 24
Finished Jul 30 07:38:49 PM PDT 24
Peak memory 198168 kb
Host smart-0b896b11-faf7-480c-aea3-c4c6ee42ba40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=699537744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.699537744
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.2730953415
Short name T866
Test name
Test status
Simulation time 30828218986 ps
CPU time 20.64 seconds
Started Jul 30 07:37:44 PM PDT 24
Finished Jul 30 07:38:05 PM PDT 24
Peak memory 199924 kb
Host smart-6215b437-8a5c-4129-9b7e-5c19545ac376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730953415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.2730953415
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3699626461
Short name T369
Test name
Test status
Simulation time 2048356014 ps
CPU time 2.24 seconds
Started Jul 30 07:37:46 PM PDT 24
Finished Jul 30 07:37:48 PM PDT 24
Peak memory 195680 kb
Host smart-92d4fa60-29cf-4218-a8dd-b4611be79a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699626461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3699626461
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.3111935129
Short name T42
Test name
Test status
Simulation time 105550203 ps
CPU time 0.92 seconds
Started Jul 30 07:37:42 PM PDT 24
Finished Jul 30 07:37:43 PM PDT 24
Peak memory 198120 kb
Host smart-502d3b07-9701-4a64-baf3-958f8e369557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111935129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.3111935129
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.2782806349
Short name T234
Test name
Test status
Simulation time 280527905938 ps
CPU time 219.52 seconds
Started Jul 30 07:37:46 PM PDT 24
Finished Jul 30 07:41:26 PM PDT 24
Peak memory 216352 kb
Host smart-5629de02-75c8-4ee5-bf9f-2bde308d533b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782806349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.2782806349
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.4029423161
Short name T769
Test name
Test status
Simulation time 186816336244 ps
CPU time 942.74 seconds
Started Jul 30 07:37:50 PM PDT 24
Finished Jul 30 07:53:33 PM PDT 24
Peak memory 224824 kb
Host smart-e90d07b3-164c-4a39-8d02-bc9945ed9e24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029423161 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.4029423161
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2086443696
Short name T404
Test name
Test status
Simulation time 7306863411 ps
CPU time 11.12 seconds
Started Jul 30 07:37:45 PM PDT 24
Finished Jul 30 07:37:57 PM PDT 24
Peak memory 199976 kb
Host smart-85484b1e-efc8-46ab-9a86-3e09c99af1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086443696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2086443696
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.2810122244
Short name T381
Test name
Test status
Simulation time 10092057464 ps
CPU time 15.72 seconds
Started Jul 30 07:42:23 PM PDT 24
Finished Jul 30 07:42:39 PM PDT 24
Peak memory 199980 kb
Host smart-ca6762f9-672d-49c0-bd55-d74ba810ee1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810122244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.2810122244
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.2892613381
Short name T213
Test name
Test status
Simulation time 26555657287 ps
CPU time 40.1 seconds
Started Jul 30 07:42:21 PM PDT 24
Finished Jul 30 07:43:01 PM PDT 24
Peak memory 199996 kb
Host smart-f1599add-407e-4678-857e-d1fa71dc4c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892613381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.2892613381
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.3239918043
Short name T619
Test name
Test status
Simulation time 116952119148 ps
CPU time 63.8 seconds
Started Jul 30 07:42:26 PM PDT 24
Finished Jul 30 07:43:30 PM PDT 24
Peak memory 199984 kb
Host smart-53ea8c7a-d840-46b6-843f-28451663816f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239918043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.3239918043
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2347337407
Short name T182
Test name
Test status
Simulation time 88431002782 ps
CPU time 134.25 seconds
Started Jul 30 07:42:26 PM PDT 24
Finished Jul 30 07:44:41 PM PDT 24
Peak memory 199872 kb
Host smart-957aa9e4-3a52-429e-a7d2-b1e8c01979a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347337407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2347337407
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.2003338816
Short name T200
Test name
Test status
Simulation time 53646231698 ps
CPU time 93.45 seconds
Started Jul 30 07:42:31 PM PDT 24
Finished Jul 30 07:44:05 PM PDT 24
Peak memory 199952 kb
Host smart-1f92e6ec-be83-43f3-b231-01f217c70f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003338816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.2003338816
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.3734272261
Short name T683
Test name
Test status
Simulation time 13344535240 ps
CPU time 59.96 seconds
Started Jul 30 07:42:32 PM PDT 24
Finished Jul 30 07:43:32 PM PDT 24
Peak memory 199876 kb
Host smart-c639c8a1-8e69-4c77-b6b7-b6aac104b7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734272261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3734272261
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.2591361626
Short name T484
Test name
Test status
Simulation time 28550898033 ps
CPU time 64.63 seconds
Started Jul 30 07:42:30 PM PDT 24
Finished Jul 30 07:43:35 PM PDT 24
Peak memory 199952 kb
Host smart-3f1bcb36-4cbf-47ac-8372-6c599347a3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591361626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.2591361626
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1531215847
Short name T173
Test name
Test status
Simulation time 31214733606 ps
CPU time 52.45 seconds
Started Jul 30 07:42:30 PM PDT 24
Finished Jul 30 07:43:23 PM PDT 24
Peak memory 199956 kb
Host smart-3b810cc1-1ba1-4c4c-999a-6483093127fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531215847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1531215847
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3731487154
Short name T451
Test name
Test status
Simulation time 10950544 ps
CPU time 0.56 seconds
Started Jul 30 07:36:34 PM PDT 24
Finished Jul 30 07:36:35 PM PDT 24
Peak memory 195636 kb
Host smart-c791864a-8ed6-4e68-ac3e-adceb8922083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731487154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3731487154
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3806833363
Short name T280
Test name
Test status
Simulation time 85727162481 ps
CPU time 150.46 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:39:06 PM PDT 24
Peak memory 199948 kb
Host smart-8828b705-5eab-490b-b814-074c5b0ac84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806833363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3806833363
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.89863174
Short name T41
Test name
Test status
Simulation time 24511664206 ps
CPU time 39.72 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:37:14 PM PDT 24
Peak memory 199908 kb
Host smart-421e0b9a-a672-430b-8815-f36ecf0cfa6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89863174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.89863174
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3890869952
Short name T716
Test name
Test status
Simulation time 27255610646 ps
CPU time 42.93 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:37:18 PM PDT 24
Peak memory 198264 kb
Host smart-5538462d-7481-45b2-b1e4-2ac2d775b468
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890869952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3890869952
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2359450424
Short name T628
Test name
Test status
Simulation time 88444872949 ps
CPU time 113.93 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:38:31 PM PDT 24
Peak memory 199928 kb
Host smart-81e0c41e-3968-4e17-8c26-6807bcd00e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2359450424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2359450424
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.681319839
Short name T680
Test name
Test status
Simulation time 4772917252 ps
CPU time 9.98 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:36:46 PM PDT 24
Peak memory 198924 kb
Host smart-a9b20e2c-21bb-473b-9114-b215e98cc61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681319839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.681319839
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3040914914
Short name T1157
Test name
Test status
Simulation time 21344955690 ps
CPU time 35.39 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:37:11 PM PDT 24
Peak memory 200048 kb
Host smart-ddb3eb7c-28d3-4c7f-bf48-df9107c0d531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040914914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3040914914
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.965694780
Short name T1174
Test name
Test status
Simulation time 10548386004 ps
CPU time 284.32 seconds
Started Jul 30 07:36:33 PM PDT 24
Finished Jul 30 07:41:18 PM PDT 24
Peak memory 199956 kb
Host smart-3c22fac1-f882-46ec-ad39-aed3b0b0e845
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965694780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.965694780
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.463031407
Short name T935
Test name
Test status
Simulation time 1385459972 ps
CPU time 1.55 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:36:38 PM PDT 24
Peak memory 196456 kb
Host smart-f0bd4924-6b41-49a2-aa71-42c6b2772dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463031407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.463031407
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.3666280152
Short name T610
Test name
Test status
Simulation time 22684726674 ps
CPU time 34.01 seconds
Started Jul 30 07:36:34 PM PDT 24
Finished Jul 30 07:37:08 PM PDT 24
Peak memory 199992 kb
Host smart-bf8aa72f-dd1c-454c-b270-fc458d4262bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666280152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3666280152
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.3179575176
Short name T1045
Test name
Test status
Simulation time 3917895094 ps
CPU time 1.3 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:36:37 PM PDT 24
Peak memory 196460 kb
Host smart-41ff0951-633b-449e-8681-22d11524a3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179575176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.3179575176
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3308542282
Short name T30
Test name
Test status
Simulation time 36161849 ps
CPU time 0.79 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:39 PM PDT 24
Peak memory 218464 kb
Host smart-6692fb74-2102-4acd-b106-62b35e7c8dab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308542282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3308542282
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.891453757
Short name T363
Test name
Test status
Simulation time 790698048 ps
CPU time 1.22 seconds
Started Jul 30 07:36:35 PM PDT 24
Finished Jul 30 07:36:36 PM PDT 24
Peak memory 199580 kb
Host smart-ebc0c2d1-745f-4116-a836-41bf59c1e3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891453757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.891453757
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.3284461924
Short name T953
Test name
Test status
Simulation time 17218093765 ps
CPU time 173.8 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:39:30 PM PDT 24
Peak memory 215832 kb
Host smart-6451e423-4abe-4fe0-a42e-c72e4425bb94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284461924 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.3284461924
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3150562634
Short name T1066
Test name
Test status
Simulation time 1301530969 ps
CPU time 2.76 seconds
Started Jul 30 07:36:39 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 199768 kb
Host smart-65350571-2eaf-4f0b-a521-a142c071fe03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150562634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3150562634
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1159976645
Short name T276
Test name
Test status
Simulation time 318749132207 ps
CPU time 38.25 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:37:16 PM PDT 24
Peak memory 199952 kb
Host smart-d0eb740d-bcac-4b56-ab38-de2366b52521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159976645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1159976645
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.48181924
Short name T752
Test name
Test status
Simulation time 21891672 ps
CPU time 0.58 seconds
Started Jul 30 07:37:52 PM PDT 24
Finished Jul 30 07:37:52 PM PDT 24
Peak memory 195356 kb
Host smart-ebad8a86-2406-448b-afe9-bf4b565d7377
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48181924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.48181924
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.446037176
Short name T1032
Test name
Test status
Simulation time 108840324479 ps
CPU time 49.11 seconds
Started Jul 30 07:37:44 PM PDT 24
Finished Jul 30 07:38:34 PM PDT 24
Peak memory 199996 kb
Host smart-4faae6ad-3944-411a-aa16-1ce8e9fb2702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446037176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.446037176
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2269897541
Short name T968
Test name
Test status
Simulation time 135471228969 ps
CPU time 51.22 seconds
Started Jul 30 07:37:45 PM PDT 24
Finished Jul 30 07:38:37 PM PDT 24
Peak memory 199944 kb
Host smart-9d7713c5-3ad5-4357-b11b-38c46e7da4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269897541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2269897541
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.2873686245
Short name T1167
Test name
Test status
Simulation time 53260836704 ps
CPU time 25.11 seconds
Started Jul 30 07:37:44 PM PDT 24
Finished Jul 30 07:38:10 PM PDT 24
Peak memory 199944 kb
Host smart-5f1507c8-a635-45e4-abc5-f2495ee6e7af
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873686245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2873686245
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3916518875
Short name T727
Test name
Test status
Simulation time 69354022571 ps
CPU time 381.78 seconds
Started Jul 30 07:37:51 PM PDT 24
Finished Jul 30 07:44:13 PM PDT 24
Peak memory 199988 kb
Host smart-9e8c1479-c006-41c1-b37f-7b37f1ebec51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3916518875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3916518875
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2923596839
Short name T867
Test name
Test status
Simulation time 5258015398 ps
CPU time 4.04 seconds
Started Jul 30 07:37:52 PM PDT 24
Finished Jul 30 07:37:56 PM PDT 24
Peak memory 199912 kb
Host smart-ddbf14a0-497e-4888-a7d4-411ca3632e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923596839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2923596839
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1279096063
Short name T586
Test name
Test status
Simulation time 131127533609 ps
CPU time 51.2 seconds
Started Jul 30 07:37:50 PM PDT 24
Finished Jul 30 07:38:41 PM PDT 24
Peak memory 208280 kb
Host smart-a763be6c-9ba0-4c37-84e8-064b2bc424b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279096063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1279096063
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1606489880
Short name T329
Test name
Test status
Simulation time 3324918374 ps
CPU time 92.81 seconds
Started Jul 30 07:37:48 PM PDT 24
Finished Jul 30 07:39:21 PM PDT 24
Peak memory 199924 kb
Host smart-ec1047fc-d887-4625-83ec-7466101918e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1606489880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1606489880
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.3775217575
Short name T480
Test name
Test status
Simulation time 5623641488 ps
CPU time 48.89 seconds
Started Jul 30 07:37:45 PM PDT 24
Finished Jul 30 07:38:34 PM PDT 24
Peak memory 199404 kb
Host smart-ac528c39-4962-4c76-8446-74e3ab161876
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775217575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3775217575
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3958333775
Short name T122
Test name
Test status
Simulation time 89450957460 ps
CPU time 75.05 seconds
Started Jul 30 07:37:49 PM PDT 24
Finished Jul 30 07:39:04 PM PDT 24
Peak memory 199964 kb
Host smart-bfa79249-71cf-44c3-8544-4c7a5406036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958333775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3958333775
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.2578188765
Short name T945
Test name
Test status
Simulation time 4318191396 ps
CPU time 2.35 seconds
Started Jul 30 07:37:50 PM PDT 24
Finished Jul 30 07:37:53 PM PDT 24
Peak memory 196820 kb
Host smart-a26d1e52-0535-4636-bb65-cd82ca729dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578188765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.2578188765
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.2589066755
Short name T433
Test name
Test status
Simulation time 677091589 ps
CPU time 1.5 seconds
Started Jul 30 07:37:45 PM PDT 24
Finished Jul 30 07:37:47 PM PDT 24
Peak memory 199776 kb
Host smart-c895819d-183a-46c1-bb8b-eb661954e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589066755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.2589066755
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.3211017867
Short name T443
Test name
Test status
Simulation time 135118017652 ps
CPU time 1114.9 seconds
Started Jul 30 07:37:51 PM PDT 24
Finished Jul 30 07:56:27 PM PDT 24
Peak memory 227044 kb
Host smart-25f9af5c-5149-4edd-9ec0-2be691db2a80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211017867 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.3211017867
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.2637050165
Short name T298
Test name
Test status
Simulation time 2302683180 ps
CPU time 1.88 seconds
Started Jul 30 07:37:49 PM PDT 24
Finished Jul 30 07:37:51 PM PDT 24
Peak memory 199864 kb
Host smart-15798479-432d-4c1e-8172-9dbe72248d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637050165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2637050165
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1580602275
Short name T257
Test name
Test status
Simulation time 93719728026 ps
CPU time 45.43 seconds
Started Jul 30 07:37:51 PM PDT 24
Finished Jul 30 07:38:37 PM PDT 24
Peak memory 199928 kb
Host smart-daf2a1ea-75d4-49d2-92fd-6b986fa24d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580602275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1580602275
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.4094332753
Short name T217
Test name
Test status
Simulation time 57345508963 ps
CPU time 82.86 seconds
Started Jul 30 07:42:31 PM PDT 24
Finished Jul 30 07:43:54 PM PDT 24
Peak memory 199932 kb
Host smart-2a77e72d-fa50-4477-a9ee-e4defb578ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094332753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.4094332753
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.105083645
Short name T677
Test name
Test status
Simulation time 36965944345 ps
CPU time 14.55 seconds
Started Jul 30 07:42:30 PM PDT 24
Finished Jul 30 07:42:45 PM PDT 24
Peak memory 199960 kb
Host smart-163e0f78-8647-4824-91c5-533ca0310f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105083645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.105083645
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3411012298
Short name T575
Test name
Test status
Simulation time 97094991648 ps
CPU time 88.14 seconds
Started Jul 30 07:42:37 PM PDT 24
Finished Jul 30 07:44:05 PM PDT 24
Peak memory 199948 kb
Host smart-024a69a0-d468-420b-acb5-244bfe25f6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411012298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3411012298
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3906192182
Short name T603
Test name
Test status
Simulation time 143405730148 ps
CPU time 54.72 seconds
Started Jul 30 07:42:34 PM PDT 24
Finished Jul 30 07:43:29 PM PDT 24
Peak memory 200004 kb
Host smart-5e21c228-ccdd-4676-9271-528c6a6995be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906192182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3906192182
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.4168705739
Short name T176
Test name
Test status
Simulation time 23267517094 ps
CPU time 11.72 seconds
Started Jul 30 07:42:35 PM PDT 24
Finished Jul 30 07:42:47 PM PDT 24
Peak memory 199904 kb
Host smart-29690e55-9c02-4ee9-833d-14a11179f3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168705739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.4168705739
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.1747108320
Short name T658
Test name
Test status
Simulation time 28068316317 ps
CPU time 26.19 seconds
Started Jul 30 07:42:35 PM PDT 24
Finished Jul 30 07:43:01 PM PDT 24
Peak memory 199940 kb
Host smart-bdd8e894-2198-41d1-aaae-b581344e95b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747108320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.1747108320
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.3616010994
Short name T1003
Test name
Test status
Simulation time 61766254585 ps
CPU time 90.85 seconds
Started Jul 30 07:42:33 PM PDT 24
Finished Jul 30 07:44:04 PM PDT 24
Peak memory 199876 kb
Host smart-e87f5350-ea03-47e6-a673-4aba795c73bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616010994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.3616010994
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1101761864
Short name T701
Test name
Test status
Simulation time 2489388030 ps
CPU time 3.25 seconds
Started Jul 30 07:42:33 PM PDT 24
Finished Jul 30 07:42:36 PM PDT 24
Peak memory 199884 kb
Host smart-0196b93a-8d34-4000-b74f-4fb8c39d3c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101761864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1101761864
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.4030023941
Short name T191
Test name
Test status
Simulation time 30314419325 ps
CPU time 23.95 seconds
Started Jul 30 07:42:34 PM PDT 24
Finished Jul 30 07:42:58 PM PDT 24
Peak memory 199628 kb
Host smart-30d07e11-8f7f-4233-9611-3afdd63baf26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030023941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.4030023941
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2934558050
Short name T318
Test name
Test status
Simulation time 30944396984 ps
CPU time 22.52 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:43:00 PM PDT 24
Peak memory 199888 kb
Host smart-f65d9d8c-19c0-47a1-9275-c4040c74d075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934558050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2934558050
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.3556939955
Short name T722
Test name
Test status
Simulation time 16768129 ps
CPU time 0.58 seconds
Started Jul 30 07:37:56 PM PDT 24
Finished Jul 30 07:37:57 PM PDT 24
Peak memory 195392 kb
Host smart-721d983e-33d8-47d5-8018-d1958384566a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556939955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.3556939955
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3738742101
Short name T961
Test name
Test status
Simulation time 71752625973 ps
CPU time 12.5 seconds
Started Jul 30 07:37:49 PM PDT 24
Finished Jul 30 07:38:02 PM PDT 24
Peak memory 199624 kb
Host smart-56dfddca-89bc-4260-99e1-e9cb6196be2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738742101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3738742101
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.3978252005
Short name T994
Test name
Test status
Simulation time 31037283166 ps
CPU time 17.69 seconds
Started Jul 30 07:37:53 PM PDT 24
Finished Jul 30 07:38:11 PM PDT 24
Peak memory 199932 kb
Host smart-6861e1e9-108d-4ec1-ba4d-4836c3eb130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978252005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3978252005
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3051513469
Short name T138
Test name
Test status
Simulation time 14577989918 ps
CPU time 7 seconds
Started Jul 30 07:37:53 PM PDT 24
Finished Jul 30 07:38:00 PM PDT 24
Peak memory 199696 kb
Host smart-f9ce5a79-3999-4ea8-b716-9d70798fd17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051513469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3051513469
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.955230494
Short name T652
Test name
Test status
Simulation time 23145385464 ps
CPU time 35.6 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:38:31 PM PDT 24
Peak memory 199948 kb
Host smart-73f75b1d-7b9d-4956-884a-1675e7ca2ea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955230494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.955230494
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1554783360
Short name T1046
Test name
Test status
Simulation time 95295047119 ps
CPU time 846.91 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:52:02 PM PDT 24
Peak memory 199984 kb
Host smart-6e79f8d2-851d-4d51-b3b1-4fd7d1db678a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1554783360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1554783360
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1922265450
Short name T649
Test name
Test status
Simulation time 2633304071 ps
CPU time 4.62 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:38:00 PM PDT 24
Peak memory 196248 kb
Host smart-3e6345f0-b6c2-4c54-ae50-b0b548bdcd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922265450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1922265450
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.4167021115
Short name T513
Test name
Test status
Simulation time 26876282080 ps
CPU time 10.48 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 199848 kb
Host smart-d2d099dd-8f8e-4d87-9ba6-2ec0c399c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167021115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.4167021115
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1180798555
Short name T679
Test name
Test status
Simulation time 20181262179 ps
CPU time 216.47 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:41:31 PM PDT 24
Peak memory 200012 kb
Host smart-1e08aba9-dded-454d-b26c-4b4871cced43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1180798555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1180798555
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1425029180
Short name T851
Test name
Test status
Simulation time 1722342770 ps
CPU time 2.78 seconds
Started Jul 30 07:37:54 PM PDT 24
Finished Jul 30 07:37:57 PM PDT 24
Peak memory 198080 kb
Host smart-be0a862a-f459-418e-bfc3-e6c79b555004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1425029180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1425029180
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.2832975836
Short name T1014
Test name
Test status
Simulation time 143057103424 ps
CPU time 13.2 seconds
Started Jul 30 07:37:53 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 199952 kb
Host smart-8a4596c2-450e-4483-8680-bce61a592966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832975836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2832975836
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.918971508
Short name T700
Test name
Test status
Simulation time 45402842197 ps
CPU time 33.85 seconds
Started Jul 30 07:37:55 PM PDT 24
Finished Jul 30 07:38:29 PM PDT 24
Peak memory 195844 kb
Host smart-8d468160-5add-4642-a95f-cb7ea5d6ae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918971508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.918971508
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.557370147
Short name T848
Test name
Test status
Simulation time 890070671 ps
CPU time 1.49 seconds
Started Jul 30 07:37:50 PM PDT 24
Finished Jul 30 07:37:51 PM PDT 24
Peak memory 199840 kb
Host smart-0641ca8b-7c90-4fdc-9493-32b75d1aedb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557370147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.557370147
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.508677523
Short name T398
Test name
Test status
Simulation time 58068494650 ps
CPU time 89.56 seconds
Started Jul 30 07:37:57 PM PDT 24
Finished Jul 30 07:39:27 PM PDT 24
Peak memory 199916 kb
Host smart-82db0ec5-c724-498e-8598-ccee857bb2ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508677523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.508677523
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.3431645676
Short name T662
Test name
Test status
Simulation time 8705147050 ps
CPU time 115.19 seconds
Started Jul 30 07:37:54 PM PDT 24
Finished Jul 30 07:39:49 PM PDT 24
Peak memory 215372 kb
Host smart-de794f35-bd7c-4240-bccf-df1326872c60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431645676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.3431645676
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.3483046969
Short name T401
Test name
Test status
Simulation time 8374514686 ps
CPU time 11.79 seconds
Started Jul 30 07:37:54 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 199828 kb
Host smart-29c7d4f4-0d49-4836-8960-6feafc5e6498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483046969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.3483046969
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.679896849
Short name T900
Test name
Test status
Simulation time 106506196690 ps
CPU time 43.8 seconds
Started Jul 30 07:37:52 PM PDT 24
Finished Jul 30 07:38:36 PM PDT 24
Peak memory 199920 kb
Host smart-ef6bcc02-a481-4afd-ba31-f3fcd6b97ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679896849 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.679896849
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.3543968820
Short name T111
Test name
Test status
Simulation time 78950905236 ps
CPU time 34.75 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:43:13 PM PDT 24
Peak memory 199940 kb
Host smart-419cb106-2b67-4de0-8dad-c3a6f2de8ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543968820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.3543968820
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.2499144208
Short name T1138
Test name
Test status
Simulation time 109272151776 ps
CPU time 24.1 seconds
Started Jul 30 07:42:37 PM PDT 24
Finished Jul 30 07:43:02 PM PDT 24
Peak memory 199776 kb
Host smart-a0751a95-5f04-4cba-a2ae-78662bda90c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499144208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.2499144208
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.709102610
Short name T612
Test name
Test status
Simulation time 29512670242 ps
CPU time 46.27 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:43:25 PM PDT 24
Peak memory 199916 kb
Host smart-577be1c5-b91c-4606-bfd6-36890e3e2fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709102610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.709102610
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.823265784
Short name T973
Test name
Test status
Simulation time 100846666267 ps
CPU time 19.94 seconds
Started Jul 30 07:42:39 PM PDT 24
Finished Jul 30 07:42:59 PM PDT 24
Peak memory 200000 kb
Host smart-a487f87f-e87f-4605-82f9-b7b509a1ef91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823265784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.823265784
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.2338903871
Short name T1020
Test name
Test status
Simulation time 38104591655 ps
CPU time 16.47 seconds
Started Jul 30 07:42:38 PM PDT 24
Finished Jul 30 07:42:55 PM PDT 24
Peak memory 198880 kb
Host smart-a03fbe87-3f8f-46f6-a18c-0754ea7a2bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338903871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.2338903871
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.182724171
Short name T1034
Test name
Test status
Simulation time 276524908691 ps
CPU time 127.36 seconds
Started Jul 30 07:42:37 PM PDT 24
Finished Jul 30 07:44:44 PM PDT 24
Peak memory 199932 kb
Host smart-fc31c344-1136-4d79-9bc3-0142b9d1de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182724171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.182724171
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2351425398
Short name T1155
Test name
Test status
Simulation time 23089908234 ps
CPU time 41.73 seconds
Started Jul 30 07:42:42 PM PDT 24
Finished Jul 30 07:43:23 PM PDT 24
Peak memory 200048 kb
Host smart-e4af0026-ea44-4f96-bb2d-3832d1504bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351425398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2351425398
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3917085455
Short name T837
Test name
Test status
Simulation time 71741931614 ps
CPU time 111.45 seconds
Started Jul 30 07:42:49 PM PDT 24
Finished Jul 30 07:44:41 PM PDT 24
Peak memory 199952 kb
Host smart-501ee9ee-ebd9-4151-8a0e-e50d529931c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917085455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3917085455
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2935906009
Short name T890
Test name
Test status
Simulation time 14939798 ps
CPU time 0.57 seconds
Started Jul 30 07:38:06 PM PDT 24
Finished Jul 30 07:38:07 PM PDT 24
Peak memory 195636 kb
Host smart-74769ab7-3073-4711-8b3e-ca70de8f05b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935906009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2935906009
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.1296135407
Short name T811
Test name
Test status
Simulation time 28475613349 ps
CPU time 37.18 seconds
Started Jul 30 07:37:58 PM PDT 24
Finished Jul 30 07:38:35 PM PDT 24
Peak memory 199956 kb
Host smart-68f079a0-b106-41fc-992a-ce10bc35bef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296135407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1296135407
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.415197661
Short name T824
Test name
Test status
Simulation time 61359352311 ps
CPU time 61.6 seconds
Started Jul 30 07:37:57 PM PDT 24
Finished Jul 30 07:38:59 PM PDT 24
Peak memory 199928 kb
Host smart-042a32c2-ed89-49e1-a3d4-36bfaa61f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415197661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.415197661
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.3916202518
Short name T921
Test name
Test status
Simulation time 14137483155 ps
CPU time 26.26 seconds
Started Jul 30 07:37:58 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 199924 kb
Host smart-e86b4d36-92cd-46cc-b020-cacbb91c58cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916202518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.3916202518
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.61008856
Short name T814
Test name
Test status
Simulation time 3252999637 ps
CPU time 1.18 seconds
Started Jul 30 07:37:58 PM PDT 24
Finished Jul 30 07:37:59 PM PDT 24
Peak memory 196664 kb
Host smart-d7dd9e45-430a-4e3c-9584-8ea8108c9d2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61008856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.61008856
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1573964456
Short name T4
Test name
Test status
Simulation time 94422025581 ps
CPU time 520.43 seconds
Started Jul 30 07:37:59 PM PDT 24
Finished Jul 30 07:46:40 PM PDT 24
Peak memory 199948 kb
Host smart-5e895f6c-8d8b-4822-9629-8540094be0b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1573964456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1573964456
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1822502761
Short name T348
Test name
Test status
Simulation time 1567008680 ps
CPU time 3.07 seconds
Started Jul 30 07:38:05 PM PDT 24
Finished Jul 30 07:38:08 PM PDT 24
Peak memory 196128 kb
Host smart-b4e4f102-d6d4-4870-987d-622e373ce538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822502761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1822502761
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.166644683
Short name T1027
Test name
Test status
Simulation time 135457107704 ps
CPU time 15.78 seconds
Started Jul 30 07:37:57 PM PDT 24
Finished Jul 30 07:38:13 PM PDT 24
Peak memory 208252 kb
Host smart-21e50ddc-85c2-4226-9a2a-879285a498f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166644683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.166644683
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.466596173
Short name T620
Test name
Test status
Simulation time 14830044065 ps
CPU time 329.18 seconds
Started Jul 30 07:38:01 PM PDT 24
Finished Jul 30 07:43:30 PM PDT 24
Peak memory 199960 kb
Host smart-be2a98b0-75ef-4ddb-815d-eacfd63652c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466596173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.466596173
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.3671427261
Short name T15
Test name
Test status
Simulation time 7011046019 ps
CPU time 13.7 seconds
Started Jul 30 07:38:00 PM PDT 24
Finished Jul 30 07:38:13 PM PDT 24
Peak memory 198644 kb
Host smart-9e7c1f81-b9bc-4158-9cc3-415f398888dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3671427261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3671427261
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.4222716806
Short name T570
Test name
Test status
Simulation time 25075098756 ps
CPU time 34.73 seconds
Started Jul 30 07:38:00 PM PDT 24
Finished Jul 30 07:38:35 PM PDT 24
Peak memory 199884 kb
Host smart-d6be703f-fb6e-4e3d-8d1f-53b2bb0ec66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222716806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4222716806
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1838484730
Short name T905
Test name
Test status
Simulation time 30800665744 ps
CPU time 23.37 seconds
Started Jul 30 07:37:57 PM PDT 24
Finished Jul 30 07:38:21 PM PDT 24
Peak memory 196820 kb
Host smart-b412b243-6af0-428b-b12d-a4f213f54f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838484730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1838484730
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3790464521
Short name T1118
Test name
Test status
Simulation time 6067949552 ps
CPU time 17.14 seconds
Started Jul 30 07:37:57 PM PDT 24
Finished Jul 30 07:38:14 PM PDT 24
Peak memory 199772 kb
Host smart-a5f5de6a-7ac1-4b27-b92c-dac8b0be5c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790464521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3790464521
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.2082248625
Short name T508
Test name
Test status
Simulation time 80880292452 ps
CPU time 122.37 seconds
Started Jul 30 07:38:06 PM PDT 24
Finished Jul 30 07:40:09 PM PDT 24
Peak memory 199976 kb
Host smart-be7627ff-e3ec-4a2b-aec0-ba8c96b97881
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082248625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.2082248625
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3250101855
Short name T323
Test name
Test status
Simulation time 556410447472 ps
CPU time 1563.16 seconds
Started Jul 30 07:38:02 PM PDT 24
Finished Jul 30 08:04:05 PM PDT 24
Peak memory 231732 kb
Host smart-3f5ac776-950c-409d-bab0-acc5d0443c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250101855 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3250101855
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.3309745832
Short name T498
Test name
Test status
Simulation time 977356653 ps
CPU time 3.28 seconds
Started Jul 30 07:38:00 PM PDT 24
Finished Jul 30 07:38:04 PM PDT 24
Peak memory 198264 kb
Host smart-e10414b1-02ad-4e67-bf09-db9d453c83f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309745832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.3309745832
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.2715317503
Short name T997
Test name
Test status
Simulation time 43040882412 ps
CPU time 70.74 seconds
Started Jul 30 07:37:56 PM PDT 24
Finished Jul 30 07:39:07 PM PDT 24
Peak memory 200008 kb
Host smart-fbede6c2-d4af-45c2-a88b-0304b9d587d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715317503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2715317503
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.1231740430
Short name T595
Test name
Test status
Simulation time 26208049828 ps
CPU time 48.17 seconds
Started Jul 30 07:42:48 PM PDT 24
Finished Jul 30 07:43:36 PM PDT 24
Peak memory 199880 kb
Host smart-d1a71532-62e8-4cc3-b785-f24f1c3a91aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231740430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.1231740430
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3271584694
Short name T511
Test name
Test status
Simulation time 65794776227 ps
CPU time 23.46 seconds
Started Jul 30 07:42:48 PM PDT 24
Finished Jul 30 07:43:11 PM PDT 24
Peak memory 199932 kb
Host smart-8c9e86ed-abf5-40f5-8774-d8cd35b02bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271584694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3271584694
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2493104515
Short name T747
Test name
Test status
Simulation time 38669548080 ps
CPU time 63.86 seconds
Started Jul 30 07:42:47 PM PDT 24
Finished Jul 30 07:43:51 PM PDT 24
Peak memory 199892 kb
Host smart-6610722f-c328-4fee-9f21-a5d4e0156f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493104515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2493104515
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1205578668
Short name T772
Test name
Test status
Simulation time 62841813986 ps
CPU time 54.46 seconds
Started Jul 30 07:42:46 PM PDT 24
Finished Jul 30 07:43:40 PM PDT 24
Peak memory 199912 kb
Host smart-1c7a18a9-ca2e-4f94-826d-6a50fb49b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205578668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1205578668
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1267169413
Short name T177
Test name
Test status
Simulation time 17156989721 ps
CPU time 18 seconds
Started Jul 30 07:42:48 PM PDT 24
Finished Jul 30 07:43:06 PM PDT 24
Peak memory 199952 kb
Host smart-3bf57957-ada7-41d5-9638-9b7115912338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267169413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1267169413
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.4103336884
Short name T1169
Test name
Test status
Simulation time 190689106720 ps
CPU time 26.41 seconds
Started Jul 30 07:42:46 PM PDT 24
Finished Jul 30 07:43:12 PM PDT 24
Peak memory 199904 kb
Host smart-e0686ccb-2fd6-4afb-a4e8-571b1e791ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103336884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.4103336884
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3746887589
Short name T491
Test name
Test status
Simulation time 17803660528 ps
CPU time 26.22 seconds
Started Jul 30 07:42:47 PM PDT 24
Finished Jul 30 07:43:13 PM PDT 24
Peak memory 199924 kb
Host smart-033952d2-da40-4338-acd7-7c23ce4d0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746887589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3746887589
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3557877453
Short name T291
Test name
Test status
Simulation time 194638152934 ps
CPU time 70.26 seconds
Started Jul 30 07:42:46 PM PDT 24
Finished Jul 30 07:43:56 PM PDT 24
Peak memory 199908 kb
Host smart-972d8533-8c9c-4ba5-9811-0e8ef3305c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557877453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3557877453
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.3571004477
Short name T697
Test name
Test status
Simulation time 22091733154 ps
CPU time 8.14 seconds
Started Jul 30 07:42:47 PM PDT 24
Finished Jul 30 07:42:55 PM PDT 24
Peak memory 199756 kb
Host smart-63eddd5f-f59e-4453-a14e-d08e53ccea00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571004477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.3571004477
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.116370267
Short name T535
Test name
Test status
Simulation time 37066317504 ps
CPU time 16.18 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:43:06 PM PDT 24
Peak memory 199920 kb
Host smart-a1408207-6dec-42b6-94ce-3b843d5d0a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116370267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.116370267
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1893215454
Short name T106
Test name
Test status
Simulation time 68535304 ps
CPU time 0.54 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:38:09 PM PDT 24
Peak memory 194760 kb
Host smart-cf539ab5-f5e7-47c9-ac6e-8513c6d1b14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893215454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1893215454
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1897593036
Short name T146
Test name
Test status
Simulation time 46334297845 ps
CPU time 37.86 seconds
Started Jul 30 07:38:05 PM PDT 24
Finished Jul 30 07:38:43 PM PDT 24
Peak memory 199900 kb
Host smart-5647c1ef-0d7b-400f-a401-cd53310f2e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897593036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1897593036
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.981745654
Short name T309
Test name
Test status
Simulation time 175155310563 ps
CPU time 67.97 seconds
Started Jul 30 07:38:04 PM PDT 24
Finished Jul 30 07:39:12 PM PDT 24
Peak memory 199712 kb
Host smart-019ee37e-2531-4d9f-a50f-1216f70ed955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981745654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.981745654
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.96189691
Short name T180
Test name
Test status
Simulation time 39747375851 ps
CPU time 63.91 seconds
Started Jul 30 07:38:03 PM PDT 24
Finished Jul 30 07:39:07 PM PDT 24
Peak memory 199956 kb
Host smart-abab2ce5-53b7-401a-b613-134fcdd22132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96189691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.96189691
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.153426752
Short name T810
Test name
Test status
Simulation time 118968648232 ps
CPU time 166.48 seconds
Started Jul 30 07:38:10 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 199912 kb
Host smart-5cbf354f-716e-459f-8027-a5ffbba51cdb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153426752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.153426752
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.1646872244
Short name T988
Test name
Test status
Simulation time 2203171592 ps
CPU time 2.67 seconds
Started Jul 30 07:38:05 PM PDT 24
Finished Jul 30 07:38:08 PM PDT 24
Peak memory 197320 kb
Host smart-defca3d5-eeab-4645-b2d8-36c1cf9b88dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646872244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1646872244
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1313198270
Short name T252
Test name
Test status
Simulation time 270201348652 ps
CPU time 192.93 seconds
Started Jul 30 07:38:04 PM PDT 24
Finished Jul 30 07:41:17 PM PDT 24
Peak memory 199308 kb
Host smart-3e1a6130-a9f8-4a34-a2c0-391ec81772c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313198270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1313198270
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.623111685
Short name T1173
Test name
Test status
Simulation time 8863353468 ps
CPU time 33.87 seconds
Started Jul 30 07:38:04 PM PDT 24
Finished Jul 30 07:38:38 PM PDT 24
Peak memory 199900 kb
Host smart-6afec20b-e548-401b-9ceb-44a3fff59aff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=623111685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.623111685
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1057813877
Short name T470
Test name
Test status
Simulation time 1730744367 ps
CPU time 2.22 seconds
Started Jul 30 07:38:04 PM PDT 24
Finished Jul 30 07:38:06 PM PDT 24
Peak memory 198408 kb
Host smart-3eef4025-41ca-4364-8b77-fcb1ed1f31b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057813877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1057813877
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1763518959
Short name T405
Test name
Test status
Simulation time 34740781852 ps
CPU time 14.41 seconds
Started Jul 30 07:38:05 PM PDT 24
Finished Jul 30 07:38:20 PM PDT 24
Peak memory 199500 kb
Host smart-513fe5a3-ce00-472f-8d51-c3b33f156c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763518959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1763518959
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.720710822
Short name T366
Test name
Test status
Simulation time 541251979 ps
CPU time 1.48 seconds
Started Jul 30 07:38:07 PM PDT 24
Finished Jul 30 07:38:09 PM PDT 24
Peak memory 195484 kb
Host smart-7709abba-bfd0-46cb-bf7e-8fd7dc27645d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720710822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.720710822
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.103855732
Short name T775
Test name
Test status
Simulation time 935642132 ps
CPU time 4.25 seconds
Started Jul 30 07:38:05 PM PDT 24
Finished Jul 30 07:38:09 PM PDT 24
Peak memory 198824 kb
Host smart-d1768769-d32a-457e-aa92-0e29f5dca94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103855732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.103855732
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.4141972113
Short name T669
Test name
Test status
Simulation time 168002336439 ps
CPU time 1454.01 seconds
Started Jul 30 07:38:08 PM PDT 24
Finished Jul 30 08:02:22 PM PDT 24
Peak memory 199844 kb
Host smart-7464a0db-59d8-461f-be6b-4516c937f542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141972113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4141972113
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.2528192850
Short name T922
Test name
Test status
Simulation time 264527197878 ps
CPU time 418.47 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:45:08 PM PDT 24
Peak memory 216576 kb
Host smart-afb1d2b0-fbf6-44be-bc45-7d6ad90eda88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528192850 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.2528192850
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.1642942626
Short name T1132
Test name
Test status
Simulation time 1473643828 ps
CPU time 2.39 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:38:12 PM PDT 24
Peak memory 199512 kb
Host smart-a12e6bff-7002-4764-884b-64fc8da8229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642942626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.1642942626
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.2392091580
Short name T939
Test name
Test status
Simulation time 67038315628 ps
CPU time 31.59 seconds
Started Jul 30 07:38:03 PM PDT 24
Finished Jul 30 07:38:35 PM PDT 24
Peak memory 199964 kb
Host smart-4f9b2704-4908-4f1d-9d08-b7e4b7cf5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392091580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.2392091580
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.1570275184
Short name T542
Test name
Test status
Simulation time 20495252763 ps
CPU time 11.66 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:43:02 PM PDT 24
Peak memory 199952 kb
Host smart-eaa8192f-979c-4e1a-af92-ec3b1f4b6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570275184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.1570275184
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1588953784
Short name T187
Test name
Test status
Simulation time 44843295247 ps
CPU time 13.28 seconds
Started Jul 30 07:42:49 PM PDT 24
Finished Jul 30 07:43:03 PM PDT 24
Peak memory 199940 kb
Host smart-f27d8ff9-4fce-46ac-8b74-5a44e7f51d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588953784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1588953784
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.824836001
Short name T370
Test name
Test status
Simulation time 136309460790 ps
CPU time 183.17 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:45:54 PM PDT 24
Peak memory 199948 kb
Host smart-4099e614-fa32-49cc-96a1-6f7ab9083f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824836001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.824836001
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.4002153743
Short name T409
Test name
Test status
Simulation time 18808930450 ps
CPU time 30.38 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:43:20 PM PDT 24
Peak memory 199944 kb
Host smart-a0c6d55a-0d12-44ca-9fe9-53d96a9e32bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002153743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.4002153743
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.3507147350
Short name T579
Test name
Test status
Simulation time 36423450181 ps
CPU time 15.17 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:43:06 PM PDT 24
Peak memory 199964 kb
Host smart-928e640b-f028-410d-9e25-8f1191564849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507147350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.3507147350
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.1310088505
Short name T943
Test name
Test status
Simulation time 29973926074 ps
CPU time 54.09 seconds
Started Jul 30 07:42:50 PM PDT 24
Finished Jul 30 07:43:44 PM PDT 24
Peak memory 199932 kb
Host smart-ba02ff18-83fc-4f16-becc-7f42f87a9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310088505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1310088505
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2471607881
Short name T834
Test name
Test status
Simulation time 40693699858 ps
CPU time 33.77 seconds
Started Jul 30 07:42:52 PM PDT 24
Finished Jul 30 07:43:26 PM PDT 24
Peak memory 199888 kb
Host smart-868442c0-ce04-4f67-a53b-eecc80b8b65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471607881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2471607881
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.3197660348
Short name T472
Test name
Test status
Simulation time 15373816 ps
CPU time 0.57 seconds
Started Jul 30 07:38:13 PM PDT 24
Finished Jul 30 07:38:14 PM PDT 24
Peak memory 195632 kb
Host smart-6e62664d-11cd-4418-950e-87b1a24e9b78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197660348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.3197660348
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.4003835771
Short name T715
Test name
Test status
Simulation time 47966207828 ps
CPU time 76.27 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:39:25 PM PDT 24
Peak memory 199880 kb
Host smart-198ca5d6-e13f-4c92-9968-966bdce6dc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003835771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.4003835771
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2307855714
Short name T744
Test name
Test status
Simulation time 20039418899 ps
CPU time 16.22 seconds
Started Jul 30 07:38:08 PM PDT 24
Finished Jul 30 07:38:25 PM PDT 24
Peak memory 199892 kb
Host smart-ac03048a-160d-4126-836b-62f1412303a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307855714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2307855714
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.1786653079
Short name T117
Test name
Test status
Simulation time 138817029425 ps
CPU time 208.94 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:41:38 PM PDT 24
Peak memory 199848 kb
Host smart-a399879b-0025-47be-b58f-beb35a9f3456
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786653079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.1786653079
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.1037934371
Short name T668
Test name
Test status
Simulation time 132416224782 ps
CPU time 218.19 seconds
Started Jul 30 07:38:14 PM PDT 24
Finished Jul 30 07:41:52 PM PDT 24
Peak memory 199948 kb
Host smart-8a9a5010-a273-4df1-8fec-00da24091acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1037934371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1037934371
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1587708635
Short name T767
Test name
Test status
Simulation time 7523664131 ps
CPU time 12.39 seconds
Started Jul 30 07:38:13 PM PDT 24
Finished Jul 30 07:38:26 PM PDT 24
Peak memory 197780 kb
Host smart-daf5afc2-9349-43b5-832b-7007c0d7b85f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587708635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1587708635
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.2955514840
Short name T949
Test name
Test status
Simulation time 50711727153 ps
CPU time 75.56 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:39:25 PM PDT 24
Peak memory 199896 kb
Host smart-dc7cf792-e3b8-46d0-88ec-2984dead31dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955514840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.2955514840
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.3272222273
Short name T388
Test name
Test status
Simulation time 10675969998 ps
CPU time 147.27 seconds
Started Jul 30 07:38:12 PM PDT 24
Finished Jul 30 07:40:39 PM PDT 24
Peak memory 199944 kb
Host smart-33a2bf6b-9a66-42c0-9ba9-0e2450057e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3272222273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3272222273
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1563422281
Short name T1055
Test name
Test status
Simulation time 4529842986 ps
CPU time 16.62 seconds
Started Jul 30 07:38:08 PM PDT 24
Finished Jul 30 07:38:25 PM PDT 24
Peak memory 198096 kb
Host smart-0165827c-8e07-4643-a31e-55d44c1aabd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1563422281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1563422281
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.909900913
Short name T533
Test name
Test status
Simulation time 107599477039 ps
CPU time 84.83 seconds
Started Jul 30 07:38:12 PM PDT 24
Finished Jul 30 07:39:37 PM PDT 24
Peak memory 199932 kb
Host smart-9f2eb04a-e189-4fbe-aeb7-ed4eb7a530a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909900913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.909900913
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.1444983092
Short name T781
Test name
Test status
Simulation time 4266383923 ps
CPU time 3.3 seconds
Started Jul 30 07:38:10 PM PDT 24
Finished Jul 30 07:38:13 PM PDT 24
Peak memory 196856 kb
Host smart-6df256b8-fc9b-4bee-8078-1620e619c6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444983092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.1444983092
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.4206072795
Short name T1039
Test name
Test status
Simulation time 690468702 ps
CPU time 2.6 seconds
Started Jul 30 07:38:08 PM PDT 24
Finished Jul 30 07:38:10 PM PDT 24
Peak memory 198828 kb
Host smart-c9d04677-77c0-40cd-99ab-1553f0d5e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206072795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.4206072795
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1926118103
Short name T296
Test name
Test status
Simulation time 95245055790 ps
CPU time 660.65 seconds
Started Jul 30 07:38:14 PM PDT 24
Finished Jul 30 07:49:15 PM PDT 24
Peak memory 228980 kb
Host smart-816fbf9c-1469-41d5-8c5e-bb8b9810c148
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926118103 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1926118103
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.3943998515
Short name T1151
Test name
Test status
Simulation time 9151193019 ps
CPU time 8.44 seconds
Started Jul 30 07:38:14 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 199972 kb
Host smart-0cf18473-0b86-4e10-b77b-8aa64d4f74fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943998515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.3943998515
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2465214957
Short name T303
Test name
Test status
Simulation time 93862062928 ps
CPU time 143.41 seconds
Started Jul 30 07:38:09 PM PDT 24
Finished Jul 30 07:40:33 PM PDT 24
Peak memory 199988 kb
Host smart-94518bc9-b879-4d8b-ad29-c37d2b7d230b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465214957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2465214957
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.1106333562
Short name T1163
Test name
Test status
Simulation time 71102703706 ps
CPU time 74.89 seconds
Started Jul 30 07:42:55 PM PDT 24
Finished Jul 30 07:44:10 PM PDT 24
Peak memory 199992 kb
Host smart-c41a5e82-e98e-4ffd-a9e9-9f547a734e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106333562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.1106333562
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.2177999514
Short name T957
Test name
Test status
Simulation time 36024095648 ps
CPU time 83.99 seconds
Started Jul 30 07:42:54 PM PDT 24
Finished Jul 30 07:44:18 PM PDT 24
Peak memory 199940 kb
Host smart-aed8e449-99b0-43f5-bc7c-0594bdc32325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177999514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.2177999514
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.664973464
Short name T434
Test name
Test status
Simulation time 31656737111 ps
CPU time 25.3 seconds
Started Jul 30 07:42:53 PM PDT 24
Finished Jul 30 07:43:19 PM PDT 24
Peak memory 199952 kb
Host smart-54a16030-c528-4ba2-b77e-6e9ec6fb97fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664973464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.664973464
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3804765458
Short name T493
Test name
Test status
Simulation time 24157704196 ps
CPU time 20.09 seconds
Started Jul 30 07:42:57 PM PDT 24
Finished Jul 30 07:43:17 PM PDT 24
Peak memory 199704 kb
Host smart-70257b42-56de-4ba5-9ff1-7568baad7ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804765458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3804765458
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.2353034675
Short name T1075
Test name
Test status
Simulation time 186891063171 ps
CPU time 548.01 seconds
Started Jul 30 07:42:54 PM PDT 24
Finished Jul 30 07:52:02 PM PDT 24
Peak memory 200000 kb
Host smart-ec82a750-4c51-480b-8a67-19ec2a472808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353034675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.2353034675
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2026775852
Short name T273
Test name
Test status
Simulation time 71395154493 ps
CPU time 51.95 seconds
Started Jul 30 07:42:56 PM PDT 24
Finished Jul 30 07:43:48 PM PDT 24
Peak memory 199992 kb
Host smart-76584551-1437-417e-867c-f48e0d63844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026775852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2026775852
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.2804327850
Short name T143
Test name
Test status
Simulation time 358559866351 ps
CPU time 54.73 seconds
Started Jul 30 07:42:55 PM PDT 24
Finished Jul 30 07:43:50 PM PDT 24
Peak memory 199948 kb
Host smart-edfaa38c-87a7-4bf7-9b3c-2ba79e0366bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804327850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2804327850
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2107979004
Short name T156
Test name
Test status
Simulation time 12793741667 ps
CPU time 10.74 seconds
Started Jul 30 07:42:54 PM PDT 24
Finished Jul 30 07:43:05 PM PDT 24
Peak memory 199832 kb
Host smart-2a850e71-d0e1-4926-b1bf-f8b70638b4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107979004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2107979004
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.26501713
Short name T165
Test name
Test status
Simulation time 21645871036 ps
CPU time 11.14 seconds
Started Jul 30 07:42:53 PM PDT 24
Finished Jul 30 07:43:04 PM PDT 24
Peak memory 199784 kb
Host smart-aa98bb90-f47e-43ee-8c7a-6248e1d4f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26501713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.26501713
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2677665660
Short name T958
Test name
Test status
Simulation time 11834462106 ps
CPU time 20.19 seconds
Started Jul 30 07:42:55 PM PDT 24
Finished Jul 30 07:43:15 PM PDT 24
Peak memory 199912 kb
Host smart-94609d5d-123e-4f58-9124-a473de3bf68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677665660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2677665660
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1579572003
Short name T853
Test name
Test status
Simulation time 19761384 ps
CPU time 0.54 seconds
Started Jul 30 07:38:15 PM PDT 24
Finished Jul 30 07:38:16 PM PDT 24
Peak memory 194328 kb
Host smart-0d058004-a515-4833-bd1d-d4fab1b1b28d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579572003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1579572003
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.2388194777
Short name T888
Test name
Test status
Simulation time 154114564289 ps
CPU time 230.15 seconds
Started Jul 30 07:38:12 PM PDT 24
Finished Jul 30 07:42:03 PM PDT 24
Peak memory 199932 kb
Host smart-751434d3-9b53-4f92-b53f-eacae708e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388194777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.2388194777
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.2533770341
Short name T249
Test name
Test status
Simulation time 97150331564 ps
CPU time 27.23 seconds
Started Jul 30 07:38:14 PM PDT 24
Finished Jul 30 07:38:41 PM PDT 24
Peak memory 199968 kb
Host smart-31136df6-8632-4b99-9615-9720f0e7eab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533770341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.2533770341
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.509578161
Short name T740
Test name
Test status
Simulation time 29505367810 ps
CPU time 6.23 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 199908 kb
Host smart-4212e07a-252c-4e04-97e8-f6bfdcaaeaaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509578161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.509578161
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.3678483632
Short name T991
Test name
Test status
Simulation time 291882364414 ps
CPU time 515.75 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:46:52 PM PDT 24
Peak memory 199916 kb
Host smart-d66bc120-5c4e-43e4-947d-fce752b2762f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3678483632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.3678483632
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.1663115150
Short name T1087
Test name
Test status
Simulation time 6963901775 ps
CPU time 16.42 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:38:33 PM PDT 24
Peak memory 199940 kb
Host smart-845d3ae8-8515-481b-9cea-d97f0f47ed77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663115150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.1663115150
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.3259649183
Short name T832
Test name
Test status
Simulation time 69243632871 ps
CPU time 32.08 seconds
Started Jul 30 07:38:17 PM PDT 24
Finished Jul 30 07:38:49 PM PDT 24
Peak memory 200272 kb
Host smart-c4d65fb6-0354-4a02-9c8b-5a730ceaf1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259649183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.3259649183
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.270310117
Short name T860
Test name
Test status
Simulation time 18832973914 ps
CPU time 279.05 seconds
Started Jul 30 07:38:17 PM PDT 24
Finished Jul 30 07:42:57 PM PDT 24
Peak memory 199964 kb
Host smart-f260c33c-70f9-4bcf-984c-522cc0eb3f42
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270310117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.270310117
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.2578353563
Short name T471
Test name
Test status
Simulation time 3816743482 ps
CPU time 30.29 seconds
Started Jul 30 07:38:15 PM PDT 24
Finished Jul 30 07:38:46 PM PDT 24
Peak memory 198032 kb
Host smart-6d068a0f-4dbc-474b-a44f-f625f7bfe530
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2578353563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2578353563
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3785216387
Short name T1131
Test name
Test status
Simulation time 136801026069 ps
CPU time 45.6 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:39:02 PM PDT 24
Peak memory 199852 kb
Host smart-1417b6f4-b4bc-4c61-9ac5-44a7c51c0693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785216387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3785216387
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.3689160749
Short name T910
Test name
Test status
Simulation time 6022335523 ps
CPU time 1.22 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:38:17 PM PDT 24
Peak memory 196116 kb
Host smart-ddea6b54-fd3c-4581-8f81-f58814515d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689160749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.3689160749
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.2752568402
Short name T459
Test name
Test status
Simulation time 692594749 ps
CPU time 1.49 seconds
Started Jul 30 07:38:12 PM PDT 24
Finished Jul 30 07:38:13 PM PDT 24
Peak memory 198608 kb
Host smart-d30a1196-cc38-4d73-b935-93649b48573e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752568402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2752568402
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.1444127123
Short name T911
Test name
Test status
Simulation time 216249104614 ps
CPU time 525.82 seconds
Started Jul 30 07:38:15 PM PDT 24
Finished Jul 30 07:47:01 PM PDT 24
Peak memory 224916 kb
Host smart-9e9a566a-865d-4066-9720-960178b67c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444127123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.1444127123
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2041570835
Short name T1158
Test name
Test status
Simulation time 7595838147 ps
CPU time 11.93 seconds
Started Jul 30 07:38:15 PM PDT 24
Finished Jul 30 07:38:28 PM PDT 24
Peak memory 199552 kb
Host smart-bba3be0f-9f7a-46ea-ae3e-b9e834f1a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041570835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2041570835
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2812160495
Short name T779
Test name
Test status
Simulation time 41137394475 ps
CPU time 67.22 seconds
Started Jul 30 07:38:13 PM PDT 24
Finished Jul 30 07:39:20 PM PDT 24
Peak memory 199916 kb
Host smart-0553e3ca-94c5-4599-b7e3-f237e0930310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812160495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2812160495
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3494614594
Short name T932
Test name
Test status
Simulation time 15495944527 ps
CPU time 22.32 seconds
Started Jul 30 07:42:58 PM PDT 24
Finished Jul 30 07:43:21 PM PDT 24
Peak memory 199740 kb
Host smart-90007f59-7379-4ad5-a6ac-f1bc419be47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494614594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3494614594
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.1611365090
Short name T1114
Test name
Test status
Simulation time 30747783370 ps
CPU time 22.5 seconds
Started Jul 30 07:42:58 PM PDT 24
Finished Jul 30 07:43:21 PM PDT 24
Peak memory 199932 kb
Host smart-a8834c52-92b8-4f4c-a6d2-7601e74e6270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611365090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.1611365090
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.4048370550
Short name T206
Test name
Test status
Simulation time 155517996998 ps
CPU time 352.61 seconds
Started Jul 30 07:42:58 PM PDT 24
Finished Jul 30 07:48:51 PM PDT 24
Peak memory 199900 kb
Host smart-2cb5078c-1b5a-405b-aa44-319ef6322de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048370550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.4048370550
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.138405412
Short name T463
Test name
Test status
Simulation time 70831911144 ps
CPU time 29.05 seconds
Started Jul 30 07:42:58 PM PDT 24
Finished Jul 30 07:43:27 PM PDT 24
Peak memory 199892 kb
Host smart-4170a91f-abdb-4035-b6cb-3add55a88bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138405412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.138405412
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3142878940
Short name T645
Test name
Test status
Simulation time 94664577503 ps
CPU time 35.03 seconds
Started Jul 30 07:42:57 PM PDT 24
Finished Jul 30 07:43:32 PM PDT 24
Peak memory 199996 kb
Host smart-b0d5c618-ed9f-49d4-8f54-c2a969494135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142878940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3142878940
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3232937477
Short name T166
Test name
Test status
Simulation time 92267333347 ps
CPU time 39.57 seconds
Started Jul 30 07:42:57 PM PDT 24
Finished Jul 30 07:43:37 PM PDT 24
Peak memory 199912 kb
Host smart-a8d26a2a-e520-41f9-9a02-a7f145cc3e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232937477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3232937477
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.4061314536
Short name T666
Test name
Test status
Simulation time 109889807695 ps
CPU time 49.94 seconds
Started Jul 30 07:42:58 PM PDT 24
Finished Jul 30 07:43:48 PM PDT 24
Peak memory 199912 kb
Host smart-8e6d1e2f-6440-44a7-88cb-2cdf74135f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061314536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.4061314536
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.3281208612
Short name T799
Test name
Test status
Simulation time 114704770146 ps
CPU time 26.55 seconds
Started Jul 30 07:43:03 PM PDT 24
Finished Jul 30 07:43:30 PM PDT 24
Peak memory 199924 kb
Host smart-3bd8106d-0b05-44ca-8485-a38e65e06cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281208612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.3281208612
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.2071972182
Short name T800
Test name
Test status
Simulation time 16489960819 ps
CPU time 32.58 seconds
Started Jul 30 07:43:02 PM PDT 24
Finished Jul 30 07:43:34 PM PDT 24
Peak memory 199868 kb
Host smart-afceefca-8724-468f-9d07-9184212bb6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071972182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.2071972182
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.1676028139
Short name T246
Test name
Test status
Simulation time 152899298461 ps
CPU time 116.77 seconds
Started Jul 30 07:43:01 PM PDT 24
Finished Jul 30 07:44:58 PM PDT 24
Peak memory 199980 kb
Host smart-a7a0085e-e44b-4546-bfb1-80a43d378c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676028139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1676028139
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.4246528462
Short name T27
Test name
Test status
Simulation time 40508165 ps
CPU time 0.57 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 195624 kb
Host smart-0025e9b6-dc57-4f12-868e-06f0df3b1366
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246528462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.4246528462
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1691000722
Short name T962
Test name
Test status
Simulation time 73861533008 ps
CPU time 95.44 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:39:56 PM PDT 24
Peak memory 199892 kb
Host smart-90b258a3-f789-4648-bf14-1e0380649e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691000722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1691000722
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.1704808435
Short name T926
Test name
Test status
Simulation time 51073438767 ps
CPU time 85.69 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:39:49 PM PDT 24
Peak memory 199804 kb
Host smart-bff3f1b8-b9aa-4b3c-9116-43de477310e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704808435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1704808435
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1523719793
Short name T426
Test name
Test status
Simulation time 21986698396 ps
CPU time 16.4 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:38:36 PM PDT 24
Peak memory 199520 kb
Host smart-c471378c-762b-4efd-ad5d-024abf0d7354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523719793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1523719793
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.752058496
Short name T930
Test name
Test status
Simulation time 24123813449 ps
CPU time 19.91 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:38:40 PM PDT 24
Peak memory 199984 kb
Host smart-bd77c0ba-3ac3-45d0-96da-41bafaff46b8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752058496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.752058496
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.4222942467
Short name T510
Test name
Test status
Simulation time 133897999057 ps
CPU time 906.79 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:53:27 PM PDT 24
Peak memory 199964 kb
Host smart-190571d5-3261-4f38-a47b-a9c7256d3d95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222942467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.4222942467
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.86513109
Short name T661
Test name
Test status
Simulation time 385717751 ps
CPU time 0.97 seconds
Started Jul 30 07:38:21 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 198252 kb
Host smart-c10084e9-3bdc-4cff-b8fb-c4667ee132b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86513109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.86513109
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.226273705
Short name T956
Test name
Test status
Simulation time 54101012382 ps
CPU time 46.23 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:39:09 PM PDT 24
Peak memory 200028 kb
Host smart-48a6a98d-d0e7-4b7e-bddb-ff9f94fb8aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226273705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.226273705
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.273703099
Short name T524
Test name
Test status
Simulation time 3064818672 ps
CPU time 169.95 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:41:10 PM PDT 24
Peak memory 199872 kb
Host smart-86a4a469-3750-4e6b-bd55-2c6d7c3e6567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=273703099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.273703099
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.1291033674
Short name T830
Test name
Test status
Simulation time 1503673909 ps
CPU time 1.89 seconds
Started Jul 30 07:38:21 PM PDT 24
Finished Jul 30 07:38:23 PM PDT 24
Peak memory 198088 kb
Host smart-7ac6f0b0-be01-43cb-a705-e6181bcfe011
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1291033674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1291033674
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.697338155
Short name T355
Test name
Test status
Simulation time 185791631803 ps
CPU time 69.59 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:39:30 PM PDT 24
Peak memory 199968 kb
Host smart-9b490808-a28f-44ce-8193-b3140b115216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697338155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.697338155
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.582950419
Short name T546
Test name
Test status
Simulation time 2842867265 ps
CPU time 1.33 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 196432 kb
Host smart-649252a5-569d-48c5-94ce-418425006ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582950419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.582950419
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1259064691
Short name T667
Test name
Test status
Simulation time 310733338 ps
CPU time 1.06 seconds
Started Jul 30 07:38:16 PM PDT 24
Finished Jul 30 07:38:17 PM PDT 24
Peak memory 198304 kb
Host smart-115fbffc-cd99-4a4f-b5b0-7ce9b49520ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259064691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1259064691
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3237858350
Short name T34
Test name
Test status
Simulation time 222157166114 ps
CPU time 759.68 seconds
Started Jul 30 07:38:26 PM PDT 24
Finished Jul 30 07:51:06 PM PDT 24
Peak memory 216464 kb
Host smart-50dd605a-758d-43e0-a51c-b45f2ddd5c9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237858350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3237858350
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1475893098
Short name T17
Test name
Test status
Simulation time 7508155350 ps
CPU time 11.73 seconds
Started Jul 30 07:38:19 PM PDT 24
Finished Jul 30 07:38:31 PM PDT 24
Peak memory 199788 kb
Host smart-b9a872f9-d722-491f-86b8-c46ee31433f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475893098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1475893098
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.3066361498
Short name T589
Test name
Test status
Simulation time 54988065913 ps
CPU time 31.89 seconds
Started Jul 30 07:38:20 PM PDT 24
Finished Jul 30 07:38:51 PM PDT 24
Peak memory 199996 kb
Host smart-b87d7686-3ab2-4c5a-a06a-d34a30feb364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066361498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.3066361498
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.722889691
Short name T976
Test name
Test status
Simulation time 43993027796 ps
CPU time 35.6 seconds
Started Jul 30 07:43:02 PM PDT 24
Finished Jul 30 07:43:38 PM PDT 24
Peak memory 199704 kb
Host smart-68f7e392-3ca4-4784-9617-14b9169cd391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722889691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.722889691
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.2990319089
Short name T1150
Test name
Test status
Simulation time 69107518163 ps
CPU time 96.93 seconds
Started Jul 30 07:43:04 PM PDT 24
Finished Jul 30 07:44:41 PM PDT 24
Peak memory 199952 kb
Host smart-e158c940-f42b-457d-953d-30f66f5038d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990319089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2990319089
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4201718406
Short name T540
Test name
Test status
Simulation time 47168261000 ps
CPU time 17.51 seconds
Started Jul 30 07:43:03 PM PDT 24
Finished Jul 30 07:43:20 PM PDT 24
Peak memory 200012 kb
Host smart-3850edf8-5343-49b4-a3aa-f5ced4c29222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201718406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4201718406
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1653812297
Short name T681
Test name
Test status
Simulation time 23005669178 ps
CPU time 37.48 seconds
Started Jul 30 07:43:03 PM PDT 24
Finished Jul 30 07:43:41 PM PDT 24
Peak memory 199900 kb
Host smart-34b036f8-07b1-4593-84ac-25d2617c4154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653812297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1653812297
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1627510797
Short name T538
Test name
Test status
Simulation time 62095722863 ps
CPU time 101.57 seconds
Started Jul 30 07:43:02 PM PDT 24
Finished Jul 30 07:44:44 PM PDT 24
Peak memory 199900 kb
Host smart-de3c25df-1d25-467a-bf17-f6fbf358ec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627510797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1627510797
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1741771737
Short name T123
Test name
Test status
Simulation time 8195803847 ps
CPU time 12.94 seconds
Started Jul 30 07:43:02 PM PDT 24
Finished Jul 30 07:43:15 PM PDT 24
Peak memory 199984 kb
Host smart-e04ec9af-49f0-4f7d-8ffd-b407342dacf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741771737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1741771737
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.1152468182
Short name T194
Test name
Test status
Simulation time 133557227416 ps
CPU time 20.85 seconds
Started Jul 30 07:43:06 PM PDT 24
Finished Jul 30 07:43:27 PM PDT 24
Peak memory 199988 kb
Host smart-cfe7d422-ba7d-47f5-8151-07b86fc52b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152468182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.1152468182
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1520357946
Short name T158
Test name
Test status
Simulation time 101480257604 ps
CPU time 140.52 seconds
Started Jul 30 07:43:05 PM PDT 24
Finished Jul 30 07:45:25 PM PDT 24
Peak memory 199928 kb
Host smart-ca4eceb4-bd0b-42ea-b17a-95ac9ba6cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520357946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1520357946
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.4198320306
Short name T205
Test name
Test status
Simulation time 70346255131 ps
CPU time 21.87 seconds
Started Jul 30 07:43:07 PM PDT 24
Finished Jul 30 07:43:29 PM PDT 24
Peak memory 199944 kb
Host smart-8abc0a90-303b-42da-a713-9fe619334583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198320306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.4198320306
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2576304158
Short name T340
Test name
Test status
Simulation time 33298580 ps
CPU time 0.52 seconds
Started Jul 30 07:38:27 PM PDT 24
Finished Jul 30 07:38:28 PM PDT 24
Peak memory 195612 kb
Host smart-6ffc587f-c49e-43e6-aacc-e269af1f2241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576304158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2576304158
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.2053126043
Short name T877
Test name
Test status
Simulation time 119182024254 ps
CPU time 63.49 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:39:27 PM PDT 24
Peak memory 199992 kb
Host smart-e798c606-71b6-4324-a71b-de2613f25b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053126043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.2053126043
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3593801727
Short name T1093
Test name
Test status
Simulation time 129176406179 ps
CPU time 177.36 seconds
Started Jul 30 07:38:24 PM PDT 24
Finished Jul 30 07:41:21 PM PDT 24
Peak memory 199976 kb
Host smart-f778819f-5f48-47b8-82e5-71e1d57e5010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593801727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3593801727
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.4005755023
Short name T721
Test name
Test status
Simulation time 70459130430 ps
CPU time 18.64 seconds
Started Jul 30 07:38:24 PM PDT 24
Finished Jul 30 07:38:42 PM PDT 24
Peak memory 199876 kb
Host smart-533d5a7d-c954-44ff-a9d8-04c04671165a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005755023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.4005755023
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2419971552
Short name T622
Test name
Test status
Simulation time 43240930087 ps
CPU time 6.84 seconds
Started Jul 30 07:38:24 PM PDT 24
Finished Jul 30 07:38:30 PM PDT 24
Peak memory 196072 kb
Host smart-4fe54164-2738-40b9-b765-f8306c2f1b75
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419971552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2419971552
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1764756122
Short name T802
Test name
Test status
Simulation time 183214395642 ps
CPU time 1158.91 seconds
Started Jul 30 07:38:29 PM PDT 24
Finished Jul 30 07:57:48 PM PDT 24
Peak memory 199972 kb
Host smart-e4b29a5f-9665-474a-b130-d28987dd14be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764756122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1764756122
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2834280254
Short name T933
Test name
Test status
Simulation time 1556537132 ps
CPU time 4.28 seconds
Started Jul 30 07:38:26 PM PDT 24
Finished Jul 30 07:38:31 PM PDT 24
Peak memory 198640 kb
Host smart-218df785-ec80-47f0-8366-7b968207fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834280254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2834280254
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.1220154628
Short name T655
Test name
Test status
Simulation time 33730686292 ps
CPU time 10.22 seconds
Started Jul 30 07:38:24 PM PDT 24
Finished Jul 30 07:38:34 PM PDT 24
Peak memory 194624 kb
Host smart-68114dd7-75df-484d-b681-66575c168f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220154628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.1220154628
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.265836289
Short name T617
Test name
Test status
Simulation time 10416669529 ps
CPU time 125.68 seconds
Started Jul 30 07:38:28 PM PDT 24
Finished Jul 30 07:40:33 PM PDT 24
Peak memory 199816 kb
Host smart-644a5349-6726-45e5-9769-9df3cdf12d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=265836289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.265836289
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1350524387
Short name T1022
Test name
Test status
Simulation time 6178188731 ps
CPU time 46.62 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:39:10 PM PDT 24
Peak memory 199256 kb
Host smart-a4e9eb65-bb07-43f3-bfae-7fb15d52fcae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1350524387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1350524387
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.1788688491
Short name T148
Test name
Test status
Simulation time 17610221729 ps
CPU time 14.56 seconds
Started Jul 30 07:38:27 PM PDT 24
Finished Jul 30 07:38:41 PM PDT 24
Peak memory 199916 kb
Host smart-5639fa89-4c51-44ab-97b4-63f6c8ef511f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788688491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.1788688491
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1976776613
Short name T556
Test name
Test status
Simulation time 3807452388 ps
CPU time 1.72 seconds
Started Jul 30 07:38:27 PM PDT 24
Finished Jul 30 07:38:29 PM PDT 24
Peak memory 196112 kb
Host smart-61f939f2-f94d-418b-9d93-38572304e24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976776613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1976776613
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.449279407
Short name T623
Test name
Test status
Simulation time 900205744 ps
CPU time 3.39 seconds
Started Jul 30 07:38:25 PM PDT 24
Finished Jul 30 07:38:28 PM PDT 24
Peak memory 199576 kb
Host smart-24ef963a-3525-4fd7-8534-73a3034ac996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449279407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.449279407
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.3124464692
Short name T537
Test name
Test status
Simulation time 90420949093 ps
CPU time 38.4 seconds
Started Jul 30 07:38:27 PM PDT 24
Finished Jul 30 07:39:06 PM PDT 24
Peak memory 199956 kb
Host smart-6a09cca6-df00-408a-a02b-a03ca722122f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124464692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3124464692
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.3104303362
Short name T646
Test name
Test status
Simulation time 10700177601 ps
CPU time 170.61 seconds
Started Jul 30 07:38:27 PM PDT 24
Finished Jul 30 07:41:18 PM PDT 24
Peak memory 216080 kb
Host smart-225905d1-dc0d-4f1c-97ff-7621abaa48ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104303362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.3104303362
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.3717819423
Short name T502
Test name
Test status
Simulation time 7092157065 ps
CPU time 15.6 seconds
Started Jul 30 07:38:28 PM PDT 24
Finished Jul 30 07:38:43 PM PDT 24
Peak memory 199956 kb
Host smart-baa21872-eab9-4336-9711-2f5215d533f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717819423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.3717819423
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.510985774
Short name T712
Test name
Test status
Simulation time 68884438696 ps
CPU time 70.35 seconds
Started Jul 30 07:38:23 PM PDT 24
Finished Jul 30 07:39:33 PM PDT 24
Peak memory 199888 kb
Host smart-5a0f9577-1dcd-4504-aa24-0cd84678f0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510985774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.510985774
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.380968655
Short name T785
Test name
Test status
Simulation time 11787118751 ps
CPU time 14.86 seconds
Started Jul 30 07:43:05 PM PDT 24
Finished Jul 30 07:43:20 PM PDT 24
Peak memory 199940 kb
Host smart-f2250a7c-374d-4618-be83-bae19ddf4c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380968655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.380968655
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.804526284
Short name T688
Test name
Test status
Simulation time 17160571825 ps
CPU time 15.35 seconds
Started Jul 30 07:43:05 PM PDT 24
Finished Jul 30 07:43:20 PM PDT 24
Peak memory 199900 kb
Host smart-64f7f866-aaab-4747-b9ea-ade01c19a96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804526284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.804526284
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3220343788
Short name T664
Test name
Test status
Simulation time 37276045676 ps
CPU time 16.07 seconds
Started Jul 30 07:43:06 PM PDT 24
Finished Jul 30 07:43:22 PM PDT 24
Peak memory 199896 kb
Host smart-8ddbbd6e-2a27-4c23-8492-6bc791baf564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220343788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3220343788
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.924272062
Short name T228
Test name
Test status
Simulation time 43758642497 ps
CPU time 65.93 seconds
Started Jul 30 07:43:07 PM PDT 24
Finished Jul 30 07:44:13 PM PDT 24
Peak memory 199892 kb
Host smart-f6de0130-2f88-433b-8d7f-86f2646838b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924272062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.924272062
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2779658655
Short name T297
Test name
Test status
Simulation time 53899755159 ps
CPU time 30.89 seconds
Started Jul 30 07:43:10 PM PDT 24
Finished Jul 30 07:43:41 PM PDT 24
Peak memory 199964 kb
Host smart-17fd640e-f01d-4b1f-b1f4-bcc5d1697a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779658655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2779658655
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.311031609
Short name T894
Test name
Test status
Simulation time 47748076053 ps
CPU time 21.25 seconds
Started Jul 30 07:43:14 PM PDT 24
Finished Jul 30 07:43:36 PM PDT 24
Peak memory 199780 kb
Host smart-85268afe-c627-48c8-8171-7b3058016efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311031609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.311031609
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.412190109
Short name T696
Test name
Test status
Simulation time 125282268137 ps
CPU time 115.15 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:45:08 PM PDT 24
Peak memory 199956 kb
Host smart-3a87429f-11f6-46d4-8354-751e49988b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412190109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.412190109
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.2530696477
Short name T1106
Test name
Test status
Simulation time 104724574050 ps
CPU time 163.45 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:45:55 PM PDT 24
Peak memory 199948 kb
Host smart-7b9ffd58-e458-47d2-9ac1-8b4d46d2b762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530696477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2530696477
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.400461182
Short name T26
Test name
Test status
Simulation time 18373460 ps
CPU time 0.55 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:38:35 PM PDT 24
Peak memory 194800 kb
Host smart-fe3e1c07-3778-415b-a3b3-831725837539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400461182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.400461182
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3309907042
Short name T691
Test name
Test status
Simulation time 30785639820 ps
CPU time 55.07 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:39:26 PM PDT 24
Peak memory 199932 kb
Host smart-bfea63b8-a89e-4cda-bc19-ecc8fa82c5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309907042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3309907042
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.609125380
Short name T656
Test name
Test status
Simulation time 17412364532 ps
CPU time 28.02 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:38:59 PM PDT 24
Peak memory 199972 kb
Host smart-268f0e16-8929-4531-b8cb-476a7fa5611d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609125380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.609125380
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.4056193904
Short name T184
Test name
Test status
Simulation time 119820038079 ps
CPU time 48.44 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:39:19 PM PDT 24
Peak memory 199916 kb
Host smart-b710c4b8-ea27-421e-8379-cb37d736d603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056193904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.4056193904
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3413128477
Short name T702
Test name
Test status
Simulation time 44120117678 ps
CPU time 50.35 seconds
Started Jul 30 07:38:32 PM PDT 24
Finished Jul 30 07:39:22 PM PDT 24
Peak memory 199972 kb
Host smart-d646a770-18ab-44bb-9ef7-726a1b350124
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413128477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3413128477
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2104869524
Short name T539
Test name
Test status
Simulation time 121226367435 ps
CPU time 723.67 seconds
Started Jul 30 07:38:36 PM PDT 24
Finished Jul 30 07:50:40 PM PDT 24
Peak memory 199988 kb
Host smart-07721e38-6f04-42c6-86d0-a006b8e68d06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104869524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2104869524
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.2893781707
Short name T685
Test name
Test status
Simulation time 6891919114 ps
CPU time 17.68 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:38:53 PM PDT 24
Peak memory 199960 kb
Host smart-394e3ca5-f9a2-4bb7-8fe2-3d4f9a81a2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893781707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.2893781707
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4069556503
Short name T566
Test name
Test status
Simulation time 37236060714 ps
CPU time 15.06 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:38:46 PM PDT 24
Peak memory 199436 kb
Host smart-113e6d2b-f525-4631-8de9-64d40e25316d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069556503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4069556503
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.2014637055
Short name T260
Test name
Test status
Simulation time 8873471272 ps
CPU time 92.96 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:40:08 PM PDT 24
Peak memory 199936 kb
Host smart-35159764-5745-4ca8-b6f4-e75fcdee86cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2014637055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.2014637055
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.704940150
Short name T352
Test name
Test status
Simulation time 2439876299 ps
CPU time 1.59 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:38:33 PM PDT 24
Peak memory 198156 kb
Host smart-cb712a8a-6a3e-42b4-9fe5-10853a0b369b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704940150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.704940150
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.4261891737
Short name T1035
Test name
Test status
Simulation time 79818636852 ps
CPU time 32.18 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:39:08 PM PDT 24
Peak memory 199896 kb
Host smart-003bad3f-4c4f-46e2-98df-1cd3f47894d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261891737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.4261891737
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2595045704
Short name T372
Test name
Test status
Simulation time 5836779903 ps
CPU time 3.07 seconds
Started Jul 30 07:38:31 PM PDT 24
Finished Jul 30 07:38:34 PM PDT 24
Peak memory 196320 kb
Host smart-c9de3cda-f7cd-47f6-94f7-b57e0c6502ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595045704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2595045704
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.775704055
Short name T665
Test name
Test status
Simulation time 469092118 ps
CPU time 1.46 seconds
Started Jul 30 07:38:28 PM PDT 24
Finished Jul 30 07:38:29 PM PDT 24
Peak memory 198380 kb
Host smart-e8e51b42-8896-4e33-943b-2740e850ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775704055 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.775704055
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.2203243051
Short name T971
Test name
Test status
Simulation time 73318944772 ps
CPU time 119.12 seconds
Started Jul 30 07:38:36 PM PDT 24
Finished Jul 30 07:40:36 PM PDT 24
Peak memory 208240 kb
Host smart-c9ac414f-addd-4560-80f7-b87606337ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203243051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.2203243051
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1782862802
Short name T131
Test name
Test status
Simulation time 42976368896 ps
CPU time 755.29 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:51:10 PM PDT 24
Peak memory 212076 kb
Host smart-e05b2815-83e8-42e8-9f9e-43d7c5c9cc86
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782862802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1782862802
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.2701130268
Short name T1101
Test name
Test status
Simulation time 1331600453 ps
CPU time 1.56 seconds
Started Jul 30 07:38:35 PM PDT 24
Finished Jul 30 07:38:37 PM PDT 24
Peak memory 198452 kb
Host smart-152ea95f-cb12-4581-a227-bfa8da846572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701130268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.2701130268
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.3495855753
Short name T1064
Test name
Test status
Simulation time 64099439310 ps
CPU time 123.91 seconds
Started Jul 30 07:38:32 PM PDT 24
Finished Jul 30 07:40:36 PM PDT 24
Peak memory 199916 kb
Host smart-50bd68dc-a698-42d0-9b03-721940364dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495855753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.3495855753
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4017335759
Short name T850
Test name
Test status
Simulation time 94300717092 ps
CPU time 40.56 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:43:53 PM PDT 24
Peak memory 199940 kb
Host smart-0becbdf0-1cc7-4467-b478-6817aa65dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017335759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4017335759
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2391167165
Short name T324
Test name
Test status
Simulation time 30845109113 ps
CPU time 22.72 seconds
Started Jul 30 07:43:09 PM PDT 24
Finished Jul 30 07:43:32 PM PDT 24
Peak memory 200080 kb
Host smart-13b3fddf-03d3-490f-92d2-e8eb87cf55a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391167165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2391167165
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.608403077
Short name T175
Test name
Test status
Simulation time 106368918986 ps
CPU time 147.69 seconds
Started Jul 30 07:43:10 PM PDT 24
Finished Jul 30 07:45:38 PM PDT 24
Peak memory 199968 kb
Host smart-a77f70b2-b084-47a7-bdfb-b5b0390517ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608403077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.608403077
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.2690709497
Short name T778
Test name
Test status
Simulation time 93154416591 ps
CPU time 34.49 seconds
Started Jul 30 07:43:09 PM PDT 24
Finished Jul 30 07:43:44 PM PDT 24
Peak memory 199768 kb
Host smart-1fb74364-ee89-4d23-a7d1-ebe42ac7dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690709497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.2690709497
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1925600770
Short name T243
Test name
Test status
Simulation time 49398924562 ps
CPU time 79.06 seconds
Started Jul 30 07:43:11 PM PDT 24
Finished Jul 30 07:44:30 PM PDT 24
Peak memory 199888 kb
Host smart-3578e643-9a3f-434b-86ec-8cdaa0cac623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925600770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1925600770
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.2436182791
Short name T509
Test name
Test status
Simulation time 42129694675 ps
CPU time 65.65 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:44:17 PM PDT 24
Peak memory 199976 kb
Host smart-f663773c-167f-4b85-a9b7-3a1984908cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436182791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.2436182791
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2041185856
Short name T199
Test name
Test status
Simulation time 27197859317 ps
CPU time 42.65 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:43:55 PM PDT 24
Peak memory 199920 kb
Host smart-37224152-98b1-4073-8f55-0c3c9429b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041185856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2041185856
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.4198480101
Short name T525
Test name
Test status
Simulation time 18032437371 ps
CPU time 29.36 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:43:42 PM PDT 24
Peak memory 199940 kb
Host smart-fa95833a-9386-4272-8fe0-2d844820aeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198480101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.4198480101
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3770681315
Short name T870
Test name
Test status
Simulation time 24641544 ps
CPU time 0.53 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:38:40 PM PDT 24
Peak memory 194800 kb
Host smart-26d80f1e-91dc-4855-8d06-b198954d24b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770681315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3770681315
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.3253885357
Short name T547
Test name
Test status
Simulation time 103581512525 ps
CPU time 38.78 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:39:18 PM PDT 24
Peak memory 199884 kb
Host smart-721a4d17-f0a1-43aa-aa2c-de480f30ff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253885357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.3253885357
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1123177145
Short name T876
Test name
Test status
Simulation time 185380520299 ps
CPU time 91.17 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:40:10 PM PDT 24
Peak memory 199920 kb
Host smart-2cdd3cbf-6b64-49a4-aea2-1a6fab67c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123177145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1123177145
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.848860509
Short name T179
Test name
Test status
Simulation time 33218982308 ps
CPU time 31.13 seconds
Started Jul 30 07:38:40 PM PDT 24
Finished Jul 30 07:39:11 PM PDT 24
Peak memory 200080 kb
Host smart-28baf7dc-5ede-4e91-a25f-6184361284f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848860509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.848860509
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1406952215
Short name T267
Test name
Test status
Simulation time 32288201972 ps
CPU time 53.6 seconds
Started Jul 30 07:38:40 PM PDT 24
Finished Jul 30 07:39:34 PM PDT 24
Peak memory 199884 kb
Host smart-ab828f38-4263-4492-9d58-6aebbf84981e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406952215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1406952215
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.25190828
Short name T465
Test name
Test status
Simulation time 90316638748 ps
CPU time 756.99 seconds
Started Jul 30 07:38:41 PM PDT 24
Finished Jul 30 07:51:19 PM PDT 24
Peak memory 199932 kb
Host smart-b1d3c900-7410-446e-aefe-2cd6cd065c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=25190828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.25190828
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.2247448136
Short name T317
Test name
Test status
Simulation time 5866625580 ps
CPU time 6.54 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:38:54 PM PDT 24
Peak memory 199576 kb
Host smart-dc81c89b-041a-41c6-85cc-74d3eff2ee18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247448136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.2247448136
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3991618621
Short name T1025
Test name
Test status
Simulation time 54561983010 ps
CPU time 14.29 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:39:01 PM PDT 24
Peak memory 199868 kb
Host smart-2a183c33-d953-4df5-9341-9276193e8cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991618621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3991618621
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.4115724036
Short name T397
Test name
Test status
Simulation time 10221289285 ps
CPU time 75.12 seconds
Started Jul 30 07:38:46 PM PDT 24
Finished Jul 30 07:40:01 PM PDT 24
Peak memory 199864 kb
Host smart-dc2e8322-fd44-46ae-a3a8-afac94b7395e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4115724036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.4115724036
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.4290948891
Short name T550
Test name
Test status
Simulation time 1885870515 ps
CPU time 4.3 seconds
Started Jul 30 07:38:40 PM PDT 24
Finished Jul 30 07:38:44 PM PDT 24
Peak memory 197828 kb
Host smart-20555c75-5850-416d-926a-eb4a7f4223f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290948891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.4290948891
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.730672850
Short name T553
Test name
Test status
Simulation time 28703542646 ps
CPU time 19.94 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:39:07 PM PDT 24
Peak memory 199964 kb
Host smart-499d072c-827d-41ea-aa45-3d9c55ed881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730672850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.730672850
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3149013001
Short name T1037
Test name
Test status
Simulation time 644133497 ps
CPU time 0.86 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:38:40 PM PDT 24
Peak memory 195484 kb
Host smart-0cdb6550-c7fc-4335-b338-02358cda8f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149013001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3149013001
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.912155050
Short name T580
Test name
Test status
Simulation time 448561376 ps
CPU time 2.25 seconds
Started Jul 30 07:38:37 PM PDT 24
Finished Jul 30 07:38:39 PM PDT 24
Peak memory 198340 kb
Host smart-910f7996-a9d8-407e-8604-e7a2eda85c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912155050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.912155050
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.2768910744
Short name T829
Test name
Test status
Simulation time 1048431836345 ps
CPU time 216.9 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:42:16 PM PDT 24
Peak memory 208264 kb
Host smart-28e141c7-a752-4f5f-8902-14fea45bb51c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768910744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.2768910744
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.479542802
Short name T845
Test name
Test status
Simulation time 153798843238 ps
CPU time 1262.77 seconds
Started Jul 30 07:38:38 PM PDT 24
Finished Jul 30 07:59:41 PM PDT 24
Peak memory 224808 kb
Host smart-19cca2c5-75ca-4991-a959-b824c7673c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479542802 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.479542802
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.617302011
Short name T983
Test name
Test status
Simulation time 6616149590 ps
CPU time 12.55 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:38:52 PM PDT 24
Peak memory 199404 kb
Host smart-ded2e17d-9ef3-4486-a070-2c19905adf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617302011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.617302011
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.3118040923
Short name T379
Test name
Test status
Simulation time 68471483113 ps
CPU time 56.29 seconds
Started Jul 30 07:38:48 PM PDT 24
Finished Jul 30 07:39:44 PM PDT 24
Peak memory 199892 kb
Host smart-b787983d-9aa9-4a70-a571-cabeca577d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118040923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.3118040923
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.2893813484
Short name T737
Test name
Test status
Simulation time 59897744693 ps
CPU time 159.13 seconds
Started Jul 30 07:43:14 PM PDT 24
Finished Jul 30 07:45:53 PM PDT 24
Peak memory 199756 kb
Host smart-866be57c-1d13-46b3-807f-c66e816074bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893813484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.2893813484
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.1181187716
Short name T795
Test name
Test status
Simulation time 24330222696 ps
CPU time 38.43 seconds
Started Jul 30 07:43:09 PM PDT 24
Finished Jul 30 07:43:48 PM PDT 24
Peak memory 199996 kb
Host smart-7040813c-b5fe-4b35-9a9e-6f6792baaf51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181187716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.1181187716
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.2463176462
Short name T137
Test name
Test status
Simulation time 105269541990 ps
CPU time 20.75 seconds
Started Jul 30 07:43:14 PM PDT 24
Finished Jul 30 07:43:35 PM PDT 24
Peak memory 199880 kb
Host smart-6d486f3e-e920-4eac-83ac-f783dedfe876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463176462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.2463176462
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1259900112
Short name T6
Test name
Test status
Simulation time 71204032389 ps
CPU time 160.26 seconds
Started Jul 30 07:43:13 PM PDT 24
Finished Jul 30 07:45:53 PM PDT 24
Peak memory 199996 kb
Host smart-79ff20d6-f583-433f-a529-c20b22c2a3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259900112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1259900112
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2685811044
Short name T1043
Test name
Test status
Simulation time 61862902481 ps
CPU time 27.19 seconds
Started Jul 30 07:43:14 PM PDT 24
Finished Jul 30 07:43:42 PM PDT 24
Peak memory 199964 kb
Host smart-e39aaaee-5f10-4348-bbd7-d24436a3ed8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685811044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2685811044
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3245611090
Short name T425
Test name
Test status
Simulation time 101701512381 ps
CPU time 39.62 seconds
Started Jul 30 07:43:16 PM PDT 24
Finished Jul 30 07:43:55 PM PDT 24
Peak memory 199976 kb
Host smart-e7f90aeb-babe-4f10-9e89-12e15d183a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245611090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3245611090
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.7853141
Short name T208
Test name
Test status
Simulation time 158476935570 ps
CPU time 227.18 seconds
Started Jul 30 07:43:12 PM PDT 24
Finished Jul 30 07:47:00 PM PDT 24
Peak memory 199952 kb
Host smart-dead2fa6-e825-4e2a-a844-4bb51f31c458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7853141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.7853141
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1031008870
Short name T212
Test name
Test status
Simulation time 37854766596 ps
CPU time 36.28 seconds
Started Jul 30 07:43:14 PM PDT 24
Finished Jul 30 07:43:51 PM PDT 24
Peak memory 199872 kb
Host smart-17c6215d-2b0a-437c-891b-1dc74a7054b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031008870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1031008870
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3962393579
Short name T806
Test name
Test status
Simulation time 120266138751 ps
CPU time 12.16 seconds
Started Jul 30 07:43:17 PM PDT 24
Finished Jul 30 07:43:29 PM PDT 24
Peak memory 199992 kb
Host smart-8bf07df5-cb9e-4143-9627-95b0196ac295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962393579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3962393579
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.4176565144
Short name T820
Test name
Test status
Simulation time 13193462 ps
CPU time 0.57 seconds
Started Jul 30 07:36:39 PM PDT 24
Finished Jul 30 07:36:39 PM PDT 24
Peak memory 194724 kb
Host smart-1e7fe662-4b11-4a51-a715-aa38936b9a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176565144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.4176565144
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.933358371
Short name T393
Test name
Test status
Simulation time 101881350585 ps
CPU time 24.46 seconds
Started Jul 30 07:36:39 PM PDT 24
Finished Jul 30 07:37:04 PM PDT 24
Peak memory 199908 kb
Host smart-ce390316-feca-4b36-85b8-82846abc5edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933358371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.933358371
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.305185854
Short name T48
Test name
Test status
Simulation time 85410410592 ps
CPU time 109.68 seconds
Started Jul 30 07:36:39 PM PDT 24
Finished Jul 30 07:38:29 PM PDT 24
Peak memory 199800 kb
Host smart-db50c5f6-4ff0-4c47-95a0-7bfc1c012c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305185854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.305185854
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.2498038857
Short name T1127
Test name
Test status
Simulation time 40484993825 ps
CPU time 66.74 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 199924 kb
Host smart-cdb2b463-f3c9-4176-a705-5ddda50123fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498038857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.2498038857
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.882483007
Short name T1166
Test name
Test status
Simulation time 305748324329 ps
CPU time 476.41 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:44:34 PM PDT 24
Peak memory 198516 kb
Host smart-f0b7eca7-487f-4581-a538-281a3ca69c61
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882483007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.882483007
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.4081606828
Short name T351
Test name
Test status
Simulation time 67945993377 ps
CPU time 648.9 seconds
Started Jul 30 07:36:39 PM PDT 24
Finished Jul 30 07:47:28 PM PDT 24
Peak memory 199900 kb
Host smart-190d6d48-a083-420e-ba7e-ec0d82c31a82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4081606828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.4081606828
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.3813797745
Short name T316
Test name
Test status
Simulation time 2793820833 ps
CPU time 4.41 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 198712 kb
Host smart-aa31fa97-fd25-4527-8859-41f3fd9c8666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813797745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.3813797745
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.3328044071
Short name T891
Test name
Test status
Simulation time 124880294618 ps
CPU time 62.16 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 198784 kb
Host smart-7b9ad9b0-208c-4bda-9c3e-1083dbf6b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328044071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.3328044071
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2765107523
Short name T1088
Test name
Test status
Simulation time 23116065322 ps
CPU time 1351.37 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:59:09 PM PDT 24
Peak memory 199940 kb
Host smart-06a58319-c1ad-4c5d-93fa-f613554860cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2765107523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2765107523
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3213944450
Short name T333
Test name
Test status
Simulation time 3036652055 ps
CPU time 3.11 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 198096 kb
Host smart-dcc3a55d-990f-43f1-8c96-da396bdc7c3f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3213944450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3213944450
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1405490714
Short name T1041
Test name
Test status
Simulation time 9053433076 ps
CPU time 4.46 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:43 PM PDT 24
Peak memory 199068 kb
Host smart-c48cda6a-ea11-4310-bfd3-b5ca9c1a8b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405490714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1405490714
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.3810655420
Short name T343
Test name
Test status
Simulation time 1817032883 ps
CPU time 3.43 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:41 PM PDT 24
Peak memory 195464 kb
Host smart-a67ddbf7-cc23-4cfb-9b55-f926a94dfbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810655420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3810655420
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.906130275
Short name T95
Test name
Test status
Simulation time 69508177 ps
CPU time 0.85 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:36:37 PM PDT 24
Peak memory 218352 kb
Host smart-76ffb4af-a09d-4c03-9f15-f1b0ad99ecc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906130275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.906130275
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2422562133
Short name T288
Test name
Test status
Simulation time 577651343 ps
CPU time 1.16 seconds
Started Jul 30 07:36:36 PM PDT 24
Finished Jul 30 07:36:37 PM PDT 24
Peak memory 199836 kb
Host smart-96585101-da29-42ab-a277-543d9f18f6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422562133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2422562133
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.846517728
Short name T1116
Test name
Test status
Simulation time 53083820703 ps
CPU time 94.76 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:38:13 PM PDT 24
Peak memory 199876 kb
Host smart-a9ec950e-708d-4f13-ba1a-50fe9da01e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846517728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.846517728
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.4261348111
Short name T1112
Test name
Test status
Simulation time 143929200660 ps
CPU time 238.32 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:40:36 PM PDT 24
Peak memory 216664 kb
Host smart-fdf25676-bb38-4e6d-9286-c6197d4554fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261348111 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.4261348111
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.2494803473
Short name T531
Test name
Test status
Simulation time 985298676 ps
CPU time 1.48 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 198728 kb
Host smart-07ae38bc-909a-4b9d-9bc8-be636ee0b36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494803473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.2494803473
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.790875781
Short name T673
Test name
Test status
Simulation time 36774505567 ps
CPU time 70.55 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:37:48 PM PDT 24
Peak memory 199972 kb
Host smart-903f4076-b76e-427a-adf6-1406f5b7c392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790875781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.790875781
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.1637982663
Short name T1110
Test name
Test status
Simulation time 47436531 ps
CPU time 0.56 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:38:48 PM PDT 24
Peak memory 195628 kb
Host smart-b3a2a7e7-9b58-4749-a17f-aa13505f9c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637982663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.1637982663
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.660190631
Short name T614
Test name
Test status
Simulation time 89622543873 ps
CPU time 32.19 seconds
Started Jul 30 07:38:41 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 199944 kb
Host smart-7e33bd5c-d68a-44f8-8421-4d4307a775b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660190631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.660190631
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1045474993
Short name T7
Test name
Test status
Simulation time 326575350240 ps
CPU time 25.48 seconds
Started Jul 30 07:38:43 PM PDT 24
Finished Jul 30 07:39:08 PM PDT 24
Peak memory 200072 kb
Host smart-d8dde24f-7755-4174-8480-c11eb6468c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045474993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1045474993
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1023703170
Short name T605
Test name
Test status
Simulation time 111393196366 ps
CPU time 80.33 seconds
Started Jul 30 07:38:41 PM PDT 24
Finished Jul 30 07:40:02 PM PDT 24
Peak memory 199984 kb
Host smart-f479d22f-98b3-47bb-8f62-6cf4e400e025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023703170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1023703170
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3796208357
Short name T506
Test name
Test status
Simulation time 262714037954 ps
CPU time 197.09 seconds
Started Jul 30 07:38:43 PM PDT 24
Finished Jul 30 07:42:01 PM PDT 24
Peak memory 199872 kb
Host smart-32a6fb43-5201-42df-beb3-4a01130d7c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796208357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3796208357
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.829018653
Short name T477
Test name
Test status
Simulation time 10097484021 ps
CPU time 15.71 seconds
Started Jul 30 07:38:44 PM PDT 24
Finished Jul 30 07:39:00 PM PDT 24
Peak memory 199992 kb
Host smart-6fbf2a95-485d-4088-82c8-4efcfe108474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829018653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.829018653
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.2341639689
Short name T46
Test name
Test status
Simulation time 125179781525 ps
CPU time 44.98 seconds
Started Jul 30 07:38:42 PM PDT 24
Finished Jul 30 07:39:27 PM PDT 24
Peak memory 198964 kb
Host smart-4b7eac5b-6e91-46e0-9d3d-c4c04a6b1481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341639689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.2341639689
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.2412843106
Short name T964
Test name
Test status
Simulation time 10089575661 ps
CPU time 432.55 seconds
Started Jul 30 07:38:43 PM PDT 24
Finished Jul 30 07:45:56 PM PDT 24
Peak memory 199928 kb
Host smart-59189f80-c813-4025-9270-036f757bb6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412843106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2412843106
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.2193009875
Short name T663
Test name
Test status
Simulation time 2214682556 ps
CPU time 5.96 seconds
Started Jul 30 07:38:44 PM PDT 24
Finished Jul 30 07:38:50 PM PDT 24
Peak memory 198028 kb
Host smart-b0b18bf4-81f4-4a5f-adc5-9a3c0cb9d404
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2193009875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.2193009875
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2439480869
Short name T998
Test name
Test status
Simulation time 240184175465 ps
CPU time 357.92 seconds
Started Jul 30 07:38:42 PM PDT 24
Finished Jul 30 07:44:40 PM PDT 24
Peak memory 199912 kb
Host smart-4745f161-ffe8-40bf-98e2-72c23b6a512d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439480869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2439480869
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.1453852072
Short name T412
Test name
Test status
Simulation time 43455171475 ps
CPU time 57.53 seconds
Started Jul 30 07:38:41 PM PDT 24
Finished Jul 30 07:39:39 PM PDT 24
Peak memory 196468 kb
Host smart-629be306-142c-4c06-b98c-090922ada69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453852072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.1453852072
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1023791203
Short name T1079
Test name
Test status
Simulation time 428673380 ps
CPU time 2.11 seconds
Started Jul 30 07:38:46 PM PDT 24
Finished Jul 30 07:38:48 PM PDT 24
Peak memory 199524 kb
Host smart-bea34c6f-643b-43db-ac13-926c29098e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023791203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1023791203
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.1852162324
Short name T609
Test name
Test status
Simulation time 101854058955 ps
CPU time 179.07 seconds
Started Jul 30 07:38:43 PM PDT 24
Finished Jul 30 07:41:42 PM PDT 24
Peak memory 199940 kb
Host smart-fe175869-7a6e-4573-a21f-274f86c2af25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852162324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.1852162324
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3163940951
Short name T464
Test name
Test status
Simulation time 252239983822 ps
CPU time 236.81 seconds
Started Jul 30 07:38:42 PM PDT 24
Finished Jul 30 07:42:39 PM PDT 24
Peak memory 216472 kb
Host smart-83071be9-ea80-41be-ac03-3c7c9ae8df42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163940951 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3163940951
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1000474036
Short name T450
Test name
Test status
Simulation time 6631162183 ps
CPU time 20.61 seconds
Started Jul 30 07:38:44 PM PDT 24
Finished Jul 30 07:39:04 PM PDT 24
Peak memory 199780 kb
Host smart-f2f49989-132c-4e52-8713-bbbc1db908be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000474036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1000474036
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.4221312410
Short name T478
Test name
Test status
Simulation time 53913132465 ps
CPU time 99.41 seconds
Started Jul 30 07:38:39 PM PDT 24
Finished Jul 30 07:40:19 PM PDT 24
Peak memory 199868 kb
Host smart-cda70309-bffd-4af8-9da7-9115c6215fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221312410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.4221312410
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4186932430
Short name T849
Test name
Test status
Simulation time 24848625 ps
CPU time 0.55 seconds
Started Jul 30 07:38:54 PM PDT 24
Finished Jul 30 07:38:54 PM PDT 24
Peak memory 195568 kb
Host smart-bdb448a0-9293-40dc-bcc3-0d017e99a8e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186932430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4186932430
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1259880727
Short name T573
Test name
Test status
Simulation time 44052441140 ps
CPU time 17.1 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:39:04 PM PDT 24
Peak memory 200048 kb
Host smart-405d0ce0-4be4-4acf-b8ed-cedffd9d5003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259880727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1259880727
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.3474054623
Short name T790
Test name
Test status
Simulation time 17679391989 ps
CPU time 25.26 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:39:12 PM PDT 24
Peak memory 199884 kb
Host smart-e6e32e2f-5ec3-42db-89c2-6761d4b66f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474054623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.3474054623
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.2923490662
Short name T1097
Test name
Test status
Simulation time 78841309641 ps
CPU time 39.51 seconds
Started Jul 30 07:38:46 PM PDT 24
Finished Jul 30 07:39:26 PM PDT 24
Peak memory 199892 kb
Host smart-cd473268-2983-480d-bfd0-288cb4d85680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923490662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.2923490662
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1809253886
Short name T693
Test name
Test status
Simulation time 76403404342 ps
CPU time 40.38 seconds
Started Jul 30 07:38:51 PM PDT 24
Finished Jul 30 07:39:31 PM PDT 24
Peak memory 199976 kb
Host smart-f1eb4f16-9e1d-4a30-899a-72325cbab827
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809253886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1809253886
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.1840096050
Short name T885
Test name
Test status
Simulation time 38623504159 ps
CPU time 184.95 seconds
Started Jul 30 07:38:51 PM PDT 24
Finished Jul 30 07:41:56 PM PDT 24
Peak memory 200000 kb
Host smart-4b61c08c-f272-4144-a4ca-1af8e3c8ae15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840096050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1840096050
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.1410208730
Short name T990
Test name
Test status
Simulation time 355319859 ps
CPU time 1.04 seconds
Started Jul 30 07:38:51 PM PDT 24
Finished Jul 30 07:38:52 PM PDT 24
Peak memory 196752 kb
Host smart-315c9117-4583-4c28-8053-8e55d0781101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410208730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.1410208730
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3786548420
Short name T1015
Test name
Test status
Simulation time 51813854618 ps
CPU time 31.55 seconds
Started Jul 30 07:38:49 PM PDT 24
Finished Jul 30 07:39:21 PM PDT 24
Peak memory 200116 kb
Host smart-ab3753da-6abd-433b-aa07-212890301eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786548420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3786548420
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.3576984729
Short name T929
Test name
Test status
Simulation time 18458189032 ps
CPU time 245.2 seconds
Started Jul 30 07:38:52 PM PDT 24
Finished Jul 30 07:42:57 PM PDT 24
Peak memory 199944 kb
Host smart-7251cfcc-28e7-4813-a38d-eb06e5f51b1b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3576984729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.3576984729
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.2380210603
Short name T1172
Test name
Test status
Simulation time 2339388483 ps
CPU time 17.01 seconds
Started Jul 30 07:38:49 PM PDT 24
Finished Jul 30 07:39:06 PM PDT 24
Peak memory 198140 kb
Host smart-a9f33575-f094-493f-8a68-1d715e77c469
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2380210603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.2380210603
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3810406762
Short name T153
Test name
Test status
Simulation time 25799693429 ps
CPU time 42.67 seconds
Started Jul 30 07:38:47 PM PDT 24
Finished Jul 30 07:39:30 PM PDT 24
Peak memory 199936 kb
Host smart-56abadaf-bb1f-4238-9247-94262d53177c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810406762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3810406762
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.2071364129
Short name T966
Test name
Test status
Simulation time 1550472222 ps
CPU time 3.09 seconds
Started Jul 30 07:38:48 PM PDT 24
Finished Jul 30 07:38:51 PM PDT 24
Peak memory 195492 kb
Host smart-5046a6cb-4798-4cd5-9ba2-d915a0f3c633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071364129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.2071364129
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.329162400
Short name T1011
Test name
Test status
Simulation time 268965749 ps
CPU time 1.84 seconds
Started Jul 30 07:38:48 PM PDT 24
Finished Jul 30 07:38:50 PM PDT 24
Peak memory 199908 kb
Host smart-acbf1093-3222-42d4-8c82-0f029e0d6b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329162400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.329162400
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.2349804012
Short name T1146
Test name
Test status
Simulation time 63468685663 ps
CPU time 108.63 seconds
Started Jul 30 07:38:53 PM PDT 24
Finished Jul 30 07:40:41 PM PDT 24
Peak memory 199960 kb
Host smart-0618627d-f5f0-4ee8-86cc-1d29a3183b75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349804012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2349804012
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.102597351
Short name T504
Test name
Test status
Simulation time 44730327866 ps
CPU time 722.28 seconds
Started Jul 30 07:38:55 PM PDT 24
Finished Jul 30 07:50:57 PM PDT 24
Peak memory 216428 kb
Host smart-34b255c8-c274-47d5-a604-66b5f773eaa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102597351 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.102597351
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1197102682
Short name T373
Test name
Test status
Simulation time 1916226048 ps
CPU time 2.88 seconds
Started Jul 30 07:38:49 PM PDT 24
Finished Jul 30 07:38:52 PM PDT 24
Peak memory 198348 kb
Host smart-f587a23c-2287-4225-bd75-d4aeb25e1886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197102682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1197102682
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.2410053218
Short name T616
Test name
Test status
Simulation time 237270033088 ps
CPU time 51.31 seconds
Started Jul 30 07:38:46 PM PDT 24
Finished Jul 30 07:39:38 PM PDT 24
Peak memory 199996 kb
Host smart-b2a4daf9-987d-4c3e-89c5-e04c962efbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410053218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.2410053218
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.3335317429
Short name T331
Test name
Test status
Simulation time 15382381 ps
CPU time 0.61 seconds
Started Jul 30 07:39:01 PM PDT 24
Finished Jul 30 07:39:02 PM PDT 24
Peak memory 195672 kb
Host smart-265f4e4b-f367-4ec7-b0a7-e1b747785439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335317429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3335317429
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3528429776
Short name T163
Test name
Test status
Simulation time 134517037878 ps
CPU time 13.47 seconds
Started Jul 30 07:38:53 PM PDT 24
Finished Jul 30 07:39:06 PM PDT 24
Peak memory 199924 kb
Host smart-4fbb2e29-7d6e-43d3-8210-e1e2d37a1122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528429776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3528429776
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.671699398
Short name T787
Test name
Test status
Simulation time 32068939166 ps
CPU time 13.65 seconds
Started Jul 30 07:38:56 PM PDT 24
Finished Jul 30 07:39:10 PM PDT 24
Peak memory 199936 kb
Host smart-3f87aa28-a0d3-4326-a7c8-dfcbcf3831bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671699398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.671699398
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.3920115539
Short name T170
Test name
Test status
Simulation time 47737556273 ps
CPU time 69.81 seconds
Started Jul 30 07:38:54 PM PDT 24
Finished Jul 30 07:40:04 PM PDT 24
Peak memory 199992 kb
Host smart-2de427dc-62ce-4997-b8e6-ac5e4716b2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920115539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.3920115539
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.704921741
Short name T321
Test name
Test status
Simulation time 40184034341 ps
CPU time 17.18 seconds
Started Jul 30 07:38:56 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 199844 kb
Host smart-baf7c149-edb2-4fab-8117-52c5b5a49f80
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704921741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.704921741
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2973134032
Short name T1042
Test name
Test status
Simulation time 63610920497 ps
CPU time 165.9 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:41:48 PM PDT 24
Peak memory 199908 kb
Host smart-27281c3a-8eae-47cc-bf13-40dc1aabd873
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973134032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2973134032
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.1266412790
Short name T350
Test name
Test status
Simulation time 10304998221 ps
CPU time 19.12 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:39:21 PM PDT 24
Peak memory 198488 kb
Host smart-462d03a1-bff3-4c18-8cf6-32c7100ae01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266412790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.1266412790
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.1622080089
Short name T805
Test name
Test status
Simulation time 168989408975 ps
CPU time 52.49 seconds
Started Jul 30 07:38:55 PM PDT 24
Finished Jul 30 07:39:48 PM PDT 24
Peak memory 208208 kb
Host smart-675b6ef8-c998-47c5-86d9-ab74f6c64ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622080089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.1622080089
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.1872797701
Short name T1007
Test name
Test status
Simulation time 17623290131 ps
CPU time 211.86 seconds
Started Jul 30 07:38:59 PM PDT 24
Finished Jul 30 07:42:31 PM PDT 24
Peak memory 199872 kb
Host smart-6572826b-a8a3-437f-8d81-c67677076232
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872797701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.1872797701
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.2984910569
Short name T367
Test name
Test status
Simulation time 2964555502 ps
CPU time 5.78 seconds
Started Jul 30 07:38:56 PM PDT 24
Finished Jul 30 07:39:02 PM PDT 24
Peak memory 198960 kb
Host smart-84056334-9bfa-499e-9f79-53522e0f6a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2984910569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2984910569
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.1495902052
Short name T723
Test name
Test status
Simulation time 50567086315 ps
CPU time 37.3 seconds
Started Jul 30 07:38:58 PM PDT 24
Finished Jul 30 07:39:35 PM PDT 24
Peak memory 199964 kb
Host smart-27274907-468c-41f5-9a92-7d22316b3411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495902052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.1495902052
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2273383279
Short name T597
Test name
Test status
Simulation time 5144305439 ps
CPU time 1.91 seconds
Started Jul 30 07:38:58 PM PDT 24
Finished Jul 30 07:39:00 PM PDT 24
Peak memory 196120 kb
Host smart-a5d65dd1-67c9-4058-9233-ec3f93e6391e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273383279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2273383279
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.96801484
Short name T448
Test name
Test status
Simulation time 885067700 ps
CPU time 3.89 seconds
Started Jul 30 07:38:54 PM PDT 24
Finished Jul 30 07:38:58 PM PDT 24
Peak memory 198140 kb
Host smart-55e982cc-845d-41c0-98ae-baa61161d221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96801484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.96801484
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3889213880
Short name T847
Test name
Test status
Simulation time 40488833300 ps
CPU time 1259.35 seconds
Started Jul 30 07:39:01 PM PDT 24
Finished Jul 30 08:00:01 PM PDT 24
Peak memory 199976 kb
Host smart-fb0a8d72-ef5b-4955-8d90-4423274a0c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889213880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3889213880
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2314969468
Short name T1149
Test name
Test status
Simulation time 29695094001 ps
CPU time 192.53 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:42:15 PM PDT 24
Peak memory 216624 kb
Host smart-9f00166a-4f4d-4792-9c40-dbbc0382df25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314969468 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2314969468
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.4225318133
Short name T1123
Test name
Test status
Simulation time 1157734317 ps
CPU time 1.71 seconds
Started Jul 30 07:39:00 PM PDT 24
Finished Jul 30 07:39:01 PM PDT 24
Peak memory 198760 kb
Host smart-7aa216c1-4879-48ad-8076-df9754ec0836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225318133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.4225318133
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.2840974047
Short name T842
Test name
Test status
Simulation time 61015795733 ps
CPU time 55.22 seconds
Started Jul 30 07:38:56 PM PDT 24
Finished Jul 30 07:39:51 PM PDT 24
Peak memory 199928 kb
Host smart-e9fcb344-310c-42f6-9a58-775bb41e6bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840974047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.2840974047
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.203541713
Short name T415
Test name
Test status
Simulation time 140235660 ps
CPU time 0.56 seconds
Started Jul 30 07:39:05 PM PDT 24
Finished Jul 30 07:39:06 PM PDT 24
Peak memory 195384 kb
Host smart-a09e0061-ef73-4b50-9d06-1390fa52e94c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203541713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.203541713
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.1516287048
Short name T400
Test name
Test status
Simulation time 31446738872 ps
CPU time 13.1 seconds
Started Jul 30 07:39:00 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 199904 kb
Host smart-a3dd7481-2c12-4b19-8be0-89d5c26599bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516287048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.1516287048
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3871311291
Short name T71
Test name
Test status
Simulation time 33284541936 ps
CPU time 42.5 seconds
Started Jul 30 07:39:00 PM PDT 24
Finished Jul 30 07:39:42 PM PDT 24
Peak memory 199964 kb
Host smart-ee4508e2-4756-4a24-947b-b452cf163d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871311291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3871311291
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2262093169
Short name T1006
Test name
Test status
Simulation time 25885157212 ps
CPU time 21.24 seconds
Started Jul 30 07:39:01 PM PDT 24
Finished Jul 30 07:39:22 PM PDT 24
Peak memory 199888 kb
Host smart-c008804d-1182-4773-abdd-7768e3f86baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262093169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2262093169
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2583103505
Short name T746
Test name
Test status
Simulation time 76247894540 ps
CPU time 114.43 seconds
Started Jul 30 07:39:01 PM PDT 24
Finished Jul 30 07:40:56 PM PDT 24
Peak memory 199940 kb
Host smart-1af82c3c-3ab1-4854-82f7-814ebf218e8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583103505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2583103505
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.621599643
Short name T879
Test name
Test status
Simulation time 182057126848 ps
CPU time 474.94 seconds
Started Jul 30 07:39:03 PM PDT 24
Finished Jul 30 07:46:58 PM PDT 24
Peak memory 199836 kb
Host smart-073a803a-afc3-4880-90d6-5d3e3d5aca7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621599643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.621599643
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1588789424
Short name T638
Test name
Test status
Simulation time 110400952 ps
CPU time 0.76 seconds
Started Jul 30 07:39:03 PM PDT 24
Finished Jul 30 07:39:04 PM PDT 24
Peak memory 195836 kb
Host smart-8b03e81a-ac8f-4e15-b5d0-fcc0104fe1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588789424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1588789424
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.3729513953
Short name T630
Test name
Test status
Simulation time 452846816115 ps
CPU time 59.19 seconds
Started Jul 30 07:39:03 PM PDT 24
Finished Jul 30 07:40:02 PM PDT 24
Peak memory 208376 kb
Host smart-faf9a507-b7c0-4405-96c6-d376ba5e4663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729513953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.3729513953
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1899351150
Short name T476
Test name
Test status
Simulation time 7471030686 ps
CPU time 105.14 seconds
Started Jul 30 07:39:03 PM PDT 24
Finished Jul 30 07:40:48 PM PDT 24
Peak memory 199956 kb
Host smart-3e694053-a1d3-4675-8d80-bfdb563b56b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899351150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1899351150
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2138278334
Short name T855
Test name
Test status
Simulation time 5567744481 ps
CPU time 11.42 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:39:14 PM PDT 24
Peak memory 198104 kb
Host smart-7f7feb1b-c855-4e03-8c04-3f24e1be1d87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138278334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2138278334
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.4144563053
Short name T1176
Test name
Test status
Simulation time 164220351895 ps
CPU time 130.69 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:41:13 PM PDT 24
Peak memory 199992 kb
Host smart-8714b034-fedc-4368-a1f5-34ac8256a893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144563053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.4144563053
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.3424056837
Short name T982
Test name
Test status
Simulation time 46533284127 ps
CPU time 9.21 seconds
Started Jul 30 07:39:00 PM PDT 24
Finished Jul 30 07:39:09 PM PDT 24
Peak memory 195964 kb
Host smart-2736c303-d3df-43bc-81fb-8be440e0ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424056837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.3424056837
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.2588937721
Short name T346
Test name
Test status
Simulation time 247859015 ps
CPU time 1.34 seconds
Started Jul 30 07:38:59 PM PDT 24
Finished Jul 30 07:39:00 PM PDT 24
Peak memory 198224 kb
Host smart-b3329300-af7e-4e0a-bf49-1bf869f38c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588937721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.2588937721
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3107122524
Short name T460
Test name
Test status
Simulation time 331876907674 ps
CPU time 593.29 seconds
Started Jul 30 07:39:04 PM PDT 24
Finished Jul 30 07:48:58 PM PDT 24
Peak memory 208216 kb
Host smart-ac903ac9-d782-421e-83c3-5004dac0f754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107122524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3107122524
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.492118194
Short name T50
Test name
Test status
Simulation time 67635426356 ps
CPU time 365.34 seconds
Started Jul 30 07:39:03 PM PDT 24
Finished Jul 30 07:45:09 PM PDT 24
Peak memory 216072 kb
Host smart-79f8826c-56a4-44f5-8b44-c1fd2268d41a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492118194 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.492118194
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.382624645
Short name T736
Test name
Test status
Simulation time 1121401868 ps
CPU time 2.41 seconds
Started Jul 30 07:39:02 PM PDT 24
Finished Jul 30 07:39:05 PM PDT 24
Peak memory 199112 kb
Host smart-9a59b0a9-2239-4cc8-b6c9-e5f6d99d0c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382624645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.382624645
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.3514369872
Short name T796
Test name
Test status
Simulation time 38568118992 ps
CPU time 52.71 seconds
Started Jul 30 07:38:58 PM PDT 24
Finished Jul 30 07:39:51 PM PDT 24
Peak memory 199904 kb
Host smart-393dcf5d-410c-412a-ab51-dafae237c1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514369872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.3514369872
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1546236154
Short name T676
Test name
Test status
Simulation time 33594832 ps
CPU time 0.55 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:10 PM PDT 24
Peak memory 195388 kb
Host smart-fb39431a-a86b-44dd-85dc-86ee5dbf9b15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546236154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1546236154
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.623634712
Short name T920
Test name
Test status
Simulation time 221138318498 ps
CPU time 82.48 seconds
Started Jul 30 07:39:06 PM PDT 24
Finished Jul 30 07:40:29 PM PDT 24
Peak memory 199840 kb
Host smart-ac2cedef-90a9-4001-8380-cdacb06ac71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623634712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.623634712
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.219160131
Short name T1018
Test name
Test status
Simulation time 7676397768 ps
CPU time 12.53 seconds
Started Jul 30 07:39:04 PM PDT 24
Finished Jul 30 07:39:17 PM PDT 24
Peak memory 199768 kb
Host smart-35422e0f-340d-4c13-9ceb-f6976770521b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219160131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.219160131
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.3630239523
Short name T1120
Test name
Test status
Simulation time 41539599304 ps
CPU time 44.7 seconds
Started Jul 30 07:39:06 PM PDT 24
Finished Jul 30 07:39:51 PM PDT 24
Peak memory 199932 kb
Host smart-429fee60-6b48-428f-bd74-7430e8e08ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630239523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.3630239523
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2067008007
Short name T960
Test name
Test status
Simulation time 109060238861 ps
CPU time 84.07 seconds
Started Jul 30 07:39:06 PM PDT 24
Finished Jul 30 07:40:31 PM PDT 24
Peak memory 199868 kb
Host smart-a28f789a-1526-4b3b-ab4f-f68383ba94a3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067008007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2067008007
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.1770197347
Short name T903
Test name
Test status
Simulation time 121298110128 ps
CPU time 783.81 seconds
Started Jul 30 07:39:11 PM PDT 24
Finished Jul 30 07:52:15 PM PDT 24
Peak memory 199892 kb
Host smart-f87ca3f3-f4b5-429f-9702-fdd199fb3ffd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1770197347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.1770197347
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.3581557807
Short name T763
Test name
Test status
Simulation time 8604800024 ps
CPU time 19.04 seconds
Started Jul 30 07:39:11 PM PDT 24
Finished Jul 30 07:39:30 PM PDT 24
Peak memory 199608 kb
Host smart-d62527e8-7c4e-40b9-8bcc-31c849514b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581557807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3581557807
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1574092740
Short name T749
Test name
Test status
Simulation time 46474701521 ps
CPU time 9.89 seconds
Started Jul 30 07:39:05 PM PDT 24
Finished Jul 30 07:39:15 PM PDT 24
Peak memory 199920 kb
Host smart-b7b153f0-a196-47d8-b200-4c4954ed010a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574092740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1574092740
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.3549475791
Short name T642
Test name
Test status
Simulation time 13123078105 ps
CPU time 203.16 seconds
Started Jul 30 07:39:10 PM PDT 24
Finished Jul 30 07:42:33 PM PDT 24
Peak memory 199932 kb
Host smart-8e007ae8-660d-4c5d-a232-5a8fc0aac455
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3549475791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.3549475791
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.908947791
Short name T445
Test name
Test status
Simulation time 5644152296 ps
CPU time 47.24 seconds
Started Jul 30 07:39:07 PM PDT 24
Finished Jul 30 07:39:54 PM PDT 24
Peak memory 198836 kb
Host smart-89bf5d4f-db3e-493a-88b7-df15c6e5d3d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908947791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.908947791
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.4032907002
Short name T869
Test name
Test status
Simulation time 19024745410 ps
CPU time 25.48 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:34 PM PDT 24
Peak memory 199860 kb
Host smart-09d19b07-73bb-4abc-8e04-4c17e438bcdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032907002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.4032907002
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.299578243
Short name T353
Test name
Test status
Simulation time 632969307 ps
CPU time 1.66 seconds
Started Jul 30 07:39:05 PM PDT 24
Finished Jul 30 07:39:07 PM PDT 24
Peak memory 195676 kb
Host smart-2c740e76-5b6b-4dc9-91f1-466dc4ef3f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299578243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.299578243
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2044027140
Short name T618
Test name
Test status
Simulation time 6210880345 ps
CPU time 20.52 seconds
Started Jul 30 07:39:07 PM PDT 24
Finished Jul 30 07:39:28 PM PDT 24
Peak memory 199728 kb
Host smart-253144c5-32af-4410-8f05-0d9bb9662182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044027140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2044027140
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2227953581
Short name T967
Test name
Test status
Simulation time 215559617593 ps
CPU time 935.36 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:54:45 PM PDT 24
Peak memory 224788 kb
Host smart-6628f45e-310c-4960-90ee-8d194a729949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227953581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2227953581
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1243150595
Short name T557
Test name
Test status
Simulation time 780459950 ps
CPU time 2.55 seconds
Started Jul 30 07:39:08 PM PDT 24
Finished Jul 30 07:39:10 PM PDT 24
Peak memory 198576 kb
Host smart-e4127e2d-10c9-4760-a484-c439cb4a1908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243150595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1243150595
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1729903833
Short name T604
Test name
Test status
Simulation time 85738233657 ps
CPU time 105.68 seconds
Started Jul 30 07:39:08 PM PDT 24
Finished Jul 30 07:40:54 PM PDT 24
Peak memory 200008 kb
Host smart-ac6659ba-66df-4596-bff7-4b43a8d43dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729903833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1729903833
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3271257069
Short name T1058
Test name
Test status
Simulation time 34539745 ps
CPU time 0.54 seconds
Started Jul 30 07:39:12 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 195632 kb
Host smart-c3e2f9fe-76a2-42ee-a169-a3f6b4546416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271257069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3271257069
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.575295174
Short name T1017
Test name
Test status
Simulation time 13922108733 ps
CPU time 23.84 seconds
Started Jul 30 07:39:11 PM PDT 24
Finished Jul 30 07:39:35 PM PDT 24
Peak memory 199996 kb
Host smart-eb2f91f1-dea3-4f97-941b-3050102d7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575295174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.575295174
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.4160889739
Short name T766
Test name
Test status
Simulation time 41318256280 ps
CPU time 69.52 seconds
Started Jul 30 07:39:08 PM PDT 24
Finished Jul 30 07:40:18 PM PDT 24
Peak memory 199988 kb
Host smart-45b442a9-bee1-42f5-85f8-daa9134b7ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160889739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.4160889739
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.4278239710
Short name T522
Test name
Test status
Simulation time 2298083140 ps
CPU time 4.39 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 199992 kb
Host smart-833a54c8-3cb3-4668-8d1b-efcc0862e208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278239710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.4278239710
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.799074083
Short name T654
Test name
Test status
Simulation time 75451395686 ps
CPU time 16.55 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:26 PM PDT 24
Peak memory 199952 kb
Host smart-4bce0e15-0d74-4d62-994a-3638c044ae33
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799074083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.799074083
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2407883973
Short name T635
Test name
Test status
Simulation time 155086861269 ps
CPU time 234.68 seconds
Started Jul 30 07:39:12 PM PDT 24
Finished Jul 30 07:43:07 PM PDT 24
Peak memory 199936 kb
Host smart-72cc06eb-08d1-4e67-bef1-273e38e7ebf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2407883973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2407883973
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2195389758
Short name T819
Test name
Test status
Simulation time 5487531072 ps
CPU time 5.72 seconds
Started Jul 30 07:39:12 PM PDT 24
Finished Jul 30 07:39:18 PM PDT 24
Peak memory 198644 kb
Host smart-6cf2d702-2467-4fb2-a4dc-787689aa73de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195389758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2195389758
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1231513820
Short name T1030
Test name
Test status
Simulation time 25663199567 ps
CPU time 9.35 seconds
Started Jul 30 07:39:08 PM PDT 24
Finished Jul 30 07:39:17 PM PDT 24
Peak memory 194540 kb
Host smart-2bb5c1e1-0c00-4679-9db3-a9a1a5158ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231513820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1231513820
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2495012182
Short name T47
Test name
Test status
Simulation time 28583101594 ps
CPU time 275.68 seconds
Started Jul 30 07:39:12 PM PDT 24
Finished Jul 30 07:43:48 PM PDT 24
Peak memory 199944 kb
Host smart-0feb8e63-a189-418a-a48c-c55505dd62a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495012182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2495012182
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3769834329
Short name T1068
Test name
Test status
Simulation time 6785486897 ps
CPU time 31.64 seconds
Started Jul 30 07:39:10 PM PDT 24
Finished Jul 30 07:39:42 PM PDT 24
Peak memory 198060 kb
Host smart-309b0055-4e12-4206-8dce-30592d0239f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769834329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3769834329
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.3710801826
Short name T548
Test name
Test status
Simulation time 42956852724 ps
CPU time 19.28 seconds
Started Jul 30 07:39:10 PM PDT 24
Finished Jul 30 07:39:30 PM PDT 24
Peak memory 199980 kb
Host smart-8730fd9f-b2f9-414f-bc73-af6c2aa44452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710801826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3710801826
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.1879094413
Short name T515
Test name
Test status
Simulation time 3753396458 ps
CPU time 6.2 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:16 PM PDT 24
Peak memory 196480 kb
Host smart-fd0877d5-1338-4b1a-b8e4-a1b73ab716a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879094413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.1879094413
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.14504398
Short name T583
Test name
Test status
Simulation time 294057475 ps
CPU time 1.23 seconds
Started Jul 30 07:39:11 PM PDT 24
Finished Jul 30 07:39:12 PM PDT 24
Peak memory 198388 kb
Host smart-ed8d894a-f23f-4448-a47b-286c1b86ff41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14504398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.14504398
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.397393392
Short name T1013
Test name
Test status
Simulation time 55625392238 ps
CPU time 94.99 seconds
Started Jul 30 07:39:14 PM PDT 24
Finished Jul 30 07:40:49 PM PDT 24
Peak memory 200100 kb
Host smart-66aa9d34-a57e-496d-ba0c-023692d96dbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397393392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.397393392
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1058874191
Short name T186
Test name
Test status
Simulation time 37932803608 ps
CPU time 342.32 seconds
Started Jul 30 07:39:13 PM PDT 24
Finished Jul 30 07:44:55 PM PDT 24
Peak memory 216076 kb
Host smart-3290e83c-7634-4ac4-a234-503f9f0505d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058874191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1058874191
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.498731986
Short name T287
Test name
Test status
Simulation time 1063562015 ps
CPU time 3.05 seconds
Started Jul 30 07:39:09 PM PDT 24
Finished Jul 30 07:39:13 PM PDT 24
Peak memory 198744 kb
Host smart-1be46026-0d86-43bd-a970-9e53012e411a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498731986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.498731986
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.2071699658
Short name T311
Test name
Test status
Simulation time 39077656059 ps
CPU time 68.39 seconds
Started Jul 30 07:39:12 PM PDT 24
Finished Jul 30 07:40:20 PM PDT 24
Peak memory 199964 kb
Host smart-d230f215-78eb-41ee-a454-441596e04f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071699658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.2071699658
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2351870902
Short name T897
Test name
Test status
Simulation time 20574374 ps
CPU time 0.55 seconds
Started Jul 30 07:39:29 PM PDT 24
Finished Jul 30 07:39:29 PM PDT 24
Peak memory 195000 kb
Host smart-7a1a03c0-fd74-4022-aa21-b99420dea49f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351870902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2351870902
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2513774379
Short name T1136
Test name
Test status
Simulation time 124544906376 ps
CPU time 64.5 seconds
Started Jul 30 07:39:16 PM PDT 24
Finished Jul 30 07:40:21 PM PDT 24
Peak memory 199880 kb
Host smart-8eba7185-6fb0-4e57-904e-fdde253fc13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513774379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2513774379
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1427850240
Short name T453
Test name
Test status
Simulation time 54406482126 ps
CPU time 21.41 seconds
Started Jul 30 07:39:15 PM PDT 24
Finished Jul 30 07:39:37 PM PDT 24
Peak memory 199856 kb
Host smart-b2a425bc-6b5d-4b6a-b66e-292177263bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427850240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1427850240
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1377859472
Short name T704
Test name
Test status
Simulation time 26433418089 ps
CPU time 8.14 seconds
Started Jul 30 07:39:17 PM PDT 24
Finished Jul 30 07:39:26 PM PDT 24
Peak memory 199808 kb
Host smart-a5de8264-0832-4432-a7bb-2d9066efba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377859472 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1377859472
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.691441687
Short name T602
Test name
Test status
Simulation time 72305809820 ps
CPU time 33.02 seconds
Started Jul 30 07:39:16 PM PDT 24
Finished Jul 30 07:39:49 PM PDT 24
Peak memory 199856 kb
Host smart-72b814fb-0898-499f-8c87-d05e8f728789
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691441687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.691441687
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.1077314279
Short name T1119
Test name
Test status
Simulation time 242422992328 ps
CPU time 392.83 seconds
Started Jul 30 07:39:20 PM PDT 24
Finished Jul 30 07:45:53 PM PDT 24
Peak memory 199936 kb
Host smart-7597baf7-864b-4b10-bc09-d68db4b8e131
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1077314279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1077314279
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.693994212
Short name T315
Test name
Test status
Simulation time 6305247599 ps
CPU time 5.4 seconds
Started Jul 30 07:39:21 PM PDT 24
Finished Jul 30 07:39:26 PM PDT 24
Peak memory 196684 kb
Host smart-be02f699-f3d2-498c-8cff-c4dea8005c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693994212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.693994212
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.2486785067
Short name T1048
Test name
Test status
Simulation time 211701519260 ps
CPU time 81.98 seconds
Started Jul 30 07:39:17 PM PDT 24
Finished Jul 30 07:40:39 PM PDT 24
Peak memory 200092 kb
Host smart-e83d1f83-8b80-49ad-91db-398ae42a62d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486785067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.2486785067
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.166984838
Short name T1107
Test name
Test status
Simulation time 21115456250 ps
CPU time 228.41 seconds
Started Jul 30 07:39:21 PM PDT 24
Finished Jul 30 07:43:10 PM PDT 24
Peak memory 199980 kb
Host smart-f123c4f8-70de-4923-a94c-923d656ae698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166984838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.166984838
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3074052770
Short name T774
Test name
Test status
Simulation time 6280075512 ps
CPU time 5.47 seconds
Started Jul 30 07:39:17 PM PDT 24
Finished Jul 30 07:39:22 PM PDT 24
Peak memory 199832 kb
Host smart-7e1ae6f0-d8c4-4101-8721-6a8af7e8089a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074052770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3074052770
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.3351127317
Short name T1154
Test name
Test status
Simulation time 177458824878 ps
CPU time 110.07 seconds
Started Jul 30 07:39:18 PM PDT 24
Finished Jul 30 07:41:08 PM PDT 24
Peak memory 199920 kb
Host smart-060948bc-ef30-45c9-bc29-b47b4c0bf901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351127317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3351127317
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2961698153
Short name T651
Test name
Test status
Simulation time 3958583584 ps
CPU time 3.64 seconds
Started Jul 30 07:39:15 PM PDT 24
Finished Jul 30 07:39:19 PM PDT 24
Peak memory 196060 kb
Host smart-56483b63-b225-4cd4-ac7f-29cfb75f09b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961698153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2961698153
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3446570778
Short name T577
Test name
Test status
Simulation time 138720219 ps
CPU time 0.94 seconds
Started Jul 30 07:39:14 PM PDT 24
Finished Jul 30 07:39:15 PM PDT 24
Peak memory 198852 kb
Host smart-0107c6da-3714-432d-975c-de632565b5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446570778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3446570778
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.2046143745
Short name T694
Test name
Test status
Simulation time 196822252193 ps
CPU time 136.79 seconds
Started Jul 30 07:39:20 PM PDT 24
Finished Jul 30 07:41:37 PM PDT 24
Peak memory 215548 kb
Host smart-5a3a6c02-6309-4f7c-a8f9-ae263ddb1bb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046143745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.2046143745
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.2068110287
Short name T615
Test name
Test status
Simulation time 212367132167 ps
CPU time 1224.73 seconds
Started Jul 30 07:39:21 PM PDT 24
Finished Jul 30 07:59:46 PM PDT 24
Peak memory 227640 kb
Host smart-877da508-90c1-4224-a25d-c5e481d772f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068110287 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.2068110287
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.2670202653
Short name T934
Test name
Test status
Simulation time 7099742441 ps
CPU time 26.68 seconds
Started Jul 30 07:39:18 PM PDT 24
Finished Jul 30 07:39:45 PM PDT 24
Peak memory 199876 kb
Host smart-f15ced6f-7601-4ff4-b42c-47845e41147c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670202653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2670202653
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1733033754
Short name T913
Test name
Test status
Simulation time 142346476650 ps
CPU time 70.82 seconds
Started Jul 30 07:39:14 PM PDT 24
Finished Jul 30 07:40:25 PM PDT 24
Peak memory 199964 kb
Host smart-3572724b-8154-495e-ab9d-e805829b9066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733033754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1733033754
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.390877561
Short name T742
Test name
Test status
Simulation time 82475978 ps
CPU time 0.59 seconds
Started Jul 30 07:39:32 PM PDT 24
Finished Jul 30 07:39:32 PM PDT 24
Peak memory 195336 kb
Host smart-b10652cd-9da6-448d-8794-d66be7fb7a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390877561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.390877561
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.211880851
Short name T875
Test name
Test status
Simulation time 147495340071 ps
CPU time 63.07 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:40:31 PM PDT 24
Peak memory 200076 kb
Host smart-fbc3b35e-f8e9-4405-ac5c-beeae75cc3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211880851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.211880851
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.2619370569
Short name T1009
Test name
Test status
Simulation time 15513334652 ps
CPU time 6.9 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:39:35 PM PDT 24
Peak memory 199788 kb
Host smart-62ea14de-87b0-47b8-9a18-1177de8a5d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619370569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.2619370569
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4272414813
Short name T1084
Test name
Test status
Simulation time 41295607720 ps
CPU time 63.28 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:40:31 PM PDT 24
Peak memory 199924 kb
Host smart-52295713-af22-4e61-9559-0404ac36faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272414813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4272414813
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1013978953
Short name T1028
Test name
Test status
Simulation time 37357779981 ps
CPU time 36.31 seconds
Started Jul 30 07:39:29 PM PDT 24
Finished Jul 30 07:40:06 PM PDT 24
Peak memory 200004 kb
Host smart-77fbf3d6-9272-48ce-8de7-6afeccb544b0
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013978953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1013978953
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.842498424
Short name T1063
Test name
Test status
Simulation time 71298718565 ps
CPU time 297.16 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:44:25 PM PDT 24
Peak memory 199972 kb
Host smart-6ee58555-3132-4d13-adeb-f2224f126af0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=842498424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.842498424
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2446445799
Short name T626
Test name
Test status
Simulation time 7735390075 ps
CPU time 5.12 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:39:33 PM PDT 24
Peak memory 199944 kb
Host smart-db927ea0-9632-49cf-bcb3-65ad5cd35087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446445799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2446445799
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1298493939
Short name T327
Test name
Test status
Simulation time 79563439651 ps
CPU time 84.61 seconds
Started Jul 30 07:39:27 PM PDT 24
Finished Jul 30 07:40:52 PM PDT 24
Peak memory 199556 kb
Host smart-4bc905ac-e209-4a98-bca7-6271972ae90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298493939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1298493939
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.1315554954
Short name T952
Test name
Test status
Simulation time 13335569360 ps
CPU time 370.44 seconds
Started Jul 30 07:39:25 PM PDT 24
Finished Jul 30 07:45:36 PM PDT 24
Peak memory 199988 kb
Host smart-1026a280-12b8-41c8-afaf-dbc6a572cf0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1315554954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.1315554954
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.2890158405
Short name T1
Test name
Test status
Simulation time 1735039785 ps
CPU time 1.31 seconds
Started Jul 30 07:39:26 PM PDT 24
Finished Jul 30 07:39:27 PM PDT 24
Peak memory 198904 kb
Host smart-88051f15-e08a-4239-8aad-e03a57250a5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2890158405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.2890158405
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.728278772
Short name T660
Test name
Test status
Simulation time 289734145635 ps
CPU time 299.03 seconds
Started Jul 30 07:39:26 PM PDT 24
Finished Jul 30 07:44:25 PM PDT 24
Peak memory 199808 kb
Host smart-9d671cdf-65cf-42f3-8dda-cea0f49233b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728278772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.728278772
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3036301379
Short name T1074
Test name
Test status
Simulation time 2971762535 ps
CPU time 4.93 seconds
Started Jul 30 07:39:27 PM PDT 24
Finished Jul 30 07:39:32 PM PDT 24
Peak memory 195916 kb
Host smart-73b96a0e-4e4e-46de-960a-e03abe9d8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036301379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3036301379
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.3437379942
Short name T399
Test name
Test status
Simulation time 316287052 ps
CPU time 1.21 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:39:29 PM PDT 24
Peak memory 199892 kb
Host smart-460c8d92-c043-4fe8-b516-085718965581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437379942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.3437379942
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.295069587
Short name T624
Test name
Test status
Simulation time 611384232006 ps
CPU time 134.05 seconds
Started Jul 30 07:39:27 PM PDT 24
Finished Jul 30 07:41:42 PM PDT 24
Peak memory 199956 kb
Host smart-29e0a459-fbbf-46d3-93ad-2242a4ed2c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295069587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.295069587
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.2315494642
Short name T755
Test name
Test status
Simulation time 7108459418 ps
CPU time 24.11 seconds
Started Jul 30 07:39:28 PM PDT 24
Finished Jul 30 07:39:52 PM PDT 24
Peak memory 199876 kb
Host smart-0e5204c5-e303-417f-9253-9f1d09ab213b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315494642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.2315494642
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.219550596
Short name T828
Test name
Test status
Simulation time 73932822678 ps
CPU time 60.6 seconds
Started Jul 30 07:39:27 PM PDT 24
Finished Jul 30 07:40:28 PM PDT 24
Peak memory 199996 kb
Host smart-c1c5ad3d-d524-4b48-b37e-d1253d094cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219550596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.219550596
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.974858958
Short name T738
Test name
Test status
Simulation time 31412731 ps
CPU time 0.54 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:39:39 PM PDT 24
Peak memory 194768 kb
Host smart-8cdd9e56-cb8a-4d0e-a01d-c2e1a20176a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974858958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.974858958
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2112199945
Short name T268
Test name
Test status
Simulation time 90531422379 ps
CPU time 41.71 seconds
Started Jul 30 07:39:31 PM PDT 24
Finished Jul 30 07:40:13 PM PDT 24
Peak memory 199904 kb
Host smart-b5dde110-4c84-4c7b-af8a-4c427557303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112199945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2112199945
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2028666950
Short name T171
Test name
Test status
Simulation time 63206909767 ps
CPU time 18.44 seconds
Started Jul 30 07:39:32 PM PDT 24
Finished Jul 30 07:39:50 PM PDT 24
Peak memory 200004 kb
Host smart-d1d71c6f-5bbc-486c-a2a2-dab3d53b81be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028666950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2028666950
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3843831621
Short name T893
Test name
Test status
Simulation time 134060105461 ps
CPU time 106.7 seconds
Started Jul 30 07:39:33 PM PDT 24
Finished Jul 30 07:41:19 PM PDT 24
Peak memory 199924 kb
Host smart-9133e35d-e3f9-41d5-a725-3eab99584c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843831621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3843831621
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.3113267063
Short name T403
Test name
Test status
Simulation time 60913440306 ps
CPU time 16.98 seconds
Started Jul 30 07:39:35 PM PDT 24
Finished Jul 30 07:39:52 PM PDT 24
Peak memory 199956 kb
Host smart-2e977630-6c52-46f2-94c2-1d1f9c814b42
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113267063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.3113267063
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.1113840028
Short name T569
Test name
Test status
Simulation time 266506408871 ps
CPU time 177.89 seconds
Started Jul 30 07:39:38 PM PDT 24
Finished Jul 30 07:42:36 PM PDT 24
Peak memory 199884 kb
Host smart-ee2b233c-f20b-4bd6-959d-c6e770f855a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1113840028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1113840028
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1235189876
Short name T942
Test name
Test status
Simulation time 5128048342 ps
CPU time 3.57 seconds
Started Jul 30 07:39:34 PM PDT 24
Finished Jul 30 07:39:38 PM PDT 24
Peak memory 198920 kb
Host smart-99e8bc06-f381-48ba-af09-8a0024674b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235189876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1235189876
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.2217231058
Short name T305
Test name
Test status
Simulation time 70540712294 ps
CPU time 57.64 seconds
Started Jul 30 07:39:35 PM PDT 24
Finished Jul 30 07:40:33 PM PDT 24
Peak memory 200032 kb
Host smart-e37b2b5d-bdfb-43af-abef-16f471092a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217231058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2217231058
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.3563391783
Short name T266
Test name
Test status
Simulation time 23237285926 ps
CPU time 1120.28 seconds
Started Jul 30 07:39:36 PM PDT 24
Finished Jul 30 07:58:17 PM PDT 24
Peak memory 199948 kb
Host smart-503e6450-c6c3-4823-9ecc-b9a2b634df09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3563391783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.3563391783
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.3397324807
Short name T776
Test name
Test status
Simulation time 1809445206 ps
CPU time 3.76 seconds
Started Jul 30 07:39:38 PM PDT 24
Finished Jul 30 07:39:42 PM PDT 24
Peak memory 198028 kb
Host smart-139dc763-5c89-4df5-9cf9-ba39ede96e97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397324807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.3397324807
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1870791383
Short name T275
Test name
Test status
Simulation time 76041639723 ps
CPU time 120.91 seconds
Started Jul 30 07:39:35 PM PDT 24
Finished Jul 30 07:41:36 PM PDT 24
Peak memory 199960 kb
Host smart-1ce8ef68-1c8b-41f5-9f59-2a011a507c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870791383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1870791383
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.1460768074
Short name T608
Test name
Test status
Simulation time 70445147924 ps
CPU time 16.1 seconds
Started Jul 30 07:39:36 PM PDT 24
Finished Jul 30 07:39:53 PM PDT 24
Peak memory 195792 kb
Host smart-644a8304-600b-4c58-9c39-8ea627ef3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460768074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1460768074
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3934803223
Short name T977
Test name
Test status
Simulation time 6284659688 ps
CPU time 6.82 seconds
Started Jul 30 07:39:31 PM PDT 24
Finished Jul 30 07:39:38 PM PDT 24
Peak memory 199680 kb
Host smart-b4290c6a-1b64-47be-9c5d-fa428dd144fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934803223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3934803223
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3885359945
Short name T70
Test name
Test status
Simulation time 484073744092 ps
CPU time 903.59 seconds
Started Jul 30 07:39:34 PM PDT 24
Finished Jul 30 07:54:38 PM PDT 24
Peak memory 199904 kb
Host smart-6e47dc10-4620-4b09-9d31-3dfd823bcc34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885359945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3885359945
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1165456763
Short name T390
Test name
Test status
Simulation time 198107044988 ps
CPU time 708.48 seconds
Started Jul 30 07:39:36 PM PDT 24
Finished Jul 30 07:51:25 PM PDT 24
Peak memory 224836 kb
Host smart-1f14491d-85e2-4f48-9ead-e86e3a620974
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165456763 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1165456763
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.116679828
Short name T601
Test name
Test status
Simulation time 8198559369 ps
CPU time 7.91 seconds
Started Jul 30 07:39:36 PM PDT 24
Finished Jul 30 07:39:44 PM PDT 24
Peak memory 199324 kb
Host smart-8db8f211-18d8-4230-aca5-0e5e60c32376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116679828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.116679828
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2190613431
Short name T726
Test name
Test status
Simulation time 3416928845 ps
CPU time 2.25 seconds
Started Jul 30 07:39:32 PM PDT 24
Finished Jul 30 07:39:34 PM PDT 24
Peak memory 197544 kb
Host smart-76b1f43b-1671-41ce-8fc1-95a0ad0afd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190613431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2190613431
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.3535027766
Short name T793
Test name
Test status
Simulation time 42914595 ps
CPU time 0.55 seconds
Started Jul 30 07:39:44 PM PDT 24
Finished Jul 30 07:39:44 PM PDT 24
Peak memory 195392 kb
Host smart-dde6b02b-1ab8-4732-ac33-19411377f540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535027766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.3535027766
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.2533842023
Short name T500
Test name
Test status
Simulation time 148161346516 ps
CPU time 15.54 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:39:54 PM PDT 24
Peak memory 199992 kb
Host smart-a2cdd165-ee28-4ac5-8ef4-912324780362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533842023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.2533842023
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.4259318516
Short name T634
Test name
Test status
Simulation time 21698201779 ps
CPU time 32.99 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:40:12 PM PDT 24
Peak memory 199608 kb
Host smart-d8a28091-04ea-4332-8796-abfd242decc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259318516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.4259318516
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2589683726
Short name T225
Test name
Test status
Simulation time 200949530686 ps
CPU time 21.28 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:40:00 PM PDT 24
Peak memory 199928 kb
Host smart-5273839e-7030-4448-afad-8b97ce5d31f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589683726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2589683726
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.1640573860
Short name T368
Test name
Test status
Simulation time 320892377276 ps
CPU time 127.62 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:41:47 PM PDT 24
Peak memory 197400 kb
Host smart-f8a4931f-9f88-4fb4-b452-b076b9aaaab8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640573860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1640573860
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1724057397
Short name T647
Test name
Test status
Simulation time 84621099162 ps
CPU time 186.63 seconds
Started Jul 30 07:39:40 PM PDT 24
Finished Jul 30 07:42:47 PM PDT 24
Peak memory 199960 kb
Host smart-406d00ca-bb0f-4841-aee1-2fd8d509126a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1724057397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1724057397
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.2567847277
Short name T838
Test name
Test status
Simulation time 4490116652 ps
CPU time 8.81 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:39:48 PM PDT 24
Peak memory 199924 kb
Host smart-3006eac2-08ec-4962-b432-1e091340bf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567847277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2567847277
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.3805740698
Short name T584
Test name
Test status
Simulation time 82253238850 ps
CPU time 22.71 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:40:02 PM PDT 24
Peak memory 198736 kb
Host smart-bc187b9f-08b2-4b15-a4c4-ae69d23c135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805740698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.3805740698
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.606820463
Short name T485
Test name
Test status
Simulation time 13168888814 ps
CPU time 320.42 seconds
Started Jul 30 07:39:41 PM PDT 24
Finished Jul 30 07:45:01 PM PDT 24
Peak memory 200020 kb
Host smart-2693a6c9-d8ec-4872-881b-c0f4fc445479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=606820463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.606820463
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.2726675114
Short name T840
Test name
Test status
Simulation time 7759437358 ps
CPU time 16.9 seconds
Started Jul 30 07:39:41 PM PDT 24
Finished Jul 30 07:39:58 PM PDT 24
Peak memory 199240 kb
Host smart-cb69c7fb-1765-4f14-85c6-786f47258c91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2726675114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2726675114
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3068238013
Short name T823
Test name
Test status
Simulation time 290190263866 ps
CPU time 442.7 seconds
Started Jul 30 07:39:40 PM PDT 24
Finished Jul 30 07:47:03 PM PDT 24
Peak memory 199916 kb
Host smart-e871e77e-5b09-45d3-aa1f-527d2aefc20b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068238013 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3068238013
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3711463008
Short name T607
Test name
Test status
Simulation time 3604762664 ps
CPU time 5.99 seconds
Started Jul 30 07:39:40 PM PDT 24
Finished Jul 30 07:39:47 PM PDT 24
Peak memory 196524 kb
Host smart-d992a27c-11b3-4e17-af11-db92807cb716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711463008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3711463008
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2092952105
Short name T441
Test name
Test status
Simulation time 458697657 ps
CPU time 3.62 seconds
Started Jul 30 07:39:41 PM PDT 24
Finished Jul 30 07:39:45 PM PDT 24
Peak memory 198944 kb
Host smart-4bf37145-c70a-40f9-8b35-4b6f0c0bb4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092952105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2092952105
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3845534680
Short name T1012
Test name
Test status
Simulation time 252579674277 ps
CPU time 385.38 seconds
Started Jul 30 07:39:43 PM PDT 24
Finished Jul 30 07:46:09 PM PDT 24
Peak memory 200140 kb
Host smart-81db32bc-50eb-4059-82fa-b47c32648f13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845534680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3845534680
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.2809284690
Short name T157
Test name
Test status
Simulation time 53760454923 ps
CPU time 267.12 seconds
Started Jul 30 07:39:40 PM PDT 24
Finished Jul 30 07:44:07 PM PDT 24
Peak memory 216624 kb
Host smart-5f2e6c3d-6714-4a2b-92a0-8d3cd494cd5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809284690 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.2809284690
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2029572328
Short name T1050
Test name
Test status
Simulation time 6191601302 ps
CPU time 14.32 seconds
Started Jul 30 07:39:39 PM PDT 24
Finished Jul 30 07:39:53 PM PDT 24
Peak memory 199240 kb
Host smart-3f4e0541-cd98-436f-8147-c7ee7f6993db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029572328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2029572328
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.1200091444
Short name T1054
Test name
Test status
Simulation time 75716093876 ps
CPU time 71.52 seconds
Started Jul 30 07:39:40 PM PDT 24
Finished Jul 30 07:40:51 PM PDT 24
Peak memory 199928 kb
Host smart-3818cb5f-75ab-4a08-9813-f389e6760489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200091444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1200091444
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.1818009461
Short name T105
Test name
Test status
Simulation time 17360401 ps
CPU time 0.57 seconds
Started Jul 30 07:36:44 PM PDT 24
Finished Jul 30 07:36:44 PM PDT 24
Peak memory 195352 kb
Host smart-b77515a5-1da9-4026-bb14-ffcd160abc59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818009461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.1818009461
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2262887856
Short name T391
Test name
Test status
Simulation time 108910537880 ps
CPU time 46.28 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:37:24 PM PDT 24
Peak memory 200008 kb
Host smart-149ab403-c1f7-41fa-b2e6-8e33cf6d0a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262887856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2262887856
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2393930207
Short name T748
Test name
Test status
Simulation time 70816363461 ps
CPU time 30.08 seconds
Started Jul 30 07:36:40 PM PDT 24
Finished Jul 30 07:37:11 PM PDT 24
Peak memory 199852 kb
Host smart-7a561b33-bef4-4ac2-b9f2-859be4d7cf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393930207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2393930207
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.4256493259
Short name T241
Test name
Test status
Simulation time 138568010474 ps
CPU time 55.89 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:37:37 PM PDT 24
Peak memory 199936 kb
Host smart-b21eb04e-414f-4e8b-b57a-7161e3104bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256493259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.4256493259
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.536422915
Short name T972
Test name
Test status
Simulation time 52467483973 ps
CPU time 78.02 seconds
Started Jul 30 07:36:42 PM PDT 24
Finished Jul 30 07:38:00 PM PDT 24
Peak memory 199992 kb
Host smart-fef62470-c7e5-4a33-ac40-65b5e3568640
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536422915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.536422915
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1103337415
Short name T258
Test name
Test status
Simulation time 145839055716 ps
CPU time 123.41 seconds
Started Jul 30 07:36:42 PM PDT 24
Finished Jul 30 07:38:46 PM PDT 24
Peak memory 199920 kb
Host smart-1583dbab-f689-47f5-8339-bfcc1d3d3ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1103337415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1103337415
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.4228426470
Short name T423
Test name
Test status
Simulation time 10273026789 ps
CPU time 6.45 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:36:48 PM PDT 24
Peak memory 199972 kb
Host smart-9eecdb13-3cfa-42eb-9688-86994d02da85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228426470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.4228426470
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.4076428484
Short name T416
Test name
Test status
Simulation time 52457155492 ps
CPU time 29.44 seconds
Started Jul 30 07:36:43 PM PDT 24
Finished Jul 30 07:37:12 PM PDT 24
Peak memory 200100 kb
Host smart-fcb28d6a-3853-42e4-b68a-0c7c52af850b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076428484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.4076428484
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.227576833
Short name T599
Test name
Test status
Simulation time 9555828424 ps
CPU time 256.36 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 199996 kb
Host smart-6442c547-df92-4cf5-8203-ce94d75454b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=227576833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.227576833
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.604276208
Short name T762
Test name
Test status
Simulation time 3539608475 ps
CPU time 25.38 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:37:07 PM PDT 24
Peak memory 198172 kb
Host smart-59e67e5f-7c78-42a7-8cf5-a42882f212c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604276208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.604276208
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.1988573189
Short name T732
Test name
Test status
Simulation time 23600616141 ps
CPU time 41.58 seconds
Started Jul 30 07:36:43 PM PDT 24
Finished Jul 30 07:37:25 PM PDT 24
Peak memory 199920 kb
Host smart-3158b3c3-b73f-4690-ade7-029deb08c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988573189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.1988573189
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.3220612250
Short name T751
Test name
Test status
Simulation time 4689132483 ps
CPU time 7.88 seconds
Started Jul 30 07:36:42 PM PDT 24
Finished Jul 30 07:36:50 PM PDT 24
Peak memory 196140 kb
Host smart-20fe3042-bbb9-4060-a82e-6eb890f8d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220612250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.3220612250
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.1335610108
Short name T94
Test name
Test status
Simulation time 216863908 ps
CPU time 0.9 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:36:42 PM PDT 24
Peak memory 218360 kb
Host smart-b9fac025-916c-4f33-bb5f-f6266ce130cc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335610108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1335610108
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.476036921
Short name T986
Test name
Test status
Simulation time 533381818 ps
CPU time 2.82 seconds
Started Jul 30 07:36:38 PM PDT 24
Finished Jul 30 07:36:41 PM PDT 24
Peak memory 199652 kb
Host smart-aea00f31-5935-4929-ba0d-715d347689e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476036921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.476036921
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2662311132
Short name T561
Test name
Test status
Simulation time 45368052847 ps
CPU time 139.91 seconds
Started Jul 30 07:36:43 PM PDT 24
Finished Jul 30 07:39:03 PM PDT 24
Peak memory 199896 kb
Host smart-5d5c0d0b-7f67-4c9a-9077-8b85d60c9fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662311132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2662311132
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2834393607
Short name T439
Test name
Test status
Simulation time 1178127236 ps
CPU time 1.8 seconds
Started Jul 30 07:36:43 PM PDT 24
Finished Jul 30 07:36:45 PM PDT 24
Peak memory 198704 kb
Host smart-d0dda17d-0e1a-462f-a99f-b91adf202e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834393607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2834393607
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.3873606074
Short name T1052
Test name
Test status
Simulation time 79425538183 ps
CPU time 68.89 seconds
Started Jul 30 07:36:37 PM PDT 24
Finished Jul 30 07:37:46 PM PDT 24
Peak memory 199956 kb
Host smart-ae9c18d9-d8bf-4922-ba29-91098add8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873606074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.3873606074
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.2493212101
Short name T644
Test name
Test status
Simulation time 12391696 ps
CPU time 0.57 seconds
Started Jul 30 07:39:47 PM PDT 24
Finished Jul 30 07:39:47 PM PDT 24
Peak memory 195320 kb
Host smart-b55034fd-986a-409d-a9c3-9c13507786ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493212101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.2493212101
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.2965306460
Short name T600
Test name
Test status
Simulation time 73447585267 ps
CPU time 32.49 seconds
Started Jul 30 07:39:44 PM PDT 24
Finished Jul 30 07:40:16 PM PDT 24
Peak memory 199940 kb
Host smart-4aa08741-cb84-4154-a887-c13669e58844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965306460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2965306460
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.403102805
Short name T362
Test name
Test status
Simulation time 15899638094 ps
CPU time 23.33 seconds
Started Jul 30 07:39:44 PM PDT 24
Finished Jul 30 07:40:08 PM PDT 24
Peak memory 200044 kb
Host smart-264d1943-0ab3-459c-8186-c2c8a6bb3c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403102805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.403102805
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.3259017529
Short name T568
Test name
Test status
Simulation time 185592004461 ps
CPU time 73.15 seconds
Started Jul 30 07:39:44 PM PDT 24
Finished Jul 30 07:40:58 PM PDT 24
Peak memory 199948 kb
Host smart-ea8e4085-0bdb-4146-b7ad-b328b6f70638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259017529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3259017529
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1788774811
Short name T844
Test name
Test status
Simulation time 40240906821 ps
CPU time 42.35 seconds
Started Jul 30 07:39:42 PM PDT 24
Finished Jul 30 07:40:24 PM PDT 24
Peak memory 199896 kb
Host smart-77a50d93-ebae-4821-bdfa-a907442a2d85
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788774811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1788774811
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3784244852
Short name T1104
Test name
Test status
Simulation time 100856608072 ps
CPU time 163.61 seconds
Started Jul 30 07:39:47 PM PDT 24
Finished Jul 30 07:42:31 PM PDT 24
Peak memory 199936 kb
Host smart-887b3728-3cb6-49e4-9867-acfe1e21a13b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3784244852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3784244852
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2816580565
Short name T65
Test name
Test status
Simulation time 11070693927 ps
CPU time 1.95 seconds
Started Jul 30 07:39:46 PM PDT 24
Finished Jul 30 07:39:48 PM PDT 24
Peak memory 199212 kb
Host smart-fda7b529-6f45-4c70-a931-0942e3d098c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816580565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2816580565
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.3735761992
Short name T286
Test name
Test status
Simulation time 54175134998 ps
CPU time 100.34 seconds
Started Jul 30 07:39:45 PM PDT 24
Finished Jul 30 07:41:25 PM PDT 24
Peak memory 200116 kb
Host smart-beb5e176-8c93-440a-9835-00db1ce970b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735761992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3735761992
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.1372093482
Short name T791
Test name
Test status
Simulation time 17847039319 ps
CPU time 826.55 seconds
Started Jul 30 07:39:48 PM PDT 24
Finished Jul 30 07:53:35 PM PDT 24
Peak memory 200080 kb
Host smart-4cf199ee-66d3-4df3-a465-c1630f768c63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1372093482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1372093482
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.216885150
Short name T364
Test name
Test status
Simulation time 5195992422 ps
CPU time 47.07 seconds
Started Jul 30 07:39:43 PM PDT 24
Finished Jul 30 07:40:31 PM PDT 24
Peak memory 198204 kb
Host smart-20290fff-b7e0-483f-9089-9967b27b6f17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216885150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.216885150
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.3753437670
Short name T1121
Test name
Test status
Simulation time 106622572095 ps
CPU time 118.8 seconds
Started Jul 30 07:39:46 PM PDT 24
Finished Jul 30 07:41:45 PM PDT 24
Peak memory 199956 kb
Host smart-c546bf9e-10ba-477a-af4d-c1c49b3afb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753437670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.3753437670
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.555527323
Short name T692
Test name
Test status
Simulation time 2891924853 ps
CPU time 4.48 seconds
Started Jul 30 07:39:42 PM PDT 24
Finished Jul 30 07:39:47 PM PDT 24
Peak memory 196524 kb
Host smart-54c8f644-233c-4b4a-b8ad-163d765191ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555527323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.555527323
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.790266134
Short name T886
Test name
Test status
Simulation time 289097889 ps
CPU time 1.5 seconds
Started Jul 30 07:39:44 PM PDT 24
Finished Jul 30 07:39:45 PM PDT 24
Peak memory 198484 kb
Host smart-ed5d24b1-11e6-446b-ac26-6c937f59b86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790266134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.790266134
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.606981995
Short name T993
Test name
Test status
Simulation time 430711784704 ps
CPU time 86.1 seconds
Started Jul 30 07:39:45 PM PDT 24
Finished Jul 30 07:41:11 PM PDT 24
Peak memory 199928 kb
Host smart-c58bd39b-3dee-4166-9894-e5bea06a5493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606981995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.606981995
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.3016542467
Short name T1145
Test name
Test status
Simulation time 59769604162 ps
CPU time 516.47 seconds
Started Jul 30 07:39:46 PM PDT 24
Finished Jul 30 07:48:23 PM PDT 24
Peak memory 216492 kb
Host smart-04b5affd-830c-47a1-b6a7-9d59602e679f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016542467 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.3016542467
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2563641832
Short name T507
Test name
Test status
Simulation time 281980706 ps
CPU time 1.3 seconds
Started Jul 30 07:39:43 PM PDT 24
Finished Jul 30 07:39:44 PM PDT 24
Peak memory 198500 kb
Host smart-5bb5a551-9c44-4e34-807a-ac141d10a7b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563641832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2563641832
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2981875328
Short name T714
Test name
Test status
Simulation time 8122307428 ps
CPU time 5.98 seconds
Started Jul 30 07:39:45 PM PDT 24
Finished Jul 30 07:39:51 PM PDT 24
Peak memory 199732 kb
Host smart-37c6575b-e698-4213-96e3-4ee0db12ba41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981875328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2981875328
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.2132263837
Short name T332
Test name
Test status
Simulation time 10740070 ps
CPU time 0.54 seconds
Started Jul 30 07:39:51 PM PDT 24
Finished Jul 30 07:39:52 PM PDT 24
Peak memory 194536 kb
Host smart-f0614a08-fdca-4234-9728-3f7094e702a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132263837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.2132263837
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3423834869
Short name T126
Test name
Test status
Simulation time 24952375221 ps
CPU time 6.72 seconds
Started Jul 30 07:39:47 PM PDT 24
Finished Jul 30 07:39:54 PM PDT 24
Peak memory 199728 kb
Host smart-ddc154bd-4c52-4514-8d36-e7c1f3e00ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423834869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3423834869
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.1198058639
Short name T804
Test name
Test status
Simulation time 139498213777 ps
CPU time 108.28 seconds
Started Jul 30 07:39:47 PM PDT 24
Finished Jul 30 07:41:35 PM PDT 24
Peak memory 199844 kb
Host smart-0524885d-29bd-4ed3-ab2b-bdf66aa2ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198058639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.1198058639
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.2126470364
Short name T242
Test name
Test status
Simulation time 97988692081 ps
CPU time 39.82 seconds
Started Jul 30 07:39:48 PM PDT 24
Finished Jul 30 07:40:27 PM PDT 24
Peak memory 199964 kb
Host smart-f66e7ea7-1005-49e9-8d5e-c19eaa419e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126470364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.2126470364
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1841330250
Short name T880
Test name
Test status
Simulation time 336059263203 ps
CPU time 488.02 seconds
Started Jul 30 07:39:49 PM PDT 24
Finished Jul 30 07:47:57 PM PDT 24
Peak memory 197644 kb
Host smart-6849737f-b0fe-4170-bfec-039669c13d0e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841330250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1841330250
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.1095074970
Short name T719
Test name
Test status
Simulation time 58613546657 ps
CPU time 303.38 seconds
Started Jul 30 07:39:52 PM PDT 24
Finished Jul 30 07:44:55 PM PDT 24
Peak memory 199936 kb
Host smart-635ecda1-36de-4055-abb8-bedcfacd3bbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1095074970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.1095074970
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.1457731899
Short name T530
Test name
Test status
Simulation time 2420995956 ps
CPU time 5.15 seconds
Started Jul 30 07:39:53 PM PDT 24
Finished Jul 30 07:39:58 PM PDT 24
Peak memory 198924 kb
Host smart-d65bd198-83c3-4ebe-a1dc-a046cc11536f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457731899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.1457731899
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.3553463665
Short name T585
Test name
Test status
Simulation time 107476232383 ps
CPU time 183.13 seconds
Started Jul 30 07:39:46 PM PDT 24
Finished Jul 30 07:42:50 PM PDT 24
Peak memory 199672 kb
Host smart-de779ef4-082d-46c8-bf5a-23ed705fd4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553463665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.3553463665
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.2742350397
Short name T625
Test name
Test status
Simulation time 10680863348 ps
CPU time 577.71 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:49:33 PM PDT 24
Peak memory 199960 kb
Host smart-4a0ccba7-d207-419a-aa2d-f4808b839124
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742350397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.2742350397
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.3759293537
Short name T526
Test name
Test status
Simulation time 6948017944 ps
CPU time 59.5 seconds
Started Jul 30 07:39:48 PM PDT 24
Finished Jul 30 07:40:48 PM PDT 24
Peak memory 198096 kb
Host smart-9247ad63-bbc0-4e5d-bee6-7e5a2d23ccda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759293537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.3759293537
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4054317483
Short name T803
Test name
Test status
Simulation time 23504685974 ps
CPU time 29.9 seconds
Started Jul 30 07:39:52 PM PDT 24
Finished Jul 30 07:40:22 PM PDT 24
Peak memory 200008 kb
Host smart-9eaeff9f-7aaf-4faf-9e96-69bb7c6921ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054317483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4054317483
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.1855865029
Short name T349
Test name
Test status
Simulation time 2574665833 ps
CPU time 1.9 seconds
Started Jul 30 07:39:52 PM PDT 24
Finished Jul 30 07:39:54 PM PDT 24
Peak memory 195936 kb
Host smart-785fceac-e60f-4678-b55e-b714c67bf730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855865029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.1855865029
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2446629734
Short name T750
Test name
Test status
Simulation time 998512823 ps
CPU time 2.13 seconds
Started Jul 30 07:39:50 PM PDT 24
Finished Jul 30 07:39:52 PM PDT 24
Peak memory 198300 kb
Host smart-a63a7bce-e9e0-4a8f-bc85-efe58073d43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446629734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2446629734
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.3512176795
Short name T1067
Test name
Test status
Simulation time 33899642982 ps
CPU time 53.06 seconds
Started Jul 30 07:39:52 PM PDT 24
Finished Jul 30 07:40:45 PM PDT 24
Peak memory 199948 kb
Host smart-6e8b11a2-0eab-401f-b0e9-b48ee04b9966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512176795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.3512176795
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1222583265
Short name T1094
Test name
Test status
Simulation time 48259068430 ps
CPU time 709.37 seconds
Started Jul 30 07:39:51 PM PDT 24
Finished Jul 30 07:51:41 PM PDT 24
Peak memory 216644 kb
Host smart-e29db8bf-d584-4559-b68b-137ba1ff0215
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222583265 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1222583265
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.1700485063
Short name T1060
Test name
Test status
Simulation time 1881574453 ps
CPU time 1.8 seconds
Started Jul 30 07:39:52 PM PDT 24
Finished Jul 30 07:39:54 PM PDT 24
Peak memory 197836 kb
Host smart-5c4ff1d3-f896-4d95-b3fc-b6dc4c8cdd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700485063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.1700485063
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1455273101
Short name T812
Test name
Test status
Simulation time 258547667573 ps
CPU time 28.33 seconds
Started Jul 30 07:39:49 PM PDT 24
Finished Jul 30 07:40:17 PM PDT 24
Peak memory 199952 kb
Host smart-70b649b7-093b-417e-8263-fc1323a4f92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455273101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1455273101
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1351589797
Short name T928
Test name
Test status
Simulation time 13210951 ps
CPU time 0.56 seconds
Started Jul 30 07:39:59 PM PDT 24
Finished Jul 30 07:39:59 PM PDT 24
Peak memory 195344 kb
Host smart-b34d12df-2054-43f6-af25-ca9c552bb455
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351589797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1351589797
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3527930640
Short name T944
Test name
Test status
Simulation time 59229781467 ps
CPU time 23.11 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:40:18 PM PDT 24
Peak memory 199744 kb
Host smart-54af3d91-3af0-4465-a073-05af50057afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527930640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3527930640
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.4145733456
Short name T770
Test name
Test status
Simulation time 39375224051 ps
CPU time 53.77 seconds
Started Jul 30 07:39:54 PM PDT 24
Finished Jul 30 07:40:48 PM PDT 24
Peak memory 199852 kb
Host smart-96a7b221-d14d-4d5f-a13f-d1c208b01836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145733456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.4145733456
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4066360929
Short name T759
Test name
Test status
Simulation time 72765966759 ps
CPU time 30.43 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:40:25 PM PDT 24
Peak memory 199916 kb
Host smart-93536a0a-072e-4c86-950b-ba5ff08d5e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066360929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4066360929
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2912417518
Short name T543
Test name
Test status
Simulation time 30292815314 ps
CPU time 41.71 seconds
Started Jul 30 07:39:54 PM PDT 24
Finished Jul 30 07:40:36 PM PDT 24
Peak memory 198392 kb
Host smart-f5b41dee-38ad-4794-b990-6d8ab55a18eb
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912417518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2912417518
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.4146630795
Short name T549
Test name
Test status
Simulation time 132733110090 ps
CPU time 303.23 seconds
Started Jul 30 07:40:00 PM PDT 24
Finished Jul 30 07:45:03 PM PDT 24
Peak memory 199904 kb
Host smart-c809c3a5-f225-4c3b-8173-1d90b71c0a8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4146630795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.4146630795
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.2888534239
Short name T528
Test name
Test status
Simulation time 8634716470 ps
CPU time 5.36 seconds
Started Jul 30 07:40:00 PM PDT 24
Finished Jul 30 07:40:05 PM PDT 24
Peak memory 198528 kb
Host smart-d3cc7a60-4fb8-4ab0-846c-66227690e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888534239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.2888534239
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.2714828970
Short name T581
Test name
Test status
Simulation time 13347339752 ps
CPU time 11.17 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:40:06 PM PDT 24
Peak memory 200104 kb
Host smart-6b970655-007f-485c-a13b-f6a869fc6fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714828970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.2714828970
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.1709387319
Short name T1092
Test name
Test status
Simulation time 14487569151 ps
CPU time 133.37 seconds
Started Jul 30 07:39:59 PM PDT 24
Finished Jul 30 07:42:12 PM PDT 24
Peak memory 199832 kb
Host smart-6be73b40-c677-4677-8738-a5eb0c7fed57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1709387319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1709387319
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.3054497954
Short name T689
Test name
Test status
Simulation time 3674570686 ps
CPU time 18.65 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:40:14 PM PDT 24
Peak memory 198080 kb
Host smart-202c357d-5312-4d16-93c0-7ae3a350a8a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054497954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.3054497954
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.1453470749
Short name T1133
Test name
Test status
Simulation time 12114862286 ps
CPU time 9.42 seconds
Started Jul 30 07:39:55 PM PDT 24
Finished Jul 30 07:40:04 PM PDT 24
Peak memory 199948 kb
Host smart-aaf5b932-0ead-4afb-9b29-996068bc3eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453470749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.1453470749
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.3645958512
Short name T365
Test name
Test status
Simulation time 3783811215 ps
CPU time 4.08 seconds
Started Jul 30 07:39:56 PM PDT 24
Finished Jul 30 07:40:00 PM PDT 24
Peak memory 196124 kb
Host smart-82fad1a4-0056-4c03-84a3-bdfbc4b9ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645958512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3645958512
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3777669022
Short name T1029
Test name
Test status
Simulation time 934163451 ps
CPU time 3.6 seconds
Started Jul 30 07:39:51 PM PDT 24
Finished Jul 30 07:39:55 PM PDT 24
Peak memory 198824 kb
Host smart-a527a693-4d5b-48de-b015-7b2b021bf4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777669022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3777669022
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1969813591
Short name T1135
Test name
Test status
Simulation time 183450094483 ps
CPU time 452.25 seconds
Started Jul 30 07:39:58 PM PDT 24
Finished Jul 30 07:47:30 PM PDT 24
Peak memory 199860 kb
Host smart-679718c8-649c-46c4-afdf-31fad3df672d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969813591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1969813591
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.563709826
Short name T707
Test name
Test status
Simulation time 267931555137 ps
CPU time 762.38 seconds
Started Jul 30 07:40:01 PM PDT 24
Finished Jul 30 07:52:44 PM PDT 24
Peak memory 216452 kb
Host smart-23802a69-2b24-49b6-8e2a-a1ea19b28bb9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563709826 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.563709826
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.3154846016
Short name T852
Test name
Test status
Simulation time 12090371783 ps
CPU time 20.24 seconds
Started Jul 30 07:40:00 PM PDT 24
Finished Jul 30 07:40:20 PM PDT 24
Peak memory 199988 kb
Host smart-d5afc7c3-390d-4cd2-aea9-cea9ef1e2bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154846016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3154846016
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.3806538136
Short name T306
Test name
Test status
Simulation time 67627556091 ps
CPU time 163.88 seconds
Started Jul 30 07:39:51 PM PDT 24
Finished Jul 30 07:42:35 PM PDT 24
Peak memory 199968 kb
Host smart-12f1a8ed-a1df-4fb0-9c82-051ea00c70d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806538136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.3806538136
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3708067022
Short name T965
Test name
Test status
Simulation time 36721420 ps
CPU time 0.54 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:08 PM PDT 24
Peak memory 195380 kb
Host smart-3aca47b6-f5a2-4df0-9d3a-5abae6861cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708067022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3708067022
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3802318518
Short name T1103
Test name
Test status
Simulation time 167014490557 ps
CPU time 326.43 seconds
Started Jul 30 07:39:59 PM PDT 24
Finished Jul 30 07:45:25 PM PDT 24
Peak memory 199900 kb
Host smart-ddb5010a-33a0-4589-85e0-41d520808087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802318518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3802318518
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.2922867738
Short name T753
Test name
Test status
Simulation time 180370642587 ps
CPU time 66.72 seconds
Started Jul 30 07:39:59 PM PDT 24
Finished Jul 30 07:41:06 PM PDT 24
Peak memory 199380 kb
Host smart-a5d35cee-ca00-433d-88aa-a74ab5986c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922867738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.2922867738
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.897730830
Short name T326
Test name
Test status
Simulation time 33529724023 ps
CPU time 14.16 seconds
Started Jul 30 07:40:00 PM PDT 24
Finished Jul 30 07:40:14 PM PDT 24
Peak memory 199988 kb
Host smart-5edd63f3-88dc-48f4-987d-714739484660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897730830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.897730830
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1531396497
Short name T786
Test name
Test status
Simulation time 5364761653 ps
CPU time 13.36 seconds
Started Jul 30 07:40:03 PM PDT 24
Finished Jul 30 07:40:16 PM PDT 24
Peak memory 200012 kb
Host smart-33991f88-e25d-413c-81ae-e391afe6d281
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531396497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1531396497
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3150106103
Short name T10
Test name
Test status
Simulation time 23198824016 ps
CPU time 56.58 seconds
Started Jul 30 07:40:02 PM PDT 24
Finished Jul 30 07:40:59 PM PDT 24
Peak memory 199932 kb
Host smart-661a5c2f-8053-4b48-bf24-8191540a0751
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150106103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3150106103
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.1065209375
Short name T643
Test name
Test status
Simulation time 7224957409 ps
CPU time 3.5 seconds
Started Jul 30 07:40:03 PM PDT 24
Finished Jul 30 07:40:06 PM PDT 24
Peak memory 199392 kb
Host smart-921179d2-e903-4113-870b-530a579e3bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065209375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.1065209375
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.3344556869
Short name T418
Test name
Test status
Simulation time 67957551413 ps
CPU time 28.82 seconds
Started Jul 30 07:40:01 PM PDT 24
Finished Jul 30 07:40:30 PM PDT 24
Peak memory 208304 kb
Host smart-05765b57-65bf-48c0-ad35-fa010a4e86e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344556869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.3344556869
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.2429454425
Short name T1156
Test name
Test status
Simulation time 1746549209 ps
CPU time 53.07 seconds
Started Jul 30 07:40:03 PM PDT 24
Finished Jul 30 07:40:56 PM PDT 24
Peak memory 199884 kb
Host smart-c7f57f55-2a16-4738-89f7-f1190a1c5053
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429454425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2429454425
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.319080027
Short name T338
Test name
Test status
Simulation time 2123626645 ps
CPU time 13.06 seconds
Started Jul 30 07:39:58 PM PDT 24
Finished Jul 30 07:40:11 PM PDT 24
Peak memory 198200 kb
Host smart-99625bbe-195f-4068-8391-6722f0cba1ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=319080027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.319080027
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.229414314
Short name T947
Test name
Test status
Simulation time 107029251484 ps
CPU time 288.92 seconds
Started Jul 30 07:40:04 PM PDT 24
Finished Jul 30 07:44:53 PM PDT 24
Peak memory 199844 kb
Host smart-d32c1694-76ba-4611-839d-d8bd66e375dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229414314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.229414314
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.2169573578
Short name T5
Test name
Test status
Simulation time 3653440532 ps
CPU time 2.82 seconds
Started Jul 30 07:40:02 PM PDT 24
Finished Jul 30 07:40:05 PM PDT 24
Peak memory 196272 kb
Host smart-fa1c026d-06b4-44f5-8fa7-4c6fc9c8bf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169573578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2169573578
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1137315788
Short name T534
Test name
Test status
Simulation time 534203054 ps
CPU time 2.03 seconds
Started Jul 30 07:40:00 PM PDT 24
Finished Jul 30 07:40:02 PM PDT 24
Peak memory 198236 kb
Host smart-7739cc6e-d988-493d-8c08-2b85a4e0f6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137315788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1137315788
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.562733774
Short name T1000
Test name
Test status
Simulation time 33346168253 ps
CPU time 198.16 seconds
Started Jul 30 07:40:03 PM PDT 24
Finished Jul 30 07:43:21 PM PDT 24
Peak memory 216604 kb
Host smart-83c64f01-cb21-4069-8b20-3695c429ddc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562733774 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.562733774
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.2421333961
Short name T1128
Test name
Test status
Simulation time 836942772 ps
CPU time 1.81 seconds
Started Jul 30 07:40:04 PM PDT 24
Finished Jul 30 07:40:06 PM PDT 24
Peak memory 198880 kb
Host smart-17afa2a7-9d29-4af8-ba52-c56653b1026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421333961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.2421333961
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.3394575586
Short name T760
Test name
Test status
Simulation time 23828065788 ps
CPU time 9.13 seconds
Started Jul 30 07:39:59 PM PDT 24
Finished Jul 30 07:40:08 PM PDT 24
Peak memory 199984 kb
Host smart-eaed068a-1828-4192-a0dd-77e748ca6b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394575586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3394575586
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.135153531
Short name T995
Test name
Test status
Simulation time 18133856 ps
CPU time 0.56 seconds
Started Jul 30 07:40:13 PM PDT 24
Finished Jul 30 07:40:14 PM PDT 24
Peak memory 195352 kb
Host smart-0fd701aa-3b9e-46e8-886e-46594699110a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135153531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.135153531
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.180370424
Short name T782
Test name
Test status
Simulation time 32889255270 ps
CPU time 26.47 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:33 PM PDT 24
Peak memory 199864 kb
Host smart-04ac3288-0949-4929-b428-868541127dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180370424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.180370424
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1683760705
Short name T430
Test name
Test status
Simulation time 190917187498 ps
CPU time 39.81 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:47 PM PDT 24
Peak memory 199876 kb
Host smart-20098987-52dc-436b-849b-291b2eae553c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683760705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1683760705
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.423699515
Short name T197
Test name
Test status
Simulation time 63713897571 ps
CPU time 56.93 seconds
Started Jul 30 07:40:13 PM PDT 24
Finished Jul 30 07:41:10 PM PDT 24
Peak memory 199920 kb
Host smart-a8637d8d-a39f-48c1-b2b8-00424162f94a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423699515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.423699515
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.231980287
Short name T671
Test name
Test status
Simulation time 37593515238 ps
CPU time 15.72 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:23 PM PDT 24
Peak memory 199964 kb
Host smart-deab03f6-3d92-4830-93ce-5b78c070e3d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231980287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.231980287
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2020465622
Short name T1142
Test name
Test status
Simulation time 100788691402 ps
CPU time 179.09 seconds
Started Jul 30 07:40:15 PM PDT 24
Finished Jul 30 07:43:14 PM PDT 24
Peak memory 199956 kb
Host smart-dd72c5b1-8e9b-48f3-8f2b-8e972c2a6d23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020465622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2020465622
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.3122886344
Short name T466
Test name
Test status
Simulation time 5389702327 ps
CPU time 3.73 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:11 PM PDT 24
Peak memory 199804 kb
Host smart-b05993ac-969b-4e2b-972a-b439ae8b9182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122886344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.3122886344
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.468578839
Short name T489
Test name
Test status
Simulation time 33491619698 ps
CPU time 59.78 seconds
Started Jul 30 07:40:08 PM PDT 24
Finished Jul 30 07:41:08 PM PDT 24
Peak memory 198612 kb
Host smart-2cfa5441-1490-4b0f-9ca3-061e074ec10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468578839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.468578839
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.3898516723
Short name T468
Test name
Test status
Simulation time 10766895381 ps
CPU time 620.83 seconds
Started Jul 30 07:40:10 PM PDT 24
Finished Jul 30 07:50:31 PM PDT 24
Peak memory 199880 kb
Host smart-8c104aa8-41d1-4d60-9f0e-09c8f3db8774
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3898516723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3898516723
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2605347366
Short name T361
Test name
Test status
Simulation time 2110571707 ps
CPU time 5.18 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:12 PM PDT 24
Peak memory 199260 kb
Host smart-de5e32a4-7804-4cf7-bfca-2397fb649c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605347366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2605347366
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1301929559
Short name T440
Test name
Test status
Simulation time 202973997239 ps
CPU time 46.85 seconds
Started Jul 30 07:40:07 PM PDT 24
Finished Jul 30 07:40:54 PM PDT 24
Peak memory 199964 kb
Host smart-4d98c435-18f1-4c69-88f7-fb7c549daf21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301929559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1301929559
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.3922019133
Short name T103
Test name
Test status
Simulation time 1633150827 ps
CPU time 1.89 seconds
Started Jul 30 07:40:09 PM PDT 24
Finished Jul 30 07:40:11 PM PDT 24
Peak memory 195616 kb
Host smart-3a66caca-cea9-4b6f-b67a-6c23ee7fd8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922019133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.3922019133
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1513268341
Short name T717
Test name
Test status
Simulation time 510122102 ps
CPU time 3.44 seconds
Started Jul 30 07:40:10 PM PDT 24
Finished Jul 30 07:40:14 PM PDT 24
Peak memory 199696 kb
Host smart-6e15de1e-bd48-452a-85a2-a3a587e31221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513268341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1513268341
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1228790067
Short name T807
Test name
Test status
Simulation time 112589079329 ps
CPU time 449 seconds
Started Jul 30 07:40:13 PM PDT 24
Finished Jul 30 07:47:42 PM PDT 24
Peak memory 199976 kb
Host smart-4651e4d4-3cb1-41d1-b182-0cf2687be03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228790067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1228790067
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.3955732303
Short name T35
Test name
Test status
Simulation time 79839540193 ps
CPU time 152.37 seconds
Started Jul 30 07:40:10 PM PDT 24
Finished Jul 30 07:42:43 PM PDT 24
Peak memory 216424 kb
Host smart-8e05225b-d628-4502-b490-bab91f102b40
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955732303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.3955732303
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.2168899491
Short name T670
Test name
Test status
Simulation time 1575073425 ps
CPU time 1.77 seconds
Started Jul 30 07:40:06 PM PDT 24
Finished Jul 30 07:40:08 PM PDT 24
Peak memory 199664 kb
Host smart-62f598bd-0db7-4478-8db6-dfdaf4edd404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168899491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.2168899491
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.2031498813
Short name T512
Test name
Test status
Simulation time 19198722881 ps
CPU time 22.98 seconds
Started Jul 30 07:40:09 PM PDT 24
Finished Jul 30 07:40:32 PM PDT 24
Peak memory 199884 kb
Host smart-a6890495-de38-48ce-9d11-0971fdc21fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031498813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.2031498813
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3912015430
Short name T417
Test name
Test status
Simulation time 18928900 ps
CPU time 0.54 seconds
Started Jul 30 07:40:20 PM PDT 24
Finished Jul 30 07:40:21 PM PDT 24
Peak memory 195352 kb
Host smart-c049d9f4-816a-4312-bb8a-a807f039cb85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912015430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3912015430
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3375083779
Short name T887
Test name
Test status
Simulation time 53794294289 ps
CPU time 50.5 seconds
Started Jul 30 07:40:15 PM PDT 24
Finished Jul 30 07:41:05 PM PDT 24
Peak memory 199968 kb
Host smart-5179fea4-d74d-4ddb-9a7f-fc11108151fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375083779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3375083779
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.1929592503
Short name T695
Test name
Test status
Simulation time 71656657785 ps
CPU time 90.98 seconds
Started Jul 30 07:40:16 PM PDT 24
Finished Jul 30 07:41:47 PM PDT 24
Peak memory 199896 kb
Host smart-6374b3a4-652e-4de8-8e0a-5b8ec4efc8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929592503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.1929592503
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3114546651
Short name T564
Test name
Test status
Simulation time 35550595129 ps
CPU time 12.08 seconds
Started Jul 30 07:40:14 PM PDT 24
Finished Jul 30 07:40:26 PM PDT 24
Peak memory 199932 kb
Host smart-b64dedda-3aef-46a2-8296-28c40caaae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114546651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3114546651
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.952679595
Short name T948
Test name
Test status
Simulation time 311752822802 ps
CPU time 440.73 seconds
Started Jul 30 07:40:17 PM PDT 24
Finished Jul 30 07:47:38 PM PDT 24
Peak memory 198212 kb
Host smart-f151de78-7299-44b5-a5a9-7d2be7086801
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952679595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.952679595
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2610872349
Short name T1021
Test name
Test status
Simulation time 81518106580 ps
CPU time 520.15 seconds
Started Jul 30 07:40:20 PM PDT 24
Finished Jul 30 07:49:00 PM PDT 24
Peak memory 199960 kb
Host smart-7ff709bc-b792-49fd-98e5-8e92edab8361
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2610872349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2610872349
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.4107136107
Short name T487
Test name
Test status
Simulation time 107746714 ps
CPU time 0.74 seconds
Started Jul 30 07:40:18 PM PDT 24
Finished Jul 30 07:40:19 PM PDT 24
Peak memory 195940 kb
Host smart-08bed66d-4b74-4a24-bdce-4e7eaff62ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107136107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.4107136107
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.423292100
Short name T319
Test name
Test status
Simulation time 52657544617 ps
CPU time 43.82 seconds
Started Jul 30 07:40:14 PM PDT 24
Finished Jul 30 07:40:58 PM PDT 24
Peak memory 200108 kb
Host smart-4d714a2d-c2f2-4aea-b575-822fd312d8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423292100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.423292100
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.2130972638
Short name T436
Test name
Test status
Simulation time 13410969655 ps
CPU time 121.32 seconds
Started Jul 30 07:40:19 PM PDT 24
Finished Jul 30 07:42:20 PM PDT 24
Peak memory 199956 kb
Host smart-e457c70a-6839-4ba9-b593-aa900947b490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2130972638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2130972638
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2536787110
Short name T978
Test name
Test status
Simulation time 2905859481 ps
CPU time 17.64 seconds
Started Jul 30 07:40:17 PM PDT 24
Finished Jul 30 07:40:35 PM PDT 24
Peak memory 199016 kb
Host smart-f0667345-0706-4af2-91c5-610fdf869ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536787110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2536787110
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1053057942
Short name T1177
Test name
Test status
Simulation time 24912910603 ps
CPU time 43.33 seconds
Started Jul 30 07:40:18 PM PDT 24
Finished Jul 30 07:41:01 PM PDT 24
Peak memory 199932 kb
Host smart-867f183c-629a-4b0a-8cd4-531334e99130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053057942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1053057942
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3155304080
Short name T431
Test name
Test status
Simulation time 5982443181 ps
CPU time 8.94 seconds
Started Jul 30 07:40:21 PM PDT 24
Finished Jul 30 07:40:30 PM PDT 24
Peak memory 196292 kb
Host smart-b614131f-c157-4531-a559-c5ddff7dfa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155304080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3155304080
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.1098410487
Short name T951
Test name
Test status
Simulation time 465482289 ps
CPU time 2.15 seconds
Started Jul 30 07:40:13 PM PDT 24
Finished Jul 30 07:40:15 PM PDT 24
Peak memory 199380 kb
Host smart-9f2fcb92-2640-4f87-bbff-fc7b4791742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098410487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.1098410487
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.1830756593
Short name T427
Test name
Test status
Simulation time 24978568492 ps
CPU time 171.05 seconds
Started Jul 30 07:40:19 PM PDT 24
Finished Jul 30 07:43:10 PM PDT 24
Peak memory 208264 kb
Host smart-927d7c7f-dbb6-4af4-91e6-afc0c141efa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830756593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.1830756593
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.3939507641
Short name T62
Test name
Test status
Simulation time 312369785163 ps
CPU time 390.44 seconds
Started Jul 30 07:40:19 PM PDT 24
Finished Jul 30 07:46:50 PM PDT 24
Peak memory 208288 kb
Host smart-a0ac0e74-9322-4745-ae6e-8bdbf1a46074
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939507641 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.3939507641
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2076064723
Short name T871
Test name
Test status
Simulation time 917517315 ps
CPU time 2.74 seconds
Started Jul 30 07:40:18 PM PDT 24
Finished Jul 30 07:40:21 PM PDT 24
Peak memory 198508 kb
Host smart-42092393-b7d7-42b8-967e-69b05e88fcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076064723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2076064723
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.3938451172
Short name T1089
Test name
Test status
Simulation time 148132729803 ps
CPU time 73.98 seconds
Started Jul 30 07:40:15 PM PDT 24
Finished Jul 30 07:41:29 PM PDT 24
Peak memory 199876 kb
Host smart-6d9657ce-9bfb-48af-8d3b-e2a8ebdacda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938451172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.3938451172
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.3796869891
Short name T784
Test name
Test status
Simulation time 32851406 ps
CPU time 0.56 seconds
Started Jul 30 07:40:26 PM PDT 24
Finished Jul 30 07:40:27 PM PDT 24
Peak memory 194964 kb
Host smart-feb452f2-154d-475d-b555-ca9513a9704c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796869891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3796869891
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.3177328782
Short name T1102
Test name
Test status
Simulation time 40549908927 ps
CPU time 37.39 seconds
Started Jul 30 07:40:18 PM PDT 24
Finished Jul 30 07:40:55 PM PDT 24
Peak memory 199976 kb
Host smart-27f1edbe-1531-4002-881a-70a79b90093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177328782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.3177328782
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1391038911
Short name T554
Test name
Test status
Simulation time 140396990969 ps
CPU time 63.05 seconds
Started Jul 30 07:40:22 PM PDT 24
Finished Jul 30 07:41:25 PM PDT 24
Peak memory 199932 kb
Host smart-be55cef6-926e-4b6e-a0f8-bde8e4e9d1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391038911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1391038911
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.1943600905
Short name T518
Test name
Test status
Simulation time 31105103432 ps
CPU time 14.98 seconds
Started Jul 30 07:40:25 PM PDT 24
Finished Jul 30 07:40:40 PM PDT 24
Peak memory 199844 kb
Host smart-ec824b6a-8403-46c0-b6d1-7fc860ba6a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943600905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.1943600905
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.1719820539
Short name T698
Test name
Test status
Simulation time 118177880075 ps
CPU time 671.53 seconds
Started Jul 30 07:40:27 PM PDT 24
Finished Jul 30 07:51:39 PM PDT 24
Peak memory 199892 kb
Host smart-3975e724-c008-4962-8971-55fd2a1934c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719820539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.1719820539
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1885702000
Short name T896
Test name
Test status
Simulation time 3903654563 ps
CPU time 2.76 seconds
Started Jul 30 07:40:22 PM PDT 24
Finished Jul 30 07:40:25 PM PDT 24
Peak memory 199784 kb
Host smart-d395a005-e3be-4fb5-822b-6ca17f1bf7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885702000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1885702000
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3544576147
Short name T1152
Test name
Test status
Simulation time 162168995105 ps
CPU time 108.7 seconds
Started Jul 30 07:40:23 PM PDT 24
Finished Jul 30 07:42:11 PM PDT 24
Peak memory 208200 kb
Host smart-be4d0063-9fe6-4233-9ded-b36fafe8297f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544576147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3544576147
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2059698289
Short name T788
Test name
Test status
Simulation time 8241529767 ps
CPU time 94.74 seconds
Started Jul 30 07:40:22 PM PDT 24
Finished Jul 30 07:41:56 PM PDT 24
Peak memory 199968 kb
Host smart-85f48a59-42db-4698-8853-d170d108423b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059698289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2059698289
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2528875199
Short name T984
Test name
Test status
Simulation time 2622762345 ps
CPU time 18.48 seconds
Started Jul 30 07:40:22 PM PDT 24
Finished Jul 30 07:40:41 PM PDT 24
Peak memory 198228 kb
Host smart-93b1d465-b310-4aa3-8c89-ed7a879956bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528875199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2528875199
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2958530573
Short name T1069
Test name
Test status
Simulation time 24872816741 ps
CPU time 41.75 seconds
Started Jul 30 07:40:23 PM PDT 24
Finished Jul 30 07:41:05 PM PDT 24
Peak memory 199968 kb
Host smart-86c97db0-d4de-4cfd-af2a-e403d26440e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958530573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2958530573
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3256266806
Short name T302
Test name
Test status
Simulation time 435557778 ps
CPU time 1.24 seconds
Started Jul 30 07:40:23 PM PDT 24
Finished Jul 30 07:40:24 PM PDT 24
Peak memory 195532 kb
Host smart-b4c2f43c-7fe0-4cbd-be3b-fc45cb97a35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256266806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3256266806
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2445753989
Short name T999
Test name
Test status
Simulation time 693497827 ps
CPU time 3.36 seconds
Started Jul 30 07:40:19 PM PDT 24
Finished Jul 30 07:40:23 PM PDT 24
Peak memory 198864 kb
Host smart-4772adb7-df90-4171-b384-8a8a58610a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445753989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2445753989
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.977769821
Short name T264
Test name
Test status
Simulation time 245801789462 ps
CPU time 58.44 seconds
Started Jul 30 07:40:27 PM PDT 24
Finished Jul 30 07:41:26 PM PDT 24
Peak memory 216152 kb
Host smart-ce37a5fb-2602-4ed8-99b2-4b00a33ed038
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977769821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.977769821
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.3796899237
Short name T636
Test name
Test status
Simulation time 313827868 ps
CPU time 1.34 seconds
Started Jul 30 07:40:25 PM PDT 24
Finished Jul 30 07:40:26 PM PDT 24
Peak memory 198680 kb
Host smart-9c8ee187-c8db-471c-9333-9228648534ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796899237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3796899237
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.2727813764
Short name T941
Test name
Test status
Simulation time 39889495065 ps
CPU time 59.26 seconds
Started Jul 30 07:40:19 PM PDT 24
Finished Jul 30 07:41:18 PM PDT 24
Peak memory 199968 kb
Host smart-a9aee8ec-68af-4858-b7a4-f48987614c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727813764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2727813764
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.3932421567
Short name T881
Test name
Test status
Simulation time 13962666 ps
CPU time 0.54 seconds
Started Jul 30 07:40:32 PM PDT 24
Finished Jul 30 07:40:32 PM PDT 24
Peak memory 194320 kb
Host smart-5ba2ee0f-8363-476d-a051-dde4b484954a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932421567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.3932421567
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3708532679
Short name T955
Test name
Test status
Simulation time 208526982038 ps
CPU time 82.34 seconds
Started Jul 30 07:40:27 PM PDT 24
Finished Jul 30 07:41:49 PM PDT 24
Peak memory 199872 kb
Host smart-3fd24382-63a6-4204-b811-c9fac5b6a2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708532679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3708532679
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2780156718
Short name T745
Test name
Test status
Simulation time 80092487999 ps
CPU time 125.83 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:42:34 PM PDT 24
Peak memory 200004 kb
Host smart-498dd917-2a01-451f-9ff8-f4787dfd0252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780156718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2780156718
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2147956690
Short name T394
Test name
Test status
Simulation time 56443935615 ps
CPU time 75.59 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:41:44 PM PDT 24
Peak memory 199892 kb
Host smart-ba9cdcfd-f6cf-46fb-9a74-da6baf7871de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147956690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2147956690
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2499907315
Short name T901
Test name
Test status
Simulation time 25402874461 ps
CPU time 43.43 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:41:12 PM PDT 24
Peak memory 199952 kb
Host smart-71861229-ce91-4861-b7d4-b43c6b7ffd9f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499907315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2499907315
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2791763421
Short name T454
Test name
Test status
Simulation time 164158440415 ps
CPU time 472.12 seconds
Started Jul 30 07:40:32 PM PDT 24
Finished Jul 30 07:48:25 PM PDT 24
Peak memory 199948 kb
Host smart-80c1c39a-6c2c-4069-bbf4-5b66a01d83d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791763421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2791763421
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3337434502
Short name T882
Test name
Test status
Simulation time 2549745760 ps
CPU time 4.45 seconds
Started Jul 30 07:40:31 PM PDT 24
Finished Jul 30 07:40:36 PM PDT 24
Peak memory 196296 kb
Host smart-1d0c9d08-17fe-4599-89cb-09964c7c7637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337434502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3337434502
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.2856239432
Short name T555
Test name
Test status
Simulation time 84585682271 ps
CPU time 128.25 seconds
Started Jul 30 07:40:30 PM PDT 24
Finished Jul 30 07:42:38 PM PDT 24
Peak memory 199460 kb
Host smart-a46898bf-2c90-4f43-90df-cd571e2cb9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856239432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.2856239432
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.294045158
Short name T996
Test name
Test status
Simulation time 4743717795 ps
CPU time 47.84 seconds
Started Jul 30 07:40:32 PM PDT 24
Finished Jul 30 07:41:20 PM PDT 24
Peak memory 199956 kb
Host smart-79785c4a-9744-4ed6-b40a-741c74d58d5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=294045158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.294045158
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1655406957
Short name T532
Test name
Test status
Simulation time 4215570835 ps
CPU time 30.44 seconds
Started Jul 30 07:40:26 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 198040 kb
Host smart-a6aacddd-b256-477e-9644-c10d51490a20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1655406957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1655406957
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.66467736
Short name T499
Test name
Test status
Simulation time 175849023590 ps
CPU time 119.41 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:42:28 PM PDT 24
Peak memory 199756 kb
Host smart-974ffc9f-140b-4551-a583-e790f1f846e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66467736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.66467736
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.3242085908
Short name T374
Test name
Test status
Simulation time 37860641027 ps
CPU time 16.07 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:40:45 PM PDT 24
Peak memory 196144 kb
Host smart-6388f1d5-070c-48f3-84b2-3309cb50232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242085908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.3242085908
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.509139086
Short name T1168
Test name
Test status
Simulation time 647556810 ps
CPU time 3.27 seconds
Started Jul 30 07:40:27 PM PDT 24
Finished Jul 30 07:40:31 PM PDT 24
Peak memory 199468 kb
Host smart-11f873d3-9bff-4343-bedb-b07702694a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509139086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.509139086
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4009771791
Short name T699
Test name
Test status
Simulation time 161880335793 ps
CPU time 228.81 seconds
Started Jul 30 07:40:31 PM PDT 24
Finished Jul 30 07:44:20 PM PDT 24
Peak memory 199924 kb
Host smart-bbffc4fe-8855-4d21-ba6e-771a3c96f081
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009771791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4009771791
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2633605667
Short name T100
Test name
Test status
Simulation time 42654230550 ps
CPU time 140.87 seconds
Started Jul 30 07:40:32 PM PDT 24
Finished Jul 30 07:42:53 PM PDT 24
Peak memory 216348 kb
Host smart-d1b80f36-47ff-406f-a1e8-9f88aee42582
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633605667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2633605667
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2006681136
Short name T344
Test name
Test status
Simulation time 1188961063 ps
CPU time 2.39 seconds
Started Jul 30 07:40:32 PM PDT 24
Finished Jul 30 07:40:35 PM PDT 24
Peak memory 198964 kb
Host smart-c943db83-62d7-4710-951f-90952de3a2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006681136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2006681136
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2567459227
Short name T301
Test name
Test status
Simulation time 74451178203 ps
CPU time 51.73 seconds
Started Jul 30 07:40:28 PM PDT 24
Finished Jul 30 07:41:20 PM PDT 24
Peak memory 199872 kb
Host smart-1e9a339e-27a0-4ba6-9728-c1dc0241952c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567459227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2567459227
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.824804817
Short name T792
Test name
Test status
Simulation time 32422992 ps
CPU time 0.58 seconds
Started Jul 30 07:40:40 PM PDT 24
Finished Jul 30 07:40:41 PM PDT 24
Peak memory 195668 kb
Host smart-9014b1d9-9773-4dcc-a4aa-1571befcb398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824804817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.824804817
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.2062534936
Short name T139
Test name
Test status
Simulation time 110951361261 ps
CPU time 52.97 seconds
Started Jul 30 07:40:37 PM PDT 24
Finished Jul 30 07:41:30 PM PDT 24
Peak memory 199932 kb
Host smart-e532f2df-0f9d-46b3-ae93-b0e0346be2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062534936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2062534936
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1321901831
Short name T592
Test name
Test status
Simulation time 25524666094 ps
CPU time 48.97 seconds
Started Jul 30 07:40:39 PM PDT 24
Finished Jul 30 07:41:28 PM PDT 24
Peak memory 200004 kb
Host smart-5861db29-d404-4b84-8509-5f3b22fad61e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321901831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1321901831
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.662303142
Short name T289
Test name
Test status
Simulation time 12627351362 ps
CPU time 21.57 seconds
Started Jul 30 07:40:35 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 199932 kb
Host smart-30873cc2-f878-415c-b078-bbafe68722b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662303142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.662303142
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.4263507104
Short name T269
Test name
Test status
Simulation time 61146843364 ps
CPU time 501.47 seconds
Started Jul 30 07:40:41 PM PDT 24
Finished Jul 30 07:49:03 PM PDT 24
Peak memory 199992 kb
Host smart-0ceeca0c-5c51-42ce-9294-d6c7f82e963f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4263507104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.4263507104
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2240841790
Short name T386
Test name
Test status
Simulation time 7348222872 ps
CPU time 14.81 seconds
Started Jul 30 07:40:42 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 199940 kb
Host smart-90da48f7-0fd4-4d77-bfd8-b44ea170d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240841790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2240841790
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.3643268215
Short name T902
Test name
Test status
Simulation time 103653011123 ps
CPU time 43.38 seconds
Started Jul 30 07:40:37 PM PDT 24
Finished Jul 30 07:41:21 PM PDT 24
Peak memory 198284 kb
Host smart-4b946c0a-3a35-4f57-945a-2dd6476da969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643268215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.3643268215
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3823739676
Short name T259
Test name
Test status
Simulation time 12142676691 ps
CPU time 272.22 seconds
Started Jul 30 07:40:42 PM PDT 24
Finished Jul 30 07:45:14 PM PDT 24
Peak memory 199964 kb
Host smart-db94411a-7348-4d8b-927b-b324ee37a2b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3823739676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3823739676
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1135603244
Short name T446
Test name
Test status
Simulation time 2843487173 ps
CPU time 6.44 seconds
Started Jul 30 07:40:39 PM PDT 24
Finished Jul 30 07:40:45 PM PDT 24
Peak memory 198972 kb
Host smart-63cea3b1-3255-48f7-80b5-a80a38476a2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1135603244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1135603244
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2007212432
Short name T285
Test name
Test status
Simulation time 231484965365 ps
CPU time 259.13 seconds
Started Jul 30 07:40:41 PM PDT 24
Finished Jul 30 07:45:00 PM PDT 24
Peak memory 199956 kb
Host smart-07195809-f7c0-49a4-be9d-b56f46c81782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007212432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2007212432
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.84860164
Short name T371
Test name
Test status
Simulation time 3562924664 ps
CPU time 3.74 seconds
Started Jul 30 07:40:37 PM PDT 24
Finished Jul 30 07:40:41 PM PDT 24
Peak memory 196108 kb
Host smart-8eb26a16-fd60-4cc8-9e1f-19a4da999207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84860164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.84860164
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2674582720
Short name T429
Test name
Test status
Simulation time 271653566 ps
CPU time 1.39 seconds
Started Jul 30 07:40:36 PM PDT 24
Finished Jul 30 07:40:37 PM PDT 24
Peak memory 198240 kb
Host smart-6cafd99f-a6f4-4f76-9757-cd23bff9a040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674582720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2674582720
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.1935071284
Short name T1171
Test name
Test status
Simulation time 97382698334 ps
CPU time 164.94 seconds
Started Jul 30 07:40:40 PM PDT 24
Finished Jul 30 07:43:26 PM PDT 24
Peak memory 199920 kb
Host smart-45365721-b7d9-4705-97cb-aed6a0a466aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935071284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1935071284
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1052879982
Short name T101
Test name
Test status
Simulation time 32731215328 ps
CPU time 193.76 seconds
Started Jul 30 07:40:42 PM PDT 24
Finished Jul 30 07:43:56 PM PDT 24
Peak memory 216652 kb
Host smart-c93d0c7b-d6b0-4e91-a292-f891380bc30b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052879982 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1052879982
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.2625970802
Short name T659
Test name
Test status
Simulation time 8857576223 ps
CPU time 17.2 seconds
Started Jul 30 07:40:40 PM PDT 24
Finished Jul 30 07:40:57 PM PDT 24
Peak memory 199632 kb
Host smart-32388db9-a9d1-4610-b55c-d8bc3f044be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625970802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.2625970802
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3077338772
Short name T578
Test name
Test status
Simulation time 111715286857 ps
CPU time 15.87 seconds
Started Jul 30 07:40:36 PM PDT 24
Finished Jul 30 07:40:52 PM PDT 24
Peak memory 199456 kb
Host smart-afb8f5e8-1120-47bb-ba0c-8bc4547b3af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077338772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3077338772
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3130955731
Short name T1113
Test name
Test status
Simulation time 34138902 ps
CPU time 0.55 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:40:50 PM PDT 24
Peak memory 195376 kb
Host smart-adacf501-b995-4885-a313-e3616952a2c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130955731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3130955731
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3459685529
Short name T536
Test name
Test status
Simulation time 126542060717 ps
CPU time 239.84 seconds
Started Jul 30 07:40:42 PM PDT 24
Finished Jul 30 07:44:42 PM PDT 24
Peak memory 199940 kb
Host smart-39fec013-380c-4898-9b0d-1abf138da2c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459685529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3459685529
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1874377877
Short name T421
Test name
Test status
Simulation time 31701912955 ps
CPU time 17.38 seconds
Started Jul 30 07:40:42 PM PDT 24
Finished Jul 30 07:41:00 PM PDT 24
Peak memory 199932 kb
Host smart-7eb7d6a9-9ddd-494f-ad2e-c37f6756787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874377877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1874377877
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.3108243322
Short name T827
Test name
Test status
Simulation time 87214601775 ps
CPU time 132.55 seconds
Started Jul 30 07:40:44 PM PDT 24
Finished Jul 30 07:42:57 PM PDT 24
Peak memory 199964 kb
Host smart-454b2056-5bfb-4aab-ae86-ee8168807366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108243322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.3108243322
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.1547155220
Short name T639
Test name
Test status
Simulation time 47996214302 ps
CPU time 22.27 seconds
Started Jul 30 07:40:43 PM PDT 24
Finished Jul 30 07:41:06 PM PDT 24
Peak memory 199976 kb
Host smart-87f67ba4-e769-4afd-9ac1-fc96dc5f7170
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547155220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.1547155220
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.1428969992
Short name T906
Test name
Test status
Simulation time 96775534788 ps
CPU time 412.28 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:47:42 PM PDT 24
Peak memory 199944 kb
Host smart-8e9e0004-0198-466c-b822-4533436ea62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428969992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.1428969992
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.3579176026
Short name T1091
Test name
Test status
Simulation time 10088049190 ps
CPU time 3.32 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:40:52 PM PDT 24
Peak memory 199484 kb
Host smart-b2ba0a06-cb3e-49d3-b742-fb78db9b1888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579176026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.3579176026
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1968041486
Short name T107
Test name
Test status
Simulation time 80413318547 ps
CPU time 93.77 seconds
Started Jul 30 07:40:45 PM PDT 24
Finished Jul 30 07:42:19 PM PDT 24
Peak memory 208292 kb
Host smart-23aacdc8-8b77-4991-b28d-0b168df08982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968041486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1968041486
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.4150151711
Short name T771
Test name
Test status
Simulation time 12401798044 ps
CPU time 163.68 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:43:33 PM PDT 24
Peak memory 199960 kb
Host smart-e33ca195-a87b-48a0-801e-246514572ea4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4150151711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.4150151711
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.3300176327
Short name T501
Test name
Test status
Simulation time 6608230975 ps
CPU time 57.4 seconds
Started Jul 30 07:40:44 PM PDT 24
Finished Jul 30 07:41:41 PM PDT 24
Peak memory 198528 kb
Host smart-6a42d055-2f3c-4586-b5a7-bc86bed57b87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3300176327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.3300176327
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2349101897
Short name T419
Test name
Test status
Simulation time 76972510312 ps
CPU time 56.54 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:41:46 PM PDT 24
Peak memory 199732 kb
Host smart-6bba2fcf-0329-4980-9d1b-e204ff969395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349101897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2349101897
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1493764229
Short name T310
Test name
Test status
Simulation time 37785924505 ps
CPU time 29.12 seconds
Started Jul 30 07:40:43 PM PDT 24
Finished Jul 30 07:41:13 PM PDT 24
Peak memory 195920 kb
Host smart-e114ff1a-195e-455e-91de-0736bd144e5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493764229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1493764229
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3413914728
Short name T516
Test name
Test status
Simulation time 259168696 ps
CPU time 1.01 seconds
Started Jul 30 07:40:41 PM PDT 24
Finished Jul 30 07:40:42 PM PDT 24
Peak memory 198260 kb
Host smart-db3d7f9b-aac7-436a-94a8-aebfde5246ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413914728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3413914728
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1238678147
Short name T544
Test name
Test status
Simulation time 127144464999 ps
CPU time 417.77 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:47:47 PM PDT 24
Peak memory 199960 kb
Host smart-bf681b17-0a12-44fc-8af3-4b4ceb7516e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238678147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1238678147
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.984226625
Short name T481
Test name
Test status
Simulation time 22164386008 ps
CPU time 494.62 seconds
Started Jul 30 07:40:47 PM PDT 24
Finished Jul 30 07:49:02 PM PDT 24
Peak memory 216468 kb
Host smart-47e60a5e-0310-4079-8340-6012b18c9eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984226625 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.984226625
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.492068975
Short name T989
Test name
Test status
Simulation time 1371465439 ps
CPU time 4.78 seconds
Started Jul 30 07:40:49 PM PDT 24
Finished Jul 30 07:40:53 PM PDT 24
Peak memory 198312 kb
Host smart-7e8b6f6a-2578-4bac-91db-81e66acdc9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492068975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.492068975
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1301625207
Short name T256
Test name
Test status
Simulation time 87441133555 ps
CPU time 153.19 seconds
Started Jul 30 07:40:41 PM PDT 24
Finished Jul 30 07:43:15 PM PDT 24
Peak memory 200000 kb
Host smart-87671282-e100-41e8-921b-6d486627ab33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301625207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1301625207
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1729680169
Short name T1126
Test name
Test status
Simulation time 13207902 ps
CPU time 0.56 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:36:55 PM PDT 24
Peak memory 195664 kb
Host smart-300091ff-c6b6-419a-baf3-892463a9dfd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729680169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1729680169
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.343727523
Short name T904
Test name
Test status
Simulation time 352642216913 ps
CPU time 127.72 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:39:03 PM PDT 24
Peak memory 199960 kb
Host smart-0cd02dd9-1940-4a20-bb6e-cdbb899ca149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343727523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.343727523
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3680702080
Short name T44
Test name
Test status
Simulation time 57293312099 ps
CPU time 29.48 seconds
Started Jul 30 07:36:44 PM PDT 24
Finished Jul 30 07:37:13 PM PDT 24
Peak memory 199960 kb
Host smart-ce214482-9934-4a47-a4d1-491d19d4780d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680702080 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3680702080
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.927395380
Short name T121
Test name
Test status
Simulation time 72706984751 ps
CPU time 100.72 seconds
Started Jul 30 07:36:45 PM PDT 24
Finished Jul 30 07:38:26 PM PDT 24
Peak memory 200012 kb
Host smart-bb5abcaf-55b0-4709-bd93-d83037052675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927395380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.927395380
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1068184398
Short name T253
Test name
Test status
Simulation time 13355334682 ps
CPU time 14.09 seconds
Started Jul 30 07:36:44 PM PDT 24
Finished Jul 30 07:36:58 PM PDT 24
Peak memory 200048 kb
Host smart-3f2c3eb8-c7d0-4092-91a2-7d19332bba19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068184398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1068184398
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3080206837
Short name T102
Test name
Test status
Simulation time 97886827494 ps
CPU time 275.99 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:41:22 PM PDT 24
Peak memory 199948 kb
Host smart-ddd6a759-86df-4ad8-a0dc-ecfcab2afbaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3080206837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3080206837
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3802518846
Short name T835
Test name
Test status
Simulation time 11025771325 ps
CPU time 20.28 seconds
Started Jul 30 07:36:44 PM PDT 24
Finished Jul 30 07:37:04 PM PDT 24
Peak memory 199992 kb
Host smart-02f93563-a452-412a-a76f-99ae4a54812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802518846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3802518846
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3081675889
Short name T908
Test name
Test status
Simulation time 86334525662 ps
CPU time 31.48 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:21 PM PDT 24
Peak memory 208320 kb
Host smart-e388ea74-532a-4765-8d93-c5ff15d26c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081675889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3081675889
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.356918028
Short name T813
Test name
Test status
Simulation time 7586796991 ps
CPU time 208.27 seconds
Started Jul 30 07:36:45 PM PDT 24
Finished Jul 30 07:40:14 PM PDT 24
Peak memory 199968 kb
Host smart-41558e8f-4dec-494e-b947-757a0145b971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356918028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.356918028
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.3535336223
Short name T444
Test name
Test status
Simulation time 6655928538 ps
CPU time 57.98 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:37:44 PM PDT 24
Peak memory 198000 kb
Host smart-3d005270-751a-4997-a0d5-da3cac3e1f41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3535336223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.3535336223
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.276121334
Short name T469
Test name
Test status
Simulation time 31630749206 ps
CPU time 44.02 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:33 PM PDT 24
Peak memory 199684 kb
Host smart-a08b653d-0893-4226-9650-8afebac0efad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276121334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.276121334
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1099454962
Short name T527
Test name
Test status
Simulation time 1867755232 ps
CPU time 3.4 seconds
Started Jul 30 07:36:47 PM PDT 24
Finished Jul 30 07:36:51 PM PDT 24
Peak memory 195536 kb
Host smart-fa6e56ef-cfd1-4769-9059-1bf5fdff1074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099454962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1099454962
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2590876930
Short name T1080
Test name
Test status
Simulation time 5535265659 ps
CPU time 11.97 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:36:58 PM PDT 24
Peak memory 199688 kb
Host smart-a361fa1e-6702-43fd-8cdb-12d1ddead4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590876930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2590876930
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3056471412
Short name T322
Test name
Test status
Simulation time 168975066285 ps
CPU time 65.61 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:37:52 PM PDT 24
Peak memory 199928 kb
Host smart-e66bdbca-f7d3-4cc2-87ae-d8710e56d0fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056471412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3056471412
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.2424214172
Short name T711
Test name
Test status
Simulation time 302010078676 ps
CPU time 1005.94 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:53:41 PM PDT 24
Peak memory 216484 kb
Host smart-e7edb214-08d9-4e74-869a-e12c2f07aecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424214172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.2424214172
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.245688457
Short name T483
Test name
Test status
Simulation time 507074914 ps
CPU time 2.45 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:36:57 PM PDT 24
Peak memory 198676 kb
Host smart-61afcdfc-f496-4ee2-bea8-ec56bdd980de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245688457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.245688457
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.3428786832
Short name T442
Test name
Test status
Simulation time 55002967184 ps
CPU time 105.41 seconds
Started Jul 30 07:36:41 PM PDT 24
Finished Jul 30 07:38:27 PM PDT 24
Peak memory 199976 kb
Host smart-2c123915-1c2d-41a3-b229-159cd6e8988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428786832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.3428786832
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.1638004520
Short name T728
Test name
Test status
Simulation time 8642459808 ps
CPU time 14.08 seconds
Started Jul 30 07:40:51 PM PDT 24
Finished Jul 30 07:41:05 PM PDT 24
Peak memory 199980 kb
Host smart-7b21b3d8-d3b4-4d05-a1be-24488b2f5202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638004520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1638004520
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2470674945
Short name T1108
Test name
Test status
Simulation time 15111166024 ps
CPU time 504.43 seconds
Started Jul 30 07:40:48 PM PDT 24
Finished Jul 30 07:49:13 PM PDT 24
Peak memory 208376 kb
Host smart-77bb4c10-42f1-49e3-97e9-8d648c7f273c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470674945 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2470674945
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.1901453376
Short name T520
Test name
Test status
Simulation time 87273977717 ps
CPU time 156.14 seconds
Started Jul 30 07:40:48 PM PDT 24
Finished Jul 30 07:43:24 PM PDT 24
Peak memory 199960 kb
Host smart-23d6c387-8308-43a1-a14a-137045b1a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901453376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1901453376
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.328014411
Short name T237
Test name
Test status
Simulation time 337392822221 ps
CPU time 72.63 seconds
Started Jul 30 07:40:52 PM PDT 24
Finished Jul 30 07:42:05 PM PDT 24
Peak memory 199972 kb
Host smart-4f0afdb9-6110-480b-8f57-6c28a97c5edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328014411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.328014411
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2364304955
Short name T300
Test name
Test status
Simulation time 24208017897 ps
CPU time 133.73 seconds
Started Jul 30 07:40:53 PM PDT 24
Finished Jul 30 07:43:07 PM PDT 24
Peak memory 208368 kb
Host smart-6bbb550e-98e0-4f12-98f2-529102e4a153
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364304955 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2364304955
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.582124350
Short name T1016
Test name
Test status
Simulation time 19457854676 ps
CPU time 32.16 seconds
Started Jul 30 07:41:01 PM PDT 24
Finished Jul 30 07:41:34 PM PDT 24
Peak memory 199944 kb
Host smart-203b7bb3-6be9-4dda-b45d-943e204ac2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582124350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.582124350
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.171079741
Short name T1099
Test name
Test status
Simulation time 187809345551 ps
CPU time 914.53 seconds
Started Jul 30 07:40:53 PM PDT 24
Finished Jul 30 07:56:08 PM PDT 24
Peak memory 228676 kb
Host smart-2ec8c883-305f-43a5-95f7-6446b193b318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171079741 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.171079741
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.3545998850
Short name T733
Test name
Test status
Simulation time 52569419444 ps
CPU time 54.22 seconds
Started Jul 30 07:40:52 PM PDT 24
Finished Jul 30 07:41:47 PM PDT 24
Peak memory 199904 kb
Host smart-df241c0b-1a97-4fc0-b380-848680311346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545998850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.3545998850
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.92096471
Short name T765
Test name
Test status
Simulation time 258960855675 ps
CPU time 2230.51 seconds
Started Jul 30 07:40:54 PM PDT 24
Finished Jul 30 08:18:05 PM PDT 24
Peak memory 232976 kb
Host smart-87a6e533-69c8-4d74-bb44-8369e747ffce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92096471 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.92096471
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.145158455
Short name T360
Test name
Test status
Simulation time 46946188680 ps
CPU time 20.81 seconds
Started Jul 30 07:40:53 PM PDT 24
Finished Jul 30 07:41:14 PM PDT 24
Peak memory 199920 kb
Host smart-32699d43-d5e9-4ec9-a247-10f0f4bfedd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145158455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.145158455
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3790469799
Short name T281
Test name
Test status
Simulation time 181603181628 ps
CPU time 623.19 seconds
Started Jul 30 07:40:54 PM PDT 24
Finished Jul 30 07:51:17 PM PDT 24
Peak memory 224740 kb
Host smart-5581187e-27f5-46ff-805c-66f126c96e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790469799 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3790469799
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.1057630335
Short name T1004
Test name
Test status
Simulation time 38184643369 ps
CPU time 32.22 seconds
Started Jul 30 07:40:58 PM PDT 24
Finished Jul 30 07:41:30 PM PDT 24
Peak memory 199932 kb
Host smart-0ffd94a1-f3d9-426c-9854-291919cda18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057630335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.1057630335
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2987674438
Short name T981
Test name
Test status
Simulation time 13250668018 ps
CPU time 254.47 seconds
Started Jul 30 07:40:56 PM PDT 24
Finished Jul 30 07:45:10 PM PDT 24
Peak memory 208324 kb
Host smart-223173da-1166-4d2a-813e-c68a612dc46d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987674438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2987674438
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2480231826
Short name T729
Test name
Test status
Simulation time 81726282198 ps
CPU time 68.08 seconds
Started Jul 30 07:40:57 PM PDT 24
Finished Jul 30 07:42:05 PM PDT 24
Peak memory 199860 kb
Host smart-ce95af41-8ed4-43d0-adfb-5b0bb4e1b22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480231826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2480231826
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1456016047
Short name T18
Test name
Test status
Simulation time 41242827129 ps
CPU time 526.44 seconds
Started Jul 30 07:40:56 PM PDT 24
Finished Jul 30 07:49:43 PM PDT 24
Peak memory 216512 kb
Host smart-0f5ce4a0-5036-4224-b848-51adaff17728
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456016047 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1456016047
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1887869361
Short name T821
Test name
Test status
Simulation time 157389912448 ps
CPU time 24.98 seconds
Started Jul 30 07:40:56 PM PDT 24
Finished Jul 30 07:41:21 PM PDT 24
Peak memory 199972 kb
Host smart-d9f4a26f-f798-4b55-b1f1-78718aed547f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887869361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1887869361
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.383156008
Short name T863
Test name
Test status
Simulation time 30296223521 ps
CPU time 265.6 seconds
Started Jul 30 07:40:56 PM PDT 24
Finished Jul 30 07:45:21 PM PDT 24
Peak memory 216304 kb
Host smart-3d5f1c03-ac11-4c2b-9085-7fe12bc4baf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383156008 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.383156008
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3078247270
Short name T938
Test name
Test status
Simulation time 60749837465 ps
CPU time 48.78 seconds
Started Jul 30 07:40:57 PM PDT 24
Finished Jul 30 07:41:46 PM PDT 24
Peak memory 199948 kb
Host smart-22e2b12f-6689-4eb2-96df-71953026e380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078247270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3078247270
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1096758836
Short name T591
Test name
Test status
Simulation time 34126912 ps
CPU time 0.54 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:36:55 PM PDT 24
Peak memory 195344 kb
Host smart-6278e3c9-538e-49fc-ba8e-c20b72533a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096758836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1096758836
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3161951192
Short name T1129
Test name
Test status
Simulation time 74095974351 ps
CPU time 24.06 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:37:19 PM PDT 24
Peak memory 199996 kb
Host smart-6982230a-c176-4097-a453-c16e897a9a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161951192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3161951192
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3423738973
Short name T672
Test name
Test status
Simulation time 100047180197 ps
CPU time 46.43 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:41 PM PDT 24
Peak memory 199996 kb
Host smart-d4d963b2-281f-4212-a5c6-3df1f618bfe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423738973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3423738973
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2570661556
Short name T789
Test name
Test status
Simulation time 73488046286 ps
CPU time 16.51 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:10 PM PDT 24
Peak memory 199892 kb
Host smart-5bdc8221-30b8-4f36-aa7b-832da4c1984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570661556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2570661556
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2785422745
Short name T815
Test name
Test status
Simulation time 3038386944 ps
CPU time 2.98 seconds
Started Jul 30 07:36:45 PM PDT 24
Finished Jul 30 07:36:49 PM PDT 24
Peak memory 196728 kb
Host smart-dc01fb43-80e5-489b-a36c-02b54fcf6b03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785422745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2785422745
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2054604304
Short name T831
Test name
Test status
Simulation time 77729531967 ps
CPU time 292.03 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:41:46 PM PDT 24
Peak memory 199920 kb
Host smart-6fcee693-ac56-47b2-b4a1-73b5f5138057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2054604304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2054604304
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.2597618457
Short name T408
Test name
Test status
Simulation time 6906797126 ps
CPU time 4.61 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:36:59 PM PDT 24
Peak memory 198804 kb
Host smart-28cbc1ea-1217-42c9-85d9-06ccff81f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597618457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.2597618457
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1483016701
Short name T1019
Test name
Test status
Simulation time 74754872431 ps
CPU time 77.52 seconds
Started Jul 30 07:36:44 PM PDT 24
Finished Jul 30 07:38:02 PM PDT 24
Peak memory 198252 kb
Host smart-398cc810-c441-4762-a581-f7b5eba0cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483016701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1483016701
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.870145105
Short name T856
Test name
Test status
Simulation time 17161896194 ps
CPU time 262.55 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:41:12 PM PDT 24
Peak memory 199976 kb
Host smart-84fe1334-5843-473d-ad67-d20af6a5c82c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=870145105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.870145105
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.1442090501
Short name T24
Test name
Test status
Simulation time 5660273774 ps
CPU time 11.87 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:37:00 PM PDT 24
Peak memory 198532 kb
Host smart-92a7f1a9-8192-4c6e-bdeb-cc9c376f7233
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1442090501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1442090501
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1373094829
Short name T839
Test name
Test status
Simulation time 46195195938 ps
CPU time 70.89 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:38:00 PM PDT 24
Peak memory 199660 kb
Host smart-9e559d75-aae7-4af5-bed1-dd81748936bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373094829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1373094829
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.167520152
Short name T687
Test name
Test status
Simulation time 36262119584 ps
CPU time 6.91 seconds
Started Jul 30 07:36:47 PM PDT 24
Finished Jul 30 07:36:55 PM PDT 24
Peak memory 195824 kb
Host smart-08c57746-96c9-4329-9e47-f2d58b14f181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167520152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.167520152
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.29805119
Short name T1053
Test name
Test status
Simulation time 678031376 ps
CPU time 1.94 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:36:48 PM PDT 24
Peak memory 198716 kb
Host smart-feff47d8-dc9f-4bb8-8dc3-b4949ad61e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29805119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.29805119
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3369846430
Short name T462
Test name
Test status
Simulation time 249900219893 ps
CPU time 512.92 seconds
Started Jul 30 07:36:47 PM PDT 24
Finished Jul 30 07:45:20 PM PDT 24
Peak memory 228228 kb
Host smart-5e5cc7f4-f553-40bb-b869-c13a9bf7b457
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369846430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3369846430
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.1946732244
Short name T1096
Test name
Test status
Simulation time 741985821 ps
CPU time 2.75 seconds
Started Jul 30 07:36:46 PM PDT 24
Finished Jul 30 07:36:49 PM PDT 24
Peak memory 198984 kb
Host smart-c9561c5b-acb2-42bb-89ab-8c546e4201b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946732244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.1946732244
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1143399491
Short name T1085
Test name
Test status
Simulation time 182211941874 ps
CPU time 135.46 seconds
Started Jul 30 07:36:47 PM PDT 24
Finished Jul 30 07:39:02 PM PDT 24
Peak memory 199920 kb
Host smart-a30a72b1-4ab5-4b85-93ce-03bf8d91045e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143399491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1143399491
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.4001403410
Short name T133
Test name
Test status
Simulation time 142860798120 ps
CPU time 118.85 seconds
Started Jul 30 07:40:56 PM PDT 24
Finished Jul 30 07:42:55 PM PDT 24
Peak memory 199972 kb
Host smart-5b23b621-b2a4-477a-811f-1409ca614a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001403410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.4001403410
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3522832606
Short name T274
Test name
Test status
Simulation time 74102915907 ps
CPU time 714 seconds
Started Jul 30 07:40:57 PM PDT 24
Finished Jul 30 07:52:51 PM PDT 24
Peak memory 216468 kb
Host smart-6a6a3d3e-c940-45c6-8b6d-7537575e1b7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522832606 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3522832606
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.3402028640
Short name T455
Test name
Test status
Simulation time 72356235779 ps
CPU time 52.61 seconds
Started Jul 30 07:41:04 PM PDT 24
Finished Jul 30 07:41:57 PM PDT 24
Peak memory 199920 kb
Host smart-5669aaa4-a9fa-479f-892c-2eebc6694f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402028640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.3402028640
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2366087908
Short name T674
Test name
Test status
Simulation time 85390866405 ps
CPU time 919.3 seconds
Started Jul 30 07:41:02 PM PDT 24
Finished Jul 30 07:56:22 PM PDT 24
Peak memory 227000 kb
Host smart-1b7cef34-7f41-4793-bd38-6267b632a3c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366087908 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2366087908
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3943702044
Short name T808
Test name
Test status
Simulation time 152063478267 ps
CPU time 129.65 seconds
Started Jul 30 07:41:04 PM PDT 24
Finished Jul 30 07:43:14 PM PDT 24
Peak memory 199940 kb
Host smart-6e0f6180-e42a-4e22-9d20-bd65143efd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943702044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3943702044
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1893583235
Short name T222
Test name
Test status
Simulation time 45015545668 ps
CPU time 500.8 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:49:23 PM PDT 24
Peak memory 216464 kb
Host smart-35953969-f93f-4f2a-93df-26c71cd96452
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893583235 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1893583235
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2954168229
Short name T132
Test name
Test status
Simulation time 79475189755 ps
CPU time 17.59 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:41:20 PM PDT 24
Peak memory 199912 kb
Host smart-b59dd793-b83e-4d00-baae-5b2a0ad4e767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954168229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2954168229
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1905205355
Short name T1005
Test name
Test status
Simulation time 187215720233 ps
CPU time 984.32 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:57:27 PM PDT 24
Peak memory 229528 kb
Host smart-9a47170d-2ba8-4887-ba29-2b4318aea687
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905205355 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1905205355
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.1225632986
Short name T209
Test name
Test status
Simulation time 106417820849 ps
CPU time 44.46 seconds
Started Jul 30 07:41:00 PM PDT 24
Finished Jul 30 07:41:44 PM PDT 24
Peak memory 199780 kb
Host smart-7c424101-165d-47ed-b96f-abdf569fa084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225632986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.1225632986
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.3938018278
Short name T899
Test name
Test status
Simulation time 421237920373 ps
CPU time 540.12 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:50:03 PM PDT 24
Peak memory 216712 kb
Host smart-6bb5f009-1043-40af-a9ed-01ab45128833
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938018278 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.3938018278
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1775119386
Short name T32
Test name
Test status
Simulation time 14305511968 ps
CPU time 126.07 seconds
Started Jul 30 07:40:59 PM PDT 24
Finished Jul 30 07:43:06 PM PDT 24
Peak memory 208400 kb
Host smart-79b53557-982f-4564-842a-c36f42cd7694
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775119386 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1775119386
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.234636178
Short name T152
Test name
Test status
Simulation time 13962037360 ps
CPU time 21.33 seconds
Started Jul 30 07:41:03 PM PDT 24
Finished Jul 30 07:41:24 PM PDT 24
Peak memory 199892 kb
Host smart-e27ef642-c2d9-45a5-aadb-72fd4d358125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234636178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.234636178
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2221584986
Short name T304
Test name
Test status
Simulation time 76433032165 ps
CPU time 253.08 seconds
Started Jul 30 07:41:01 PM PDT 24
Finished Jul 30 07:45:14 PM PDT 24
Peak memory 216472 kb
Host smart-ad6f1bc9-24b9-4fac-b8ab-ce194c986c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221584986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2221584986
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3104052088
Short name T251
Test name
Test status
Simulation time 38876465664 ps
CPU time 16.62 seconds
Started Jul 30 07:41:05 PM PDT 24
Finished Jul 30 07:41:22 PM PDT 24
Peak memory 199952 kb
Host smart-37fc877e-43c2-4612-bc63-cd23092e2a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104052088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3104052088
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1169486012
Short name T97
Test name
Test status
Simulation time 213789913099 ps
CPU time 888.32 seconds
Started Jul 30 07:41:05 PM PDT 24
Finished Jul 30 07:55:53 PM PDT 24
Peak memory 216528 kb
Host smart-b24f8c5e-0b4e-4d5f-abfd-29b61dbc8dfb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169486012 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1169486012
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.3464420957
Short name T1056
Test name
Test status
Simulation time 25340420647 ps
CPU time 12.69 seconds
Started Jul 30 07:41:07 PM PDT 24
Finished Jul 30 07:41:20 PM PDT 24
Peak memory 200000 kb
Host smart-46dd3c26-8610-4212-879c-e4bb4574fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464420957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3464420957
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.3921860768
Short name T238
Test name
Test status
Simulation time 204091339000 ps
CPU time 643.47 seconds
Started Jul 30 07:41:06 PM PDT 24
Finished Jul 30 07:51:50 PM PDT 24
Peak memory 216464 kb
Host smart-288fe0f9-2584-49a6-9dbd-11782f359a65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921860768 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.3921860768
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2981283836
Short name T859
Test name
Test status
Simulation time 73868623846 ps
CPU time 1290.61 seconds
Started Jul 30 07:41:05 PM PDT 24
Finished Jul 30 08:02:36 PM PDT 24
Peak memory 225788 kb
Host smart-91774f5b-c135-4a0a-a4f4-c500c7ad8349
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981283836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2981283836
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.1823247645
Short name T28
Test name
Test status
Simulation time 61825828 ps
CPU time 0.58 seconds
Started Jul 30 07:36:52 PM PDT 24
Finished Jul 30 07:36:53 PM PDT 24
Peak memory 195300 kb
Host smart-c2df3464-83f6-4526-825d-026e5673adbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823247645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.1823247645
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3631488851
Short name T1051
Test name
Test status
Simulation time 23878431053 ps
CPU time 36.99 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:31 PM PDT 24
Peak memory 199936 kb
Host smart-03936a7e-c0f4-4ca8-9699-fea8f80084e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631488851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3631488851
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.3744671774
Short name T130
Test name
Test status
Simulation time 84694800867 ps
CPU time 128.66 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:39:03 PM PDT 24
Peak memory 199928 kb
Host smart-ba9a41c9-33a0-47f3-82d0-fade2004b660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744671774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.3744671774
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1917737187
Short name T1148
Test name
Test status
Simulation time 21055599820 ps
CPU time 8.46 seconds
Started Jul 30 07:36:50 PM PDT 24
Finished Jul 30 07:36:58 PM PDT 24
Peak memory 199812 kb
Host smart-338244b5-5356-4eec-b722-feb00ce263ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917737187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1917737187
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3983119048
Short name T841
Test name
Test status
Simulation time 29439260474 ps
CPU time 11.98 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:37:00 PM PDT 24
Peak memory 198284 kb
Host smart-ec13013d-def4-4002-bd43-e20ed0b98c52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983119048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3983119048
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3219389793
Short name T1144
Test name
Test status
Simulation time 64876842235 ps
CPU time 592.26 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:46:42 PM PDT 24
Peak memory 199888 kb
Host smart-0d7a674b-31f8-4032-a133-6658b23a4a7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219389793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3219389793
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.3011129963
Short name T335
Test name
Test status
Simulation time 2673806862 ps
CPU time 4.77 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:36:53 PM PDT 24
Peak memory 199708 kb
Host smart-2c824940-8d3f-4ad0-bfb9-f8b8a928a375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011129963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3011129963
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.567278912
Short name T255
Test name
Test status
Simulation time 41965091391 ps
CPU time 35.25 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:30 PM PDT 24
Peak memory 198884 kb
Host smart-71a4fef8-4d2f-4ee6-9397-18c41aaa851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567278912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.567278912
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.2479814917
Short name T780
Test name
Test status
Simulation time 19538148502 ps
CPU time 492.09 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:45:01 PM PDT 24
Peak memory 199928 kb
Host smart-5fbf8030-f5b2-48e3-a056-4b1f7b80dedb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2479814917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2479814917
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.3844047105
Short name T571
Test name
Test status
Simulation time 4956667334 ps
CPU time 5.36 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:36:54 PM PDT 24
Peak memory 198064 kb
Host smart-ea3089a3-b9df-464b-8ae3-5ccdd8814aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3844047105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3844047105
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.734044961
Short name T764
Test name
Test status
Simulation time 850593228 ps
CPU time 1.04 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:36:51 PM PDT 24
Peak memory 195644 kb
Host smart-97582db8-2406-41a2-860a-2a37de25deb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734044961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.734044961
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.1685072297
Short name T279
Test name
Test status
Simulation time 970850841 ps
CPU time 1.97 seconds
Started Jul 30 07:36:47 PM PDT 24
Finished Jul 30 07:36:50 PM PDT 24
Peak memory 199888 kb
Host smart-d5eefc2e-01c5-465e-be6b-9ab53c82b7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685072297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.1685072297
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2039917892
Short name T1033
Test name
Test status
Simulation time 204351183660 ps
CPU time 274.53 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:41:24 PM PDT 24
Peak memory 199908 kb
Host smart-f4d204cd-ea8a-4e0c-9453-0fe611e19caa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039917892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2039917892
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.935521700
Short name T406
Test name
Test status
Simulation time 89950242844 ps
CPU time 714.56 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:48:44 PM PDT 24
Peak memory 216128 kb
Host smart-ee04b3b9-a195-4d49-96aa-da312d125caa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935521700 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.935521700
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.1374581316
Short name T347
Test name
Test status
Simulation time 532508802 ps
CPU time 1.58 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:36:50 PM PDT 24
Peak memory 198248 kb
Host smart-246f148b-27fd-4c18-af78-93437d5fd8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374581316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.1374581316
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.2175485115
Short name T428
Test name
Test status
Simulation time 47804791983 ps
CPU time 67.84 seconds
Started Jul 30 07:36:45 PM PDT 24
Finished Jul 30 07:37:53 PM PDT 24
Peak memory 199972 kb
Host smart-cdaf8fdc-6492-40e9-ba28-228d0ef0300b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175485115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.2175485115
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.520976327
Short name T220
Test name
Test status
Simulation time 55934093980 ps
CPU time 63.85 seconds
Started Jul 30 07:41:05 PM PDT 24
Finished Jul 30 07:42:09 PM PDT 24
Peak memory 199688 kb
Host smart-728aeab9-62e4-48dc-8aee-c0c2fed47a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520976327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.520976327
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.710663544
Short name T541
Test name
Test status
Simulation time 23054772003 ps
CPU time 25.81 seconds
Started Jul 30 07:41:06 PM PDT 24
Finished Jul 30 07:41:32 PM PDT 24
Peak memory 199944 kb
Host smart-873a4acb-35e7-4e71-a14d-66d9335ad6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710663544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.710663544
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2212661483
Short name T21
Test name
Test status
Simulation time 77638069795 ps
CPU time 234.92 seconds
Started Jul 30 07:41:05 PM PDT 24
Finished Jul 30 07:45:00 PM PDT 24
Peak memory 216556 kb
Host smart-34213462-a716-4e92-b471-fc2e1b29e87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212661483 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2212661483
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.3359719067
Short name T43
Test name
Test status
Simulation time 41069079701 ps
CPU time 15.1 seconds
Started Jul 30 07:41:04 PM PDT 24
Finished Jul 30 07:41:19 PM PDT 24
Peak memory 199892 kb
Host smart-2a62e371-53b3-4838-b885-1fe888d1837d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359719067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.3359719067
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1740732696
Short name T98
Test name
Test status
Simulation time 56042889911 ps
CPU time 326.01 seconds
Started Jul 30 07:41:06 PM PDT 24
Finished Jul 30 07:46:32 PM PDT 24
Peak memory 216552 kb
Host smart-5a8d9372-3b87-4761-b0b2-c51c83211c61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740732696 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1740732696
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.555621401
Short name T675
Test name
Test status
Simulation time 97746829845 ps
CPU time 148.74 seconds
Started Jul 30 07:41:11 PM PDT 24
Finished Jul 30 07:43:40 PM PDT 24
Peak memory 199964 kb
Host smart-22a18d1a-93a4-4c02-82db-4c8d093ecfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555621401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.555621401
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.216534291
Short name T265
Test name
Test status
Simulation time 149267621564 ps
CPU time 483.63 seconds
Started Jul 30 07:41:08 PM PDT 24
Finished Jul 30 07:49:12 PM PDT 24
Peak memory 216492 kb
Host smart-284dcb60-0ed2-488b-9092-ea43fca06554
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216534291 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.216534291
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.364086897
Short name T183
Test name
Test status
Simulation time 77180774382 ps
CPU time 23.08 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 07:41:32 PM PDT 24
Peak memory 199880 kb
Host smart-70b61217-1f53-4e75-803f-19b9abd74eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364086897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.364086897
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.2509801790
Short name T411
Test name
Test status
Simulation time 824456079830 ps
CPU time 1195.8 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 08:01:05 PM PDT 24
Peak memory 224712 kb
Host smart-31a83fdb-4845-42dc-9ccb-ae9fa4d3fd38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509801790 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.2509801790
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3528426469
Short name T826
Test name
Test status
Simulation time 84184674555 ps
CPU time 356.1 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 07:47:05 PM PDT 24
Peak memory 199940 kb
Host smart-ae4697e6-d776-4e0c-ab6c-ea5ff54631e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528426469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3528426469
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.3693455359
Short name T53
Test name
Test status
Simulation time 175439002637 ps
CPU time 683.4 seconds
Started Jul 30 07:41:10 PM PDT 24
Finished Jul 30 07:52:34 PM PDT 24
Peak memory 224800 kb
Host smart-97209f5d-be3e-49fa-8d37-bed72fbe3c30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693455359 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.3693455359
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.36051376
Short name T937
Test name
Test status
Simulation time 136377634369 ps
CPU time 119.22 seconds
Started Jul 30 07:41:08 PM PDT 24
Finished Jul 30 07:43:08 PM PDT 24
Peak memory 199900 kb
Host smart-9a9165dc-f7ad-4c7a-9406-b34753bc553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36051376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.36051376
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3659838701
Short name T777
Test name
Test status
Simulation time 42489703529 ps
CPU time 874.91 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 07:55:44 PM PDT 24
Peak memory 216552 kb
Host smart-06619c12-6f08-47b4-ac26-2bc2cdb091c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659838701 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3659838701
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1758950695
Short name T215
Test name
Test status
Simulation time 12660469006 ps
CPU time 22.37 seconds
Started Jul 30 07:41:12 PM PDT 24
Finished Jul 30 07:41:34 PM PDT 24
Peak memory 199928 kb
Host smart-91d6b276-7905-4c42-a3a4-1f74a35f249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758950695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1758950695
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.303478701
Short name T1082
Test name
Test status
Simulation time 59405530513 ps
CPU time 646.52 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 07:51:56 PM PDT 24
Peak memory 216740 kb
Host smart-ab669f02-fafb-461c-8fe3-9123439931e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303478701 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.303478701
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3118540287
Short name T979
Test name
Test status
Simulation time 15644596122 ps
CPU time 13.67 seconds
Started Jul 30 07:41:08 PM PDT 24
Finished Jul 30 07:41:22 PM PDT 24
Peak memory 199504 kb
Host smart-2d3d75c0-0e1c-4214-80cb-0aba182bed91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118540287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3118540287
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2328583257
Short name T1162
Test name
Test status
Simulation time 33443980666 ps
CPU time 907.04 seconds
Started Jul 30 07:41:09 PM PDT 24
Finished Jul 30 07:56:16 PM PDT 24
Peak memory 216492 kb
Host smart-d53009ca-4b49-4083-a1e4-1bff7ec0e534
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328583257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2328583257
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3269516095
Short name T308
Test name
Test status
Simulation time 69426850214 ps
CPU time 49.87 seconds
Started Jul 30 07:41:13 PM PDT 24
Finished Jul 30 07:42:03 PM PDT 24
Peak memory 199820 kb
Host smart-67638af0-be70-4b0d-a39d-9fe7332b2ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269516095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3269516095
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2703877363
Short name T551
Test name
Test status
Simulation time 47074865659 ps
CPU time 295.83 seconds
Started Jul 30 07:41:14 PM PDT 24
Finished Jul 30 07:46:10 PM PDT 24
Peak memory 216576 kb
Host smart-d890ccb6-4d14-41ef-b13f-c4e7c2d2f913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703877363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2703877363
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1924535752
Short name T336
Test name
Test status
Simulation time 23552667 ps
CPU time 0.54 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:36:52 PM PDT 24
Peak memory 195328 kb
Host smart-00dc15c9-01d6-4f82-a2c8-ad790fb2cb78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924535752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1924535752
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3079086
Short name T1083
Test name
Test status
Simulation time 117306211611 ps
CPU time 92.28 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:38:24 PM PDT 24
Peak memory 199928 kb
Host smart-3a911b25-fe09-414b-a390-2e1c45386365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3079086
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2725079345
Short name T162
Test name
Test status
Simulation time 131018319644 ps
CPU time 50.65 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:37:41 PM PDT 24
Peak memory 199892 kb
Host smart-896b8011-648e-41ed-8d73-170db2b3308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725079345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2725079345
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1075734152
Short name T1180
Test name
Test status
Simulation time 18922715390 ps
CPU time 29.08 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:19 PM PDT 24
Peak memory 199908 kb
Host smart-5798fee4-7dbd-4a69-9fac-f3ae789321e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075734152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1075734152
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2132727434
Short name T1175
Test name
Test status
Simulation time 14646230677 ps
CPU time 19.72 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:09 PM PDT 24
Peak memory 197860 kb
Host smart-33a756e9-944e-41bd-90af-ab338a378c2d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132727434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2132727434
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.3913554604
Short name T452
Test name
Test status
Simulation time 121022758116 ps
CPU time 798.01 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:50:06 PM PDT 24
Peak memory 199936 kb
Host smart-5038d3e6-fa56-4e56-9a64-e58a78bf086c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3913554604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3913554604
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.3980589209
Short name T1072
Test name
Test status
Simulation time 7816047825 ps
CPU time 5.7 seconds
Started Jul 30 07:36:50 PM PDT 24
Finished Jul 30 07:36:56 PM PDT 24
Peak memory 200004 kb
Host smart-e3939643-bb5b-4e9e-bb58-2ae2097acbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980589209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.3980589209
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.846685043
Short name T1023
Test name
Test status
Simulation time 190594557055 ps
CPU time 15.66 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:37:05 PM PDT 24
Peak memory 196244 kb
Host smart-5f7c592d-09d7-47a2-bf72-6174e1f4dfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846685043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.846685043
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.613118470
Short name T437
Test name
Test status
Simulation time 21706810483 ps
CPU time 900.09 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:51:48 PM PDT 24
Peak memory 199940 kb
Host smart-208d63cb-200d-4b0c-a763-2d502b193c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613118470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.613118470
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2745331219
Short name T909
Test name
Test status
Simulation time 2716208592 ps
CPU time 1.67 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:36:51 PM PDT 24
Peak memory 199004 kb
Host smart-e58555a5-6e60-4439-9eb8-f55633b69c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745331219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2745331219
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4093558164
Short name T154
Test name
Test status
Simulation time 105508853053 ps
CPU time 42.14 seconds
Started Jul 30 07:36:50 PM PDT 24
Finished Jul 30 07:37:32 PM PDT 24
Peak memory 199940 kb
Host smart-12de6358-5963-48d8-b613-20bd6a10a246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093558164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4093558164
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1070478826
Short name T631
Test name
Test status
Simulation time 39529366622 ps
CPU time 60.29 seconds
Started Jul 30 07:36:48 PM PDT 24
Finished Jul 30 07:37:48 PM PDT 24
Peak memory 196260 kb
Host smart-c1de9b05-c6c3-452d-a591-969c43872dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070478826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1070478826
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.644909549
Short name T773
Test name
Test status
Simulation time 6244477894 ps
CPU time 27.35 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:37:18 PM PDT 24
Peak memory 199852 kb
Host smart-6118fe0c-04ef-4c6c-b8ab-51ef312bdaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644909549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.644909549
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.69156864
Short name T761
Test name
Test status
Simulation time 165750334034 ps
CPU time 269.82 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:41:21 PM PDT 24
Peak memory 200020 kb
Host smart-9dd06591-0c28-41f1-9879-850bf44dd5dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69156864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.69156864
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.587671676
Short name T357
Test name
Test status
Simulation time 6668459733 ps
CPU time 22.66 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:37:14 PM PDT 24
Peak memory 199868 kb
Host smart-8db447fc-cb58-4e3e-94df-d7cbb46f356f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587671676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.587671676
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3205362235
Short name T1057
Test name
Test status
Simulation time 8378653392 ps
CPU time 6.84 seconds
Started Jul 30 07:36:49 PM PDT 24
Finished Jul 30 07:36:56 PM PDT 24
Peak memory 196812 kb
Host smart-b2234068-ec17-4a9d-8844-97bcb213f791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205362235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3205362235
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.1542250991
Short name T230
Test name
Test status
Simulation time 192958636130 ps
CPU time 131.05 seconds
Started Jul 30 07:41:12 PM PDT 24
Finished Jul 30 07:43:23 PM PDT 24
Peak memory 199984 kb
Host smart-a97c7b05-61aa-4023-b3d0-7ecb52ac1cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542250991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.1542250991
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.605279959
Short name T678
Test name
Test status
Simulation time 44039913638 ps
CPU time 29.41 seconds
Started Jul 30 07:41:12 PM PDT 24
Finished Jul 30 07:41:42 PM PDT 24
Peak memory 199784 kb
Host smart-6f3f324e-ed39-477f-80f8-56e852524e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605279959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.605279959
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2827926001
Short name T313
Test name
Test status
Simulation time 193948363946 ps
CPU time 804.17 seconds
Started Jul 30 07:41:12 PM PDT 24
Finished Jul 30 07:54:37 PM PDT 24
Peak memory 224996 kb
Host smart-3fdb643e-8688-414f-baa7-9d9c94883c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827926001 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2827926001
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.626217924
Short name T201
Test name
Test status
Simulation time 123771376250 ps
CPU time 924.24 seconds
Started Jul 30 07:41:18 PM PDT 24
Finished Jul 30 07:56:42 PM PDT 24
Peak memory 215612 kb
Host smart-ce413736-999d-4e37-8fba-0b252c7c9936
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626217924 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.626217924
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3379726546
Short name T40
Test name
Test status
Simulation time 18177175695 ps
CPU time 8.55 seconds
Started Jul 30 07:41:17 PM PDT 24
Finished Jul 30 07:41:26 PM PDT 24
Peak memory 197592 kb
Host smart-e052b2c1-3cb2-4064-87ee-b8d682684bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379726546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3379726546
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.653513977
Short name T293
Test name
Test status
Simulation time 168502584417 ps
CPU time 145.87 seconds
Started Jul 30 07:41:16 PM PDT 24
Finished Jul 30 07:43:42 PM PDT 24
Peak memory 199984 kb
Host smart-a464128b-aa02-4e84-881d-9ccf8ebd17d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653513977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.653513977
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3546313236
Short name T204
Test name
Test status
Simulation time 194406978949 ps
CPU time 656.4 seconds
Started Jul 30 07:41:19 PM PDT 24
Finished Jul 30 07:52:16 PM PDT 24
Peak memory 216384 kb
Host smart-62c46476-5d74-49df-bcd6-5efaaa66c654
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546313236 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3546313236
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1514859739
Short name T878
Test name
Test status
Simulation time 67478988624 ps
CPU time 48.92 seconds
Started Jul 30 07:41:21 PM PDT 24
Finished Jul 30 07:42:10 PM PDT 24
Peak memory 199896 kb
Host smart-7fc1448c-4891-43cf-82a3-8062378dac10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514859739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1514859739
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.4171012636
Short name T358
Test name
Test status
Simulation time 34924657866 ps
CPU time 27.39 seconds
Started Jul 30 07:41:22 PM PDT 24
Finished Jul 30 07:41:50 PM PDT 24
Peak memory 199964 kb
Host smart-1ebd92ad-ce29-4f41-8696-fb90d8c6a529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171012636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.4171012636
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.260640078
Short name T637
Test name
Test status
Simulation time 23278221018 ps
CPU time 34.89 seconds
Started Jul 30 07:41:21 PM PDT 24
Finished Jul 30 07:41:56 PM PDT 24
Peak memory 199944 kb
Host smart-58b9d331-1eab-49a4-8877-6c7c4985facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260640078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.260640078
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.534541165
Short name T36
Test name
Test status
Simulation time 90907790037 ps
CPU time 1125.94 seconds
Started Jul 30 07:41:22 PM PDT 24
Finished Jul 30 08:00:08 PM PDT 24
Peak memory 216508 kb
Host smart-9506bcf8-a4bd-448b-9599-65dd7ab6d3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534541165 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.534541165
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2637347799
Short name T214
Test name
Test status
Simulation time 38636964038 ps
CPU time 67.98 seconds
Started Jul 30 07:41:22 PM PDT 24
Finished Jul 30 07:42:30 PM PDT 24
Peak memory 199964 kb
Host smart-b3c930f3-a281-45cb-b678-116017f34655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637347799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2637347799
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.1750038068
Short name T1077
Test name
Test status
Simulation time 13810833446 ps
CPU time 118.84 seconds
Started Jul 30 07:41:20 PM PDT 24
Finished Jul 30 07:43:19 PM PDT 24
Peak memory 216000 kb
Host smart-d796cc18-45df-4f75-b44c-f5d2d29009af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750038068 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.1750038068
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3579822224
Short name T816
Test name
Test status
Simulation time 30445704165 ps
CPU time 34.13 seconds
Started Jul 30 07:41:25 PM PDT 24
Finished Jul 30 07:42:00 PM PDT 24
Peak memory 199964 kb
Host smart-f285adad-b0b2-462c-a6fa-e6af7b547198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579822224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3579822224
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.3426828330
Short name T51
Test name
Test status
Simulation time 76403313332 ps
CPU time 421.54 seconds
Started Jul 30 07:41:26 PM PDT 24
Finished Jul 30 07:48:28 PM PDT 24
Peak memory 216244 kb
Host smart-0f698479-2a7b-4685-b56a-70cea0afa947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426828330 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.3426828330
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.4228043459
Short name T1047
Test name
Test status
Simulation time 32445500 ps
CPU time 0.56 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:36:56 PM PDT 24
Peak memory 195328 kb
Host smart-5fbc3de6-d88f-433d-a3c0-4fec3eaca598
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228043459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.4228043459
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.2719530094
Short name T1117
Test name
Test status
Simulation time 63696039704 ps
CPU time 55.44 seconds
Started Jul 30 07:36:52 PM PDT 24
Finished Jul 30 07:37:48 PM PDT 24
Peak memory 199900 kb
Host smart-95521da9-4b1c-4d9a-b8a2-158ad4881e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719530094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.2719530094
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.1993148040
Short name T1139
Test name
Test status
Simulation time 39177938176 ps
CPU time 19.57 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:37:11 PM PDT 24
Peak memory 199920 kb
Host smart-a5b8d5c0-fa83-48c7-bd31-852471f4cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993148040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.1993148040
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1442638237
Short name T64
Test name
Test status
Simulation time 64512123540 ps
CPU time 48.63 seconds
Started Jul 30 07:36:53 PM PDT 24
Finished Jul 30 07:37:42 PM PDT 24
Peak memory 199912 kb
Host smart-53152b91-77cd-4a90-a716-a27cb16233a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442638237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1442638237
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.1025751218
Short name T22
Test name
Test status
Simulation time 21261107115 ps
CPU time 39.71 seconds
Started Jul 30 07:36:53 PM PDT 24
Finished Jul 30 07:37:33 PM PDT 24
Peak memory 199968 kb
Host smart-4c057d68-20ef-4376-908a-d5ac7d1848c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025751218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.1025751218
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.1954799486
Short name T359
Test name
Test status
Simulation time 98828165921 ps
CPU time 443.67 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:44:15 PM PDT 24
Peak memory 199948 kb
Host smart-b6b31587-23be-434b-8503-37b9fe91993d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954799486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.1954799486
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.4279027712
Short name T724
Test name
Test status
Simulation time 4304948666 ps
CPU time 9.1 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:03 PM PDT 24
Peak memory 198848 kb
Host smart-a95d3096-6068-4f15-bfe6-1dce17547ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279027712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.4279027712
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1780610846
Short name T741
Test name
Test status
Simulation time 44147748838 ps
CPU time 70.58 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:38:05 PM PDT 24
Peak memory 200040 kb
Host smart-b20883cd-1131-4be3-82ef-46e0e08694fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780610846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1780610846
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.2418177886
Short name T385
Test name
Test status
Simulation time 3010292111 ps
CPU time 88.82 seconds
Started Jul 30 07:36:53 PM PDT 24
Finished Jul 30 07:38:22 PM PDT 24
Peak memory 199908 kb
Host smart-950ae7b0-bda8-472e-9bbc-0952c284fff4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418177886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.2418177886
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2191505113
Short name T354
Test name
Test status
Simulation time 3465343346 ps
CPU time 25.8 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:37:17 PM PDT 24
Peak memory 198696 kb
Host smart-72357cfc-461b-457d-81cc-ed964c71acc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191505113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2191505113
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3680107289
Short name T141
Test name
Test status
Simulation time 138671009444 ps
CPU time 22.16 seconds
Started Jul 30 07:36:55 PM PDT 24
Finished Jul 30 07:37:17 PM PDT 24
Peak memory 200000 kb
Host smart-497fbd01-fd41-4a3c-b13c-fe852a5be22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680107289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3680107289
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.4157303232
Short name T519
Test name
Test status
Simulation time 3176711407 ps
CPU time 2.6 seconds
Started Jul 30 07:36:50 PM PDT 24
Finished Jul 30 07:36:53 PM PDT 24
Peak memory 196724 kb
Host smart-b1b34c64-f05c-462e-9dc0-41837f62aae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157303232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4157303232
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.2846545384
Short name T857
Test name
Test status
Simulation time 6208278626 ps
CPU time 23.47 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:37:18 PM PDT 24
Peak memory 199076 kb
Host smart-e3e470e6-4ec7-4368-9933-cad2512bfa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846545384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.2846545384
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3981364249
Short name T703
Test name
Test status
Simulation time 42724998220 ps
CPU time 1600.46 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 08:03:34 PM PDT 24
Peak memory 199896 kb
Host smart-0eb2b398-5d3f-41fd-9463-0f802b1a0194
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981364249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3981364249
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1928695171
Short name T263
Test name
Test status
Simulation time 131616577300 ps
CPU time 451.01 seconds
Started Jul 30 07:36:51 PM PDT 24
Finished Jul 30 07:44:23 PM PDT 24
Peak memory 224664 kb
Host smart-48833941-39d3-4518-9072-bea50d0bb822
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928695171 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1928695171
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.1212630542
Short name T730
Test name
Test status
Simulation time 995714646 ps
CPU time 2.81 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:36:56 PM PDT 24
Peak memory 198288 kb
Host smart-e5ef8f53-1342-42b0-b71d-ba3dd26da0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212630542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1212630542
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.423680843
Short name T307
Test name
Test status
Simulation time 119677813351 ps
CPU time 87.75 seconds
Started Jul 30 07:36:54 PM PDT 24
Finished Jul 30 07:38:21 PM PDT 24
Peak memory 199884 kb
Host smart-7fd85f8f-ade7-4110-a2b9-c96d2fc0de6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423680843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.423680843
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4291099050
Short name T1134
Test name
Test status
Simulation time 20765005134 ps
CPU time 16.66 seconds
Started Jul 30 07:41:25 PM PDT 24
Finished Jul 30 07:41:41 PM PDT 24
Peak memory 199872 kb
Host smart-06fbf1ff-c57d-4576-9a39-1aea7ed007f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291099050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4291099050
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.970960880
Short name T822
Test name
Test status
Simulation time 259651464080 ps
CPU time 819.28 seconds
Started Jul 30 07:41:26 PM PDT 24
Finished Jul 30 07:55:06 PM PDT 24
Peak memory 224100 kb
Host smart-6e0d0d1b-04ce-4e2a-a23f-c396facec573
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970960880 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.970960880
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.476839421
Short name T457
Test name
Test status
Simulation time 12845373263 ps
CPU time 21.88 seconds
Started Jul 30 07:41:23 PM PDT 24
Finished Jul 30 07:41:45 PM PDT 24
Peak memory 199888 kb
Host smart-e36a005a-45ad-49bf-b494-7733bf3867a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476839421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.476839421
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.153914565
Short name T31
Test name
Test status
Simulation time 22348483418 ps
CPU time 259.29 seconds
Started Jul 30 07:41:25 PM PDT 24
Finished Jul 30 07:45:44 PM PDT 24
Peak memory 215624 kb
Host smart-aaedf452-73fd-463a-8969-5cec334d542e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153914565 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.153914565
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.2258558268
Short name T193
Test name
Test status
Simulation time 29301638399 ps
CPU time 67.71 seconds
Started Jul 30 07:41:30 PM PDT 24
Finished Jul 30 07:42:38 PM PDT 24
Peak memory 200000 kb
Host smart-ba8c4716-e595-4a22-921e-129e8b5f1ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258558268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.2258558268
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3236974687
Short name T492
Test name
Test status
Simulation time 16524507889 ps
CPU time 689.08 seconds
Started Jul 30 07:41:28 PM PDT 24
Finished Jul 30 07:52:58 PM PDT 24
Peak memory 215904 kb
Host smart-974138a8-ef69-44b4-9f7b-b1f4569e547b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236974687 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3236974687
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.1543740458
Short name T1137
Test name
Test status
Simulation time 58501230126 ps
CPU time 89.84 seconds
Started Jul 30 07:41:28 PM PDT 24
Finished Jul 30 07:42:58 PM PDT 24
Peak memory 199896 kb
Host smart-c9b18a68-1c4c-4ba1-9d70-19b729917e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543740458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.1543740458
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1383164160
Short name T495
Test name
Test status
Simulation time 117392192851 ps
CPU time 1681.98 seconds
Started Jul 30 07:41:31 PM PDT 24
Finished Jul 30 08:09:34 PM PDT 24
Peak memory 224676 kb
Host smart-898cd4a9-6e0d-4186-8381-7ff803f3c9ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383164160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1383164160
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1113921366
Short name T709
Test name
Test status
Simulation time 142018578655 ps
CPU time 95.36 seconds
Started Jul 30 07:41:29 PM PDT 24
Finished Jul 30 07:43:04 PM PDT 24
Peak memory 199916 kb
Host smart-839f61d0-5f78-4cd5-9890-86c5403bb165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113921366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1113921366
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3585192750
Short name T725
Test name
Test status
Simulation time 62119105881 ps
CPU time 222.52 seconds
Started Jul 30 07:41:29 PM PDT 24
Finished Jul 30 07:45:11 PM PDT 24
Peak memory 213576 kb
Host smart-7d205d11-8bdb-4a7b-b6ea-b26442b39009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585192750 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3585192750
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.2084091417
Short name T207
Test name
Test status
Simulation time 172711278186 ps
CPU time 121.79 seconds
Started Jul 30 07:41:29 PM PDT 24
Finished Jul 30 07:43:30 PM PDT 24
Peak memory 199944 kb
Host smart-f81a4e5c-e76a-4964-b235-bac28273cf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084091417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.2084091417
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3116034591
Short name T739
Test name
Test status
Simulation time 36707272357 ps
CPU time 644 seconds
Started Jul 30 07:41:30 PM PDT 24
Finished Jul 30 07:52:14 PM PDT 24
Peak memory 208464 kb
Host smart-dd60f60d-a221-4453-9a2f-1c91ee084ea5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116034591 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3116034591
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.711060030
Short name T1164
Test name
Test status
Simulation time 42856739594 ps
CPU time 36.65 seconds
Started Jul 30 07:41:28 PM PDT 24
Finished Jul 30 07:42:04 PM PDT 24
Peak memory 199952 kb
Host smart-7d0c9847-e0b9-48eb-aa12-890e405c7c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711060030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.711060030
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1482781237
Short name T946
Test name
Test status
Simulation time 116163242471 ps
CPU time 44.65 seconds
Started Jul 30 07:41:35 PM PDT 24
Finished Jul 30 07:42:20 PM PDT 24
Peak memory 199984 kb
Host smart-5bc4b1bb-64bf-4cb0-9392-032b6db21246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482781237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1482781237
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.3415806582
Short name T632
Test name
Test status
Simulation time 27296976195 ps
CPU time 353.19 seconds
Started Jul 30 07:41:32 PM PDT 24
Finished Jul 30 07:47:26 PM PDT 24
Peak memory 216628 kb
Host smart-8ab6a531-a79c-485b-8280-79bd607aabfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415806582 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.3415806582
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.2817682291
Short name T1073
Test name
Test status
Simulation time 19205712485 ps
CPU time 29.48 seconds
Started Jul 30 07:41:33 PM PDT 24
Finished Jul 30 07:42:02 PM PDT 24
Peak memory 199856 kb
Host smart-9d4edf9b-8a8b-487a-b6b1-255735501abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817682291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2817682291
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.4121717646
Short name T1044
Test name
Test status
Simulation time 560150340939 ps
CPU time 798.32 seconds
Started Jul 30 07:41:33 PM PDT 24
Finished Jul 30 07:54:52 PM PDT 24
Peak memory 224832 kb
Host smart-a1e4b3c4-f8c0-403d-944d-910ba69b7a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121717646 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.4121717646
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.3529750578
Short name T284
Test name
Test status
Simulation time 57707682449 ps
CPU time 62.02 seconds
Started Jul 30 07:41:33 PM PDT 24
Finished Jul 30 07:42:35 PM PDT 24
Peak memory 199972 kb
Host smart-c1975684-b235-47f0-a738-4ce33f1a23b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529750578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.3529750578
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3348066139
Short name T768
Test name
Test status
Simulation time 344043266713 ps
CPU time 350.29 seconds
Started Jul 30 07:41:35 PM PDT 24
Finished Jul 30 07:47:25 PM PDT 24
Peak memory 216580 kb
Host smart-5f8b8fd2-eb9a-4ae4-90f4-d76a054452b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348066139 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3348066139
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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