Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	121842	1			T1	1		T2	13		T3	70
all_values[1]	121842	1			T1	1		T2	13		T3	70
all_values[2]	121842	1			T1	1		T2	13		T3	70
all_values[3]	121842	1			T1	1		T2	13		T3	70
all_values[4]	121842	1			T1	1		T2	13		T3	70
all_values[5]	121842	1			T1	1		T2	13		T3	70
all_values[6]	121842	1			T1	1		T2	13		T3	70
all_values[7]	121842	1			T1	1		T2	13		T3	70
all_values[8]	121842	1			T1	1		T2	13		T3	70

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

542758

1

T1

7

T2

59

T3

217

auto[1]

553820

1

T1

2

T2

58

T3

413

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996670

1

T1

7

T2

89

T3

520

auto[1]

99908

1

T1

2

T2

28

T3

110

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	35955	1			T4	79		T5	10		T8	1
all_values[0]	auto[0]	auto[1]	24644	1			T1	1		T2	3		T3	13
all_values[0]	auto[1]	auto[0]	35691	1			T3	30		T4	156		T5	363
all_values[0]	auto[1]	auto[1]	25552	1			T2	10		T3	27		T4	56
all_values[1]	auto[0]	auto[0]	57741	1			T2	3		T3	26		T4	334
all_values[1]	auto[0]	auto[1]	1561	1			T3	2		T5	4		T7	12
all_values[1]	auto[1]	auto[0]	60842	1			T1	1		T2	10		T3	42
all_values[1]	auto[1]	auto[1]	1698	1			T4	1		T5	9		T10	12
all_values[2]	auto[0]	auto[0]	55214	1			T1	1		T2	10		T3	6
all_values[2]	auto[0]	auto[1]	2745	1			T2	1		T3	3		T4	15
all_values[2]	auto[1]	auto[0]	61375	1			T2	1		T3	51		T4	272
all_values[2]	auto[1]	auto[1]	2508	1			T2	1		T3	10		T4	11
all_values[3]	auto[0]	auto[0]	59932	1			T1	1		T2	3		T3	12
all_values[3]	auto[0]	auto[1]	306	1			T4	8		T5	4		T11	1
all_values[3]	auto[1]	auto[0]	61322	1			T2	10		T3	56		T4	172
all_values[3]	auto[1]	auto[1]	282	1			T3	2		T4	1		T13	1
all_values[4]	auto[0]	auto[0]	55178	1			T2	1		T3	9		T4	194
all_values[4]	auto[0]	auto[1]	360	1			T3	6		T4	2		T5	1
all_values[4]	auto[1]	auto[0]	65905	1			T1	1		T2	12		T3	54
all_values[4]	auto[1]	auto[1]	399	1			T3	1		T4	4		T5	3
all_values[5]	auto[0]	auto[0]	59138	1			T1	1		T2	13		T3	37
all_values[5]	auto[0]	auto[1]	150	1			T4	1		T5	2		T21	4
all_values[5]	auto[1]	auto[0]	62386	1			T3	33		T4	191		T5	210
all_values[5]	auto[1]	auto[1]	168	1			T5	4		T21	2		T23	2
all_values[6]	auto[0]	auto[0]	60939	1			T1	1		T2	11		T3	38
all_values[6]	auto[0]	auto[1]	151	1			T3	1		T4	3		T5	4
all_values[6]	auto[1]	auto[0]	60583	1			T2	2		T3	30		T4	207
all_values[6]	auto[1]	auto[1]	169	1			T3	1		T4	3		T5	2
all_values[7]	auto[0]	auto[0]	64602	1			T1	1		T2	11		T3	14
all_values[7]	auto[0]	auto[1]	285	1			T3	4		T4	1		T5	6
all_values[7]	auto[1]	auto[0]	56654	1			T2	2		T3	50		T4	335
all_values[7]	auto[1]	auto[1]	301	1			T3	2		T4	2		T11	1
all_values[8]	auto[0]	auto[0]	44088	1			T3	29		T4	146		T5	56
all_values[8]	auto[0]	auto[1]	19769	1			T1	1		T2	3		T3	17
all_values[8]	auto[1]	auto[0]	39125	1			T3	3		T4	155		T5	356
all_values[8]	auto[1]	auto[1]	18860	1			T2	10		T3	21		T4	69