Unified Coverage Report :: Group :: uart_agent_pkg::uart_agent_cov::uart_reset_cg

Group : uart_agent_pkg::uart_agent_cov::uart_reset_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_agent_0.1/uart_agent_cov.sv

---

Summary for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	22	0	22	100.00

Variables for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	0
cp_rst_pos	11	0	11	100.00	100	1	1	0

Crosses for Group uart_agent_pkg::uart_agent_cov::uart_reset_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
uart_reset_cg_cc	22	0	22	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UartTx]

2573

1

T1

1

T2

1

T3

11

auto[UartRx]

2573

1

T1

1

T2

1

T3

11

---

Summary for Variable cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_rst_pos

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4546	1			T1	2		T2	2		T3	12
values[1]	63	1			T22	1		T23	1		T115	1
values[2]	65	1			T23	1		T24	3		T25	1
values[3]	52	1			T3	3		T24	2		T127	1
values[4]	47	1			T4	1		T14	2		T12	1
values[5]	64	1			T4	1		T5	3		T12	3
values[6]	45	1			T3	1		T12	1		T21	1
values[7]	50	1			T3	1		T4	1		T14	1
values[8]	56	1			T3	2		T4	3		T14	1
values[9]	63	1			T3	2		T5	1		T14	1
values[10]	66	1			T3	1		T12	3		T22	1

---

Summary for Cross uart_reset_cg_cc

Samples crossed: cp_dir cp_rst_pos

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	22	0	22	100.00

Automatically Generated Cross Bins for uart_reset_cg_cc

Bins

cp_dir	cp_rst_pos	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[UartTx]	values[0]	2363	1			T1	1		T2	1		T3	9
auto[UartTx]	values[1]	15	1			T282	1		T85	1		T35	1
auto[UartTx]	values[2]	28	1			T23	1		T24	2		T115	1
auto[UartTx]	values[3]	19	1			T3	1		T81	1		T311	1
auto[UartTx]	values[4]	19	1			T14	1		T12	1		T99	1
auto[UartTx]	values[5]	23	1			T5	1		T99	1		T83	1
auto[UartTx]	values[6]	16	1			T21	1		T25	1		T115	1
auto[UartTx]	values[7]	15	1			T14	1		T80	1		T83	1
auto[UartTx]	values[8]	22	1			T4	3		T24	1		T99	1
auto[UartTx]	values[9]	21	1			T3	1		T22	1		T99	1
auto[UartTx]	values[10]	22	1			T12	2		T24	1		T264	1
auto[UartRx]	values[0]	2183	1			T1	1		T2	1		T3	3
auto[UartRx]	values[1]	48	1			T22	1		T23	1		T115	1
auto[UartRx]	values[2]	37	1			T24	1		T25	1		T81	1
auto[UartRx]	values[3]	33	1			T3	2		T24	2		T127	1
auto[UartRx]	values[4]	28	1			T4	1		T14	1		T80	1
auto[UartRx]	values[5]	41	1			T4	1		T5	2		T12	3
auto[UartRx]	values[6]	29	1			T3	1		T12	1		T99	1
auto[UartRx]	values[7]	35	1			T3	1		T4	1		T22	2
auto[UartRx]	values[8]	34	1			T3	2		T14	1		T23	1
auto[UartRx]	values[9]	42	1			T3	1		T5	1		T14	1
auto[UartRx]	values[10]	44	1			T3	1		T12	1		T22	1