Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2346	1			T1	7		T3	1		T4	7
auto[BaudRate115200]	1923	1			T2	1		T3	3		T4	19
auto[BaudRate230400]	2000	1			T3	6		T4	15		T5	6
auto[BaudRate128Kbps]	1908	1			T2	1		T3	6		T4	19
auto[BaudRate256Kbps]	2220	1			T3	8		T4	26		T5	12
auto[BaudRate1Mbps]	1848	1			T3	6		T4	20		T5	13
auto[BaudRate1p5Mbps]	1215	1			T4	12		T5	8		T6	3

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1525	1			T5	66		T26	8		T257	2
freqs[25]	1510	1			T237	7		T312	36		T28	7
freqs[48]	507	1			T7	9		T8	5		T10	10
freqs[50]	330	1			T1	7		T11	9		T241	7
freqs[100]	1489	1			T6	9		T313	33		T103	8

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	250	1			T5	5		T261	1		T32	17
auto[BaudRate9600]	freqs[25]	235	1			T237	1		T314	3		T23	5
auto[BaudRate9600]	freqs[48]	83	1			T7	1		T305	2		T109	1
auto[BaudRate9600]	freqs[50]	51	1			T1	7		T11	2		T241	1
auto[BaudRate9600]	freqs[100]	280	1			T6	2		T313	3		T21	1
auto[BaudRate115200]	freqs[24]	242	1			T5	13		T26	2		T113	1
auto[BaudRate115200]	freqs[25]	208	1			T237	2		T312	6		T28	2
auto[BaudRate115200]	freqs[48]	63	1			T7	1		T8	1		T10	3
auto[BaudRate115200]	freqs[50]	53	1			T11	1		T241	2		T105	2
auto[BaudRate115200]	freqs[100]	178	1			T6	3		T313	3		T103	1
auto[BaudRate230400]	freqs[24]	227	1			T5	6		T26	3		T261	3
auto[BaudRate230400]	freqs[25]	208	1			T312	3		T88	1		T23	2
auto[BaudRate230400]	freqs[48]	48	1			T10	1		T309	1		T109	1
auto[BaudRate230400]	freqs[50]	48	1			T11	1		T241	1		T112	1
auto[BaudRate230400]	freqs[100]	223	1			T313	3		T103	1		T276	1
auto[BaudRate128Kbps]	freqs[24]	198	1			T5	9		T26	2		T257	1
auto[BaudRate128Kbps]	freqs[25]	214	1			T237	2		T312	6		T314	3
auto[BaudRate128Kbps]	freqs[48]	67	1			T7	2		T8	2		T10	1
auto[BaudRate128Kbps]	freqs[50]	41	1			T11	2		T105	1		T138	3
auto[BaudRate128Kbps]	freqs[100]	194	1			T313	6		T103	2		T27	3
auto[BaudRate256Kbps]	freqs[24]	222	1			T5	12		T261	1		T86	3
auto[BaudRate256Kbps]	freqs[25]	250	1			T312	9		T28	4		T314	3
auto[BaudRate256Kbps]	freqs[48]	58	1			T7	2		T10	2		T315	1
auto[BaudRate256Kbps]	freqs[50]	52	1			T11	1		T241	2		T105	1
auto[BaudRate256Kbps]	freqs[100]	231	1			T6	1		T313	9		T103	2
auto[BaudRate1Mbps]	freqs[24]	267	1			T5	13		T257	1		T261	1
auto[BaudRate1Mbps]	freqs[25]	265	1			T237	1		T312	12		T28	1
auto[BaudRate1Mbps]	freqs[48]	107	1			T7	2		T8	2		T10	3
auto[BaudRate1Mbps]	freqs[50]	40	1			T105	1		T112	1		T155	1
auto[BaudRate1Mbps]	freqs[100]	191	1			T313	3		T103	2		T21	3
auto[BaudRate1p5Mbps]	freqs[25]	130	1			T237	1		T23	3		T244	3
auto[BaudRate1p5Mbps]	freqs[48]	81	1			T7	1		T309	1		T305	2
auto[BaudRate1p5Mbps]	freqs[50]	45	1			T11	2		T241	1		T112	1
auto[BaudRate1p5Mbps]	freqs[100]	192	1			T6	3		T313	6		T27	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded