Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	13	117	90.00

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	13	117	90.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	35835424	1			T1	1		T2	54		T3	39322
all_levels[1]	210019	1			T2	18		T3	310		T4	206
all_levels[2]	2528	1			T2	5		T3	10		T4	5
all_levels[3]	1012	1			T3	8		T4	2		T5	1
all_levels[4]	785	1			T3	3		T4	5		T5	1
all_levels[5]	622	1			T3	2		T4	1		T5	1
all_levels[6]	432	1			T4	2		T5	2		T8	1
all_levels[7]	346	1			T4	1		T5	1		T7	1
all_levels[8]	339	1			T5	1		T11	1		T95	2
all_levels[9]	269	1			T4	1		T5	1		T7	1
all_levels[10]	231	1			T4	1		T95	1		T102	3
all_levels[11]	218	1			T7	2		T11	1		T102	2
all_levels[12]	198	1			T3	3		T7	2		T95	1
all_levels[13]	156	1			T4	4		T5	2		T7	1
all_levels[14]	131	1			T4	2		T11	1		T27	1
all_levels[15]	149	1			T4	1		T5	1		T95	1
all_levels[16]	94	1			T103	1		T22	2		T23	1
all_levels[17]	105	1			T5	1		T7	1		T11	1
all_levels[18]	62	1			T14	2		T102	1		T104	1
all_levels[19]	84	1			T7	1		T11	1		T105	1
all_levels[20]	73	1			T4	1		T106	1		T107	1
all_levels[21]	65	1			T9	1		T102	1		T22	2
all_levels[22]	82	1			T102	2		T22	3		T108	1
all_levels[23]	68	1			T102	1		T105	1		T23	1
all_levels[24]	63	1			T99	1		T109	1		T98	1
all_levels[25]	58	1			T22	1		T23	1		T110	2
all_levels[26]	54	1			T4	1		T111	1		T105	1
all_levels[27]	37	1			T9	1		T91	1		T109	1
all_levels[28]	49	1			T7	1		T102	1		T23	1
all_levels[29]	42	1			T105	2		T112	2		T113	1
all_levels[30]	37	1			T102	1		T21	1		T22	2
all_levels[31]	53	1			T5	1		T22	1		T114	2
all_levels[32]	29	1			T23	1		T99	2		T115	1
all_levels[33]	26	1			T102	3		T104	1		T78	2
all_levels[34]	38	1			T102	1		T106	1		T109	1
all_levels[35]	20	1			T116	1		T117	1		T118	3
all_levels[36]	22	1			T22	1		T119	2		T120	1
all_levels[37]	23	1			T102	1		T113	1		T23	1
all_levels[38]	19	1			T102	2		T121	1		T122	1
all_levels[39]	14	1			T4	1		T23	1		T99	1
all_levels[40]	14	1			T9	1		T100	1		T123	1
all_levels[41]	11	1			T99	1		T124	1		T125	1
all_levels[42]	20	1			T91	1		T99	1		T126	1
all_levels[43]	20	1			T7	1		T105	1		T99	1
all_levels[44]	6	1			T127	1		T128	1		T129	1
all_levels[45]	16	1			T127	1		T130	1		T131	1
all_levels[46]	17	1			T22	1		T132	1		T133	1
all_levels[47]	13	1			T9	2		T134	2		T125	1
all_levels[48]	18	1			T4	1		T9	1		T111	1
all_levels[49]	10	1			T135	1		T136	1		T124	1
all_levels[50]	16	1			T11	1		T105	1		T137	1
all_levels[51]	14	1			T11	1		T22	1		T138	1
all_levels[52]	10	1			T103	1		T113	2		T117	1
all_levels[53]	14	1			T5	1		T139	2		T140	2
all_levels[54]	16	1			T105	1		T141	1		T142	1
all_levels[55]	6	1			T4	1		T143	1		T144	1
all_levels[56]	4	1			T145	1		T146	1		T147	1
all_levels[57]	8	1			T131	1		T117	1		T148	1
all_levels[58]	7	1			T4	1		T146	1		T149	1
all_levels[59]	3	1			T150	1		T151	1		T152	1
all_levels[60]	4	1			T128	1		T153	1		T154	1
all_levels[61]	15	1			T99	2		T135	1		T155	1
all_levels[62]	8	1			T23	1		T156	1		T116	1
all_levels[63]	13	1			T116	1		T126	1		T157	1
all_levels[64]	114	1			T4	1		T5	1		T11	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36049710

1

T2

77

T3

39655

T4

84905

auto[1]

4763

1

T1

1

T3

3

T4

14

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	13	117	90.00	13

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[32]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[39] , all_levels[40]]	[auto[1]]	--	--	2
[all_levels[44]]	[auto[1]]	0	1	1
[all_levels[50]]	[auto[1]]	0	1	1
[all_levels[55] , all_levels[56] , all_levels[57] , all_levels[58] , all_levels[59] , all_levels[60]]	[auto[1]]	--	--	6
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	35831108	1			T2	54		T3	39321		T4	84667
all_levels[0]	auto[1]	4316	1			T1	1		T3	1		T4	14
all_levels[1]	auto[0]	209943	1			T2	18		T3	310		T4	206
all_levels[1]	auto[1]	76	1			T103	2		T158	2		T159	1
all_levels[2]	auto[0]	2499	1			T2	5		T3	10		T4	5
all_levels[2]	auto[1]	29	1			T102	1		T112	1		T77	2
all_levels[3]	auto[0]	992	1			T3	8		T4	2		T5	1
all_levels[3]	auto[1]	20	1			T119	1		T160	2		T161	1
all_levels[4]	auto[0]	769	1			T3	3		T4	5		T5	1
all_levels[4]	auto[1]	16	1			T77	2		T134	1		T162	1
all_levels[5]	auto[0]	606	1			T3	2		T4	1		T5	1
all_levels[5]	auto[1]	16	1			T163	1		T164	2		T165	2
all_levels[6]	auto[0]	424	1			T4	2		T5	2		T8	1
all_levels[6]	auto[1]	8	1			T166	1		T162	1		T138	1
all_levels[7]	auto[0]	331	1			T4	1		T5	1		T7	1
all_levels[7]	auto[1]	15	1			T167	1		T168	1		T169	1
all_levels[8]	auto[0]	325	1			T5	1		T11	1		T95	2
all_levels[8]	auto[1]	14	1			T135	2		T170	2		T171	1
all_levels[9]	auto[0]	248	1			T4	1		T5	1		T7	1
all_levels[9]	auto[1]	21	1			T172	1		T27	1		T173	1
all_levels[10]	auto[0]	214	1			T4	1		T95	1		T102	3
all_levels[10]	auto[1]	17	1			T174	2		T175	1		T176	2
all_levels[11]	auto[0]	210	1			T7	2		T11	1		T102	2
all_levels[11]	auto[1]	8	1			T177	1		T169	1		T178	1
all_levels[12]	auto[0]	183	1			T3	1		T7	2		T95	1
all_levels[12]	auto[1]	15	1			T3	2		T104	1		T81	1
all_levels[13]	auto[0]	143	1			T4	4		T5	1		T7	1
all_levels[13]	auto[1]	13	1			T5	1		T179	3		T180	1
all_levels[14]	auto[0]	123	1			T4	2		T11	1		T27	1
all_levels[14]	auto[1]	8	1			T181	1		T175	5		T176	1
all_levels[15]	auto[0]	133	1			T4	1		T5	1		T95	1
all_levels[15]	auto[1]	16	1			T174	1		T182	1		T183	2
all_levels[16]	auto[0]	89	1			T103	1		T22	2		T23	1
all_levels[16]	auto[1]	5	1			T184	3		T169	1		T185	1
all_levels[17]	auto[0]	94	1			T5	1		T7	1		T11	1
all_levels[17]	auto[1]	11	1			T186	2		T187	1		T161	1
all_levels[18]	auto[0]	61	1			T14	2		T102	1		T104	1
all_levels[18]	auto[1]	1	1			T188	1		-	-		-	-
all_levels[19]	auto[0]	80	1			T7	1		T11	1		T105	1
all_levels[19]	auto[1]	4	1			T104	1		T77	1		T189	1
all_levels[20]	auto[0]	70	1			T4	1		T106	1		T107	1
all_levels[20]	auto[1]	3	1			T100	1		T190	1		T191	1
all_levels[21]	auto[0]	54	1			T9	1		T102	1		T22	2
all_levels[21]	auto[1]	11	1			T192	2		T125	2		T37	2
all_levels[22]	auto[0]	74	1			T102	2		T22	3		T108	1
all_levels[22]	auto[1]	8	1			T165	2		T193	1		T194	1
all_levels[23]	auto[0]	63	1			T102	1		T105	1		T23	1
all_levels[23]	auto[1]	5	1			T141	2		T166	1		T195	1
all_levels[24]	auto[0]	57	1			T99	1		T109	1		T98	1
all_levels[24]	auto[1]	6	1			T196	2		T197	1		T198	1
all_levels[25]	auto[0]	54	1			T22	1		T23	1		T110	1
all_levels[25]	auto[1]	4	1			T110	1		T190	1		T199	1
all_levels[26]	auto[0]	49	1			T4	1		T111	1		T105	1
all_levels[26]	auto[1]	5	1			T200	2		T201	1		T202	1
all_levels[27]	auto[0]	32	1			T9	1		T91	1		T109	1
all_levels[27]	auto[1]	5	1			T167	1		T203	3		T204	1
all_levels[28]	auto[0]	44	1			T7	1		T102	1		T23	1
all_levels[28]	auto[1]	5	1			T205	1		T206	1		T207	3
all_levels[29]	auto[0]	33	1			T105	2		T112	1		T113	1
all_levels[29]	auto[1]	9	1			T112	1		T141	1		T208	1
all_levels[30]	auto[0]	34	1			T102	1		T21	1		T22	2
all_levels[30]	auto[1]	3	1			T209	3		-	-		-	-
all_levels[31]	auto[0]	42	1			T5	1		T22	1		T114	1
all_levels[31]	auto[1]	11	1			T114	1		T210	2		T211	3
all_levels[32]	auto[0]	29	1			T23	1		T99	2		T115	1
all_levels[33]	auto[0]	23	1			T102	1		T104	1		T78	1
all_levels[33]	auto[1]	3	1			T102	2		T78	1		-	-
all_levels[34]	auto[0]	36	1			T102	1		T106	1		T109	1
all_levels[34]	auto[1]	2	1			T212	2		-	-		-	-
all_levels[35]	auto[0]	18	1			T116	1		T117	1		T118	1
all_levels[35]	auto[1]	2	1			T118	2		-	-		-	-
all_levels[36]	auto[0]	22	1			T22	1		T119	2		T120	1
all_levels[37]	auto[0]	18	1			T102	1		T113	1		T23	1
all_levels[37]	auto[1]	5	1			T213	1		T214	2		T215	2
all_levels[38]	auto[0]	17	1			T102	2		T121	1		T122	1
all_levels[38]	auto[1]	2	1			T177	1		T216	1		-	-
all_levels[39]	auto[0]	14	1			T4	1		T23	1		T99	1
all_levels[40]	auto[0]	14	1			T9	1		T100	1		T123	1
all_levels[41]	auto[0]	10	1			T99	1		T124	1		T125	1
all_levels[41]	auto[1]	1	1			T217	1		-	-		-	-
all_levels[42]	auto[0]	16	1			T91	1		T99	1		T126	1
all_levels[42]	auto[1]	4	1			T218	1		T219	1		T202	2
all_levels[43]	auto[0]	19	1			T7	1		T105	1		T99	1
all_levels[43]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[44]	auto[0]	6	1			T127	1		T128	1		T129	1
all_levels[45]	auto[0]	14	1			T127	1		T130	1		T131	1
all_levels[45]	auto[1]	2	1			T221	1		T222	1		-	-
all_levels[46]	auto[0]	14	1			T22	1		T132	1		T133	1
all_levels[46]	auto[1]	3	1			T125	3		-	-		-	-
all_levels[47]	auto[0]	12	1			T9	2		T134	1		T125	1
all_levels[47]	auto[1]	1	1			T134	1		-	-		-	-
all_levels[48]	auto[0]	15	1			T4	1		T9	1		T111	1
all_levels[48]	auto[1]	3	1			T223	2		T224	1		-	-
all_levels[49]	auto[0]	9	1			T135	1		T136	1		T124	1
all_levels[49]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[50]	auto[0]	16	1			T11	1		T105	1		T137	1
all_levels[51]	auto[0]	12	1			T11	1		T22	1		T138	1
all_levels[51]	auto[1]	2	1			T226	1		T227	1		-	-
all_levels[52]	auto[0]	8	1			T103	1		T113	1		T117	1
all_levels[52]	auto[1]	2	1			T113	1		T149	1		-	-
all_levels[53]	auto[0]	12	1			T5	1		T139	1		T140	1
all_levels[53]	auto[1]	2	1			T139	1		T140	1		-	-
all_levels[54]	auto[0]	14	1			T105	1		T141	1		T142	1
all_levels[54]	auto[1]	2	1			T228	2		-	-		-	-
all_levels[55]	auto[0]	6	1			T4	1		T143	1		T144	1
all_levels[56]	auto[0]	4	1			T145	1		T146	1		T147	1
all_levels[57]	auto[0]	8	1			T131	1		T117	1		T148	1
all_levels[58]	auto[0]	7	1			T4	1		T146	1		T149	1
all_levels[59]	auto[0]	3	1			T150	1		T151	1		T152	1
all_levels[60]	auto[0]	4	1			T128	1		T153	1		T154	1
all_levels[61]	auto[0]	13	1			T99	2		T135	1		T155	1
all_levels[61]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[62]	auto[0]	8	1			T23	1		T156	1		T116	1
all_levels[63]	auto[0]	11	1			T116	1		T126	1		T157	1
all_levels[63]	auto[1]	2	1			T231	2		-	-		-	-
all_levels[64]	auto[0]	97	1			T4	1		T5	1		T11	1
all_levels[64]	auto[1]	17	1			T232	2		T205	1		T233	1