Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	121842	1			T1	1		T2	13		T3	70
all_pins[1]	121842	1			T1	1		T2	13		T3	70
all_pins[2]	121842	1			T1	1		T2	13		T3	70
all_pins[3]	121842	1			T1	1		T2	13		T3	70
all_pins[4]	121842	1			T1	1		T2	13		T3	70
all_pins[5]	121842	1			T1	1		T2	13		T3	70
all_pins[6]	121842	1			T1	1		T2	13		T3	70
all_pins[7]	121842	1			T1	1		T2	13		T3	70
all_pins[8]	121842	1			T1	1		T2	13		T3	70

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1045648	1			T1	9		T2	96		T3	566
values[0x1]	50930	1			T2	21		T3	64		T4	150
transitions[0x0=>0x1]	40564	1			T2	12		T3	45		T4	112
transitions[0x1=>0x0]	40346	1			T2	12		T3	45		T4	112

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	96207	1			T1	1		T2	3		T3	43
all_pins[0]	values[0x1]	25635	1			T2	10		T3	27		T4	56
all_pins[0]	transitions[0x0=>0x1]	25064	1			T2	10		T3	27		T4	56
all_pins[0]	transitions[0x1=>0x0]	1119	1			T4	1		T5	8		T10	13
all_pins[1]	values[0x0]	120152	1			T1	1		T2	13		T3	70
all_pins[1]	values[0x1]	1690	1			T4	1		T5	9		T10	13
all_pins[1]	transitions[0x0=>0x1]	1579	1			T4	1		T5	9		T10	13
all_pins[1]	transitions[0x1=>0x0]	2471	1			T2	1		T3	10		T4	11
all_pins[2]	values[0x0]	119260	1			T1	1		T2	12		T3	60
all_pins[2]	values[0x1]	2582	1			T2	1		T3	10		T4	11
all_pins[2]	transitions[0x0=>0x1]	2517	1			T2	1		T3	8		T4	11
all_pins[2]	transitions[0x1=>0x0]	217	1			T4	1		T13	1		T23	1
all_pins[3]	values[0x0]	121560	1			T1	1		T2	13		T3	68
all_pins[3]	values[0x1]	282	1			T3	2		T4	1		T13	1
all_pins[3]	transitions[0x0=>0x1]	241	1			T3	2		T4	1		T13	1
all_pins[3]	transitions[0x1=>0x0]	358	1			T3	1		T4	4		T5	3
all_pins[4]	values[0x0]	121443	1			T1	1		T2	13		T3	69
all_pins[4]	values[0x1]	399	1			T3	1		T4	4		T5	3
all_pins[4]	transitions[0x0=>0x1]	329	1			T3	1		T4	4		T5	2
all_pins[4]	transitions[0x1=>0x0]	148	1			T5	3		T13	3		T12	1
all_pins[5]	values[0x0]	121624	1			T1	1		T2	13		T3	70
all_pins[5]	values[0x1]	218	1			T5	4		T13	4		T14	2
all_pins[5]	transitions[0x0=>0x1]	173	1			T5	4		T13	4		T14	2
all_pins[5]	transitions[0x1=>0x0]	830	1			T3	1		T4	6		T5	4
all_pins[6]	values[0x0]	120967	1			T1	1		T2	13		T3	69
all_pins[6]	values[0x1]	875	1			T3	1		T4	6		T5	4
all_pins[6]	transitions[0x0=>0x1]	829	1			T3	1		T4	4		T5	4
all_pins[6]	transitions[0x1=>0x0]	255	1			T3	2		T13	5		T12	10
all_pins[7]	values[0x0]	121541	1			T1	1		T2	13		T3	68
all_pins[7]	values[0x1]	301	1			T3	2		T4	2		T11	1
all_pins[7]	transitions[0x0=>0x1]	171	1			T3	2		T11	1		T13	5
all_pins[7]	transitions[0x1=>0x0]	18818	1			T2	10		T3	21		T4	67
all_pins[8]	values[0x0]	102894	1			T1	1		T2	3		T3	49
all_pins[8]	values[0x1]	18948	1			T2	10		T3	21		T4	69
all_pins[8]	transitions[0x0=>0x1]	9661	1			T2	1		T3	4		T4	35
all_pins[8]	transitions[0x1=>0x0]	16130	1			T2	1		T3	10		T4	22