Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	9753333	1			T2	77		T3	12483		T4	14982
all_levels[1]	2086324	1			T3	12		T4	1411		T5	1270
all_levels[2]	425015	1			T3	9		T4	1431		T5	1569
all_levels[3]	267537	1			T3	5		T4	1634		T5	1369
all_levels[4]	289393	1			T3	12		T4	1458		T5	1497
all_levels[5]	632718	1			T3	10		T4	22596		T5	1409
all_levels[6]	268101	1			T3	6		T4	8844		T5	1409
all_levels[7]	338604	1			T3	13		T4	1264		T5	1213
all_levels[8]	361854	1			T3	12		T4	1141		T5	1515
all_levels[9]	363261	1			T3	23		T4	693		T5	1280
all_levels[10]	385418	1			T3	12		T4	990		T5	1516
all_levels[11]	263542	1			T3	8		T4	875		T5	1265
all_levels[12]	259496	1			T3	10		T4	850		T5	1935
all_levels[13]	386949	1			T3	8		T4	769		T5	1910
all_levels[14]	333910	1			T3	12		T4	704		T5	1934
all_levels[15]	234836	1			T3	18		T4	2215		T5	2224
all_levels[16]	479292	1			T3	24		T4	686		T5	2200
all_levels[17]	414776	1			T3	23		T4	689		T5	1413
all_levels[18]	288037	1			T3	18		T4	534		T5	1939
all_levels[19]	323930	1			T3	11		T4	657		T5	2259
all_levels[20]	218340	1			T3	8		T4	688		T5	1657
all_levels[21]	217569	1			T3	13		T4	633		T5	1937
all_levels[22]	209041	1			T3	13		T4	455		T5	2432
all_levels[23]	261726	1			T3	71		T4	729		T5	3447
all_levels[24]	312492	1			T3	13		T4	727		T5	2614
all_levels[25]	282701	1			T3	8		T4	487		T5	2157
all_levels[26]	238573	1			T3	13		T4	562		T5	2031
all_levels[27]	722626	1			T3	19		T4	727		T5	2141
all_levels[28]	232753	1			T3	21		T4	10624		T5	2373
all_levels[29]	482927	1			T3	15		T4	410		T5	2348
all_levels[30]	325975	1			T3	19		T4	738		T5	2114
all_levels[31]	696328	1			T3	1161		T4	817		T5	2570
all_levels[32]	13696710	1			T3	25556		T4	2886		T5	43341

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

36049710

1

T2

77

T3

39655

T4

84905

auto[1]

4377

1

T3

4

T4

1

T5

2

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	9750820	1			T2	77		T3	12482		T4	14982
all_levels[0]	auto[1]	2513	1			T3	1		T13	36		T14	18
all_levels[1]	auto[0]	2085985	1			T3	12		T4	1411		T5	1270
all_levels[1]	auto[1]	339	1			T111	1		T103	1		T112	2
all_levels[2]	auto[0]	424972	1			T3	9		T4	1431		T5	1569
all_levels[2]	auto[1]	43	1			T241	2		T112	1		T255	1
all_levels[3]	auto[0]	267371	1			T3	5		T4	1634		T5	1369
all_levels[3]	auto[1]	166	1			T139	4		T108	1		T283	6
all_levels[4]	auto[0]	289362	1			T3	12		T4	1458		T5	1497
all_levels[4]	auto[1]	31	1			T77	2		T114	2		T100	1
all_levels[5]	auto[0]	632681	1			T3	10		T4	22596		T5	1409
all_levels[5]	auto[1]	37	1			T297	3		T158	1		T160	2
all_levels[6]	auto[0]	268063	1			T3	6		T4	8843		T5	1409
all_levels[6]	auto[1]	38	1			T4	1		T112	1		T104	1
all_levels[7]	auto[0]	338499	1			T3	13		T4	1264		T5	1213
all_levels[7]	auto[1]	105	1			T287	1		T100	1		T316	23
all_levels[8]	auto[0]	361830	1			T3	12		T4	1141		T5	1515
all_levels[8]	auto[1]	24	1			T111	1		T112	1		T317	1
all_levels[9]	auto[0]	363224	1			T3	22		T4	693		T5	1280
all_levels[9]	auto[1]	37	1			T3	1		T103	1		T31	1
all_levels[10]	auto[0]	385390	1			T3	12		T4	990		T5	1516
all_levels[10]	auto[1]	28	1			T270	1		T114	1		T121	1
all_levels[11]	auto[0]	263501	1			T3	8		T4	875		T5	1265
all_levels[11]	auto[1]	41	1			T205	2		T127	21		T277	1
all_levels[12]	auto[0]	259458	1			T3	10		T4	850		T5	1935
all_levels[12]	auto[1]	38	1			T238	1		T93	1		T140	1
all_levels[13]	auto[0]	386926	1			T3	8		T4	769		T5	1910
all_levels[13]	auto[1]	23	1			T111	1		T103	1		T248	1
all_levels[14]	auto[0]	333884	1			T3	12		T4	704		T5	1934
all_levels[14]	auto[1]	26	1			T24	1		T318	1		T159	1
all_levels[15]	auto[0]	234765	1			T3	18		T4	2215		T5	2224
all_levels[15]	auto[1]	71	1			T14	3		T12	7		T309	1
all_levels[16]	auto[0]	479268	1			T3	24		T4	686		T5	2200
all_levels[16]	auto[1]	24	1			T319	2		T174	1		T210	3
all_levels[17]	auto[0]	414747	1			T3	23		T4	689		T5	1413
all_levels[17]	auto[1]	29	1			T112	1		T139	1		T252	2
all_levels[18]	auto[0]	288017	1			T3	18		T4	534		T5	1939
all_levels[18]	auto[1]	20	1			T112	2		T208	1		T177	1
all_levels[19]	auto[0]	323910	1			T3	11		T4	657		T5	2259
all_levels[19]	auto[1]	20	1			T24	3		T141	4		T166	1
all_levels[20]	auto[0]	218299	1			T3	8		T4	688		T5	1657
all_levels[20]	auto[1]	41	1			T75	2		T77	1		T248	1
all_levels[21]	auto[0]	217546	1			T3	13		T4	633		T5	1937
all_levels[21]	auto[1]	23	1			T172	2		T269	1		T320	3
all_levels[22]	auto[0]	209020	1			T3	13		T4	455		T5	2432
all_levels[22]	auto[1]	21	1			T110	1		T141	2		T298	1
all_levels[23]	auto[0]	261711	1			T3	71		T4	729		T5	3446
all_levels[23]	auto[1]	15	1			T5	1		T78	1		T140	2
all_levels[24]	auto[0]	312481	1			T3	13		T4	727		T5	2614
all_levels[24]	auto[1]	11	1			T234	1		T269	1		T321	1
all_levels[25]	auto[0]	282691	1			T3	8		T4	487		T5	2157
all_levels[25]	auto[1]	10	1			T103	1		T319	1		T162	1
all_levels[26]	auto[0]	238550	1			T3	13		T4	562		T5	2031
all_levels[26]	auto[1]	23	1			T103	1		T252	1		T248	1
all_levels[27]	auto[0]	722611	1			T3	19		T4	727		T5	2141
all_levels[27]	auto[1]	15	1			T261	3		T129	1		T322	1
all_levels[28]	auto[0]	232728	1			T3	21		T4	10624		T5	2373
all_levels[28]	auto[1]	25	1			T27	1		T270	1		T232	1
all_levels[29]	auto[0]	482912	1			T3	15		T4	410		T5	2348
all_levels[29]	auto[1]	15	1			T127	1		T190	2		T193	2
all_levels[30]	auto[0]	325954	1			T3	17		T4	738		T5	2114
all_levels[30]	auto[1]	21	1			T3	2		T108	1		T140	2
all_levels[31]	auto[0]	696315	1			T3	1161		T4	817		T5	2570
all_levels[31]	auto[1]	13	1			T255	1		T190	2		T323	2
all_levels[32]	auto[0]	13696219	1			T3	25556		T4	2886		T5	43340
all_levels[32]	auto[1]	491	1			T5	1		T7	1		T236	1