Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	700	1			T3	7		T4	8		T5	11
all_values[1]	700	1			T3	7		T4	8		T5	11
all_values[2]	700	1			T3	7		T4	8		T5	11
all_values[3]	700	1			T3	7		T4	8		T5	11
all_values[4]	700	1			T3	7		T4	8		T5	11
all_values[5]	700	1			T3	7		T4	8		T5	11
all_values[6]	700	1			T3	7		T4	8		T5	11
all_values[7]	700	1			T3	7		T4	8		T5	11
all_values[8]	700	1			T3	7		T4	8		T5	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3402

1

T3

31

T4

32

T5

52

auto[1]

2898

1

T3

32

T4

40

T5

47

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2108

1

T3

21

T4

24

T5

33

auto[1]

4192

1

T3

42

T4

48

T5

66

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3720

1

T3

37

T4

46

T5

67

auto[1]

2580

1

T3

26

T4

26

T5

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	219	1			T3	2		T4	1		T5	3
all_values[0]	auto[0]	auto[1]	auto[1]	198	1			T3	2		T4	5		T5	6
all_values[0]	auto[1]	auto[0]	auto[1]	158	1			T3	2		T4	2		T24	2
all_values[0]	auto[1]	auto[1]	auto[1]	125	1			T3	1		T5	2		T12	3
all_values[1]	auto[0]	auto[0]	auto[0]	227	1			T3	3		T5	1		T12	2
all_values[1]	auto[0]	auto[1]	auto[0]	202	1			T3	2		T4	7		T5	6
all_values[1]	auto[1]	auto[0]	auto[1]	128	1			T3	1		T5	2		T12	2
all_values[1]	auto[1]	auto[1]	auto[1]	143	1			T3	1		T4	1		T5	2
all_values[2]	auto[0]	auto[0]	auto[0]	138	1			T4	3		T5	2		T12	2
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T4	1		T5	2		T12	1
all_values[2]	auto[0]	auto[1]	auto[0]	121	1			T3	2		T12	1		T99	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T3	1		T5	1		T80	3
all_values[2]	auto[1]	auto[0]	auto[1]	171	1			T4	4		T5	4		T12	2
all_values[2]	auto[1]	auto[1]	auto[1]	132	1			T3	4		T5	2		T12	2
all_values[3]	auto[0]	auto[0]	auto[0]	159	1			T3	1		T4	1		T5	4
all_values[3]	auto[0]	auto[0]	auto[1]	79	1			T4	4		T5	2		T98	1
all_values[3]	auto[0]	auto[1]	auto[0]	119	1			T3	3		T5	4		T12	4
all_values[3]	auto[0]	auto[1]	auto[1]	65	1			T3	1		T24	2		T80	2
all_values[3]	auto[1]	auto[0]	auto[1]	161	1			T4	2		T5	1		T12	1
all_values[3]	auto[1]	auto[1]	auto[1]	117	1			T3	2		T4	1		T12	1
all_values[4]	auto[0]	auto[0]	auto[0]	146	1			T5	2		T21	5		T24	5
all_values[4]	auto[0]	auto[0]	auto[1]	69	1			T3	3		T5	1		T12	3
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T4	1		T5	2		T12	1
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T4	2		T5	2		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	156	1			T3	3		T4	2		T12	3
all_values[4]	auto[1]	auto[1]	auto[1]	132	1			T3	1		T4	3		T5	4
all_values[5]	auto[0]	auto[0]	auto[0]	174	1			T3	3		T4	4		T5	3
all_values[5]	auto[0]	auto[0]	auto[1]	62	1			T5	1		T21	2		T93	1
all_values[5]	auto[0]	auto[1]	auto[0]	110	1			T3	3		T4	2		T12	5
all_values[5]	auto[0]	auto[1]	auto[1]	68	1			T5	4		T21	1		T23	1
all_values[5]	auto[1]	auto[0]	auto[1]	147	1			T3	1		T4	2		T5	2
all_values[5]	auto[1]	auto[1]	auto[1]	139	1			T5	1		T21	2		T24	2
all_values[6]	auto[0]	auto[0]	auto[0]	158	1			T3	2		T4	1		T5	3
all_values[6]	auto[0]	auto[0]	auto[1]	56	1			T4	1		T5	1		T12	1
all_values[6]	auto[0]	auto[1]	auto[0]	114	1			T3	1		T12	1		T21	3
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T4	1		T5	2		T24	1
all_values[6]	auto[1]	auto[0]	auto[1]	168	1			T3	2		T4	3		T5	4
all_values[6]	auto[1]	auto[1]	auto[1]	134	1			T3	2		T4	2		T5	1
all_values[7]	auto[0]	auto[0]	auto[0]	171	1			T3	1		T5	2		T12	4
all_values[7]	auto[0]	auto[0]	auto[1]	64	1			T3	2		T5	3		T12	1
all_values[7]	auto[0]	auto[1]	auto[0]	146	1			T4	5		T5	4		T21	3
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T4	2		T12	1		T24	1
all_values[7]	auto[1]	auto[0]	auto[1]	144	1			T3	3		T5	1		T12	1
all_values[7]	auto[1]	auto[1]	auto[1]	113	1			T3	1		T4	1		T5	1
all_values[8]	auto[0]	auto[0]	auto[1]	200	1			T3	1		T5	4		T12	3
all_values[8]	auto[0]	auto[1]	auto[1]	188	1			T3	4		T4	5		T5	2
all_values[8]	auto[1]	auto[0]	auto[1]	177	1			T3	1		T4	1		T5	4
all_values[8]	auto[1]	auto[1]	auto[1]	135	1			T3	1		T4	2		T5	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal