Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.10 99.10 97.65 100.00 98.38 100.00 99.48


Total test records in report: 1315
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T1254 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4093972592 Jul 31 04:21:22 PM PDT 24 Jul 31 04:21:23 PM PDT 24 61703081 ps
T1255 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2233667675 Jul 31 04:20:33 PM PDT 24 Jul 31 04:20:35 PM PDT 24 46320538 ps
T1256 /workspace/coverage/cover_reg_top/1.uart_tl_errors.519162479 Jul 31 04:21:23 PM PDT 24 Jul 31 04:21:25 PM PDT 24 484815847 ps
T1257 /workspace/coverage/cover_reg_top/42.uart_intr_test.623554148 Jul 31 04:22:34 PM PDT 24 Jul 31 04:22:35 PM PDT 24 57469995 ps
T1258 /workspace/coverage/cover_reg_top/30.uart_intr_test.4121991555 Jul 31 04:24:41 PM PDT 24 Jul 31 04:24:42 PM PDT 24 38677241 ps
T1259 /workspace/coverage/cover_reg_top/3.uart_intr_test.228539715 Jul 31 04:22:05 PM PDT 24 Jul 31 04:22:06 PM PDT 24 53859532 ps
T1260 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4092528709 Jul 31 04:19:55 PM PDT 24 Jul 31 04:19:56 PM PDT 24 52310286 ps
T1261 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.769398887 Jul 31 04:21:45 PM PDT 24 Jul 31 04:21:46 PM PDT 24 200346467 ps
T1262 /workspace/coverage/cover_reg_top/1.uart_csr_rw.3855951885 Jul 31 04:22:10 PM PDT 24 Jul 31 04:22:10 PM PDT 24 41517609 ps
T1263 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.297739547 Jul 31 04:21:11 PM PDT 24 Jul 31 04:21:14 PM PDT 24 1634297520 ps
T1264 /workspace/coverage/cover_reg_top/13.uart_csr_rw.4265659839 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:42 PM PDT 24 46705906 ps
T1265 /workspace/coverage/cover_reg_top/5.uart_csr_rw.1472265411 Jul 31 04:21:20 PM PDT 24 Jul 31 04:21:21 PM PDT 24 32341112 ps
T1266 /workspace/coverage/cover_reg_top/12.uart_csr_rw.1952942024 Jul 31 04:21:32 PM PDT 24 Jul 31 04:21:33 PM PDT 24 34558353 ps
T1267 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3642753472 Jul 31 04:20:22 PM PDT 24 Jul 31 04:20:23 PM PDT 24 59553408 ps
T1268 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.506960478 Jul 31 04:20:16 PM PDT 24 Jul 31 04:20:18 PM PDT 24 27545642 ps
T1269 /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2651604023 Jul 31 04:24:43 PM PDT 24 Jul 31 04:24:44 PM PDT 24 77235245 ps
T1270 /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3820328984 Jul 31 04:25:44 PM PDT 24 Jul 31 04:25:45 PM PDT 24 50491541 ps
T1271 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.914701928 Jul 31 04:24:47 PM PDT 24 Jul 31 04:24:48 PM PDT 24 175500243 ps
T1272 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.886229587 Jul 31 04:22:55 PM PDT 24 Jul 31 04:22:57 PM PDT 24 90758731 ps
T47 /workspace/coverage/cover_reg_top/17.uart_csr_rw.1887916484 Jul 31 04:24:58 PM PDT 24 Jul 31 04:24:59 PM PDT 24 39430644 ps
T1273 /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.370971541 Jul 31 04:22:07 PM PDT 24 Jul 31 04:22:08 PM PDT 24 96108542 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_intr_test.351498540 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 11927846 ps
T1275 /workspace/coverage/cover_reg_top/8.uart_csr_rw.1552617810 Jul 31 04:26:13 PM PDT 24 Jul 31 04:26:14 PM PDT 24 24159916 ps
T1276 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1519991797 Jul 31 04:25:40 PM PDT 24 Jul 31 04:25:41 PM PDT 24 107254852 ps
T1277 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3746101802 Jul 31 04:20:59 PM PDT 24 Jul 31 04:21:00 PM PDT 24 102795982 ps
T1278 /workspace/coverage/cover_reg_top/27.uart_intr_test.3369320237 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:56 PM PDT 24 17315323 ps
T1279 /workspace/coverage/cover_reg_top/8.uart_tl_errors.1802435811 Jul 31 04:21:52 PM PDT 24 Jul 31 04:21:54 PM PDT 24 353591899 ps
T1280 /workspace/coverage/cover_reg_top/10.uart_csr_rw.2193357850 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 98116302 ps
T51 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2623123309 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:42 PM PDT 24 47267769 ps
T1281 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1771517640 Jul 31 04:22:35 PM PDT 24 Jul 31 04:22:35 PM PDT 24 40302711 ps
T1282 /workspace/coverage/cover_reg_top/26.uart_intr_test.1436971870 Jul 31 04:24:47 PM PDT 24 Jul 31 04:24:48 PM PDT 24 49675934 ps
T1283 /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1927427933 Jul 31 04:20:34 PM PDT 24 Jul 31 04:20:35 PM PDT 24 74939033 ps
T1284 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4191138496 Jul 31 04:21:44 PM PDT 24 Jul 31 04:21:45 PM PDT 24 30324122 ps
T1285 /workspace/coverage/cover_reg_top/32.uart_intr_test.2983976455 Jul 31 04:21:54 PM PDT 24 Jul 31 04:21:55 PM PDT 24 16308629 ps
T1286 /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.941214612 Jul 31 04:20:11 PM PDT 24 Jul 31 04:20:13 PM PDT 24 255018824 ps
T1287 /workspace/coverage/cover_reg_top/4.uart_tl_errors.3741912588 Jul 31 04:22:05 PM PDT 24 Jul 31 04:22:08 PM PDT 24 39516733 ps
T1288 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1845008596 Jul 31 04:24:20 PM PDT 24 Jul 31 04:24:23 PM PDT 24 376663453 ps
T1289 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3063606423 Jul 31 04:23:31 PM PDT 24 Jul 31 04:23:32 PM PDT 24 520219142 ps
T1290 /workspace/coverage/cover_reg_top/34.uart_intr_test.3589633289 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:41 PM PDT 24 18336681 ps
T1291 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3968665159 Jul 31 04:24:42 PM PDT 24 Jul 31 04:24:44 PM PDT 24 336454548 ps
T1292 /workspace/coverage/cover_reg_top/12.uart_intr_test.2199893985 Jul 31 04:25:43 PM PDT 24 Jul 31 04:25:44 PM PDT 24 28854251 ps
T1293 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.865203046 Jul 31 04:20:27 PM PDT 24 Jul 31 04:20:28 PM PDT 24 74262444 ps
T1294 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.389311979 Jul 31 04:24:43 PM PDT 24 Jul 31 04:24:44 PM PDT 24 28447560 ps
T1295 /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2884469982 Jul 31 04:24:48 PM PDT 24 Jul 31 04:24:49 PM PDT 24 23895214 ps
T1296 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2514488171 Jul 31 04:20:08 PM PDT 24 Jul 31 04:20:08 PM PDT 24 62557894 ps
T1297 /workspace/coverage/cover_reg_top/6.uart_intr_test.244521772 Jul 31 04:24:47 PM PDT 24 Jul 31 04:24:48 PM PDT 24 27897443 ps
T1298 /workspace/coverage/cover_reg_top/9.uart_tl_errors.1760473573 Jul 31 04:21:09 PM PDT 24 Jul 31 04:21:11 PM PDT 24 501204519 ps
T1299 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3092956253 Jul 31 04:23:25 PM PDT 24 Jul 31 04:23:26 PM PDT 24 77235147 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4174693096 Jul 31 04:21:22 PM PDT 24 Jul 31 04:21:23 PM PDT 24 80974495 ps
T1301 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1833388620 Jul 31 04:20:41 PM PDT 24 Jul 31 04:20:42 PM PDT 24 17326759 ps
T48 /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2674555513 Jul 31 04:21:47 PM PDT 24 Jul 31 04:21:48 PM PDT 24 57264099 ps
T1302 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2777949618 Jul 31 04:21:44 PM PDT 24 Jul 31 04:21:46 PM PDT 24 31746886 ps
T1303 /workspace/coverage/cover_reg_top/40.uart_intr_test.3471851022 Jul 31 04:24:55 PM PDT 24 Jul 31 04:24:56 PM PDT 24 11369368 ps
T1304 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1449634162 Jul 31 04:24:54 PM PDT 24 Jul 31 04:24:55 PM PDT 24 26543736 ps
T1305 /workspace/coverage/cover_reg_top/16.uart_csr_rw.2648360307 Jul 31 04:20:29 PM PDT 24 Jul 31 04:20:30 PM PDT 24 12545415 ps
T1306 /workspace/coverage/cover_reg_top/44.uart_intr_test.1241995778 Jul 31 04:24:39 PM PDT 24 Jul 31 04:24:40 PM PDT 24 14364069 ps
T1307 /workspace/coverage/cover_reg_top/14.uart_intr_test.185250558 Jul 31 04:23:47 PM PDT 24 Jul 31 04:23:48 PM PDT 24 14154736 ps
T1308 /workspace/coverage/cover_reg_top/24.uart_intr_test.2982863402 Jul 31 04:24:42 PM PDT 24 Jul 31 04:24:42 PM PDT 24 14455028 ps
T1309 /workspace/coverage/cover_reg_top/17.uart_tl_errors.3998920322 Jul 31 04:20:31 PM PDT 24 Jul 31 04:20:32 PM PDT 24 65292629 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4191495014 Jul 31 04:25:08 PM PDT 24 Jul 31 04:25:09 PM PDT 24 16816315 ps
T1311 /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3846009302 Jul 31 04:21:45 PM PDT 24 Jul 31 04:21:46 PM PDT 24 84849259 ps
T1312 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1409831691 Jul 31 04:24:49 PM PDT 24 Jul 31 04:24:50 PM PDT 24 104925946 ps
T1313 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2077003694 Jul 31 04:21:28 PM PDT 24 Jul 31 04:21:30 PM PDT 24 35060239 ps
T1314 /workspace/coverage/cover_reg_top/2.uart_csr_rw.3544541556 Jul 31 04:23:24 PM PDT 24 Jul 31 04:23:25 PM PDT 24 12547524 ps
T1315 /workspace/coverage/cover_reg_top/29.uart_intr_test.1176402280 Jul 31 04:21:55 PM PDT 24 Jul 31 04:21:56 PM PDT 24 23523553 ps

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2922345162
Short name T4
Test name
Test status
Simulation time 278862178350 ps
CPU time 959.89 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:42:13 PM PDT 24
Peak memory 224528 kb
Host smart-6710acbc-41ac-41a9-bd34-c5ae8f578cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922345162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2922345162
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.696978577
Short name T99
Test name
Test status
Simulation time 456904507828 ps
CPU time 693.09 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:37:09 PM PDT 24
Peak memory 224804 kb
Host smart-e5bd3664-f4f8-4bc1-8e34-4f9d85535677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696978577 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.696978577
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2570137019
Short name T22
Test name
Test status
Simulation time 459932946163 ps
CPU time 1087.38 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:44:49 PM PDT 24
Peak memory 232880 kb
Host smart-09a7fc99-5e14-4c94-9546-f5effa1f031b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570137019 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2570137019
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.945803352
Short name T6
Test name
Test status
Simulation time 32659070480 ps
CPU time 66.2 seconds
Started Jul 31 04:22:37 PM PDT 24
Finished Jul 31 04:23:44 PM PDT 24
Peak memory 199676 kb
Host smart-96235b78-8f84-426a-937f-7d04c75b782c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945803352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.945803352
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.243667018
Short name T244
Test name
Test status
Simulation time 95270252992 ps
CPU time 236.43 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 198072 kb
Host smart-56c16bb0-cc03-437a-8c16-bfb3e830f7c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243667018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.243667018
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1812144581
Short name T5
Test name
Test status
Simulation time 213323638264 ps
CPU time 703.56 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:37:16 PM PDT 24
Peak memory 213896 kb
Host smart-aa47357a-ddf6-4da0-95c6-e60312191c95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812144581 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1812144581
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.3093115154
Short name T14
Test name
Test status
Simulation time 396053561008 ps
CPU time 679.73 seconds
Started Jul 31 04:23:41 PM PDT 24
Finished Jul 31 04:35:01 PM PDT 24
Peak memory 224644 kb
Host smart-1fed2e92-5711-419f-8788-a95cf2569e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093115154 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.3093115154
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_sec_cm.1285547988
Short name T18
Test name
Test status
Simulation time 33439544 ps
CPU time 0.78 seconds
Started Jul 31 04:24:39 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 216920 kb
Host smart-c604b661-5d98-423f-9543-bae12abb4b5f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285547988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.1285547988
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2337449125
Short name T12
Test name
Test status
Simulation time 390693385103 ps
CPU time 506.26 seconds
Started Jul 31 04:26:37 PM PDT 24
Finished Jul 31 04:35:04 PM PDT 24
Peak memory 216180 kb
Host smart-e73dfd0f-17a2-4ed3-a55a-77b0ba17ac47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337449125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2337449125
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_stress_all.3942317667
Short name T243
Test name
Test status
Simulation time 220158988123 ps
CPU time 1077.67 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:43:06 PM PDT 24
Peak memory 199656 kb
Host smart-598a4a30-a285-43b6-a908-cb87912e33fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942317667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.3942317667
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1034162548
Short name T23
Test name
Test status
Simulation time 275670092399 ps
CPU time 775.08 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:39:29 PM PDT 24
Peak memory 230152 kb
Host smart-d8a5f748-c708-483b-a0b1-adb2ff15c325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034162548 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1034162548
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1563479469
Short name T269
Test name
Test status
Simulation time 1194537676834 ps
CPU time 1038.14 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:44:03 PM PDT 24
Peak memory 224848 kb
Host smart-3e54075f-6285-45bb-9525-f9f2f1803541
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563479469 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1563479469
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_stress_all.1198493417
Short name T93
Test name
Test status
Simulation time 360384346209 ps
CPU time 307.19 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:31:13 PM PDT 24
Peak memory 199720 kb
Host smart-5ed75f5f-c9d3-4403-8b2b-1fe30bdcec42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198493417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1198493417
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2442306888
Short name T63
Test name
Test status
Simulation time 365372412 ps
CPU time 1.4 seconds
Started Jul 31 04:21:08 PM PDT 24
Finished Jul 31 04:21:09 PM PDT 24
Peak memory 199508 kb
Host smart-8934b450-d883-49c6-bf3a-ef919c190dae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442306888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2442306888
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.2534952551
Short name T77
Test name
Test status
Simulation time 526580142595 ps
CPU time 53.51 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:28:01 PM PDT 24
Peak memory 199812 kb
Host smart-7e5b8fd3-fb1c-4608-ba90-47221b34597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534952551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.2534952551
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.2243776784
Short name T135
Test name
Test status
Simulation time 81087108527 ps
CPU time 71.49 seconds
Started Jul 31 04:27:19 PM PDT 24
Finished Jul 31 04:28:31 PM PDT 24
Peak memory 199788 kb
Host smart-aef6612e-30a4-44c9-9b34-97b40a100270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243776784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.2243776784
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.1675836383
Short name T331
Test name
Test status
Simulation time 13914640 ps
CPU time 0.57 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 195116 kb
Host smart-14b8e9b5-eac9-4cf2-8b1b-713e4ea54af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675836383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.1675836383
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1172702903
Short name T24
Test name
Test status
Simulation time 96936694761 ps
CPU time 615.8 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:36:24 PM PDT 24
Peak memory 216384 kb
Host smart-fc9b7141-a066-4f89-a632-9d7ea877a7f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172702903 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1172702903
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.2233245260
Short name T128
Test name
Test status
Simulation time 431732351721 ps
CPU time 665.78 seconds
Started Jul 31 04:22:35 PM PDT 24
Finished Jul 31 04:33:41 PM PDT 24
Peak memory 214584 kb
Host smart-254b192f-0ee6-42a2-9468-e51bb48de1f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233245260 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.2233245260
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2418268898
Short name T112
Test name
Test status
Simulation time 202672378417 ps
CPU time 157.49 seconds
Started Jul 31 04:27:20 PM PDT 24
Finished Jul 31 04:29:58 PM PDT 24
Peak memory 199780 kb
Host smart-839417d2-ac37-44b1-b2a7-78df5eead9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418268898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2418268898
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.460084774
Short name T30
Test name
Test status
Simulation time 156129536744 ps
CPU time 1096.13 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:43:11 PM PDT 24
Peak memory 199484 kb
Host smart-d484975c-3eb9-47a2-82c3-3e8e1682a926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460084774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.460084774
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_stress_all.2397213890
Short name T190
Test name
Test status
Simulation time 205793915459 ps
CPU time 346.53 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:31:16 PM PDT 24
Peak memory 199644 kb
Host smart-86c6f9dc-2cc4-4bc6-bdbb-f94890c33c42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397213890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.2397213890
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.3746416126
Short name T200
Test name
Test status
Simulation time 133798738548 ps
CPU time 370.31 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:32:43 PM PDT 24
Peak memory 216256 kb
Host smart-0dc2e8e0-5eac-431e-b9e5-b31b14f5d3c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746416126 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.3746416126
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2674555513
Short name T48
Test name
Test status
Simulation time 57264099 ps
CPU time 0.77 seconds
Started Jul 31 04:21:47 PM PDT 24
Finished Jul 31 04:21:48 PM PDT 24
Peak memory 196612 kb
Host smart-c28910f8-d6fd-4c32-9f2c-baa02b6e9353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674555513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2674555513
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.2692490515
Short name T54
Test name
Test status
Simulation time 83526232 ps
CPU time 0.61 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 195600 kb
Host smart-90387799-313e-4071-85fc-86eb2112f071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692490515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.2692490515
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.847440258
Short name T127
Test name
Test status
Simulation time 438386793615 ps
CPU time 586.82 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:35:34 PM PDT 24
Peak memory 224648 kb
Host smart-da404b08-1cef-47b8-bd00-4fd5dce16dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847440258 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.847440258
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1205535201
Short name T177
Test name
Test status
Simulation time 75103822926 ps
CPU time 228.72 seconds
Started Jul 31 04:26:37 PM PDT 24
Finished Jul 31 04:30:26 PM PDT 24
Peak memory 199764 kb
Host smart-22b57ec7-c14d-4b21-9cce-e09376f6ba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205535201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1205535201
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.754737960
Short name T166
Test name
Test status
Simulation time 139510574241 ps
CPU time 276.06 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:31:43 PM PDT 24
Peak memory 199620 kb
Host smart-0dbc8968-4176-4d15-9c0d-8a6e928a33fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754737960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.754737960
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.2571967222
Short name T205
Test name
Test status
Simulation time 37828726036 ps
CPU time 64.53 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199664 kb
Host smart-12a1d7b4-ca2b-4df7-bc80-9d6b5dc3942e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571967222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.2571967222
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1400501513
Short name T256
Test name
Test status
Simulation time 105891725134 ps
CPU time 144.85 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:29:38 PM PDT 24
Peak memory 199864 kb
Host smart-9fc49420-2e86-49b3-9ad6-97e36674d11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400501513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1400501513
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3155834179
Short name T105
Test name
Test status
Simulation time 44305809467 ps
CPU time 42.57 seconds
Started Jul 31 04:26:37 PM PDT 24
Finished Jul 31 04:27:20 PM PDT 24
Peak memory 199736 kb
Host smart-7da64c00-732e-4903-98d5-5b1bf90dd91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155834179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3155834179
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.1815941535
Short name T65
Test name
Test status
Simulation time 511888684 ps
CPU time 1.41 seconds
Started Jul 31 04:22:07 PM PDT 24
Finished Jul 31 04:22:09 PM PDT 24
Peak memory 199500 kb
Host smart-54fb6d0b-0a96-405d-8e47-9b1465f09324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815941535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.1815941535
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/default/25.uart_stress_all.1850563286
Short name T176
Test name
Test status
Simulation time 462321566107 ps
CPU time 205.54 seconds
Started Jul 31 04:25:07 PM PDT 24
Finished Jul 31 04:28:32 PM PDT 24
Peak memory 200108 kb
Host smart-98e34295-ce68-4826-91d1-d6fb0d6df98e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850563286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1850563286
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.4203758757
Short name T103
Test name
Test status
Simulation time 19924612876 ps
CPU time 29.76 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:26:56 PM PDT 24
Peak memory 199348 kb
Host smart-93dbd9f8-9ba0-4ebb-acbc-9d11eaeba925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203758757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.4203758757
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_stress_all.2586207888
Short name T233
Test name
Test status
Simulation time 209739743040 ps
CPU time 382.27 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:32:20 PM PDT 24
Peak memory 199744 kb
Host smart-559f2799-6087-4759-bc77-9f4aa49c498a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586207888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2586207888
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.117299910
Short name T231
Test name
Test status
Simulation time 180536971013 ps
CPU time 41.09 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:23 PM PDT 24
Peak memory 199728 kb
Host smart-b23b00e0-1bf5-47de-94fd-f506d0628890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117299910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.117299910
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.2284696675
Short name T210
Test name
Test status
Simulation time 74186463353 ps
CPU time 44.95 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:27:32 PM PDT 24
Peak memory 199648 kb
Host smart-79400eab-e711-4873-96b8-5ff125e979ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284696675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.2284696675
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1385387834
Short name T169
Test name
Test status
Simulation time 72393564914 ps
CPU time 30.87 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:27:26 PM PDT 24
Peak memory 199660 kb
Host smart-84fbf5e4-f10a-4b58-b99f-0191b7a9a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385387834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1385387834
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.2636444674
Short name T115
Test name
Test status
Simulation time 278268720424 ps
CPU time 363.14 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:30:47 PM PDT 24
Peak memory 216736 kb
Host smart-96bd2521-d547-4bc7-a910-3873211c910f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636444674 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.2636444674
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1648480406
Short name T322
Test name
Test status
Simulation time 76008288602 ps
CPU time 150.28 seconds
Started Jul 31 04:27:12 PM PDT 24
Finished Jul 31 04:29:42 PM PDT 24
Peak memory 199736 kb
Host smart-042c2d98-9cdd-49b2-a4d4-f43f979458fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648480406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1648480406
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.204092295
Short name T315
Test name
Test status
Simulation time 84983804423 ps
CPU time 67.81 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 199728 kb
Host smart-46828d17-85fc-4b74-aca9-45f07b28c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204092295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.204092295
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3154849076
Short name T146
Test name
Test status
Simulation time 24561750678 ps
CPU time 9.31 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:32 PM PDT 24
Peak memory 199440 kb
Host smart-f26c73c5-9204-4609-ae97-dbd8d19b523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154849076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3154849076
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.202383958
Short name T78
Test name
Test status
Simulation time 217037774820 ps
CPU time 219.41 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:30:33 PM PDT 24
Peak memory 199808 kb
Host smart-da5aedbe-0de4-47a0-97a9-c69075437ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202383958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.202383958
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.3764370511
Short name T319
Test name
Test status
Simulation time 23541169093 ps
CPU time 45.88 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199744 kb
Host smart-4c88fb8a-b070-4589-971b-02ce38109491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764370511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.3764370511
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.3133265949
Short name T930
Test name
Test status
Simulation time 51656548209 ps
CPU time 38.8 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:39 PM PDT 24
Peak memory 199324 kb
Host smart-a832da4f-047f-4e78-92c2-3797256948a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133265949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.3133265949
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2668394247
Short name T202
Test name
Test status
Simulation time 93590893990 ps
CPU time 191.04 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:30:28 PM PDT 24
Peak memory 199672 kb
Host smart-b8e90495-fec2-41c1-b317-cde2755f4614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668394247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2668394247
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3283944329
Short name T152
Test name
Test status
Simulation time 17248694090 ps
CPU time 14.73 seconds
Started Jul 31 04:25:34 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 199608 kb
Host smart-49d7f807-9ea8-4c9a-ab49-1445bf796d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283944329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3283944329
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3812253494
Short name T186
Test name
Test status
Simulation time 46014572303 ps
CPU time 536.7 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:35:40 PM PDT 24
Peak memory 216388 kb
Host smart-8162c01b-af32-4c8e-996f-d249c676942b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812253494 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3812253494
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2857700353
Short name T35
Test name
Test status
Simulation time 243030825189 ps
CPU time 1006.07 seconds
Started Jul 31 04:26:35 PM PDT 24
Finished Jul 31 04:43:21 PM PDT 24
Peak memory 224528 kb
Host smart-087d395c-6ca6-4df4-bb04-cbaea8f01aae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857700353 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2857700353
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.227128047
Short name T221
Test name
Test status
Simulation time 104767414297 ps
CPU time 86.16 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:28:11 PM PDT 24
Peak memory 199704 kb
Host smart-c5a1eaa1-e2ae-4eba-abd6-d8f1653d4fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227128047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.227128047
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.2967432326
Short name T224
Test name
Test status
Simulation time 76926666551 ps
CPU time 63.93 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199740 kb
Host smart-221fbcbd-36a3-4a3d-b8fd-ee82570142e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967432326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.2967432326
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.334999162
Short name T230
Test name
Test status
Simulation time 37101146517 ps
CPU time 15.32 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:16 PM PDT 24
Peak memory 199716 kb
Host smart-7649ce00-a9ac-4945-8e93-cf0a825a9dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334999162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.334999162
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_full.1156568384
Short name T268
Test name
Test status
Simulation time 103214836256 ps
CPU time 39.88 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:53 PM PDT 24
Peak memory 198376 kb
Host smart-2e752dfd-3db5-4fd7-82ce-757142172d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156568384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.1156568384
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3538804800
Short name T213
Test name
Test status
Simulation time 127803622919 ps
CPU time 53.91 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:27:49 PM PDT 24
Peak memory 199704 kb
Host smart-ee41762d-4afa-4127-8a98-8851c305adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538804800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3538804800
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.2600005901
Short name T196
Test name
Test status
Simulation time 230951939859 ps
CPU time 181.19 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:29:55 PM PDT 24
Peak memory 199828 kb
Host smart-d7fe3c83-1faa-4bde-ada7-e2484c7b87e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600005901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.2600005901
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.940938868
Short name T188
Test name
Test status
Simulation time 78090412268 ps
CPU time 43.59 seconds
Started Jul 31 04:26:57 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199688 kb
Host smart-91913566-c530-4da1-a63a-b0245658685a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940938868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.940938868
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.1602506780
Short name T212
Test name
Test status
Simulation time 26024140320 ps
CPU time 15.64 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199732 kb
Host smart-a0ce403c-6548-485e-9f92-eb9c9ed804ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602506780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.1602506780
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.820103530
Short name T134
Test name
Test status
Simulation time 132386023061 ps
CPU time 32.33 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199664 kb
Host smart-30afb6b2-a09f-4f5c-b49b-a2a9286f4c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820103530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.820103530
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.917238617
Short name T118
Test name
Test status
Simulation time 87838098267 ps
CPU time 34.59 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:27:37 PM PDT 24
Peak memory 199828 kb
Host smart-0db65a31-1eba-4f43-8e79-62ab5f5fea36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917238617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.917238617
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.601296555
Short name T194
Test name
Test status
Simulation time 13575179433 ps
CPU time 23.78 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:27:23 PM PDT 24
Peak memory 199744 kb
Host smart-c06aeb12-e50f-4223-a18e-3ed649bad6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601296555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.601296555
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.654637239
Short name T139
Test name
Test status
Simulation time 55217589129 ps
CPU time 23.01 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:23 PM PDT 24
Peak memory 199844 kb
Host smart-ca236b2d-ad21-4a82-8600-133b55fb5a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654637239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.654637239
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1550360556
Short name T217
Test name
Test status
Simulation time 17915277290 ps
CPU time 33.24 seconds
Started Jul 31 04:27:04 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199760 kb
Host smart-03876f25-8b25-4e25-99af-3aa9fd39f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550360556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1550360556
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2431079371
Short name T209
Test name
Test status
Simulation time 173997467971 ps
CPU time 231.9 seconds
Started Jul 31 04:27:09 PM PDT 24
Finished Jul 31 04:31:01 PM PDT 24
Peak memory 199744 kb
Host smart-0ae5a975-09b2-4be7-a17b-9465cfdcda90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431079371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2431079371
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.1681444627
Short name T226
Test name
Test status
Simulation time 80128352003 ps
CPU time 33.92 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199772 kb
Host smart-d903233e-77fc-47d0-845f-0adaff5463d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681444627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.1681444627
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2343147116
Short name T113
Test name
Test status
Simulation time 31749654503 ps
CPU time 12.62 seconds
Started Jul 31 04:27:04 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 199748 kb
Host smart-784ae734-42d2-4c18-8557-f4c6e5f57197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343147116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2343147116
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.1027541824
Short name T220
Test name
Test status
Simulation time 24974234561 ps
CPU time 45.27 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:28:03 PM PDT 24
Peak memory 199648 kb
Host smart-c4388b8a-e625-4fb9-831b-d73b44e88432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027541824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1027541824
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_stress_all.700745750
Short name T167
Test name
Test status
Simulation time 176627027278 ps
CPU time 261.86 seconds
Started Jul 31 04:25:46 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 199860 kb
Host smart-fc501e2c-1f59-4364-a96c-4eb74bc573c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700745750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.700745750
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.1956602353
Short name T225
Test name
Test status
Simulation time 57169234089 ps
CPU time 31.48 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 199804 kb
Host smart-3192e42f-2b48-4edc-9c39-0937e4adc550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956602353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.1956602353
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3735317353
Short name T228
Test name
Test status
Simulation time 59716714028 ps
CPU time 98.02 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:28:12 PM PDT 24
Peak memory 199648 kb
Host smart-5ee601ee-455c-4f26-aafa-9cb9185e46ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735317353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3735317353
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2833996143
Short name T125
Test name
Test status
Simulation time 378072180634 ps
CPU time 1314.96 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:45:37 PM PDT 24
Peak memory 226556 kb
Host smart-948a079a-6f63-4d29-8b98-f8912e74b309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833996143 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2833996143
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.297739547
Short name T1263
Test name
Test status
Simulation time 1634297520 ps
CPU time 2.56 seconds
Started Jul 31 04:21:11 PM PDT 24
Finished Jul 31 04:21:14 PM PDT 24
Peak memory 198252 kb
Host smart-7cd15fcd-4686-4f63-9be7-ca71090f63b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297739547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.297739547
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.3173387354
Short name T44
Test name
Test status
Simulation time 1032475667 ps
CPU time 1.94 seconds
Started Jul 31 04:20:02 PM PDT 24
Finished Jul 31 04:20:04 PM PDT 24
Peak memory 195424 kb
Host smart-95265380-a0ec-410a-9309-24d72ae0377e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173387354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.3173387354
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.562431815
Short name T1211
Test name
Test status
Simulation time 44782807 ps
CPU time 1.13 seconds
Started Jul 31 04:20:14 PM PDT 24
Finished Jul 31 04:20:16 PM PDT 24
Peak memory 200296 kb
Host smart-1c9a2d83-1fde-4206-8816-ea56c47808c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562431815 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.562431815
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.1732854727
Short name T1190
Test name
Test status
Simulation time 13188213 ps
CPU time 0.59 seconds
Started Jul 31 04:21:47 PM PDT 24
Finished Jul 31 04:21:48 PM PDT 24
Peak memory 195572 kb
Host smart-29b9d15d-81de-424b-a8f7-b7ae9a1e83cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732854727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.1732854727
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4180556439
Short name T1217
Test name
Test status
Simulation time 18779153 ps
CPU time 0.62 seconds
Started Jul 31 04:20:31 PM PDT 24
Finished Jul 31 04:20:32 PM PDT 24
Peak memory 194612 kb
Host smart-f915a6fc-40c3-4648-9ce0-adbfce3f8742
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180556439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4180556439
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4191138496
Short name T1284
Test name
Test status
Simulation time 30324122 ps
CPU time 0.66 seconds
Started Jul 31 04:21:44 PM PDT 24
Finished Jul 31 04:21:45 PM PDT 24
Peak memory 195892 kb
Host smart-b5eec207-65db-4e51-8535-4ea28445baca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191138496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr
_outstanding.4191138496
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.216059425
Short name T1241
Test name
Test status
Simulation time 196996642 ps
CPU time 1.19 seconds
Started Jul 31 04:21:45 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 200264 kb
Host smart-8d155269-314b-4207-933d-51ae0854b022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216059425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.216059425
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.1103504084
Short name T62
Test name
Test status
Simulation time 236447056 ps
CPU time 1.34 seconds
Started Jul 31 04:19:56 PM PDT 24
Finished Jul 31 04:19:57 PM PDT 24
Peak memory 198664 kb
Host smart-c745e886-5588-45fc-b9e7-1bc72e81d56e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103504084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.1103504084
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3746101802
Short name T1277
Test name
Test status
Simulation time 102795982 ps
CPU time 0.78 seconds
Started Jul 31 04:20:59 PM PDT 24
Finished Jul 31 04:21:00 PM PDT 24
Peak memory 196568 kb
Host smart-57e80638-7869-4c5a-b503-f8e7f6e60751
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746101802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3746101802
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.2443506171
Short name T43
Test name
Test status
Simulation time 76293527 ps
CPU time 2.26 seconds
Started Jul 31 04:21:23 PM PDT 24
Finished Jul 31 04:21:25 PM PDT 24
Peak memory 197948 kb
Host smart-2999d9cd-b8fa-4e49-afe6-344e5539a1fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443506171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.2443506171
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.4107385600
Short name T1185
Test name
Test status
Simulation time 13817965 ps
CPU time 0.6 seconds
Started Jul 31 04:20:29 PM PDT 24
Finished Jul 31 04:20:30 PM PDT 24
Peak memory 195448 kb
Host smart-994a4ba3-1204-4aa3-b00d-ce3bc86c0a66
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107385600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.4107385600
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.1519991797
Short name T1276
Test name
Test status
Simulation time 107254852 ps
CPU time 0.81 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 199664 kb
Host smart-44505736-d728-4a54-aea1-602da288fdd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519991797 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.1519991797
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.3855951885
Short name T1262
Test name
Test status
Simulation time 41517609 ps
CPU time 0.62 seconds
Started Jul 31 04:22:10 PM PDT 24
Finished Jul 31 04:22:10 PM PDT 24
Peak memory 195612 kb
Host smart-b1646a4c-0422-4f5e-85f4-fd442d308247
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855951885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.3855951885
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.2676691435
Short name T1183
Test name
Test status
Simulation time 79489684 ps
CPU time 0.55 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 194304 kb
Host smart-29c0b885-5f5e-4083-bf30-9b95f437fa52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676691435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.2676691435
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.865203046
Short name T1293
Test name
Test status
Simulation time 74262444 ps
CPU time 0.7 seconds
Started Jul 31 04:20:27 PM PDT 24
Finished Jul 31 04:20:28 PM PDT 24
Peak memory 196168 kb
Host smart-49124446-a7ca-498c-b485-bde2fe2c43b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865203046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr_
outstanding.865203046
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.519162479
Short name T1256
Test name
Test status
Simulation time 484815847 ps
CPU time 2.31 seconds
Started Jul 31 04:21:23 PM PDT 24
Finished Jul 31 04:21:25 PM PDT 24
Peak memory 200240 kb
Host smart-7ffb9f72-60cb-4e80-b6e1-961ef31d4153
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519162479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.519162479
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.3085787630
Short name T1251
Test name
Test status
Simulation time 26486475 ps
CPU time 0.8 seconds
Started Jul 31 04:22:35 PM PDT 24
Finished Jul 31 04:22:36 PM PDT 24
Peak memory 199568 kb
Host smart-4385921d-ca14-4343-975d-b0a011704a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085787630 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.3085787630
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.2193357850
Short name T1280
Test name
Test status
Simulation time 98116302 ps
CPU time 0.6 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 195924 kb
Host smart-b239871a-62b8-47a8-85c4-d96edd23f10a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193357850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.2193357850
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.2723361277
Short name T1200
Test name
Test status
Simulation time 48509485 ps
CPU time 0.55 seconds
Started Jul 31 04:22:36 PM PDT 24
Finished Jul 31 04:22:37 PM PDT 24
Peak memory 194564 kb
Host smart-e479bc29-e1db-4e30-aee8-1a0e7bde602e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723361277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.2723361277
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.1833388620
Short name T1301
Test name
Test status
Simulation time 17326759 ps
CPU time 0.75 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 197336 kb
Host smart-c630daa1-45d8-4699-80a2-028a2332adbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833388620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.1833388620
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.2199815322
Short name T1237
Test name
Test status
Simulation time 234496770 ps
CPU time 1.5 seconds
Started Jul 31 04:20:50 PM PDT 24
Finished Jul 31 04:20:52 PM PDT 24
Peak memory 200264 kb
Host smart-504b3aab-e6fd-4fc0-857f-b8a3ed5c1ae3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199815322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.2199815322
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.820348928
Short name T101
Test name
Test status
Simulation time 1534436180 ps
CPU time 1.33 seconds
Started Jul 31 04:23:28 PM PDT 24
Finished Jul 31 04:23:30 PM PDT 24
Peak memory 199520 kb
Host smart-3a1bfefc-6de0-445c-bd6b-9c2123398536
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820348928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.820348928
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.4046261477
Short name T1191
Test name
Test status
Simulation time 155314040 ps
CPU time 0.79 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 197636 kb
Host smart-79116174-9cdf-45cf-aa0a-f4be0758eb63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046261477 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.4046261477
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.815199539
Short name T1240
Test name
Test status
Simulation time 53339619 ps
CPU time 0.54 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 194596 kb
Host smart-a3b551dc-ade5-4960-9503-9810cb68a65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815199539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.815199539
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2991786892
Short name T1236
Test name
Test status
Simulation time 15680320 ps
CPU time 0.59 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:20:59 PM PDT 24
Peak memory 195572 kb
Host smart-1214f12e-d77a-4eb7-ad07-dec076bd23f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991786892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2991786892
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3579987897
Short name T1203
Test name
Test status
Simulation time 137594507 ps
CPU time 1.85 seconds
Started Jul 31 04:23:33 PM PDT 24
Finished Jul 31 04:23:35 PM PDT 24
Peak memory 200328 kb
Host smart-d37a84f0-bd08-47d1-ae57-1d5a121aed61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579987897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3579987897
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1409831691
Short name T1312
Test name
Test status
Simulation time 104925946 ps
CPU time 0.94 seconds
Started Jul 31 04:24:49 PM PDT 24
Finished Jul 31 04:24:50 PM PDT 24
Peak memory 199164 kb
Host smart-c95cabe5-3ce9-407b-bfdb-bbdd8f42d64d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409831691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1409831691
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3642753472
Short name T1267
Test name
Test status
Simulation time 59553408 ps
CPU time 0.88 seconds
Started Jul 31 04:20:22 PM PDT 24
Finished Jul 31 04:20:23 PM PDT 24
Peak memory 199980 kb
Host smart-891d670b-d1ce-40ce-8aaf-b42a4fb94d5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642753472 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3642753472
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.1952942024
Short name T1266
Test name
Test status
Simulation time 34558353 ps
CPU time 0.62 seconds
Started Jul 31 04:21:32 PM PDT 24
Finished Jul 31 04:21:33 PM PDT 24
Peak memory 195740 kb
Host smart-7d99e7ba-eb37-4021-8040-fed4d3606e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952942024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1952942024
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.2199893985
Short name T1292
Test name
Test status
Simulation time 28854251 ps
CPU time 0.59 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 194592 kb
Host smart-05968b69-b1c1-496a-b828-8c459d67d9b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199893985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2199893985
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.1449634162
Short name T1304
Test name
Test status
Simulation time 26543736 ps
CPU time 0.7 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 196244 kb
Host smart-35fa1a20-601e-4c92-a532-4e11cc155eff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449634162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.1449634162
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1845008596
Short name T1288
Test name
Test status
Simulation time 376663453 ps
CPU time 2.09 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:24:23 PM PDT 24
Peak memory 199128 kb
Host smart-d2745685-a0c0-43f5-829e-16767c479074
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845008596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1845008596
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.3820328984
Short name T1270
Test name
Test status
Simulation time 50491541 ps
CPU time 0.91 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199000 kb
Host smart-e7f6b675-1a8e-408e-94d2-9da89cc78135
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820328984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.3820328984
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.4174693096
Short name T1300
Test name
Test status
Simulation time 80974495 ps
CPU time 0.74 seconds
Started Jul 31 04:21:22 PM PDT 24
Finished Jul 31 04:21:23 PM PDT 24
Peak memory 198536 kb
Host smart-c8b0133c-d522-4a17-be7e-517bdfc48414
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174693096 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.4174693096
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4265659839
Short name T1264
Test name
Test status
Simulation time 46705906 ps
CPU time 0.58 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 195656 kb
Host smart-09d66d69-addd-430c-891c-1b7c4b63e412
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265659839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4265659839
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.3370685192
Short name T1207
Test name
Test status
Simulation time 108646507 ps
CPU time 0.53 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:00 PM PDT 24
Peak memory 194544 kb
Host smart-0b934fc7-80ea-4421-b56b-549d76b21125
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370685192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3370685192
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.3783327204
Short name T1238
Test name
Test status
Simulation time 27807746 ps
CPU time 0.68 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 197120 kb
Host smart-b0418285-5e52-4fdd-9126-e51e50cfe3a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783327204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.3783327204
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.3584617891
Short name T1178
Test name
Test status
Simulation time 91656726 ps
CPU time 1.72 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 198468 kb
Host smart-c2261f0f-8fd4-48e8-aee1-c2e5acf7c27e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584617891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3584617891
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.1222673691
Short name T64
Test name
Test status
Simulation time 54820914 ps
CPU time 0.95 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 198072 kb
Host smart-f2fe1d1a-3034-4158-ab0c-fbadcdb294eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222673691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.1222673691
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2514488171
Short name T1296
Test name
Test status
Simulation time 62557894 ps
CPU time 0.71 seconds
Started Jul 31 04:20:08 PM PDT 24
Finished Jul 31 04:20:08 PM PDT 24
Peak memory 197828 kb
Host smart-f1746a33-1b9d-4671-8b5c-5051ccb24138
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514488171 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2514488171
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.3311449879
Short name T52
Test name
Test status
Simulation time 13764484 ps
CPU time 0.61 seconds
Started Jul 31 04:22:35 PM PDT 24
Finished Jul 31 04:22:36 PM PDT 24
Peak memory 195968 kb
Host smart-a0984a98-85d3-48c1-86d2-3de5d8e48969
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311449879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.3311449879
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.185250558
Short name T1307
Test name
Test status
Simulation time 14154736 ps
CPU time 0.57 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:23:48 PM PDT 24
Peak memory 194604 kb
Host smart-19ed97dc-e4cf-43de-93a0-6aaf9ad79c52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185250558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.185250558
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2982286559
Short name T59
Test name
Test status
Simulation time 119065091 ps
CPU time 0.63 seconds
Started Jul 31 04:20:31 PM PDT 24
Finished Jul 31 04:20:31 PM PDT 24
Peak memory 196088 kb
Host smart-b711a88a-a1cd-42ed-89b9-45994561df8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982286559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2982286559
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.1292970098
Short name T1231
Test name
Test status
Simulation time 74345017 ps
CPU time 1.54 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 199868 kb
Host smart-0be846ae-d92a-439d-b013-acb852b834c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292970098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.1292970098
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.4281396311
Short name T61
Test name
Test status
Simulation time 79079830 ps
CPU time 0.9 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 198748 kb
Host smart-4c17ca2c-fbc0-46fb-9b14-8ae484dda4ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281396311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.4281396311
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.506960478
Short name T1268
Test name
Test status
Simulation time 27545642 ps
CPU time 0.82 seconds
Started Jul 31 04:20:16 PM PDT 24
Finished Jul 31 04:20:18 PM PDT 24
Peak memory 198612 kb
Host smart-b6cd57a1-9b2a-4caa-aee6-5cf0d3aaff8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506960478 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.506960478
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1874953541
Short name T1205
Test name
Test status
Simulation time 25169153 ps
CPU time 0.63 seconds
Started Jul 31 04:20:07 PM PDT 24
Finished Jul 31 04:20:07 PM PDT 24
Peak memory 195600 kb
Host smart-c19f1d28-6f48-4cd6-87a2-1a18e31653d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874953541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1874953541
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.419697825
Short name T1242
Test name
Test status
Simulation time 40936569 ps
CPU time 0.58 seconds
Started Jul 31 04:20:16 PM PDT 24
Finished Jul 31 04:20:16 PM PDT 24
Peak memory 194432 kb
Host smart-4d9e1b00-1ec6-4b75-9cfb-955cdda1308d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419697825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.419697825
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.4038671675
Short name T1196
Test name
Test status
Simulation time 35191582 ps
CPU time 0.83 seconds
Started Jul 31 04:20:15 PM PDT 24
Finished Jul 31 04:20:16 PM PDT 24
Peak memory 196604 kb
Host smart-f8c3bd76-3251-481a-9a75-89554b2f25a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038671675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.4038671675
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2077003694
Short name T1313
Test name
Test status
Simulation time 35060239 ps
CPU time 1.88 seconds
Started Jul 31 04:21:28 PM PDT 24
Finished Jul 31 04:21:30 PM PDT 24
Peak memory 200244 kb
Host smart-20612008-34bf-48ae-a66f-7bcc5907dbd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077003694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2077003694
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2511593733
Short name T1228
Test name
Test status
Simulation time 106521532 ps
CPU time 0.99 seconds
Started Jul 31 04:20:27 PM PDT 24
Finished Jul 31 04:20:28 PM PDT 24
Peak memory 199148 kb
Host smart-9e53bc5b-143b-41d1-9f62-82c25b01aefd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511593733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2511593733
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.943089616
Short name T1194
Test name
Test status
Simulation time 77534290 ps
CPU time 1.05 seconds
Started Jul 31 04:20:28 PM PDT 24
Finished Jul 31 04:20:29 PM PDT 24
Peak memory 200048 kb
Host smart-b88bb123-1aeb-4526-a1cf-025ffe1e0d97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943089616 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.943089616
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.2648360307
Short name T1305
Test name
Test status
Simulation time 12545415 ps
CPU time 0.66 seconds
Started Jul 31 04:20:29 PM PDT 24
Finished Jul 31 04:20:30 PM PDT 24
Peak memory 195972 kb
Host smart-2802e886-05cf-42e6-96ef-30967f839521
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648360307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.2648360307
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.2626275107
Short name T1199
Test name
Test status
Simulation time 33405083 ps
CPU time 0.64 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 192884 kb
Host smart-95b88f98-1a11-46a6-bd69-f05fcee8aba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626275107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.2626275107
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.3108533583
Short name T1212
Test name
Test status
Simulation time 54324813 ps
CPU time 0.71 seconds
Started Jul 31 04:20:36 PM PDT 24
Finished Jul 31 04:20:36 PM PDT 24
Peak memory 197336 kb
Host smart-66f0fe86-155d-4411-b8a6-97d5c7f70c6e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108533583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.3108533583
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.1038246980
Short name T1249
Test name
Test status
Simulation time 294988736 ps
CPU time 1.66 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 199152 kb
Host smart-922e463e-7c9f-4c56-95a8-a8a528639202
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038246980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.1038246980
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.2651604023
Short name T1269
Test name
Test status
Simulation time 77235245 ps
CPU time 1.24 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 198452 kb
Host smart-df98064c-fa62-4dc6-abb8-b5653b7d18ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651604023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.2651604023
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2233667675
Short name T1255
Test name
Test status
Simulation time 46320538 ps
CPU time 1.11 seconds
Started Jul 31 04:20:33 PM PDT 24
Finished Jul 31 04:20:35 PM PDT 24
Peak memory 200220 kb
Host smart-7c346fa0-91b1-4a82-88c1-bd23951dec74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233667675 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2233667675
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.1887916484
Short name T47
Test name
Test status
Simulation time 39430644 ps
CPU time 0.58 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:24:59 PM PDT 24
Peak memory 195516 kb
Host smart-561e9d4c-555e-4b15-9ada-a623b0cae97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887916484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.1887916484
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.2118089594
Short name T1225
Test name
Test status
Simulation time 19423505 ps
CPU time 0.55 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 194392 kb
Host smart-c46c2756-1d4c-4479-bc10-d24302926c8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118089594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.2118089594
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2715313316
Short name T55
Test name
Test status
Simulation time 78904427 ps
CPU time 0.77 seconds
Started Jul 31 04:20:40 PM PDT 24
Finished Jul 31 04:20:41 PM PDT 24
Peak memory 196260 kb
Host smart-2263e146-b60c-488a-9f49-c4c167f084b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715313316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2715313316
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.3998920322
Short name T1309
Test name
Test status
Simulation time 65292629 ps
CPU time 1.03 seconds
Started Jul 31 04:20:31 PM PDT 24
Finished Jul 31 04:20:32 PM PDT 24
Peak memory 200036 kb
Host smart-d23f916e-7f4b-4f47-b762-abef865e4ea6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998920322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.3998920322
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.3968665159
Short name T1291
Test name
Test status
Simulation time 336454548 ps
CPU time 1.26 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 197800 kb
Host smart-ecc00be7-4fb7-401f-a5d0-9b6c3a2fae91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968665159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.3968665159
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.1927427933
Short name T1283
Test name
Test status
Simulation time 74939033 ps
CPU time 1.07 seconds
Started Jul 31 04:20:34 PM PDT 24
Finished Jul 31 04:20:35 PM PDT 24
Peak memory 200288 kb
Host smart-2450dd7c-0dbf-4121-88ef-ec855e10e81f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927427933 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.1927427933
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3127967378
Short name T1224
Test name
Test status
Simulation time 16442500 ps
CPU time 0.68 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:25:06 PM PDT 24
Peak memory 195616 kb
Host smart-53a08b7a-ea4f-40e2-8497-d945f70ca071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127967378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3127967378
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.351498540
Short name T1274
Test name
Test status
Simulation time 11927846 ps
CPU time 0.55 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 194600 kb
Host smart-158d1f64-249d-49f3-b1c8-45d2963e74f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351498540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.351498540
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.4191495014
Short name T1310
Test name
Test status
Simulation time 16816315 ps
CPU time 0.66 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 196068 kb
Host smart-0ed593a8-a0e2-4976-8b1a-1963c2d03d4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191495014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.4191495014
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.2772122629
Short name T1244
Test name
Test status
Simulation time 25305865 ps
CPU time 1.27 seconds
Started Jul 31 04:21:41 PM PDT 24
Finished Jul 31 04:21:43 PM PDT 24
Peak memory 200236 kb
Host smart-2ccf37a0-e0f6-4f0a-b15f-fc11c005a591
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772122629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2772122629
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.769398887
Short name T1261
Test name
Test status
Simulation time 200346467 ps
CPU time 0.92 seconds
Started Jul 31 04:21:45 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 198912 kb
Host smart-1ee55843-bcd8-4d98-a975-782b80b0b1be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769398887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.769398887
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.2884469982
Short name T1295
Test name
Test status
Simulation time 23895214 ps
CPU time 0.73 seconds
Started Jul 31 04:24:48 PM PDT 24
Finished Jul 31 04:24:49 PM PDT 24
Peak memory 198484 kb
Host smart-5b957556-65a8-4ade-b588-2347f1f32844
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884469982 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.2884469982
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3623731841
Short name T50
Test name
Test status
Simulation time 46495278 ps
CPU time 0.56 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 194188 kb
Host smart-f0e5b365-8074-4526-b6ba-8ca3cb3920c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623731841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3623731841
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.963844304
Short name T1213
Test name
Test status
Simulation time 14675043 ps
CPU time 0.56 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:25:05 PM PDT 24
Peak memory 194600 kb
Host smart-c7333c48-bc5c-4018-9c9b-0eeccafabdd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963844304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.963844304
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.715925400
Short name T1227
Test name
Test status
Simulation time 23938861 ps
CPU time 0.6 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:24:43 PM PDT 24
Peak memory 195524 kb
Host smart-2b63907e-e385-4f62-9081-d9b682adef00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715925400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_csr
_outstanding.715925400
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2777949618
Short name T1302
Test name
Test status
Simulation time 31746886 ps
CPU time 1.69 seconds
Started Jul 31 04:21:44 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 200300 kb
Host smart-be41d7b2-7953-4c52-9e81-da21c5202c86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777949618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2777949618
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.573598407
Short name T67
Test name
Test status
Simulation time 157563641 ps
CPU time 1.29 seconds
Started Jul 31 04:25:03 PM PDT 24
Finished Jul 31 04:25:05 PM PDT 24
Peak memory 199360 kb
Host smart-4ced1e84-eed6-49ba-8ecc-126eb4e1494d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573598407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.573598407
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3546088301
Short name T45
Test name
Test status
Simulation time 417035023 ps
CPU time 0.76 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 195824 kb
Host smart-323d53cb-ae0e-44ea-b61b-1b65ff18cb3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546088301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3546088301
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.521873102
Short name T1184
Test name
Test status
Simulation time 672387826 ps
CPU time 2.31 seconds
Started Jul 31 04:20:59 PM PDT 24
Finished Jul 31 04:21:02 PM PDT 24
Peak memory 197744 kb
Host smart-10be80ae-3e22-4c35-9826-c9b666448a7f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521873102 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.521873102
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.744341774
Short name T1195
Test name
Test status
Simulation time 14886102 ps
CPU time 0.61 seconds
Started Jul 31 04:22:46 PM PDT 24
Finished Jul 31 04:22:47 PM PDT 24
Peak memory 195580 kb
Host smart-c718e22e-44a2-46a7-9b1c-017bf705bb43
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744341774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.744341774
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.1480979242
Short name T1232
Test name
Test status
Simulation time 85441221 ps
CPU time 0.72 seconds
Started Jul 31 04:19:56 PM PDT 24
Finished Jul 31 04:19:57 PM PDT 24
Peak memory 197424 kb
Host smart-17393444-7ece-4736-89c2-66cf835cccdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480979242 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.1480979242
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.3544541556
Short name T1314
Test name
Test status
Simulation time 12547524 ps
CPU time 0.63 seconds
Started Jul 31 04:23:24 PM PDT 24
Finished Jul 31 04:23:25 PM PDT 24
Peak memory 195772 kb
Host smart-18442448-3e4d-49c9-9261-4281632753bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544541556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.3544541556
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.2062407222
Short name T1219
Test name
Test status
Simulation time 12183825 ps
CPU time 0.58 seconds
Started Jul 31 04:21:59 PM PDT 24
Finished Jul 31 04:22:00 PM PDT 24
Peak memory 194664 kb
Host smart-23af4ed5-f021-4cfd-a269-cf13523b7c71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062407222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.2062407222
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.901201737
Short name T1229
Test name
Test status
Simulation time 28646067 ps
CPU time 0.7 seconds
Started Jul 31 04:24:17 PM PDT 24
Finished Jul 31 04:24:18 PM PDT 24
Peak memory 197208 kb
Host smart-6ece8cbd-ebbd-43c6-9774-9e22bbff714f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901201737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr_
outstanding.901201737
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.1753632388
Short name T1246
Test name
Test status
Simulation time 537671649 ps
CPU time 1.55 seconds
Started Jul 31 04:20:07 PM PDT 24
Finished Jul 31 04:20:09 PM PDT 24
Peak memory 199840 kb
Host smart-e6374e3a-4b3e-42bd-9d10-ab1a70194311
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753632388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1753632388
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3764843589
Short name T1226
Test name
Test status
Simulation time 47881079 ps
CPU time 0.96 seconds
Started Jul 31 04:19:53 PM PDT 24
Finished Jul 31 04:19:54 PM PDT 24
Peak memory 198996 kb
Host smart-a2c94965-4a72-44bd-8d56-b9498363e554
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764843589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3764843589
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.1460525407
Short name T1189
Test name
Test status
Simulation time 14102883 ps
CPU time 0.57 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:20:59 PM PDT 24
Peak memory 193740 kb
Host smart-0812d0d8-e842-46ad-9efb-2afc92431f99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460525407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.1460525407
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.102167748
Short name T1216
Test name
Test status
Simulation time 11033955 ps
CPU time 0.6 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194564 kb
Host smart-3cb5dbc9-3f2d-4aa4-b365-f7510f90e23f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102167748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.102167748
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.613409276
Short name T1186
Test name
Test status
Simulation time 53589224 ps
CPU time 0.64 seconds
Started Jul 31 04:21:31 PM PDT 24
Finished Jul 31 04:21:32 PM PDT 24
Peak memory 194616 kb
Host smart-eaaa1888-cbf5-4c0c-bdf9-717957463c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613409276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.613409276
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.4163037600
Short name T1201
Test name
Test status
Simulation time 66896565 ps
CPU time 0.57 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194564 kb
Host smart-d9658f0d-ea35-4414-a954-b77c0ed26f4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163037600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.4163037600
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2982863402
Short name T1308
Test name
Test status
Simulation time 14455028 ps
CPU time 0.61 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 193704 kb
Host smart-f094ed15-d6ca-422f-8863-d0d1e1915039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982863402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2982863402
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.1594968411
Short name T1204
Test name
Test status
Simulation time 13653127 ps
CPU time 0.55 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 193860 kb
Host smart-1601b524-c63e-4975-870f-831201fe4a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594968411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.1594968411
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.1436971870
Short name T1282
Test name
Test status
Simulation time 49675934 ps
CPU time 0.59 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 192760 kb
Host smart-a44ab1f1-8e58-40a4-9274-93eacf915d01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436971870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1436971870
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.3369320237
Short name T1278
Test name
Test status
Simulation time 17315323 ps
CPU time 0.56 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194580 kb
Host smart-893a4b15-45d7-4d59-bbe0-b7300a04f2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369320237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.3369320237
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.2336797220
Short name T1198
Test name
Test status
Simulation time 215856029 ps
CPU time 0.6 seconds
Started Jul 31 04:23:05 PM PDT 24
Finished Jul 31 04:23:05 PM PDT 24
Peak memory 194560 kb
Host smart-16ddba04-9604-401d-aafa-14797b613b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336797220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2336797220
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1176402280
Short name T1315
Test name
Test status
Simulation time 23523553 ps
CPU time 0.56 seconds
Started Jul 31 04:21:55 PM PDT 24
Finished Jul 31 04:21:56 PM PDT 24
Peak memory 194592 kb
Host smart-71d05c04-3ccb-4676-8c44-35d7763e65b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176402280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1176402280
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2623123309
Short name T51
Test name
Test status
Simulation time 47267769 ps
CPU time 0.74 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:42 PM PDT 24
Peak memory 196600 kb
Host smart-bbd71248-5ea3-44cc-9f15-71bf21c1ea18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623123309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2623123309
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.2354678004
Short name T1247
Test name
Test status
Simulation time 358603658 ps
CPU time 1.55 seconds
Started Jul 31 04:21:22 PM PDT 24
Finished Jul 31 04:21:23 PM PDT 24
Peak memory 198000 kb
Host smart-6ec96454-11ca-4853-921c-899af9950d10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354678004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.2354678004
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4088602642
Short name T1181
Test name
Test status
Simulation time 16814751 ps
CPU time 0.69 seconds
Started Jul 31 04:21:23 PM PDT 24
Finished Jul 31 04:21:24 PM PDT 24
Peak memory 195612 kb
Host smart-b7a17661-1183-49d3-82e4-700358b247ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088602642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4088602642
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3846009302
Short name T1311
Test name
Test status
Simulation time 84849259 ps
CPU time 1.04 seconds
Started Jul 31 04:21:45 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 200036 kb
Host smart-f8a4e25f-867a-4a65-8979-aa3206a0d1a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846009302 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3846009302
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.4129452153
Short name T1252
Test name
Test status
Simulation time 12407343 ps
CPU time 0.56 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 195544 kb
Host smart-91a24591-6411-4878-aae2-246bfce0fee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129452153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.4129452153
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.228539715
Short name T1259
Test name
Test status
Simulation time 53859532 ps
CPU time 0.58 seconds
Started Jul 31 04:22:05 PM PDT 24
Finished Jul 31 04:22:06 PM PDT 24
Peak memory 194568 kb
Host smart-68226cc4-7974-4938-a34d-8d437f7df8d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228539715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.228539715
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.526995971
Short name T57
Test name
Test status
Simulation time 37677167 ps
CPU time 0.67 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 195800 kb
Host smart-da112bd8-89b0-4985-a734-58c4112029b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526995971 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.526995971
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.1811963286
Short name T1248
Test name
Test status
Simulation time 274511265 ps
CPU time 1.76 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 199400 kb
Host smart-da2a3ae5-d338-4c3a-b2dd-8d69c7ca6076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811963286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.1811963286
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3871753775
Short name T60
Test name
Test status
Simulation time 40235462 ps
CPU time 0.91 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:26:17 PM PDT 24
Peak memory 198956 kb
Host smart-a7de7475-3380-4c4d-ae13-6c5be80f8a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871753775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3871753775
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.4121991555
Short name T1258
Test name
Test status
Simulation time 38677241 ps
CPU time 0.53 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 193852 kb
Host smart-1d8d6cc8-99c9-4359-9a5e-48d4917cc8b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121991555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.4121991555
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3580420681
Short name T1179
Test name
Test status
Simulation time 12871013 ps
CPU time 0.56 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194368 kb
Host smart-4a28ecf9-98fb-406b-96c1-0af1fea9634a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580420681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3580420681
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.2983976455
Short name T1285
Test name
Test status
Simulation time 16308629 ps
CPU time 0.6 seconds
Started Jul 31 04:21:54 PM PDT 24
Finished Jul 31 04:21:55 PM PDT 24
Peak memory 194612 kb
Host smart-07276ad1-da62-4bf9-8ad9-a261664c563d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983976455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.2983976455
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.981926198
Short name T1223
Test name
Test status
Simulation time 12602657 ps
CPU time 0.59 seconds
Started Jul 31 04:20:53 PM PDT 24
Finished Jul 31 04:20:54 PM PDT 24
Peak memory 194632 kb
Host smart-2949a660-e162-4770-bad4-6d0826c80c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981926198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.981926198
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.3589633289
Short name T1290
Test name
Test status
Simulation time 18336681 ps
CPU time 0.56 seconds
Started Jul 31 04:20:41 PM PDT 24
Finished Jul 31 04:20:41 PM PDT 24
Peak memory 194620 kb
Host smart-830b2caa-77da-4904-8005-0b63d14ccce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589633289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.3589633289
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1703371082
Short name T1187
Test name
Test status
Simulation time 15515282 ps
CPU time 0.6 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 04:21:40 PM PDT 24
Peak memory 194576 kb
Host smart-d11a20f8-6810-410b-9f48-beb2bafc1c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703371082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1703371082
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.3370425365
Short name T1239
Test name
Test status
Simulation time 12192236 ps
CPU time 0.56 seconds
Started Jul 31 04:20:53 PM PDT 24
Finished Jul 31 04:20:53 PM PDT 24
Peak memory 194560 kb
Host smart-c0ca7378-7d6d-48d0-bd18-3412d6e64811
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370425365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.3370425365
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.4240293323
Short name T1182
Test name
Test status
Simulation time 12861469 ps
CPU time 0.56 seconds
Started Jul 31 04:24:39 PM PDT 24
Finished Jul 31 04:24:40 PM PDT 24
Peak memory 193352 kb
Host smart-e7b57320-c674-45a0-83dd-6cc49a893dda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240293323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.4240293323
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1423025901
Short name T1245
Test name
Test status
Simulation time 12428839 ps
CPU time 0.55 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194528 kb
Host smart-6101bd0a-a8fe-484a-a2aa-9ff14508460a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423025901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1423025901
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3352120966
Short name T1180
Test name
Test status
Simulation time 43260963 ps
CPU time 0.55 seconds
Started Jul 31 04:21:46 PM PDT 24
Finished Jul 31 04:21:47 PM PDT 24
Peak memory 194552 kb
Host smart-92ef94cd-98b3-47e1-a715-08d78e51cba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352120966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3352120966
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2818575423
Short name T1250
Test name
Test status
Simulation time 153434676 ps
CPU time 0.77 seconds
Started Jul 31 04:20:01 PM PDT 24
Finished Jul 31 04:20:02 PM PDT 24
Peak memory 196156 kb
Host smart-aa3c74a9-989c-4885-88a9-44a445fff44e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818575423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2818575423
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.941214612
Short name T1286
Test name
Test status
Simulation time 255018824 ps
CPU time 2.48 seconds
Started Jul 31 04:20:11 PM PDT 24
Finished Jul 31 04:20:13 PM PDT 24
Peak memory 197928 kb
Host smart-a108d00d-b367-451f-91cd-b5a43608fb65
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941214612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.941214612
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3096470711
Short name T1214
Test name
Test status
Simulation time 1033772193 ps
CPU time 1.86 seconds
Started Jul 31 04:20:04 PM PDT 24
Finished Jul 31 04:20:06 PM PDT 24
Peak memory 195272 kb
Host smart-a91d8f70-ccc5-4f06-b1a5-1da945438244
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096470711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3096470711
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.370971541
Short name T1273
Test name
Test status
Simulation time 96108542 ps
CPU time 0.77 seconds
Started Jul 31 04:22:07 PM PDT 24
Finished Jul 31 04:22:08 PM PDT 24
Peak memory 199160 kb
Host smart-101b0210-8a70-4f82-8d40-01fc81f1535e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370971541 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.370971541
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.2388085930
Short name T46
Test name
Test status
Simulation time 50477711 ps
CPU time 0.64 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 195608 kb
Host smart-b932a040-bf28-4429-8ca2-4ecd97a7e004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388085930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2388085930
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.4021479188
Short name T1206
Test name
Test status
Simulation time 59778380 ps
CPU time 0.55 seconds
Started Jul 31 04:22:00 PM PDT 24
Finished Jul 31 04:22:00 PM PDT 24
Peak memory 194552 kb
Host smart-b0e843dc-a152-4b1b-9efa-90b88e5494ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021479188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.4021479188
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.4092528709
Short name T1260
Test name
Test status
Simulation time 52310286 ps
CPU time 0.76 seconds
Started Jul 31 04:19:55 PM PDT 24
Finished Jul 31 04:19:56 PM PDT 24
Peak memory 196744 kb
Host smart-994e13f8-57c2-4c4d-a2ab-5b119020205f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092528709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.4092528709
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3741912588
Short name T1287
Test name
Test status
Simulation time 39516733 ps
CPU time 2.1 seconds
Started Jul 31 04:22:05 PM PDT 24
Finished Jul 31 04:22:08 PM PDT 24
Peak memory 200236 kb
Host smart-18b8ce01-9dbd-485c-b70a-4f79f1e70dfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741912588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3741912588
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.3471851022
Short name T1303
Test name
Test status
Simulation time 11369368 ps
CPU time 0.55 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194596 kb
Host smart-2ba83edf-6d07-4067-90d6-086633ecfce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471851022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3471851022
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.3913518076
Short name T1230
Test name
Test status
Simulation time 40997207 ps
CPU time 0.58 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194284 kb
Host smart-033018b6-cd13-4570-b0dc-5d41a5e97784
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913518076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3913518076
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.623554148
Short name T1257
Test name
Test status
Simulation time 57469995 ps
CPU time 0.61 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:22:35 PM PDT 24
Peak memory 194636 kb
Host smart-48920199-5fca-48dd-9290-9dc1772cf30c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623554148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.623554148
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.45308187
Short name T1192
Test name
Test status
Simulation time 20422336 ps
CPU time 0.55 seconds
Started Jul 31 04:23:30 PM PDT 24
Finished Jul 31 04:23:30 PM PDT 24
Peak memory 194624 kb
Host smart-89992c12-df67-4e6b-8b98-10126f25dc3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45308187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.45308187
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.1241995778
Short name T1306
Test name
Test status
Simulation time 14364069 ps
CPU time 0.57 seconds
Started Jul 31 04:24:39 PM PDT 24
Finished Jul 31 04:24:40 PM PDT 24
Peak memory 193316 kb
Host smart-508aa2a2-e0c9-4d4f-a6d5-d804bd570e44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241995778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1241995778
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2539496318
Short name T1177
Test name
Test status
Simulation time 14618140 ps
CPU time 0.58 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 04:21:40 PM PDT 24
Peak memory 194576 kb
Host smart-b9311abd-9b27-40e0-8685-a0504fb0b22f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539496318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2539496318
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.2266079196
Short name T1209
Test name
Test status
Simulation time 20013457 ps
CPU time 0.52 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194664 kb
Host smart-f54d7a63-c02d-485a-a3f2-a57695c63ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266079196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.2266079196
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.9642837
Short name T1220
Test name
Test status
Simulation time 25636965 ps
CPU time 0.59 seconds
Started Jul 31 04:21:22 PM PDT 24
Finished Jul 31 04:21:23 PM PDT 24
Peak memory 194588 kb
Host smart-e51ea493-83e6-4c0c-a0ab-212a408a17a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9642837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.9642837
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2840743365
Short name T1202
Test name
Test status
Simulation time 17874099 ps
CPU time 0.61 seconds
Started Jul 31 04:21:08 PM PDT 24
Finished Jul 31 04:21:09 PM PDT 24
Peak memory 194624 kb
Host smart-5b4a2c9d-87a3-4889-a896-f2d0eeefd788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840743365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2840743365
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3692987585
Short name T1253
Test name
Test status
Simulation time 16725478 ps
CPU time 0.6 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 194664 kb
Host smart-7cf734cd-8c63-4b6b-b521-c673f6bcac6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692987585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3692987585
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.389311979
Short name T1294
Test name
Test status
Simulation time 28447560 ps
CPU time 1.25 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 199740 kb
Host smart-79dc50c5-1ff5-4b13-8b11-c3bdaa732d74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389311979 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.389311979
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1472265411
Short name T1265
Test name
Test status
Simulation time 32341112 ps
CPU time 0.63 seconds
Started Jul 31 04:21:20 PM PDT 24
Finished Jul 31 04:21:21 PM PDT 24
Peak memory 195780 kb
Host smart-846186fb-7a84-40a6-afe7-0a20067a2892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472265411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1472265411
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.3667526828
Short name T1222
Test name
Test status
Simulation time 32599117 ps
CPU time 0.57 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 194440 kb
Host smart-cc59fe6d-167b-4882-8f5b-404165b146ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667526828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.3667526828
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.391381641
Short name T56
Test name
Test status
Simulation time 17549072 ps
CPU time 0.64 seconds
Started Jul 31 04:21:01 PM PDT 24
Finished Jul 31 04:21:02 PM PDT 24
Peak memory 195696 kb
Host smart-1e043284-9246-48ca-8930-07f6b879cb26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391381641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr_
outstanding.391381641
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.2982530175
Short name T1188
Test name
Test status
Simulation time 375778546 ps
CPU time 1.82 seconds
Started Jul 31 04:21:54 PM PDT 24
Finished Jul 31 04:21:56 PM PDT 24
Peak memory 200292 kb
Host smart-301434ba-5be7-4bce-9a53-f711a86e6d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982530175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.2982530175
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.3092956253
Short name T1299
Test name
Test status
Simulation time 77235147 ps
CPU time 1.18 seconds
Started Jul 31 04:23:25 PM PDT 24
Finished Jul 31 04:23:26 PM PDT 24
Peak memory 199428 kb
Host smart-e36bdd50-22b8-4fb4-806e-8b8a61a807ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092956253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.3092956253
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1665350260
Short name T1243
Test name
Test status
Simulation time 104119467 ps
CPU time 0.83 seconds
Started Jul 31 04:21:46 PM PDT 24
Finished Jul 31 04:21:47 PM PDT 24
Peak memory 200380 kb
Host smart-44312dc3-14b9-41a4-9924-dab3ea00e5cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665350260 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1665350260
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.4177795696
Short name T49
Test name
Test status
Simulation time 22197455 ps
CPU time 0.68 seconds
Started Jul 31 04:21:52 PM PDT 24
Finished Jul 31 04:21:53 PM PDT 24
Peak memory 195824 kb
Host smart-38b8ad3c-9fab-4509-8cc3-5048a0f109c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177795696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.4177795696
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.244521772
Short name T1297
Test name
Test status
Simulation time 27897443 ps
CPU time 0.56 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 193188 kb
Host smart-f637c76b-6576-4a90-9195-42c8cc4dd846
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244521772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.244521772
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1948010416
Short name T1218
Test name
Test status
Simulation time 114342764 ps
CPU time 0.79 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 195748 kb
Host smart-7bbb8ac0-28c0-4a19-9741-4ce3b632558a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948010416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1948010416
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2408762915
Short name T1221
Test name
Test status
Simulation time 180451502 ps
CPU time 2.23 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:25:00 PM PDT 24
Peak memory 200092 kb
Host smart-361ee754-e662-4cdd-a348-1ecdc93a005a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408762915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2408762915
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.914701928
Short name T1271
Test name
Test status
Simulation time 175500243 ps
CPU time 0.92 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 197368 kb
Host smart-54f9e20b-1807-443f-9ba3-4752b1ac05d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914701928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.914701928
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.883540878
Short name T1215
Test name
Test status
Simulation time 78786390 ps
CPU time 0.71 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:24:21 PM PDT 24
Peak memory 197952 kb
Host smart-59f5b2ad-6561-430f-8d51-defcc9a1949b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883540878 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.883540878
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1180268500
Short name T1193
Test name
Test status
Simulation time 49371463 ps
CPU time 0.61 seconds
Started Jul 31 04:20:52 PM PDT 24
Finished Jul 31 04:20:52 PM PDT 24
Peak memory 195304 kb
Host smart-7de81ef7-288d-4242-abfa-68146421450c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180268500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1180268500
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.508572513
Short name T1234
Test name
Test status
Simulation time 37412525 ps
CPU time 0.59 seconds
Started Jul 31 04:20:13 PM PDT 24
Finished Jul 31 04:20:13 PM PDT 24
Peak memory 194648 kb
Host smart-c99e3f88-a7c3-47aa-a675-c6a89e123476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508572513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.508572513
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.500626912
Short name T1210
Test name
Test status
Simulation time 44481649 ps
CPU time 0.67 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:22:35 PM PDT 24
Peak memory 197024 kb
Host smart-23338f29-ac99-4da7-9930-d34a52f999b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500626912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr_
outstanding.500626912
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.1265630717
Short name T1208
Test name
Test status
Simulation time 105394321 ps
CPU time 2.17 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:22:36 PM PDT 24
Peak memory 200264 kb
Host smart-ab9cb39b-9a37-4205-87e2-f35d536b0226
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265630717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.1265630717
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.886229587
Short name T1272
Test name
Test status
Simulation time 90758731 ps
CPU time 1.37 seconds
Started Jul 31 04:22:55 PM PDT 24
Finished Jul 31 04:22:57 PM PDT 24
Peak memory 199680 kb
Host smart-b56adf47-8953-44d3-b0da-d98920069ac2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886229587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.886229587
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.4093972592
Short name T1254
Test name
Test status
Simulation time 61703081 ps
CPU time 0.85 seconds
Started Jul 31 04:21:22 PM PDT 24
Finished Jul 31 04:21:23 PM PDT 24
Peak memory 200048 kb
Host smart-b03c3ffe-d7ba-49cb-8cd1-9b167a6d7abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093972592 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.4093972592
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1552617810
Short name T1275
Test name
Test status
Simulation time 24159916 ps
CPU time 0.67 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 194020 kb
Host smart-fb848ecc-a64d-49cb-8fbb-cb69a96e7a26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552617810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1552617810
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2926354840
Short name T1233
Test name
Test status
Simulation time 51824844 ps
CPU time 0.59 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 193800 kb
Host smart-9eef688e-690e-4a60-88b2-05c4fdf9bf5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926354840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2926354840
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1771517640
Short name T1281
Test name
Test status
Simulation time 40302711 ps
CPU time 0.67 seconds
Started Jul 31 04:22:35 PM PDT 24
Finished Jul 31 04:22:35 PM PDT 24
Peak memory 196784 kb
Host smart-ee53d2ca-0ad0-4ade-8c29-07eb12bd5b45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771517640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1771517640
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.1802435811
Short name T1279
Test name
Test status
Simulation time 353591899 ps
CPU time 2.45 seconds
Started Jul 31 04:21:52 PM PDT 24
Finished Jul 31 04:21:54 PM PDT 24
Peak memory 200288 kb
Host smart-823ff213-a0d8-4bef-9ca0-a43c065607bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802435811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.1802435811
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3063606423
Short name T1289
Test name
Test status
Simulation time 520219142 ps
CPU time 1.33 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:23:32 PM PDT 24
Peak memory 199668 kb
Host smart-5a6b8311-cf91-49a0-98fe-d4893d83ae72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063606423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3063606423
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.181701223
Short name T1235
Test name
Test status
Simulation time 119853963 ps
CPU time 0.88 seconds
Started Jul 31 04:24:38 PM PDT 24
Finished Jul 31 04:24:39 PM PDT 24
Peak memory 200040 kb
Host smart-47289a28-217e-4584-a51b-10887997b38d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181701223 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.181701223
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.208250599
Short name T53
Test name
Test status
Simulation time 44098799 ps
CPU time 0.59 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 194424 kb
Host smart-720527e0-5707-4d23-a1ec-ec5218ef468d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208250599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.208250599
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.1868335763
Short name T1197
Test name
Test status
Simulation time 30718645 ps
CPU time 0.56 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 194488 kb
Host smart-e8d12af7-e735-408c-86ba-8e6e444a60ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868335763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.1868335763
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1304259322
Short name T58
Test name
Test status
Simulation time 26901165 ps
CPU time 0.64 seconds
Started Jul 31 04:21:10 PM PDT 24
Finished Jul 31 04:21:11 PM PDT 24
Peak memory 195712 kb
Host smart-17137748-262e-4295-bf99-a813bcb7b456
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304259322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1304259322
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.1760473573
Short name T1298
Test name
Test status
Simulation time 501204519 ps
CPU time 1.53 seconds
Started Jul 31 04:21:09 PM PDT 24
Finished Jul 31 04:21:11 PM PDT 24
Peak memory 200256 kb
Host smart-c0e921e3-6790-4f15-9cd1-a11da6c033dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760473573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.1760473573
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.1031228282
Short name T66
Test name
Test status
Simulation time 45054851 ps
CPU time 0.88 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:24:22 PM PDT 24
Peak memory 198412 kb
Host smart-85d6c5f6-7ef9-4201-b765-f169704b1fff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031228282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.1031228282
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.2253744579
Short name T1116
Test name
Test status
Simulation time 21905070 ps
CPU time 0.53 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 195212 kb
Host smart-6757f1bc-880c-41c0-82f0-6efc563deaac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253744579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2253744579
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.2278316233
Short name T122
Test name
Test status
Simulation time 49641124639 ps
CPU time 20.27 seconds
Started Jul 31 04:21:50 PM PDT 24
Finished Jul 31 04:22:10 PM PDT 24
Peak memory 199720 kb
Host smart-fbba99eb-a2b7-4de1-b1b0-f553173ffecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278316233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.2278316233
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.1087457977
Short name T400
Test name
Test status
Simulation time 21609728141 ps
CPU time 42.07 seconds
Started Jul 31 04:20:56 PM PDT 24
Finished Jul 31 04:21:38 PM PDT 24
Peak memory 199744 kb
Host smart-66a932e9-0b51-42ad-ab40-23ff1f3d164d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087457977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.1087457977
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.485960163
Short name T1129
Test name
Test status
Simulation time 540227729682 ps
CPU time 258.21 seconds
Started Jul 31 04:20:57 PM PDT 24
Finished Jul 31 04:25:16 PM PDT 24
Peak memory 199000 kb
Host smart-ec7c3d88-c1c1-4512-8e96-766cd8468357
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485960163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.485960163
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1134413583
Short name T430
Test name
Test status
Simulation time 155296887515 ps
CPU time 446.85 seconds
Started Jul 31 04:21:23 PM PDT 24
Finished Jul 31 04:28:50 PM PDT 24
Peak memory 199744 kb
Host smart-5a3d4e41-114d-442c-a7b0-2058df7ca68e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1134413583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1134413583
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.1082095433
Short name T533
Test name
Test status
Simulation time 2759073649 ps
CPU time 1.53 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:25:37 PM PDT 24
Peak memory 198028 kb
Host smart-ed602b92-a1ef-4578-9d77-2a6e3994907d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082095433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.1082095433
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.856159051
Short name T951
Test name
Test status
Simulation time 86274941818 ps
CPU time 37.75 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:25:35 PM PDT 24
Peak memory 199064 kb
Host smart-cc062732-57bf-41f9-8d3f-cddcb29c859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856159051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.856159051
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.2176746707
Short name T1024
Test name
Test status
Simulation time 16252624537 ps
CPU time 889.39 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:38:37 PM PDT 24
Peak memory 199748 kb
Host smart-c173bbba-d43b-4abd-ad72-c6256a05865f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176746707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2176746707
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2200364288
Short name T1107
Test name
Test status
Simulation time 4550905818 ps
CPU time 8.97 seconds
Started Jul 31 04:23:47 PM PDT 24
Finished Jul 31 04:23:56 PM PDT 24
Peak memory 198464 kb
Host smart-9addc48f-7367-471b-a357-38e7bf3b8685
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2200364288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2200364288
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2658446402
Short name T262
Test name
Test status
Simulation time 70636213883 ps
CPU time 10.82 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:21:09 PM PDT 24
Peak memory 199676 kb
Host smart-650e8f80-38ff-401c-bc13-a60e6afae59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658446402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2658446402
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.1391053172
Short name T1166
Test name
Test status
Simulation time 47219017284 ps
CPU time 71.2 seconds
Started Jul 31 04:23:35 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 195328 kb
Host smart-784337c4-0d74-4ebc-acf2-becc755c786c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391053172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.1391053172
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.417628711
Short name T20
Test name
Test status
Simulation time 59458784 ps
CPU time 0.87 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:24:22 PM PDT 24
Peak memory 218044 kb
Host smart-ae921da1-3840-48bd-a667-569af616647b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417628711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.417628711
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.2290127823
Short name T1106
Test name
Test status
Simulation time 5478823170 ps
CPU time 6.3 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:29 PM PDT 24
Peak memory 199652 kb
Host smart-500e1922-9ae8-4757-a5c6-934994831e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290127823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2290127823
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.624582248
Short name T1174
Test name
Test status
Simulation time 194243499604 ps
CPU time 1292.56 seconds
Started Jul 31 04:23:34 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 198212 kb
Host smart-ac8d6eb6-f43b-496a-99c1-a110ebca2c5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624582248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.624582248
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.341339742
Short name T85
Test name
Test status
Simulation time 133442303980 ps
CPU time 506.48 seconds
Started Jul 31 04:23:49 PM PDT 24
Finished Jul 31 04:32:16 PM PDT 24
Peak memory 211896 kb
Host smart-6e3b1039-6dbb-4029-a887-b009cd070a0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341339742 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.341339742
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.931121813
Short name T353
Test name
Test status
Simulation time 1011125823 ps
CPU time 2.91 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 198608 kb
Host smart-532d32d0-eee5-45e4-8883-b0a44d2d54f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931121813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.931121813
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.76580983
Short name T251
Test name
Test status
Simulation time 56482408152 ps
CPU time 38.13 seconds
Started Jul 31 04:21:11 PM PDT 24
Finished Jul 31 04:21:49 PM PDT 24
Peak memory 200124 kb
Host smart-93f1920c-954f-44d6-9da0-524005cfcf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76580983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.76580983
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.1372227105
Short name T332
Test name
Test status
Simulation time 10723294 ps
CPU time 0.53 seconds
Started Jul 31 04:21:46 PM PDT 24
Finished Jul 31 04:21:46 PM PDT 24
Peak memory 194024 kb
Host smart-cd0bde56-cc47-44f0-bee7-5350cca826a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372227105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.1372227105
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.117318560
Short name T669
Test name
Test status
Simulation time 15461713145 ps
CPU time 14.51 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:53 PM PDT 24
Peak memory 199672 kb
Host smart-c6ba9778-ec7d-493b-9890-e3945fd49cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117318560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.117318560
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.3416927664
Short name T521
Test name
Test status
Simulation time 180879047916 ps
CPU time 58.22 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 198972 kb
Host smart-dbe73bef-7974-409f-b5e9-22fc18dd12fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416927664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.3416927664
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.685960832
Short name T689
Test name
Test status
Simulation time 23861586898 ps
CPU time 21.41 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:59 PM PDT 24
Peak memory 199572 kb
Host smart-a0490667-d5c6-4b34-b04d-8fb0bafb8264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685960832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.685960832
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1559803307
Short name T638
Test name
Test status
Simulation time 29818589350 ps
CPU time 45.61 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 198344 kb
Host smart-42b50dca-1841-4a10-9fd9-82a0c4451b4c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559803307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1559803307
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.2319618867
Short name T372
Test name
Test status
Simulation time 184828413223 ps
CPU time 1007.76 seconds
Started Jul 31 04:22:03 PM PDT 24
Finished Jul 31 04:38:51 PM PDT 24
Peak memory 199760 kb
Host smart-aa4e2f26-faed-484c-8996-604a09cc3738
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2319618867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.2319618867
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.1233763295
Short name T539
Test name
Test status
Simulation time 7708146953 ps
CPU time 6.14 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:38 PM PDT 24
Peak memory 197332 kb
Host smart-4cb585d0-8ee8-4778-857f-2b15f1f63ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233763295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.1233763295
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.1696769213
Short name T567
Test name
Test status
Simulation time 93545955426 ps
CPU time 158.62 seconds
Started Jul 31 04:25:07 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 208416 kb
Host smart-9c13c602-aafd-4a1f-ba84-afd7d8d7c9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696769213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.1696769213
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2388044555
Short name T10
Test name
Test status
Simulation time 30408682856 ps
CPU time 875.55 seconds
Started Jul 31 04:20:54 PM PDT 24
Finished Jul 31 04:35:29 PM PDT 24
Peak memory 199644 kb
Host smart-b6441c98-3594-4dde-99b0-89af1dbb0787
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2388044555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2388044555
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3856656658
Short name T388
Test name
Test status
Simulation time 2194350672 ps
CPU time 3.69 seconds
Started Jul 31 04:22:50 PM PDT 24
Finished Jul 31 04:22:53 PM PDT 24
Peak memory 198388 kb
Host smart-e8d8b287-06ac-45f7-a719-2bbb2e5ffbc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3856656658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3856656658
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2966789307
Short name T466
Test name
Test status
Simulation time 40229373569 ps
CPU time 64.72 seconds
Started Jul 31 04:20:58 PM PDT 24
Finished Jul 31 04:22:03 PM PDT 24
Peak memory 198892 kb
Host smart-282ca0bb-663f-4a57-a56f-6ff04f24b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966789307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2966789307
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.3300930290
Short name T1130
Test name
Test status
Simulation time 4779015305 ps
CPU time 4.2 seconds
Started Jul 31 04:20:36 PM PDT 24
Finished Jul 31 04:20:41 PM PDT 24
Peak memory 196632 kb
Host smart-a4d48917-162b-4870-aef6-83fb160b33db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300930290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.3300930290
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_smoke.2309690112
Short name T818
Test name
Test status
Simulation time 150512129 ps
CPU time 0.7 seconds
Started Jul 31 04:25:01 PM PDT 24
Finished Jul 31 04:25:02 PM PDT 24
Peak memory 196860 kb
Host smart-68497778-5dc8-46b8-92f6-d43195b555ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309690112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2309690112
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all.717639360
Short name T795
Test name
Test status
Simulation time 215448805699 ps
CPU time 1245.91 seconds
Started Jul 31 04:21:25 PM PDT 24
Finished Jul 31 04:42:11 PM PDT 24
Peak memory 199760 kb
Host smart-3dbcec58-cf68-4d70-8928-62267c051417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717639360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.717639360
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.3912501006
Short name T362
Test name
Test status
Simulation time 964413345 ps
CPU time 3.85 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 198328 kb
Host smart-46dae36f-fbcf-40ae-8e34-1b20f5a59ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912501006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.3912501006
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.196568262
Short name T28
Test name
Test status
Simulation time 39906278114 ps
CPU time 16.42 seconds
Started Jul 31 04:21:14 PM PDT 24
Finished Jul 31 04:21:30 PM PDT 24
Peak memory 199676 kb
Host smart-beca8e92-9be2-47a2-b8f8-e2d9c8c03a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196568262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.196568262
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.914765183
Short name T1151
Test name
Test status
Simulation time 20833926 ps
CPU time 0.53 seconds
Started Jul 31 04:24:19 PM PDT 24
Finished Jul 31 04:24:19 PM PDT 24
Peak memory 194580 kb
Host smart-2f4eb010-18ff-4793-92cd-3879c7b221fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914765183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.914765183
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2365250448
Short name T810
Test name
Test status
Simulation time 234838767420 ps
CPU time 416.18 seconds
Started Jul 31 04:22:43 PM PDT 24
Finished Jul 31 04:29:39 PM PDT 24
Peak memory 199700 kb
Host smart-e09c52be-6636-4d27-8167-d6293a52ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365250448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2365250448
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.342824586
Short name T955
Test name
Test status
Simulation time 189213821716 ps
CPU time 45.03 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:25:27 PM PDT 24
Peak memory 198888 kb
Host smart-b1615eee-7c7a-42d9-b62d-30cbbd4812d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342824586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.342824586
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.3166320716
Short name T411
Test name
Test status
Simulation time 213450295062 ps
CPU time 53.93 seconds
Started Jul 31 04:22:51 PM PDT 24
Finished Jul 31 04:23:45 PM PDT 24
Peak memory 199808 kb
Host smart-6f53f1b4-3eed-4819-a5d1-aa802c29da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166320716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3166320716
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.769343970
Short name T800
Test name
Test status
Simulation time 20683648987 ps
CPU time 35.12 seconds
Started Jul 31 04:22:48 PM PDT 24
Finished Jul 31 04:23:23 PM PDT 24
Peak memory 199676 kb
Host smart-4880ff72-6a2b-4b0c-87fe-81870968b8a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769343970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.769343970
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.716752144
Short name T1093
Test name
Test status
Simulation time 131105157861 ps
CPU time 777.35 seconds
Started Jul 31 04:24:29 PM PDT 24
Finished Jul 31 04:37:27 PM PDT 24
Peak memory 199732 kb
Host smart-6aee0ab9-0033-4e40-a857-ba37608e770b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716752144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.716752144
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2999656851
Short name T688
Test name
Test status
Simulation time 8845447398 ps
CPU time 18.59 seconds
Started Jul 31 04:24:34 PM PDT 24
Finished Jul 31 04:24:52 PM PDT 24
Peak memory 199728 kb
Host smart-49f7ba54-1a18-4275-86e3-aaea17b6d424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999656851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2999656851
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1724352278
Short name T288
Test name
Test status
Simulation time 50054902503 ps
CPU time 39.33 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:26:57 PM PDT 24
Peak memory 199620 kb
Host smart-909ebd37-6cdb-4188-b796-64bfe6db142f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724352278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1724352278
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.1174428353
Short name T895
Test name
Test status
Simulation time 10969195993 ps
CPU time 636.48 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:35:19 PM PDT 24
Peak memory 199608 kb
Host smart-f3af423a-8f42-4d9e-95da-f939889c3cb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1174428353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.1174428353
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.4253203228
Short name T422
Test name
Test status
Simulation time 6958151069 ps
CPU time 5.78 seconds
Started Jul 31 04:24:34 PM PDT 24
Finished Jul 31 04:24:40 PM PDT 24
Peak memory 198468 kb
Host smart-eea3493b-a900-4a6e-94ba-a3f935258753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4253203228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.4253203228
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.1149682736
Short name T9
Test name
Test status
Simulation time 45225300938 ps
CPU time 35.19 seconds
Started Jul 31 04:23:20 PM PDT 24
Finished Jul 31 04:23:55 PM PDT 24
Peak memory 198856 kb
Host smart-f3da09c4-e3ab-4c9b-aa81-98d63299e0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149682736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.1149682736
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3785464948
Short name T902
Test name
Test status
Simulation time 4850273356 ps
CPU time 8.85 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 196072 kb
Host smart-9a3b65fa-5522-43ef-be95-d4e81ae3ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785464948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3785464948
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.431810572
Short name T777
Test name
Test status
Simulation time 5384964654 ps
CPU time 15.63 seconds
Started Jul 31 04:23:56 PM PDT 24
Finished Jul 31 04:24:12 PM PDT 24
Peak memory 199748 kb
Host smart-bef17d3e-ed30-4cda-862b-1c23dc4e95b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431810572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.431810572
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2871855913
Short name T560
Test name
Test status
Simulation time 221263633430 ps
CPU time 855.46 seconds
Started Jul 31 04:25:19 PM PDT 24
Finished Jul 31 04:39:34 PM PDT 24
Peak memory 199708 kb
Host smart-ca5b2bdc-90bf-4f8c-a75b-ac246a169b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871855913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2871855913
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4041804884
Short name T881
Test name
Test status
Simulation time 83058775613 ps
CPU time 1906.46 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:56:42 PM PDT 24
Peak memory 216432 kb
Host smart-5663d595-1399-4057-81ba-c806d76c29f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041804884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4041804884
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.2091200209
Short name T340
Test name
Test status
Simulation time 666836524 ps
CPU time 1.87 seconds
Started Jul 31 04:22:50 PM PDT 24
Finished Jul 31 04:22:52 PM PDT 24
Peak memory 197976 kb
Host smart-08463b9d-36d7-4acb-9c41-ac91199954c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091200209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.2091200209
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.4077480956
Short name T478
Test name
Test status
Simulation time 33104550131 ps
CPU time 52.7 seconds
Started Jul 31 04:22:43 PM PDT 24
Finished Jul 31 04:23:36 PM PDT 24
Peak memory 199772 kb
Host smart-555a0c8b-0280-4f51-9137-ef3d76daaad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077480956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.4077480956
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.1387280064
Short name T416
Test name
Test status
Simulation time 88522923377 ps
CPU time 37.8 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199716 kb
Host smart-430182da-f162-4e49-a6b5-fe687841eb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387280064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1387280064
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.197206648
Short name T815
Test name
Test status
Simulation time 193705314681 ps
CPU time 256.64 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:31:06 PM PDT 24
Peak memory 199744 kb
Host smart-26384793-300c-49b4-b34d-bbe47b9a3146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197206648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.197206648
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.3875929380
Short name T742
Test name
Test status
Simulation time 63962175335 ps
CPU time 27.33 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 199484 kb
Host smart-4d3c8648-2388-4336-9b82-c8b5115b0ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875929380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.3875929380
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.1029216944
Short name T545
Test name
Test status
Simulation time 48459836635 ps
CPU time 84.67 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:28:07 PM PDT 24
Peak memory 199704 kb
Host smart-af1d8e4d-9bd0-4215-ab91-a13df4d906bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029216944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.1029216944
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1277677686
Short name T704
Test name
Test status
Simulation time 20258467924 ps
CPU time 12.41 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:27:02 PM PDT 24
Peak memory 199636 kb
Host smart-c3f53202-59ae-42dc-979f-deead00c8c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277677686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1277677686
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.800705893
Short name T865
Test name
Test status
Simulation time 23916639601 ps
CPU time 37.1 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:21 PM PDT 24
Peak memory 199716 kb
Host smart-9c934564-11c3-422a-9c1f-1eab1681258a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800705893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.800705893
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.4127447424
Short name T1040
Test name
Test status
Simulation time 20088165759 ps
CPU time 19.03 seconds
Started Jul 31 04:26:46 PM PDT 24
Finished Jul 31 04:27:05 PM PDT 24
Peak memory 199748 kb
Host smart-df58bdff-aa9a-4ca3-99c9-569e96081edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127447424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.4127447424
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1603155605
Short name T137
Test name
Test status
Simulation time 154049221023 ps
CPU time 368.76 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:32:56 PM PDT 24
Peak memory 199652 kb
Host smart-12869df5-c068-4111-8469-92fd487b2bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603155605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1603155605
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3545620286
Short name T886
Test name
Test status
Simulation time 37848827 ps
CPU time 0.57 seconds
Started Jul 31 04:23:13 PM PDT 24
Finished Jul 31 04:23:14 PM PDT 24
Peak memory 195456 kb
Host smart-669ea882-52c0-4dc9-b4a5-80ccdb90999c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545620286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3545620286
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.145317991
Short name T144
Test name
Test status
Simulation time 64797133889 ps
CPU time 27.38 seconds
Started Jul 31 04:22:54 PM PDT 24
Finished Jul 31 04:23:22 PM PDT 24
Peak memory 199824 kb
Host smart-38abd8b9-c526-4e16-919e-9ab4fc2be6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145317991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.145317991
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1753004545
Short name T762
Test name
Test status
Simulation time 216538957546 ps
CPU time 86.82 seconds
Started Jul 31 04:25:03 PM PDT 24
Finished Jul 31 04:26:30 PM PDT 24
Peak memory 199808 kb
Host smart-d6ce6b7c-bed7-4aa7-ba43-ecf12324f998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753004545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1753004545
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.843616551
Short name T444
Test name
Test status
Simulation time 59362791390 ps
CPU time 94.04 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:26:31 PM PDT 24
Peak memory 197932 kb
Host smart-7131cdbb-a04c-461e-bbf5-c904d58c76de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843616551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.843616551
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1440584923
Short name T859
Test name
Test status
Simulation time 3276857464 ps
CPU time 5.23 seconds
Started Jul 31 04:23:01 PM PDT 24
Finished Jul 31 04:23:07 PM PDT 24
Peak memory 196656 kb
Host smart-47168084-6c9b-4141-abcd-dd2975c1953c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440584923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1440584923
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2170944809
Short name T883
Test name
Test status
Simulation time 320270369005 ps
CPU time 160.76 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:27:01 PM PDT 24
Peak memory 198476 kb
Host smart-ef995ced-f0c5-4423-9038-3893f974eec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2170944809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2170944809
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2738448444
Short name T407
Test name
Test status
Simulation time 6249899482 ps
CPU time 5.08 seconds
Started Jul 31 04:23:08 PM PDT 24
Finished Jul 31 04:23:13 PM PDT 24
Peak memory 198576 kb
Host smart-8ac0a3d4-ad5e-4ee6-8fad-a1333a45b66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738448444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2738448444
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2691278039
Short name T303
Test name
Test status
Simulation time 143707873258 ps
CPU time 55.71 seconds
Started Jul 31 04:23:18 PM PDT 24
Finished Jul 31 04:24:14 PM PDT 24
Peak memory 199860 kb
Host smart-f46dec28-885c-4888-83ab-f2cb0d730877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691278039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2691278039
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.1830915477
Short name T500
Test name
Test status
Simulation time 10030435106 ps
CPU time 357.38 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:30:18 PM PDT 24
Peak memory 198532 kb
Host smart-a3e510f5-f909-4a65-9a87-61cd714a3663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830915477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.1830915477
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.4097482252
Short name T819
Test name
Test status
Simulation time 5563956477 ps
CPU time 25.04 seconds
Started Jul 31 04:25:03 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 199728 kb
Host smart-3c240cbc-9a3e-4133-b207-e8b830f8eb38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4097482252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.4097482252
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3696204077
Short name T916
Test name
Test status
Simulation time 120513228061 ps
CPU time 106.74 seconds
Started Jul 31 04:23:00 PM PDT 24
Finished Jul 31 04:24:47 PM PDT 24
Peak memory 199732 kb
Host smart-2f5d43cc-da0f-4454-a91f-37c545977af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696204077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3696204077
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.77433309
Short name T1105
Test name
Test status
Simulation time 5274740909 ps
CPU time 7.33 seconds
Started Jul 31 04:22:57 PM PDT 24
Finished Jul 31 04:23:04 PM PDT 24
Peak memory 195900 kb
Host smart-208d3a81-7885-40c0-9415-6ec4b2a58c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77433309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.77433309
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.3650622540
Short name T1111
Test name
Test status
Simulation time 5545613402 ps
CPU time 8.37 seconds
Started Jul 31 04:22:55 PM PDT 24
Finished Jul 31 04:23:03 PM PDT 24
Peak memory 199672 kb
Host smart-f69090c1-f5ca-4a88-afa4-d1a36668a492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650622540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.3650622540
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.1353314236
Short name T317
Test name
Test status
Simulation time 245122313259 ps
CPU time 515.93 seconds
Started Jul 31 04:24:34 PM PDT 24
Finished Jul 31 04:33:10 PM PDT 24
Peak memory 208088 kb
Host smart-cb17ec2d-a053-490e-b169-559b565625c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353314236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.1353314236
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.974472813
Short name T963
Test name
Test status
Simulation time 155087381078 ps
CPU time 318.39 seconds
Started Jul 31 04:24:52 PM PDT 24
Finished Jul 31 04:30:10 PM PDT 24
Peak memory 215592 kb
Host smart-fc819be4-bdbd-4000-a0f6-8ac90541ff11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974472813 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.974472813
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.3523439260
Short name T541
Test name
Test status
Simulation time 842910308 ps
CPU time 1.43 seconds
Started Jul 31 04:22:58 PM PDT 24
Finished Jul 31 04:23:00 PM PDT 24
Peak memory 199536 kb
Host smart-f36d3445-c0ae-4233-8a47-8f4f97b6c58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523439260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.3523439260
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1345036741
Short name T932
Test name
Test status
Simulation time 149376640709 ps
CPU time 82.03 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:26:55 PM PDT 24
Peak memory 198980 kb
Host smart-457b9dfb-2162-4d99-bf7c-2b3f46beca15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345036741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1345036741
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2180791715
Short name T91
Test name
Test status
Simulation time 15619695799 ps
CPU time 22.43 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 199764 kb
Host smart-76d543d3-c412-43aa-abe9-fa5c5435e7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180791715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2180791715
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.2558012913
Short name T181
Test name
Test status
Simulation time 107997864249 ps
CPU time 96.99 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:28:27 PM PDT 24
Peak memory 199740 kb
Host smart-572dafc1-06bf-4ca0-a9d9-a4324eaaca88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558012913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.2558012913
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.1154272990
Short name T300
Test name
Test status
Simulation time 30014353803 ps
CPU time 47.8 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:27:35 PM PDT 24
Peak memory 199688 kb
Host smart-815d25dc-bdd3-4e46-b6c0-6277803e57c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154272990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1154272990
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.1260958905
Short name T872
Test name
Test status
Simulation time 32552566153 ps
CPU time 48.43 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199580 kb
Host smart-3d9da926-39e8-47b7-b7fc-0068fcb4914f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260958905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.1260958905
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3253108752
Short name T948
Test name
Test status
Simulation time 51115365085 ps
CPU time 33.71 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199652 kb
Host smart-a75170f6-7e69-4486-b6b6-d14dcbaf5d7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253108752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3253108752
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.74417931
Short name T1074
Test name
Test status
Simulation time 54312910169 ps
CPU time 67.49 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:28:01 PM PDT 24
Peak memory 199696 kb
Host smart-068bad9c-3c45-4c49-bb3d-44000fc65344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74417931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.74417931
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3324189409
Short name T1046
Test name
Test status
Simulation time 19114003512 ps
CPU time 42.66 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:27:30 PM PDT 24
Peak memory 199752 kb
Host smart-2029c920-0952-4ac4-b828-a0ddbd93cee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324189409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3324189409
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2822987060
Short name T919
Test name
Test status
Simulation time 5880959398 ps
CPU time 5.21 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:26:53 PM PDT 24
Peak memory 198160 kb
Host smart-f323f160-2abd-47c0-be18-7f598b03b98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822987060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2822987060
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1880352422
Short name T182
Test name
Test status
Simulation time 51421665336 ps
CPU time 20.04 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199692 kb
Host smart-8cedf2be-0808-4f8f-b210-d094ef395770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880352422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1880352422
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3449331860
Short name T1004
Test name
Test status
Simulation time 28066343 ps
CPU time 0.54 seconds
Started Jul 31 04:25:30 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 194920 kb
Host smart-33370af6-0811-4718-9e28-758182c382a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449331860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3449331860
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.906507040
Short name T747
Test name
Test status
Simulation time 137164497467 ps
CPU time 131.92 seconds
Started Jul 31 04:25:09 PM PDT 24
Finished Jul 31 04:27:21 PM PDT 24
Peak memory 199716 kb
Host smart-ef104942-2745-4e7c-9ff9-18e594565fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906507040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.906507040
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2140128263
Short name T1102
Test name
Test status
Simulation time 72246112848 ps
CPU time 123.17 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:27:51 PM PDT 24
Peak memory 199764 kb
Host smart-22b86971-415c-4d80-96ab-d48efdfdc5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140128263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2140128263
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2416033983
Short name T756
Test name
Test status
Simulation time 9245341097 ps
CPU time 14.53 seconds
Started Jul 31 04:23:13 PM PDT 24
Finished Jul 31 04:23:28 PM PDT 24
Peak memory 199376 kb
Host smart-ff8057eb-37bd-489c-8ad7-9a8a3183cafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416033983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2416033983
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.2430942655
Short name T651
Test name
Test status
Simulation time 26924637412 ps
CPU time 7.39 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 199684 kb
Host smart-8ed60591-e0d9-4fd9-8523-17297610127f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430942655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.2430942655
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2598498731
Short name T888
Test name
Test status
Simulation time 118142074940 ps
CPU time 231.6 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:28:37 PM PDT 24
Peak memory 199496 kb
Host smart-1f33029f-dc34-4c17-9c94-ed556155fb1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598498731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2598498731
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.1103868557
Short name T314
Test name
Test status
Simulation time 3332926928 ps
CPU time 3.09 seconds
Started Jul 31 04:25:10 PM PDT 24
Finished Jul 31 04:25:14 PM PDT 24
Peak memory 197848 kb
Host smart-3aea29ef-5084-431d-a67f-998d1f6476d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103868557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.1103868557
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.1082840898
Short name T706
Test name
Test status
Simulation time 109054920058 ps
CPU time 13.28 seconds
Started Jul 31 04:23:13 PM PDT 24
Finished Jul 31 04:23:26 PM PDT 24
Peak memory 196228 kb
Host smart-d5cbdc9d-8211-4a6a-8b59-03fb6057e71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082840898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.1082840898
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.1405841357
Short name T548
Test name
Test status
Simulation time 13490126604 ps
CPU time 175.46 seconds
Started Jul 31 04:23:19 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 199672 kb
Host smart-63d514f0-817e-4d18-913e-cbe4c966f9e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1405841357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.1405841357
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.3404185003
Short name T603
Test name
Test status
Simulation time 5836358951 ps
CPU time 46.95 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 198896 kb
Host smart-537e4e4f-4327-4640-94c4-2d1a42060669
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3404185003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.3404185003
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2379992229
Short name T562
Test name
Test status
Simulation time 21121374019 ps
CPU time 32.88 seconds
Started Jul 31 04:23:24 PM PDT 24
Finished Jul 31 04:23:57 PM PDT 24
Peak memory 199732 kb
Host smart-34a06f0b-33db-4bb3-b075-043e798f8e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379992229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2379992229
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1488643751
Short name T338
Test name
Test status
Simulation time 627839704 ps
CPU time 0.84 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 194980 kb
Host smart-7ab33192-4bce-4b16-87d7-1a2d523126b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488643751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1488643751
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2949430278
Short name T958
Test name
Test status
Simulation time 106748524 ps
CPU time 1 seconds
Started Jul 31 04:23:11 PM PDT 24
Finished Jul 31 04:23:12 PM PDT 24
Peak memory 198792 kb
Host smart-74fa3db7-d22b-4d52-af87-6cbe53066d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949430278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2949430278
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.404419456
Short name T514
Test name
Test status
Simulation time 459640780729 ps
CPU time 1012.95 seconds
Started Jul 31 04:24:44 PM PDT 24
Finished Jul 31 04:41:37 PM PDT 24
Peak memory 215220 kb
Host smart-967abeb6-12a6-450f-9b24-99019bf8858e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404419456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.404419456
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.4126506551
Short name T357
Test name
Test status
Simulation time 1634746843 ps
CPU time 3.92 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 196784 kb
Host smart-d88a5964-2fd0-44ea-8e66-be413f89b3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126506551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.4126506551
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.288626005
Short name T1083
Test name
Test status
Simulation time 42213961906 ps
CPU time 31.1 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 199516 kb
Host smart-01e21282-7457-4411-abcc-24b2e901a211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288626005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.288626005
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2869524199
Short name T967
Test name
Test status
Simulation time 32472806661 ps
CPU time 47.84 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:37 PM PDT 24
Peak memory 199572 kb
Host smart-65b2c60f-fda8-442b-a395-06eb272413ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869524199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2869524199
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3860701419
Short name T839
Test name
Test status
Simulation time 28168347711 ps
CPU time 56.58 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 199704 kb
Host smart-bf11f821-7388-42eb-92e1-5b1861fa9590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860701419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3860701419
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2708594489
Short name T453
Test name
Test status
Simulation time 174786663169 ps
CPU time 36.55 seconds
Started Jul 31 04:26:51 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 199840 kb
Host smart-8f49293e-bead-443a-9d7a-38d9145bf89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708594489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2708594489
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.469394998
Short name T787
Test name
Test status
Simulation time 59197337312 ps
CPU time 49.81 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199684 kb
Host smart-7c84516a-505a-48e8-bbdc-13cb5abf96b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469394998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.469394998
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2511273002
Short name T451
Test name
Test status
Simulation time 173917915206 ps
CPU time 195.62 seconds
Started Jul 31 04:26:48 PM PDT 24
Finished Jul 31 04:30:04 PM PDT 24
Peak memory 199692 kb
Host smart-68048624-2452-4085-b659-39d5c05a9756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511273002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2511273002
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.4145280961
Short name T304
Test name
Test status
Simulation time 113979642454 ps
CPU time 42.62 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199740 kb
Host smart-e903bff2-aecf-41e5-a008-18a68202e9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145280961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.4145280961
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2684308903
Short name T1158
Test name
Test status
Simulation time 17427095297 ps
CPU time 22.84 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199692 kb
Host smart-cb75b665-28b5-4012-91ea-155be7328192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684308903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2684308903
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3028338920
Short name T345
Test name
Test status
Simulation time 33938831038 ps
CPU time 6.68 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 199688 kb
Host smart-854d2f06-5202-4c0a-a94b-e5ecbeb25a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028338920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3028338920
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3043511936
Short name T129
Test name
Test status
Simulation time 26004030216 ps
CPU time 18.05 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199772 kb
Host smart-69256b0f-6261-4ce6-a9ed-98c4156ba887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043511936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3043511936
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.3678136291
Short name T376
Test name
Test status
Simulation time 14282164 ps
CPU time 0.55 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 194888 kb
Host smart-2e99a49a-f97f-497d-a6a7-1210085eb9c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678136291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3678136291
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2556956081
Short name T959
Test name
Test status
Simulation time 66990048964 ps
CPU time 111.02 seconds
Started Jul 31 04:23:16 PM PDT 24
Finished Jul 31 04:25:07 PM PDT 24
Peak memory 199712 kb
Host smart-97d4585a-f8a0-45e2-9d84-2e95b4689ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556956081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2556956081
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1388920267
Short name T299
Test name
Test status
Simulation time 13304901029 ps
CPU time 24.09 seconds
Started Jul 31 04:23:19 PM PDT 24
Finished Jul 31 04:23:44 PM PDT 24
Peak memory 199684 kb
Host smart-efe5c1f4-725e-4e46-82dc-c38b0a92bee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388920267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1388920267
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.2776175767
Short name T119
Test name
Test status
Simulation time 102238062799 ps
CPU time 37.74 seconds
Started Jul 31 04:23:22 PM PDT 24
Finished Jul 31 04:24:00 PM PDT 24
Peak memory 199448 kb
Host smart-c8b14e1a-6168-4943-9a2e-5db783d0431a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776175767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.2776175767
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1764015549
Short name T801
Test name
Test status
Simulation time 155222604670 ps
CPU time 504.01 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:33:21 PM PDT 24
Peak memory 199436 kb
Host smart-11f6a3f3-9b37-4dd1-952c-3f5e99a42576
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1764015549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1764015549
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.3323556859
Short name T940
Test name
Test status
Simulation time 8617875801 ps
CPU time 8.57 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:25:04 PM PDT 24
Peak memory 198748 kb
Host smart-2a4dfa68-d216-4a99-ad93-fb0333c980b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323556859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3323556859
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.3011014876
Short name T277
Test name
Test status
Simulation time 86862471349 ps
CPU time 149.91 seconds
Started Jul 31 04:25:01 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 208160 kb
Host smart-0604101c-ebcb-437b-8f70-313444bde230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011014876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.3011014876
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.3793520950
Short name T516
Test name
Test status
Simulation time 5948320018 ps
CPU time 284.26 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:29:24 PM PDT 24
Peak memory 198764 kb
Host smart-3d719dcf-c8f1-44d5-8c9c-0acaa2035500
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3793520950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.3793520950
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.3206630949
Short name T620
Test name
Test status
Simulation time 2659392260 ps
CPU time 10.41 seconds
Started Jul 31 04:24:38 PM PDT 24
Finished Jul 31 04:24:49 PM PDT 24
Peak memory 197052 kb
Host smart-da9fbbc1-516c-4085-af26-ac53c23d23e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3206630949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3206630949
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3758277505
Short name T492
Test name
Test status
Simulation time 113764042040 ps
CPU time 164.01 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:27:40 PM PDT 24
Peak memory 199336 kb
Host smart-4d19bfe9-ad71-447c-94aa-429b1127095d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758277505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3758277505
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1370362397
Short name T379
Test name
Test status
Simulation time 5694492697 ps
CPU time 9.7 seconds
Started Jul 31 04:25:01 PM PDT 24
Finished Jul 31 04:25:11 PM PDT 24
Peak memory 196704 kb
Host smart-7993e9be-bd7e-461e-9100-e907b6a12d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370362397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1370362397
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.380752473
Short name T851
Test name
Test status
Simulation time 105931480 ps
CPU time 0.84 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:24:59 PM PDT 24
Peak memory 197280 kb
Host smart-5af59cd7-9997-413a-bc7f-be1f22e5c442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380752473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.380752473
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.2603397104
Short name T347
Test name
Test status
Simulation time 244709765013 ps
CPU time 328.36 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:30:55 PM PDT 24
Peak memory 207320 kb
Host smart-25ccdd4b-dcd8-4452-9d15-0c4b48f23ddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603397104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.2603397104
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.775799707
Short name T831
Test name
Test status
Simulation time 95081786086 ps
CPU time 1000.16 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:42:17 PM PDT 24
Peak memory 216144 kb
Host smart-918dd15f-b1a5-4dd7-8556-407280c4b4f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775799707 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.775799707
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.384009535
Short name T457
Test name
Test status
Simulation time 3848751346 ps
CPU time 1.18 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:24:58 PM PDT 24
Peak memory 199132 kb
Host smart-c503d1f5-d915-463c-89aa-87b9ed7862f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384009535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.384009535
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.1162199079
Short name T681
Test name
Test status
Simulation time 21045540696 ps
CPU time 5.26 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:50 PM PDT 24
Peak memory 197284 kb
Host smart-a8647fe0-6132-4f5a-89de-62a45f118a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162199079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.1162199079
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.2473264622
Short name T939
Test name
Test status
Simulation time 19634158377 ps
CPU time 21.15 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199752 kb
Host smart-3e9dc594-9074-4d97-9a30-43c565d9d556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473264622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.2473264622
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.2069961664
Short name T924
Test name
Test status
Simulation time 17178681599 ps
CPU time 8.89 seconds
Started Jul 31 04:26:57 PM PDT 24
Finished Jul 31 04:27:06 PM PDT 24
Peak memory 199720 kb
Host smart-449874f1-cdc4-47d0-a1f9-063d9bef9b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069961664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.2069961664
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.403584959
Short name T705
Test name
Test status
Simulation time 97503689884 ps
CPU time 153.5 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:29:27 PM PDT 24
Peak memory 199684 kb
Host smart-101e38a1-9172-4731-9f05-c7806a3c23c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403584959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.403584959
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.468568040
Short name T158
Test name
Test status
Simulation time 14945999423 ps
CPU time 20.94 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:14 PM PDT 24
Peak memory 199504 kb
Host smart-616b1f62-0035-4c9b-ab1c-114ffdecf960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468568040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.468568040
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2366919579
Short name T793
Test name
Test status
Simulation time 106836642826 ps
CPU time 317.23 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:32:13 PM PDT 24
Peak memory 199412 kb
Host smart-99411183-57f6-4385-b6e3-96e427185b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366919579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2366919579
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.4023390571
Short name T483
Test name
Test status
Simulation time 30402458610 ps
CPU time 48.75 seconds
Started Jul 31 04:26:57 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199680 kb
Host smart-82641673-1c2b-4ba0-a6a9-10217359deae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023390571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.4023390571
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.4160671795
Short name T156
Test name
Test status
Simulation time 44067845470 ps
CPU time 14.79 seconds
Started Jul 31 04:26:56 PM PDT 24
Finished Jul 31 04:27:10 PM PDT 24
Peak memory 199704 kb
Host smart-654929a5-6e07-48f1-b6d4-8c9a24d871fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160671795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.4160671795
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.3114489763
Short name T1126
Test name
Test status
Simulation time 42911449947 ps
CPU time 15.86 seconds
Started Jul 31 04:26:52 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199704 kb
Host smart-f6c0a140-384d-47ed-83e0-17efe77e7448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114489763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.3114489763
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.898215957
Short name T223
Test name
Test status
Simulation time 25887148457 ps
CPU time 12.97 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:07 PM PDT 24
Peak memory 199744 kb
Host smart-7a23019c-9c26-4237-a7b0-a2561aea6a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898215957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.898215957
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.989457869
Short name T16
Test name
Test status
Simulation time 41605162 ps
CPU time 0.52 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:25:36 PM PDT 24
Peak memory 194100 kb
Host smart-e6d13fc5-a31e-4136-84da-f36beaead629
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989457869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.989457869
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1547514267
Short name T1104
Test name
Test status
Simulation time 38378894216 ps
CPU time 73.89 seconds
Started Jul 31 04:25:20 PM PDT 24
Finished Jul 31 04:26:34 PM PDT 24
Peak memory 198904 kb
Host smart-bd0a4f5c-7047-4d9f-be08-7a053831ae7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547514267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1547514267
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.2984850582
Short name T727
Test name
Test status
Simulation time 102917738756 ps
CPU time 37.13 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199556 kb
Host smart-c7a32ef0-4569-487a-b31e-408d61be6c7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984850582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.2984850582
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.276748812
Short name T1055
Test name
Test status
Simulation time 87098045400 ps
CPU time 24.62 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 199592 kb
Host smart-f72471ba-fa74-4427-9295-c09a963dbaae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276748812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.276748812
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.936689647
Short name T424
Test name
Test status
Simulation time 50762582718 ps
CPU time 79.03 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 198712 kb
Host smart-1fb8c130-a375-4ff1-a370-12be21f02807
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936689647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.936689647
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.2323633902
Short name T423
Test name
Test status
Simulation time 287011221248 ps
CPU time 371.85 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:31:41 PM PDT 24
Peak memory 199444 kb
Host smart-ee59a899-e7f4-4dd2-bba8-a382c30f8d5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2323633902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.2323633902
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.1654555680
Short name T935
Test name
Test status
Simulation time 2612326659 ps
CPU time 5 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 197296 kb
Host smart-572a2b0d-7f23-43ac-a66c-c7bae9174c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654555680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.1654555680
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.238073563
Short name T595
Test name
Test status
Simulation time 37530179034 ps
CPU time 34.37 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199648 kb
Host smart-8bbb95f8-9500-4889-9acc-90085a7c1049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238073563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.238073563
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.1370417842
Short name T26
Test name
Test status
Simulation time 27618308486 ps
CPU time 320.45 seconds
Started Jul 31 04:23:34 PM PDT 24
Finished Jul 31 04:28:54 PM PDT 24
Peak memory 199720 kb
Host smart-e243f6db-2877-4346-9926-7acb433d9c3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1370417842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.1370417842
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.3955787987
Short name T601
Test name
Test status
Simulation time 6211863533 ps
CPU time 53.53 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:26:29 PM PDT 24
Peak memory 197632 kb
Host smart-a82fcc19-8f95-4cd6-b2e5-903417b7a5cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3955787987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.3955787987
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.1347811909
Short name T517
Test name
Test status
Simulation time 19184939610 ps
CPU time 16.36 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:25:53 PM PDT 24
Peak memory 199516 kb
Host smart-a47cb6c7-9688-418a-87dc-51e44c979308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347811909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.1347811909
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.789158809
Short name T781
Test name
Test status
Simulation time 5486780342 ps
CPU time 9 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:25:46 PM PDT 24
Peak memory 195664 kb
Host smart-37383bd3-9600-41b0-9541-db06c5e9e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789158809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.789158809
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.925664876
Short name T604
Test name
Test status
Simulation time 461714131 ps
CPU time 2.14 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 197944 kb
Host smart-b7ff5a1e-10af-46a8-8d63-106cfd411093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925664876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.925664876
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3938433075
Short name T999
Test name
Test status
Simulation time 241398399265 ps
CPU time 105.68 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199736 kb
Host smart-48951241-ce77-46c6-b01f-6c7c06ae001b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938433075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3938433075
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.796616595
Short name T1059
Test name
Test status
Simulation time 44108382309 ps
CPU time 480.24 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:33:38 PM PDT 24
Peak memory 216276 kb
Host smart-83f123d6-3b05-4a1c-8457-b0f0f5044491
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796616595 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.796616595
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1719442316
Short name T702
Test name
Test status
Simulation time 3671128363 ps
CPU time 1.86 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 199228 kb
Host smart-56535485-3ac3-489d-8fcd-541327c127e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719442316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1719442316
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.3777759626
Short name T668
Test name
Test status
Simulation time 61272444687 ps
CPU time 47.41 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:26:21 PM PDT 24
Peak memory 199724 kb
Host smart-b76b1143-c6b0-4c43-b850-e7eb0f5c01b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777759626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.3777759626
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.1661267332
Short name T995
Test name
Test status
Simulation time 51089397747 ps
CPU time 37.29 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 199808 kb
Host smart-ef247a8f-53c9-4b2b-999d-4a4c412a4e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661267332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.1661267332
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.2686453663
Short name T440
Test name
Test status
Simulation time 23007458399 ps
CPU time 10.84 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:04 PM PDT 24
Peak memory 200124 kb
Host smart-79f6a489-c0dc-4d5e-ac3f-0345cd9431e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686453663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.2686453663
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.3901662241
Short name T846
Test name
Test status
Simulation time 40747439926 ps
CPU time 45.6 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199604 kb
Host smart-7cb95c23-433a-44fa-8aeb-3a7c9c5ff00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901662241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.3901662241
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.2370167734
Short name T1113
Test name
Test status
Simulation time 34183022530 ps
CPU time 53.48 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:42 PM PDT 24
Peak memory 199712 kb
Host smart-007a7bd1-aae9-47eb-bde0-e8def0d7e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370167734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.2370167734
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2035454295
Short name T1010
Test name
Test status
Simulation time 86364624320 ps
CPU time 219.44 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:30:29 PM PDT 24
Peak memory 199752 kb
Host smart-eda97d9c-c0a4-4123-90ec-f5fb9892bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035454295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2035454295
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.4110932562
Short name T261
Test name
Test status
Simulation time 15666581787 ps
CPU time 7.35 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:01 PM PDT 24
Peak memory 199740 kb
Host smart-0484ae01-c732-42d8-beac-671cc840c6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110932562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.4110932562
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.4237302387
Short name T663
Test name
Test status
Simulation time 31593142635 ps
CPU time 49.42 seconds
Started Jul 31 04:26:50 PM PDT 24
Finished Jul 31 04:27:39 PM PDT 24
Peak memory 199780 kb
Host smart-a798fbcf-7ee0-4f60-91a7-c34800827847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237302387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.4237302387
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.4201419242
Short name T618
Test name
Test status
Simulation time 121121587694 ps
CPU time 81.04 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:28:17 PM PDT 24
Peak memory 199344 kb
Host smart-03d7c44b-d4d8-44e1-ae00-af4d86eaa7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201419242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.4201419242
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.147416528
Short name T906
Test name
Test status
Simulation time 13592625072 ps
CPU time 22.34 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 199708 kb
Host smart-dcff3d22-46a4-4516-a2fb-16419fe82654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147416528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.147416528
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.2824608621
Short name T351
Test name
Test status
Simulation time 42875091 ps
CPU time 0.58 seconds
Started Jul 31 04:23:46 PM PDT 24
Finished Jul 31 04:23:47 PM PDT 24
Peak memory 195052 kb
Host smart-55e228ea-4bc9-451d-932a-ffc31e24166e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824608621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.2824608621
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.194151224
Short name T764
Test name
Test status
Simulation time 40398922669 ps
CPU time 57.51 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:24:37 PM PDT 24
Peak memory 199748 kb
Host smart-e6113e05-ac61-4be4-9564-41541a20fb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194151224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.194151224
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2839856986
Short name T808
Test name
Test status
Simulation time 44810750035 ps
CPU time 23.54 seconds
Started Jul 31 04:23:37 PM PDT 24
Finished Jul 31 04:24:01 PM PDT 24
Peak memory 199732 kb
Host smart-c4f5de57-28a5-45f0-bc61-d3eda83b3465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839856986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2839856986
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2675780273
Short name T703
Test name
Test status
Simulation time 120907380549 ps
CPU time 62.32 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 199688 kb
Host smart-dd57d821-0bd1-4a59-bffe-69bf6d33ec2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675780273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2675780273
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.2926224790
Short name T877
Test name
Test status
Simulation time 153612856476 ps
CPU time 52.74 seconds
Started Jul 31 04:23:39 PM PDT 24
Finished Jul 31 04:24:31 PM PDT 24
Peak memory 199732 kb
Host smart-0df21c84-2391-46b4-8cfa-17c1877e137b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926224790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.2926224790
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.2983058425
Short name T650
Test name
Test status
Simulation time 75640891610 ps
CPU time 540.56 seconds
Started Jul 31 04:24:05 PM PDT 24
Finished Jul 31 04:33:06 PM PDT 24
Peak memory 199728 kb
Host smart-5c0e578c-3a3f-4b44-a1cc-1639fa71baf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983058425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2983058425
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.248593219
Short name T432
Test name
Test status
Simulation time 9615194382 ps
CPU time 7.91 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 199504 kb
Host smart-8e95a151-c647-4b79-8396-1a067198c63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248593219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.248593219
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.4276839939
Short name T577
Test name
Test status
Simulation time 48733701604 ps
CPU time 80.27 seconds
Started Jul 31 04:25:24 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 198196 kb
Host smart-519e2300-57f7-49d6-a8e4-c447e51bbfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276839939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.4276839939
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1543384864
Short name T559
Test name
Test status
Simulation time 19504789578 ps
CPU time 1131.66 seconds
Started Jul 31 04:23:38 PM PDT 24
Finished Jul 31 04:42:30 PM PDT 24
Peak memory 199824 kb
Host smart-e9feb69b-dd5a-4a04-a136-18228e6ea363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1543384864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1543384864
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.974491317
Short name T962
Test name
Test status
Simulation time 6758178099 ps
CPU time 62.38 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:24:42 PM PDT 24
Peak memory 198016 kb
Host smart-736d46ab-37a6-452c-b807-7aad15e3999a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974491317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.974491317
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.388608154
Short name T907
Test name
Test status
Simulation time 124377106238 ps
CPU time 16.63 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:56 PM PDT 24
Peak memory 199056 kb
Host smart-4e3c92e0-edca-46f9-ab01-cb6a8721c5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388608154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.388608154
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.3376479414
Short name T463
Test name
Test status
Simulation time 719241544 ps
CPU time 0.91 seconds
Started Jul 31 04:24:04 PM PDT 24
Finished Jul 31 04:24:05 PM PDT 24
Peak memory 195232 kb
Host smart-3b94bdf4-838d-4546-b89c-46752f93a00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376479414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3376479414
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.2876533493
Short name T779
Test name
Test status
Simulation time 463587299 ps
CPU time 2.41 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:23:43 PM PDT 24
Peak memory 198020 kb
Host smart-9793b29d-b50e-4341-ba8f-e3c36aafa68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876533493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.2876533493
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.4252030494
Short name T814
Test name
Test status
Simulation time 25274746895 ps
CPU time 44.06 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:42 PM PDT 24
Peak memory 199520 kb
Host smart-b55ba175-0068-4b08-8ea2-34d9853264f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252030494 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.4252030494
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.1677422785
Short name T84
Test name
Test status
Simulation time 53647536966 ps
CPU time 119.48 seconds
Started Jul 31 04:23:54 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 215572 kb
Host smart-5154917b-bb18-46b5-854e-fae2542158ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677422785 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.1677422785
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1797340261
Short name T744
Test name
Test status
Simulation time 1508578126 ps
CPU time 1.26 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 196596 kb
Host smart-7262c069-5714-481a-b0cd-355b1e000d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797340261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1797340261
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.2496645608
Short name T697
Test name
Test status
Simulation time 26179306204 ps
CPU time 43.04 seconds
Started Jul 31 04:23:49 PM PDT 24
Finished Jul 31 04:24:32 PM PDT 24
Peak memory 199760 kb
Host smart-916644fe-6b21-4c1f-85d6-acc53cc2ccd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496645608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.2496645608
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.1941638826
Short name T241
Test name
Test status
Simulation time 16643563044 ps
CPU time 18.57 seconds
Started Jul 31 04:26:57 PM PDT 24
Finished Jul 31 04:27:16 PM PDT 24
Peak memory 199688 kb
Host smart-a59dcdc5-aedd-41b2-a014-30578d15e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941638826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.1941638826
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2522846172
Short name T234
Test name
Test status
Simulation time 262920580216 ps
CPU time 245.26 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:30:53 PM PDT 24
Peak memory 199804 kb
Host smart-1dc51d08-7746-4499-924e-81abca75bac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522846172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2522846172
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.406766882
Short name T988
Test name
Test status
Simulation time 136895463087 ps
CPU time 47.27 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 199772 kb
Host smart-c952b18f-2d95-4ebc-a543-6c04c9c13599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406766882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.406766882
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.881064353
Short name T938
Test name
Test status
Simulation time 211197541426 ps
CPU time 320.06 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:32:18 PM PDT 24
Peak memory 199760 kb
Host smart-e09035fe-0bfc-4be3-a53b-e33d0ed8269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881064353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.881064353
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.4206131093
Short name T812
Test name
Test status
Simulation time 72058717487 ps
CPU time 29.81 seconds
Started Jul 31 04:26:52 PM PDT 24
Finished Jul 31 04:27:21 PM PDT 24
Peak memory 199828 kb
Host smart-e9569f82-22ff-4332-8d57-cffe482ace1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206131093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.4206131093
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.4203055915
Short name T75
Test name
Test status
Simulation time 113343778135 ps
CPU time 46.53 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:27:44 PM PDT 24
Peak memory 199600 kb
Host smart-5cc52312-95b1-4e38-8fef-0eff4fdb4aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203055915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.4203055915
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.3426955658
Short name T773
Test name
Test status
Simulation time 88306589441 ps
CPU time 35.72 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199624 kb
Host smart-d6656ab7-74a2-4f7e-aa7f-43edae3be7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426955658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3426955658
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.4072168412
Short name T102
Test name
Test status
Simulation time 27569802494 ps
CPU time 45.57 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:45 PM PDT 24
Peak memory 199708 kb
Host smart-402a478d-e427-4f1a-8b15-d327c714c330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072168412 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.4072168412
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.545733478
Short name T273
Test name
Test status
Simulation time 121160446773 ps
CPU time 271.14 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:31:29 PM PDT 24
Peak memory 199772 kb
Host smart-4229dee9-c9e0-4510-a3b1-6b86106320d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545733478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.545733478
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.516230457
Short name T1034
Test name
Test status
Simulation time 29636149 ps
CPU time 0.56 seconds
Started Jul 31 04:24:07 PM PDT 24
Finished Jul 31 04:24:07 PM PDT 24
Peak memory 194652 kb
Host smart-7c2f36bd-debb-4c2f-975c-839436ee96b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516230457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.516230457
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.1252759546
Short name T1110
Test name
Test status
Simulation time 124201930874 ps
CPU time 108.76 seconds
Started Jul 31 04:23:55 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 199760 kb
Host smart-9979caa5-2101-4b9f-a45e-76302be8edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252759546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1252759546
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.3237954005
Short name T987
Test name
Test status
Simulation time 148715712689 ps
CPU time 132.09 seconds
Started Jul 31 04:23:49 PM PDT 24
Finished Jul 31 04:26:01 PM PDT 24
Peak memory 200032 kb
Host smart-b5ad877b-cdf2-441d-9cd4-cb43d65b5dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237954005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.3237954005
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.382977668
Short name T1096
Test name
Test status
Simulation time 31931271604 ps
CPU time 34.33 seconds
Started Jul 31 04:23:50 PM PDT 24
Finished Jul 31 04:24:25 PM PDT 24
Peak memory 199840 kb
Host smart-1dd4c2b8-b84f-46cb-9170-debf84f2073c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382977668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.382977668
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1003181944
Short name T1064
Test name
Test status
Simulation time 99491490420 ps
CPU time 181.51 seconds
Started Jul 31 04:24:01 PM PDT 24
Finished Jul 31 04:27:03 PM PDT 24
Peak memory 199668 kb
Host smart-4948082f-5177-43bc-909b-373b350bd85d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003181944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1003181944
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1535575226
Short name T312
Test name
Test status
Simulation time 7545784786 ps
CPU time 4.09 seconds
Started Jul 31 04:24:01 PM PDT 24
Finished Jul 31 04:24:05 PM PDT 24
Peak memory 199544 kb
Host smart-4096465b-2fcb-42fb-ad13-d9f84be63747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535575226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1535575226
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.952992890
Short name T679
Test name
Test status
Simulation time 418316502407 ps
CPU time 91.14 seconds
Started Jul 31 04:23:52 PM PDT 24
Finished Jul 31 04:25:23 PM PDT 24
Peak memory 199936 kb
Host smart-cdf155c4-225e-46bd-8bf4-58b9cc52d654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952992890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.952992890
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2771905395
Short name T1087
Test name
Test status
Simulation time 11566536001 ps
CPU time 71.86 seconds
Started Jul 31 04:24:07 PM PDT 24
Finished Jul 31 04:25:19 PM PDT 24
Peak memory 199764 kb
Host smart-8bcb3145-51dd-437b-88e6-b96b42a07bac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2771905395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2771905395
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1393435424
Short name T613
Test name
Test status
Simulation time 2224687540 ps
CPU time 3.86 seconds
Started Jul 31 04:24:01 PM PDT 24
Finished Jul 31 04:24:05 PM PDT 24
Peak memory 197592 kb
Host smart-8a6e44b1-e43c-4306-a465-8be048168ce8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1393435424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1393435424
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.1483954797
Short name T929
Test name
Test status
Simulation time 310838787875 ps
CPU time 29.73 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:51 PM PDT 24
Peak memory 199676 kb
Host smart-dc759350-ae82-452c-9b7a-012dc9bd5e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483954797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.1483954797
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3286594423
Short name T726
Test name
Test status
Simulation time 4124481516 ps
CPU time 1.97 seconds
Started Jul 31 04:23:58 PM PDT 24
Finished Jul 31 04:24:00 PM PDT 24
Peak memory 195880 kb
Host smart-27fce055-d8b3-4704-b9ee-c659ee82fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286594423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3286594423
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1770683843
Short name T352
Test name
Test status
Simulation time 929789431 ps
CPU time 2.68 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:16 PM PDT 24
Peak memory 197900 kb
Host smart-c8b9136a-0821-4bca-9490-5889974f4dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770683843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1770683843
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.244804914
Short name T124
Test name
Test status
Simulation time 259961720044 ps
CPU time 147.57 seconds
Started Jul 31 04:24:04 PM PDT 24
Finished Jul 31 04:26:31 PM PDT 24
Peak memory 199800 kb
Host smart-54fc5d0e-1c87-4c17-b9fa-4b9273706f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244804914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.244804914
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.550829782
Short name T978
Test name
Test status
Simulation time 40567583147 ps
CPU time 511.57 seconds
Started Jul 31 04:23:57 PM PDT 24
Finished Jul 31 04:32:29 PM PDT 24
Peak memory 216332 kb
Host smart-145f2eeb-df15-49cc-badc-daad46d535f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550829782 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.550829782
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1452874628
Short name T941
Test name
Test status
Simulation time 982509481 ps
CPU time 2.29 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 196612 kb
Host smart-e0f411af-a23d-4f1f-9aee-2bf42ac449bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452874628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1452874628
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.3996988188
Short name T1029
Test name
Test status
Simulation time 91319661825 ps
CPU time 37.01 seconds
Started Jul 31 04:23:43 PM PDT 24
Finished Jul 31 04:24:20 PM PDT 24
Peak memory 199812 kb
Host smart-9ccf4072-11fb-48e5-914a-dd60744feaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996988188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.3996988188
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.3988007907
Short name T746
Test name
Test status
Simulation time 35033772840 ps
CPU time 19.78 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:14 PM PDT 24
Peak memory 199684 kb
Host smart-55e2288e-3cf9-4ead-9ca8-4e29f0409868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988007907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.3988007907
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.617022602
Short name T897
Test name
Test status
Simulation time 28128944845 ps
CPU time 42.44 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199776 kb
Host smart-94c1c525-463b-4b78-b661-949c017e856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617022602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.617022602
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.2934908005
Short name T749
Test name
Test status
Simulation time 12005375595 ps
CPU time 18.9 seconds
Started Jul 31 04:26:49 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199712 kb
Host smart-b2fd3c1d-a210-4476-ac78-843ba987cc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934908005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.2934908005
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2298365610
Short name T896
Test name
Test status
Simulation time 40530562210 ps
CPU time 57.53 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:27:55 PM PDT 24
Peak memory 199812 kb
Host smart-38fb6fc1-48cf-458a-b136-fe5f5e0d2853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298365610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2298365610
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.185878972
Short name T644
Test name
Test status
Simulation time 57991263701 ps
CPU time 76.34 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:28:11 PM PDT 24
Peak memory 199736 kb
Host smart-3475310a-a2b4-408c-834c-1805daf6f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185878972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.185878972
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.281449358
Short name T501
Test name
Test status
Simulation time 16293146784 ps
CPU time 22.73 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:16 PM PDT 24
Peak memory 199308 kb
Host smart-2af8c6e5-7f52-4f65-aafd-1e1359cb8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281449358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.281449358
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.3640378975
Short name T192
Test name
Test status
Simulation time 20294065596 ps
CPU time 25.17 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:18 PM PDT 24
Peak memory 199748 kb
Host smart-c8ca13bb-bd70-4309-be6b-aff4055d6cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640378975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.3640378975
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2983595416
Short name T1016
Test name
Test status
Simulation time 66784758857 ps
CPU time 54.45 seconds
Started Jul 31 04:26:56 PM PDT 24
Finished Jul 31 04:27:50 PM PDT 24
Peak memory 199808 kb
Host smart-5caa7d0b-00fe-46bb-99fb-4a6c443c40e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983595416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2983595416
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.307503357
Short name T471
Test name
Test status
Simulation time 131317735394 ps
CPU time 54.92 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:48 PM PDT 24
Peak memory 199748 kb
Host smart-0c42f9ed-e6d6-481f-b0a3-1dfe29d641b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307503357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.307503357
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1383834260
Short name T405
Test name
Test status
Simulation time 11907976 ps
CPU time 0.55 seconds
Started Jul 31 04:24:06 PM PDT 24
Finished Jul 31 04:24:06 PM PDT 24
Peak memory 195468 kb
Host smart-4500c915-823a-41a6-8566-b6d3a07ad8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383834260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1383834260
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.1753804851
Short name T1076
Test name
Test status
Simulation time 46688067692 ps
CPU time 76.81 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199688 kb
Host smart-166f93b7-51dd-441a-9390-2a9000736f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753804851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1753804851
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.306701512
Short name T441
Test name
Test status
Simulation time 8961719820 ps
CPU time 3.96 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 198984 kb
Host smart-cb322a95-0a7d-4f45-91f3-2944c7ae10a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306701512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.306701512
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1482457440
Short name T1160
Test name
Test status
Simulation time 35449706220 ps
CPU time 61.07 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:27:24 PM PDT 24
Peak memory 199628 kb
Host smart-482413c2-8089-4bc7-a76f-8b8123ea5141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482457440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1482457440
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1544290840
Short name T1139
Test name
Test status
Simulation time 29404757084 ps
CPU time 21.83 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 199688 kb
Host smart-554c47d0-cd95-42eb-a169-5b8079ef6fcc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544290840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1544290840
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.2580247562
Short name T429
Test name
Test status
Simulation time 91323744990 ps
CPU time 592.69 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:34:13 PM PDT 24
Peak memory 199748 kb
Host smart-ee6f225f-5e55-492e-ae84-fabd76d90071
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2580247562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.2580247562
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.41032652
Short name T361
Test name
Test status
Simulation time 4179769506 ps
CPU time 2.91 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 198192 kb
Host smart-343c4d08-de78-4f11-8267-2b333a5fa1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41032652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.41032652
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.4218998410
Short name T73
Test name
Test status
Simulation time 50376750725 ps
CPU time 44.44 seconds
Started Jul 31 04:24:02 PM PDT 24
Finished Jul 31 04:24:46 PM PDT 24
Peak memory 199656 kb
Host smart-f33760df-ecbb-4e66-a545-3c8d5e204e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218998410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.4218998410
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2471762808
Short name T619
Test name
Test status
Simulation time 10184392093 ps
CPU time 536.01 seconds
Started Jul 31 04:24:06 PM PDT 24
Finished Jul 31 04:33:02 PM PDT 24
Peak memory 199832 kb
Host smart-ffbb8ec8-7663-45d6-9c93-162f2baf6de0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471762808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2471762808
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.3069655395
Short name T670
Test name
Test status
Simulation time 8320211633 ps
CPU time 22.13 seconds
Started Jul 31 04:24:02 PM PDT 24
Finished Jul 31 04:24:24 PM PDT 24
Peak memory 198940 kb
Host smart-66a5489d-efec-4ce2-a814-d1a0ed2e15aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3069655395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3069655395
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.3368453195
Short name T574
Test name
Test status
Simulation time 1323291978 ps
CPU time 2.71 seconds
Started Jul 31 04:26:02 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 195280 kb
Host smart-d0a938f2-0dfd-4bbd-a7ef-d52a2ab8d73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368453195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3368453195
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.4180529365
Short name T1132
Test name
Test status
Simulation time 10588453633 ps
CPU time 10.18 seconds
Started Jul 31 04:24:02 PM PDT 24
Finished Jul 31 04:24:12 PM PDT 24
Peak memory 199780 kb
Host smart-70894e6b-5bb2-4fc3-8000-2126134b7762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180529365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.4180529365
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.831587852
Short name T730
Test name
Test status
Simulation time 46452211040 ps
CPU time 215.8 seconds
Started Jul 31 04:24:19 PM PDT 24
Finished Jul 31 04:27:55 PM PDT 24
Peak memory 216324 kb
Host smart-8091695a-4dbd-4af0-a074-57b471d979bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831587852 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.831587852
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1399963220
Short name T339
Test name
Test status
Simulation time 1059284022 ps
CPU time 3.71 seconds
Started Jul 31 04:24:02 PM PDT 24
Finished Jul 31 04:24:05 PM PDT 24
Peak memory 198732 kb
Host smart-72620677-b8fc-4a7b-9dd4-5af58f3c1cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399963220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1399963220
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.285330561
Short name T737
Test name
Test status
Simulation time 136245461157 ps
CPU time 282.36 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:30:41 PM PDT 24
Peak memory 199704 kb
Host smart-411559eb-d126-47ff-9e51-7d33b82ed1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285330561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.285330561
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.1618120870
Short name T368
Test name
Test status
Simulation time 58239474797 ps
CPU time 79.46 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:28:14 PM PDT 24
Peak memory 199768 kb
Host smart-54b5a79c-fc90-46ce-b045-31b1dffd8168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618120870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.1618120870
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.944961421
Short name T178
Test name
Test status
Simulation time 146075347509 ps
CPU time 243.61 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:30:58 PM PDT 24
Peak memory 199688 kb
Host smart-7c3c3203-6f40-45dc-8980-b53f61e9c9ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944961421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.944961421
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.3789610599
Short name T141
Test name
Test status
Simulation time 163747784479 ps
CPU time 79.06 seconds
Started Jul 31 04:26:57 PM PDT 24
Finished Jul 31 04:28:16 PM PDT 24
Peak memory 199644 kb
Host smart-ece546de-7e6e-46b3-962d-c5198db4c653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789610599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.3789610599
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2270061641
Short name T114
Test name
Test status
Simulation time 193569589829 ps
CPU time 1036.08 seconds
Started Jul 31 04:26:52 PM PDT 24
Finished Jul 31 04:44:09 PM PDT 24
Peak memory 199764 kb
Host smart-0a503475-3082-4264-822d-5c9741c65261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270061641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2270061641
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1751712988
Short name T803
Test name
Test status
Simulation time 106391012376 ps
CPU time 169.57 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 199776 kb
Host smart-43099f29-5f8d-4865-b9bc-dcc97a58e6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751712988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1751712988
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.991146262
Short name T147
Test name
Test status
Simulation time 191980496733 ps
CPU time 277.26 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:31:36 PM PDT 24
Peak memory 199636 kb
Host smart-c0d4cad9-31e1-4bbb-b8f8-15ae8f5db074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991146262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.991146262
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.2638213193
Short name T722
Test name
Test status
Simulation time 13273375077 ps
CPU time 13.42 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:06 PM PDT 24
Peak memory 199756 kb
Host smart-f6aad07b-d50c-4162-b2ef-1868c49dfb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638213193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.2638213193
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1487148408
Short name T711
Test name
Test status
Simulation time 18841327042 ps
CPU time 14.02 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199752 kb
Host smart-a53b5229-d2ea-42e8-8c01-42199e557042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487148408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1487148408
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3407540786
Short name T710
Test name
Test status
Simulation time 31830028624 ps
CPU time 51.01 seconds
Started Jul 31 04:26:56 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 199708 kb
Host smart-705bd994-a1a4-4b8c-8a71-6917c5de0a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407540786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3407540786
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2553644620
Short name T797
Test name
Test status
Simulation time 38777568 ps
CPU time 0.55 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:26:17 PM PDT 24
Peak memory 194444 kb
Host smart-311cb82e-65e0-4e1a-a96a-adcccfa1736c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553644620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2553644620
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.132314362
Short name T412
Test name
Test status
Simulation time 40304703445 ps
CPU time 13.8 seconds
Started Jul 31 04:24:08 PM PDT 24
Finished Jul 31 04:24:22 PM PDT 24
Peak memory 199756 kb
Host smart-3c181590-1099-4cc2-868e-4061169fa2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132314362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.132314362
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1217894786
Short name T949
Test name
Test status
Simulation time 34546747720 ps
CPU time 90.86 seconds
Started Jul 31 04:24:06 PM PDT 24
Finished Jul 31 04:25:37 PM PDT 24
Peak memory 199800 kb
Host smart-6c4d7cf0-c6e2-4926-9a68-4dd5bdeded81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217894786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1217894786
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.2387334647
Short name T214
Test name
Test status
Simulation time 72599126835 ps
CPU time 28.03 seconds
Started Jul 31 04:24:12 PM PDT 24
Finished Jul 31 04:24:40 PM PDT 24
Peak memory 199776 kb
Host smart-ad3767c1-0075-4579-a6a2-5769edf2f797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387334647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.2387334647
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3175759453
Short name T394
Test name
Test status
Simulation time 39997173659 ps
CPU time 58.03 seconds
Started Jul 31 04:26:01 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 198820 kb
Host smart-66ece301-71b0-4524-a1e6-3cf12c18d86c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175759453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3175759453
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.3700693796
Short name T279
Test name
Test status
Simulation time 103373049476 ps
CPU time 707.98 seconds
Started Jul 31 04:24:14 PM PDT 24
Finished Jul 31 04:36:02 PM PDT 24
Peak memory 199736 kb
Host smart-8ee1afee-c84b-4a9d-a563-3d3fb6854bd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3700693796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.3700693796
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.2538176996
Short name T576
Test name
Test status
Simulation time 1710544887 ps
CPU time 3.74 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:26:21 PM PDT 24
Peak memory 198464 kb
Host smart-6271f47f-262a-4970-a5a8-c8c76e51e338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538176996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.2538176996
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.662249199
Short name T826
Test name
Test status
Simulation time 39932814431 ps
CPU time 67.35 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:26:36 PM PDT 24
Peak memory 197884 kb
Host smart-099bd0d6-c571-476d-88d9-7224ecdd4397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662249199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.662249199
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.3437078082
Short name T748
Test name
Test status
Simulation time 9552587687 ps
CPU time 247.7 seconds
Started Jul 31 04:24:14 PM PDT 24
Finished Jul 31 04:28:22 PM PDT 24
Peak memory 199720 kb
Host smart-d074d369-0293-4bec-b485-d9cc300f6d0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3437078082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.3437078082
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.2802308507
Short name T573
Test name
Test status
Simulation time 2550062033 ps
CPU time 8.58 seconds
Started Jul 31 04:24:07 PM PDT 24
Finished Jul 31 04:24:15 PM PDT 24
Peak memory 198076 kb
Host smart-dd184e93-204d-4a48-8a61-802170d5a983
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802308507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.2802308507
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1513308148
Short name T106
Test name
Test status
Simulation time 32506824043 ps
CPU time 50.17 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199660 kb
Host smart-f8a8e595-dc21-424d-bf15-47c4744826fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513308148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1513308148
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2868605791
Short name T257
Test name
Test status
Simulation time 3031492541 ps
CPU time 1.8 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 195512 kb
Host smart-44115670-c1b2-4b55-af0b-27fd03f355fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868605791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2868605791
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4029168470
Short name T1157
Test name
Test status
Simulation time 650021348 ps
CPU time 2.51 seconds
Started Jul 31 04:24:10 PM PDT 24
Finished Jul 31 04:24:13 PM PDT 24
Peak memory 199336 kb
Host smart-844ff3bf-1448-41c5-8d69-f3177e818def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029168470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4029168470
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.810395235
Short name T1176
Test name
Test status
Simulation time 279986318747 ps
CPU time 538.92 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:34:36 PM PDT 24
Peak memory 199456 kb
Host smart-411a9fb1-f232-40c6-8070-6cb6f8a51a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810395235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.810395235
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3655603836
Short name T673
Test name
Test status
Simulation time 99899980965 ps
CPU time 262.29 seconds
Started Jul 31 04:24:19 PM PDT 24
Finished Jul 31 04:28:41 PM PDT 24
Peak memory 225980 kb
Host smart-39ac614e-d460-4694-b2d9-d4682d32253a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655603836 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3655603836
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2747104888
Short name T547
Test name
Test status
Simulation time 1263105105 ps
CPU time 1.95 seconds
Started Jul 31 04:24:15 PM PDT 24
Finished Jul 31 04:24:17 PM PDT 24
Peak memory 198148 kb
Host smart-b12be5eb-923d-4072-b9c6-6ddeef99ef2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747104888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2747104888
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.3142799887
Short name T449
Test name
Test status
Simulation time 46680216528 ps
CPU time 62.08 seconds
Started Jul 31 04:24:08 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 199716 kb
Host smart-0b9cb2c0-3f2f-4426-8579-adaf576483ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142799887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.3142799887
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.901563286
Short name T121
Test name
Test status
Simulation time 249879908909 ps
CPU time 64.41 seconds
Started Jul 31 04:26:55 PM PDT 24
Finished Jul 31 04:27:59 PM PDT 24
Peak memory 199808 kb
Host smart-90932a12-9b59-47dd-8aa7-2a1ae882e257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901563286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.901563286
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.772163002
Short name T455
Test name
Test status
Simulation time 36781450414 ps
CPU time 15.02 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199548 kb
Host smart-e1144893-a9e1-44d7-8ac1-c6182ecebc00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772163002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.772163002
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.446056340
Short name T677
Test name
Test status
Simulation time 101926123530 ps
CPU time 251.54 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:31:09 PM PDT 24
Peak memory 199800 kb
Host smart-afe8fd79-5b88-4c5b-9329-084b1d541d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446056340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.446056340
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.3275839486
Short name T920
Test name
Test status
Simulation time 102866046797 ps
CPU time 154.26 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:29:33 PM PDT 24
Peak memory 199656 kb
Host smart-b6089a37-8f4c-4842-bc65-8a9ac1ea0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275839486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.3275839486
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1885654263
Short name T191
Test name
Test status
Simulation time 35065720345 ps
CPU time 66.14 seconds
Started Jul 31 04:26:58 PM PDT 24
Finished Jul 31 04:28:05 PM PDT 24
Peak memory 199688 kb
Host smart-5d90dbed-b958-45e6-8deb-78e967edf18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885654263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1885654263
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.3783896808
Short name T630
Test name
Test status
Simulation time 46092493134 ps
CPU time 81.2 seconds
Started Jul 31 04:26:53 PM PDT 24
Finished Jul 31 04:28:14 PM PDT 24
Peak memory 199664 kb
Host smart-4cb339ff-904d-4ed6-ab5d-02dd2073461e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783896808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.3783896808
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.953530397
Short name T606
Test name
Test status
Simulation time 44955703795 ps
CPU time 33.3 seconds
Started Jul 31 04:26:54 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199740 kb
Host smart-ee39322a-42c0-45fc-bbc0-7f06777f7824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953530397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.953530397
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.3913118237
Short name T1030
Test name
Test status
Simulation time 29100771 ps
CPU time 0.56 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 193324 kb
Host smart-3c543dd3-fdcb-417a-8d9c-a826d6ad56b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913118237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.3913118237
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.284540782
Short name T1045
Test name
Test status
Simulation time 207175828500 ps
CPU time 148.48 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:28:57 PM PDT 24
Peak memory 199704 kb
Host smart-44ca7147-3e1d-454d-a255-6fabd9293212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284540782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.284540782
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.2930295256
Short name T597
Test name
Test status
Simulation time 71715018723 ps
CPU time 44.26 seconds
Started Jul 31 04:24:20 PM PDT 24
Finished Jul 31 04:25:04 PM PDT 24
Peak memory 199404 kb
Host smart-c093338d-4f09-4aba-b17e-0e8dfba8997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930295256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.2930295256
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.725819765
Short name T415
Test name
Test status
Simulation time 28803886182 ps
CPU time 47.8 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 199460 kb
Host smart-7a8d0c1c-86d3-4581-9072-3826d20995e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725819765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.725819765
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.2957154451
Short name T833
Test name
Test status
Simulation time 28061444537 ps
CPU time 14.93 seconds
Started Jul 31 04:24:14 PM PDT 24
Finished Jul 31 04:24:29 PM PDT 24
Peak memory 199808 kb
Host smart-833e9368-6b8b-44f4-a9f5-8e8cdc0f39d4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957154451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.2957154451
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.459626487
Short name T79
Test name
Test status
Simulation time 112647758124 ps
CPU time 683.05 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:37:05 PM PDT 24
Peak memory 199456 kb
Host smart-465a683e-cc31-4a89-9e81-5fb0fd211f06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=459626487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.459626487
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.110879103
Short name T974
Test name
Test status
Simulation time 1263635501 ps
CPU time 6.07 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 198324 kb
Host smart-b4cc85c7-90e5-4526-aa84-1e0413a7cbe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110879103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.110879103
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.3427478969
Short name T621
Test name
Test status
Simulation time 46991948715 ps
CPU time 111.88 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:28:09 PM PDT 24
Peak memory 207940 kb
Host smart-3ee8fc82-f2fb-447f-9809-e08086fe7ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427478969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.3427478969
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.1090996561
Short name T519
Test name
Test status
Simulation time 14206253910 ps
CPU time 422.29 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:31:24 PM PDT 24
Peak memory 199832 kb
Host smart-7688bfbc-8eb3-4f56-9448-e3d104d6942e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1090996561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.1090996561
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2157605959
Short name T515
Test name
Test status
Simulation time 4401716596 ps
CPU time 15.8 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 197088 kb
Host smart-fb689060-2891-4897-8f41-b141f877e91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2157605959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2157605959
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.479865446
Short name T828
Test name
Test status
Simulation time 13863809465 ps
CPU time 22.89 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 198936 kb
Host smart-6d9ed0d8-d76e-42c7-aaad-13085afd8662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479865446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.479865446
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3583463041
Short name T1002
Test name
Test status
Simulation time 41290232997 ps
CPU time 16.8 seconds
Started Jul 31 04:24:13 PM PDT 24
Finished Jul 31 04:24:30 PM PDT 24
Peak memory 195740 kb
Host smart-1de10826-5f5f-4fe4-b636-f06629e2eb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583463041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3583463041
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2252477615
Short name T525
Test name
Test status
Simulation time 101958105 ps
CPU time 0.82 seconds
Started Jul 31 04:24:19 PM PDT 24
Finished Jul 31 04:24:20 PM PDT 24
Peak memory 196672 kb
Host smart-06462a29-6749-48cf-9abb-0eaed98e0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252477615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2252477615
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.1555703320
Short name T293
Test name
Test status
Simulation time 138577397723 ps
CPU time 205.53 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:29:13 PM PDT 24
Peak memory 199736 kb
Host smart-b71b7557-d1dc-4f0f-8747-baae5c9e2e88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555703320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1555703320
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1619222884
Short name T692
Test name
Test status
Simulation time 219599076682 ps
CPU time 433.6 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:31:35 PM PDT 24
Peak memory 216344 kb
Host smart-25dbede0-8692-4fe7-b72b-2035b4d6d012
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619222884 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1619222884
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.2752002838
Short name T665
Test name
Test status
Simulation time 1033098311 ps
CPU time 3.05 seconds
Started Jul 31 04:24:21 PM PDT 24
Finished Jul 31 04:24:24 PM PDT 24
Peak memory 199148 kb
Host smart-f75c9005-3584-4dcd-84ab-52bf9d57109a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752002838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.2752002838
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.2144282620
Short name T694
Test name
Test status
Simulation time 43465226194 ps
CPU time 74.54 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199396 kb
Host smart-f7d399a1-1828-4df9-a1be-b3575e49498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144282620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.2144282620
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.1423264035
Short name T133
Test name
Test status
Simulation time 49708851702 ps
CPU time 18.49 seconds
Started Jul 31 04:27:01 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199112 kb
Host smart-1b2b97fc-564c-4e2d-9e10-6e0cce6a23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423264035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.1423264035
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.1544156708
Short name T168
Test name
Test status
Simulation time 37553009289 ps
CPU time 79.71 seconds
Started Jul 31 04:27:05 PM PDT 24
Finished Jul 31 04:28:25 PM PDT 24
Peak memory 199736 kb
Host smart-909dde16-29ca-4118-9fd3-96f68686db6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544156708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.1544156708
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.633218592
Short name T291
Test name
Test status
Simulation time 192617958827 ps
CPU time 17.77 seconds
Started Jul 31 04:27:06 PM PDT 24
Finished Jul 31 04:27:24 PM PDT 24
Peak memory 199576 kb
Host smart-7b2364f0-cf3f-4370-9e34-08cc100ba495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633218592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.633218592
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3255954227
Short name T989
Test name
Test status
Simulation time 36978331392 ps
CPU time 13.74 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:27:13 PM PDT 24
Peak memory 199808 kb
Host smart-2376b5c8-813b-447b-8582-e1e95abb796a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255954227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3255954227
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1854858026
Short name T385
Test name
Test status
Simulation time 22598391469 ps
CPU time 47.47 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 199800 kb
Host smart-cb58b0a6-aca5-44bd-822a-a349f9b40512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854858026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1854858026
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.3009410787
Short name T564
Test name
Test status
Simulation time 95626933059 ps
CPU time 163.95 seconds
Started Jul 31 04:27:06 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 199568 kb
Host smart-975ea181-3a3b-44c1-9073-23eeefb145de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009410787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.3009410787
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.1076241721
Short name T535
Test name
Test status
Simulation time 13751856580 ps
CPU time 12.29 seconds
Started Jul 31 04:26:59 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 199476 kb
Host smart-8b4ea098-09d3-4aa9-9630-9729e2cfefca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076241721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.1076241721
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4192824370
Short name T834
Test name
Test status
Simulation time 52947317387 ps
CPU time 84.75 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:28:27 PM PDT 24
Peak memory 199808 kb
Host smart-3b6d1237-3e76-42e7-8c5f-e12de1b5563b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192824370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4192824370
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1803761183
Short name T1042
Test name
Test status
Simulation time 18643833564 ps
CPU time 14.99 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 199764 kb
Host smart-8822a103-9637-4e6b-a73e-8823a7544b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803761183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1803761183
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3600855469
Short name T969
Test name
Test status
Simulation time 12273404 ps
CPU time 0.54 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 195048 kb
Host smart-05dafec7-3f60-48bf-86cc-fe7eb554ffdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600855469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3600855469
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3599935930
Short name T890
Test name
Test status
Simulation time 27613592478 ps
CPU time 34.14 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:23:09 PM PDT 24
Peak memory 199700 kb
Host smart-160056e0-0fe8-4a81-be7a-41ec7d40dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599935930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3599935930
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.3054124473
Short name T960
Test name
Test status
Simulation time 9627766626 ps
CPU time 17.96 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:22:53 PM PDT 24
Peak memory 199528 kb
Host smart-5361c3a1-ad69-4ba3-a431-f14abf0a3280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054124473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.3054124473
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.4007828259
Short name T172
Test name
Test status
Simulation time 55512627086 ps
CPU time 80.82 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 04:23:01 PM PDT 24
Peak memory 199712 kb
Host smart-e174d782-c4c7-4729-bc11-c77d327eccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007828259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.4007828259
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.2600005605
Short name T659
Test name
Test status
Simulation time 46169756943 ps
CPU time 34.52 seconds
Started Jul 31 04:22:48 PM PDT 24
Finished Jul 31 04:23:23 PM PDT 24
Peak memory 199484 kb
Host smart-56e63b15-6f0a-4c0b-96a9-f6e2317d2d00
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600005605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2600005605
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.326202493
Short name T578
Test name
Test status
Simulation time 50051745301 ps
CPU time 264.05 seconds
Started Jul 31 04:22:51 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199612 kb
Host smart-da6a71ce-dafb-4f11-a31b-de62fcf84169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326202493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.326202493
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.3303137626
Short name T342
Test name
Test status
Simulation time 12758543303 ps
CPU time 7.62 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:25:07 PM PDT 24
Peak memory 199616 kb
Host smart-be2aa9af-4146-4e2b-b72a-036461c26242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303137626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3303137626
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.1996126826
Short name T1080
Test name
Test status
Simulation time 229001584066 ps
CPU time 91.05 seconds
Started Jul 31 04:22:50 PM PDT 24
Finished Jul 31 04:24:21 PM PDT 24
Peak memory 199896 kb
Host smart-fc57ad66-7030-4d07-9568-3aad9a96fc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996126826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.1996126826
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.392276867
Short name T530
Test name
Test status
Simulation time 10682154337 ps
CPU time 657.07 seconds
Started Jul 31 04:22:48 PM PDT 24
Finished Jul 31 04:33:45 PM PDT 24
Peak memory 199736 kb
Host smart-ae43a4b9-96fc-4e39-8c77-15f3af686cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=392276867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.392276867
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.3625749486
Short name T324
Test name
Test status
Simulation time 6978596456 ps
CPU time 65.65 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:25:46 PM PDT 24
Peak memory 197208 kb
Host smart-31dceeb6-9aa9-46a5-8c25-2a0cdfd62a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3625749486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3625749486
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.1790799346
Short name T154
Test name
Test status
Simulation time 101508365720 ps
CPU time 51.42 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 199680 kb
Host smart-547766d5-9880-4f85-b400-f4c6ccb63155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790799346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.1790799346
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.2499661198
Short name T446
Test name
Test status
Simulation time 6650970933 ps
CPU time 1.82 seconds
Started Jul 31 04:21:31 PM PDT 24
Finished Jul 31 04:21:33 PM PDT 24
Peak memory 196068 kb
Host smart-17d438d8-f4e6-47fe-8ae2-2bc2c27b3339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499661198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.2499661198
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.910771940
Short name T69
Test name
Test status
Simulation time 131919019 ps
CPU time 0.83 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:22:27 PM PDT 24
Peak memory 217956 kb
Host smart-fdd221f9-95c2-43c0-bae8-db960d5f6f7b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910771940 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.910771940
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.2381254383
Short name T656
Test name
Test status
Simulation time 502000621 ps
CPU time 1.31 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:34 PM PDT 24
Peak memory 197160 kb
Host smart-430fcfe4-c457-413b-a8b9-14750f95e427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381254383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.2381254383
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.4233464947
Short name T913
Test name
Test status
Simulation time 97603635880 ps
CPU time 104.87 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:27:26 PM PDT 24
Peak memory 199612 kb
Host smart-a838e3f2-1028-474b-b3a2-eeefcc1b9cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233464947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4233464947
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.371988146
Short name T42
Test name
Test status
Simulation time 163005984171 ps
CPU time 614.12 seconds
Started Jul 31 04:23:31 PM PDT 24
Finished Jul 31 04:33:46 PM PDT 24
Peak memory 216440 kb
Host smart-8cb9aebc-ea6b-4882-848e-f2ba4fffc562
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371988146 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.371988146
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.1767284463
Short name T841
Test name
Test status
Simulation time 1530396323 ps
CPU time 2.46 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 197608 kb
Host smart-0cc5c3d9-0839-4e37-9406-f00667a70a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767284463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.1767284463
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.4227748041
Short name T824
Test name
Test status
Simulation time 43874185600 ps
CPU time 71.85 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 199608 kb
Host smart-d4158b38-d910-4dd9-be84-befbb3cc087f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227748041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.4227748041
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3496882390
Short name T715
Test name
Test status
Simulation time 33689415 ps
CPU time 0.56 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 195128 kb
Host smart-623a3104-7d01-4ee7-a22b-0c07fe076e9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496882390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3496882390
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.1821710388
Short name T805
Test name
Test status
Simulation time 149127873283 ps
CPU time 128.06 seconds
Started Jul 31 04:24:17 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 199800 kb
Host smart-0c0fdffe-016e-46f3-b902-e740b0d73b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821710388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.1821710388
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.1324467437
Short name T763
Test name
Test status
Simulation time 47688307471 ps
CPU time 19.07 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 199720 kb
Host smart-430cb804-77e6-47b0-b476-5238813f6986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324467437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1324467437
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.4154903308
Short name T297
Test name
Test status
Simulation time 106129466269 ps
CPU time 76.28 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 199504 kb
Host smart-7733cb0b-44e5-47ae-86b1-cc3411350df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154903308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.4154903308
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.2802607224
Short name T1103
Test name
Test status
Simulation time 66991985245 ps
CPU time 96.33 seconds
Started Jul 31 04:24:33 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 199736 kb
Host smart-b50800c4-b1dc-4eb4-a132-9128c6687abf
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802607224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.2802607224
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.596273444
Short name T778
Test name
Test status
Simulation time 150395499903 ps
CPU time 339.46 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:31:28 PM PDT 24
Peak memory 199712 kb
Host smart-12edb660-e982-4346-8701-5ba425438230
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=596273444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.596273444
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.1221758260
Short name T522
Test name
Test status
Simulation time 10430017385 ps
CPU time 3.61 seconds
Started Jul 31 04:24:37 PM PDT 24
Finished Jul 31 04:24:40 PM PDT 24
Peak memory 199656 kb
Host smart-4695221c-6ffa-4bb3-8bce-8aa775bbe8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221758260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.1221758260
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.1761481444
Short name T972
Test name
Test status
Simulation time 44962858440 ps
CPU time 25.64 seconds
Started Jul 31 04:24:26 PM PDT 24
Finished Jul 31 04:24:52 PM PDT 24
Peak memory 198536 kb
Host smart-b90212c8-ee36-4201-8229-859c230cdddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761481444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.1761481444
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.3803659003
Short name T767
Test name
Test status
Simulation time 27794375005 ps
CPU time 1386.48 seconds
Started Jul 31 04:24:23 PM PDT 24
Finished Jul 31 04:47:29 PM PDT 24
Peak memory 199676 kb
Host smart-1656d5bd-26e1-455b-b870-5e7377b51d10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3803659003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3803659003
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.777359228
Short name T479
Test name
Test status
Simulation time 1274304088 ps
CPU time 5.41 seconds
Started Jul 31 04:24:26 PM PDT 24
Finished Jul 31 04:24:32 PM PDT 24
Peak memory 197600 kb
Host smart-b1dd409a-35f0-4075-9628-3a7b7ef25d0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=777359228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.777359228
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.3962955825
Short name T11
Test name
Test status
Simulation time 65369458286 ps
CPU time 51.33 seconds
Started Jul 31 04:24:26 PM PDT 24
Finished Jul 31 04:25:17 PM PDT 24
Peak memory 199648 kb
Host smart-37a46d5c-f039-4800-baad-4b79f80d146f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962955825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.3962955825
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3741697351
Short name T520
Test name
Test status
Simulation time 44424706716 ps
CPU time 5.05 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 195316 kb
Host smart-f190587d-ebc0-4d30-8b35-1b65486d0e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741697351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3741697351
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.886344030
Short name T637
Test name
Test status
Simulation time 5899052331 ps
CPU time 6.52 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 199012 kb
Host smart-5831dcde-61ce-439e-9739-f9c3768eb8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886344030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.886344030
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2657244528
Short name T666
Test name
Test status
Simulation time 326780319536 ps
CPU time 227.75 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:29:36 PM PDT 24
Peak memory 199652 kb
Host smart-f878429f-4a61-46f9-8722-0c3b86bfac3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657244528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2657244528
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2908060705
Short name T3
Test name
Test status
Simulation time 87883153163 ps
CPU time 615.53 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:34:56 PM PDT 24
Peak memory 216252 kb
Host smart-afd02b8e-8db0-4f70-ba81-04506f3ed91f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908060705 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2908060705
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3514085740
Short name T874
Test name
Test status
Simulation time 1750030201 ps
CPU time 1.84 seconds
Started Jul 31 04:24:35 PM PDT 24
Finished Jul 31 04:24:37 PM PDT 24
Peak memory 199584 kb
Host smart-1cd37573-4e8d-4786-817f-89e85b525eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514085740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3514085740
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.2631811123
Short name T977
Test name
Test status
Simulation time 70997659615 ps
CPU time 201.31 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:29:09 PM PDT 24
Peak memory 199720 kb
Host smart-c2f294ca-e6b0-4af9-9171-6df7db4a74d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631811123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2631811123
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.124521338
Short name T208
Test name
Test status
Simulation time 26906599794 ps
CPU time 36.46 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199672 kb
Host smart-6cd6818b-fd04-4e09-93f3-e80973a7d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124521338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.124521338
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.3585822178
Short name T1161
Test name
Test status
Simulation time 12170518641 ps
CPU time 8.01 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:27:10 PM PDT 24
Peak memory 199608 kb
Host smart-b1abb8ed-400a-4014-935b-1c3d6c06ffd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585822178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.3585822178
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.712386991
Short name T849
Test name
Test status
Simulation time 51840183460 ps
CPU time 77.56 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:28:18 PM PDT 24
Peak memory 199800 kb
Host smart-17d3f21f-bea2-4d3a-9527-6b9496d6a128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712386991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.712386991
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.4036278443
Short name T1094
Test name
Test status
Simulation time 35369132662 ps
CPU time 55.86 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199720 kb
Host smart-b625d853-1439-4840-adb8-5454bfa1a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036278443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.4036278443
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.2951180642
Short name T835
Test name
Test status
Simulation time 25229059809 ps
CPU time 40.24 seconds
Started Jul 31 04:27:06 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199676 kb
Host smart-31c982ea-c5e8-488f-9443-9da2b9b9286b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951180642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.2951180642
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.452164902
Short name T348
Test name
Test status
Simulation time 20569297 ps
CPU time 0.55 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 195092 kb
Host smart-ba9128b6-c85f-440b-a5ae-b501636e6e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452164902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.452164902
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.941589083
Short name T442
Test name
Test status
Simulation time 24776296921 ps
CPU time 10.38 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:58 PM PDT 24
Peak memory 198628 kb
Host smart-92b81d0f-b4fe-4af1-a7e9-78757fa53164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941589083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.941589083
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.285609529
Short name T136
Test name
Test status
Simulation time 35503450349 ps
CPU time 14.58 seconds
Started Jul 31 04:24:26 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 199348 kb
Host smart-32a65341-1668-4450-a753-c186070564f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285609529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.285609529
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3051215772
Short name T757
Test name
Test status
Simulation time 56111796536 ps
CPU time 82.03 seconds
Started Jul 31 04:24:26 PM PDT 24
Finished Jul 31 04:25:48 PM PDT 24
Peak memory 199696 kb
Host smart-fedc7a6c-41a6-44b7-a48c-de6d0d1101a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051215772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3051215772
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3821569284
Short name T807
Test name
Test status
Simulation time 186560248709 ps
CPU time 251.59 seconds
Started Jul 31 04:24:31 PM PDT 24
Finished Jul 31 04:28:43 PM PDT 24
Peak memory 199052 kb
Host smart-07b5f652-4ebd-47e8-831e-5a4e6ece84db
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821569284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3821569284
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.1011732496
Short name T690
Test name
Test status
Simulation time 91109062684 ps
CPU time 275.01 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:29:16 PM PDT 24
Peak memory 199732 kb
Host smart-771803ce-d515-4b08-aeb8-34a4c2c03da6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011732496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.1011732496
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.4068029425
Short name T699
Test name
Test status
Simulation time 5808416400 ps
CPU time 4.53 seconds
Started Jul 31 04:24:36 PM PDT 24
Finished Jul 31 04:24:41 PM PDT 24
Peak memory 199452 kb
Host smart-81966edd-6b9b-45cc-997a-53bcb69e10d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068029425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.4068029425
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.818448788
Short name T625
Test name
Test status
Simulation time 71120587853 ps
CPU time 110.93 seconds
Started Jul 31 04:24:24 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 208136 kb
Host smart-c8901b8a-aa6e-4c7b-af6e-827a83d6c20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818448788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.818448788
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.2345686533
Short name T381
Test name
Test status
Simulation time 19826428680 ps
CPU time 831.68 seconds
Started Jul 31 04:24:36 PM PDT 24
Finished Jul 31 04:38:28 PM PDT 24
Peak memory 199792 kb
Host smart-07ae5ce2-7d79-4aad-896a-29aa64f0ed30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345686533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.2345686533
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3514749604
Short name T335
Test name
Test status
Simulation time 3404867988 ps
CPU time 2.71 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:46 PM PDT 24
Peak memory 197680 kb
Host smart-b86c59d2-d94c-44e8-a7ad-3f7294fa1032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3514749604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3514749604
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.4242321852
Short name T700
Test name
Test status
Simulation time 43347046477 ps
CPU time 76.59 seconds
Started Jul 31 04:24:35 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 199648 kb
Host smart-e7e5d5fc-bf4e-44d2-808d-94874b720c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242321852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.4242321852
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3621510551
Short name T1007
Test name
Test status
Simulation time 3254760943 ps
CPU time 1.84 seconds
Started Jul 31 04:24:33 PM PDT 24
Finished Jul 31 04:24:35 PM PDT 24
Peak memory 195732 kb
Host smart-95a627cf-39e5-4cc1-b543-e8ade7f357f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621510551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3621510551
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2445895864
Short name T954
Test name
Test status
Simulation time 6247659054 ps
CPU time 19.5 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 198860 kb
Host smart-d56074e2-f79b-4685-9b1e-d1086167f988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445895864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2445895864
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.686193662
Short name T489
Test name
Test status
Simulation time 440202783772 ps
CPU time 103.39 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 199740 kb
Host smart-f7637ead-7750-4721-9fb9-682321bf205c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686193662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.686193662
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.581045235
Short name T927
Test name
Test status
Simulation time 145349280715 ps
CPU time 339.19 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:30:19 PM PDT 24
Peak memory 225908 kb
Host smart-8318150b-21c8-439e-b65d-bf8015ce8c71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581045235 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.581045235
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2724856087
Short name T552
Test name
Test status
Simulation time 6617624593 ps
CPU time 25.47 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 199744 kb
Host smart-a22a5aee-7eb2-49d8-8617-500fef8eddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724856087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2724856087
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.1754687050
Short name T1137
Test name
Test status
Simulation time 62976237355 ps
CPU time 103.92 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199720 kb
Host smart-3f0b8962-1062-4b68-b273-ac1a833ee87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754687050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.1754687050
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.674450339
Short name T717
Test name
Test status
Simulation time 15907145920 ps
CPU time 38.68 seconds
Started Jul 31 04:27:02 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199776 kb
Host smart-57d1993c-80ee-4f2d-92b4-34827b7aeb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674450339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.674450339
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.78142072
Short name T193
Test name
Test status
Simulation time 158838809779 ps
CPU time 58.16 seconds
Started Jul 31 04:27:00 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199712 kb
Host smart-5740aeb6-4fe7-4356-befa-99b86cbd2a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78142072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.78142072
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.1241089893
Short name T546
Test name
Test status
Simulation time 35041446617 ps
CPU time 26.04 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:33 PM PDT 24
Peak memory 199756 kb
Host smart-549cd3bf-8824-4a57-904a-c33c4a8290ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241089893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.1241089893
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2741467156
Short name T271
Test name
Test status
Simulation time 17584019069 ps
CPU time 7.03 seconds
Started Jul 31 04:27:06 PM PDT 24
Finished Jul 31 04:27:13 PM PDT 24
Peak memory 199744 kb
Host smart-9723a9d0-7573-45d9-a74c-7a744c8dc080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741467156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2741467156
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.284183199
Short name T207
Test name
Test status
Simulation time 62632908782 ps
CPU time 30.56 seconds
Started Jul 31 04:27:05 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199720 kb
Host smart-472ca1a4-7e62-42e4-97d9-8d371090fcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284183199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.284183199
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.2411846626
Short name T873
Test name
Test status
Simulation time 81322985374 ps
CPU time 33.75 seconds
Started Jul 31 04:27:05 PM PDT 24
Finished Jul 31 04:27:39 PM PDT 24
Peak memory 199664 kb
Host smart-bcd9da4d-2503-4c17-899b-5cbbb136669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411846626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.2411846626
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.3912502634
Short name T1026
Test name
Test status
Simulation time 159636707975 ps
CPU time 338.76 seconds
Started Jul 31 04:27:04 PM PDT 24
Finished Jul 31 04:32:43 PM PDT 24
Peak memory 199764 kb
Host smart-14f2cee7-86ff-490b-a824-ef286bf39201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912502634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3912502634
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.3373872548
Short name T255
Test name
Test status
Simulation time 82510105880 ps
CPU time 98.02 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:28:45 PM PDT 24
Peak memory 199648 kb
Host smart-d5ee3417-f493-4e19-9037-3960d337871d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373872548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.3373872548
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.143863479
Short name T425
Test name
Test status
Simulation time 13080028 ps
CPU time 0.57 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 195128 kb
Host smart-1888fb9e-e25c-47a3-be70-f43733afc97b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143863479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.143863479
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2335068442
Short name T131
Test name
Test status
Simulation time 55936764725 ps
CPU time 15.04 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 199648 kb
Host smart-5ab1846e-230c-4ef4-acb2-508cfb0b1433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335068442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2335068442
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2579396078
Short name T632
Test name
Test status
Simulation time 175490662554 ps
CPU time 272.7 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:29:20 PM PDT 24
Peak memory 199656 kb
Host smart-d961a36b-ea88-4672-a579-660be5adca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579396078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2579396078
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.2705685667
Short name T753
Test name
Test status
Simulation time 10172731790 ps
CPU time 19.53 seconds
Started Jul 31 04:24:36 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 199632 kb
Host smart-0667e8ae-2411-46e9-8378-aab2c0307185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705685667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.2705685667
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.2034141577
Short name T944
Test name
Test status
Simulation time 27260907644 ps
CPU time 53.67 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:25:36 PM PDT 24
Peak memory 199628 kb
Host smart-b1048525-0737-4c45-859f-fd6341b8b72c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034141577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2034141577
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.1559434606
Short name T337
Test name
Test status
Simulation time 218110595236 ps
CPU time 347.49 seconds
Started Jul 31 04:24:59 PM PDT 24
Finished Jul 31 04:30:47 PM PDT 24
Peak memory 199736 kb
Host smart-de491625-7d9e-4e7b-acd8-a53a7cf65d5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559434606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.1559434606
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.1511169348
Short name T341
Test name
Test status
Simulation time 1600723711 ps
CPU time 1.39 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:24:47 PM PDT 24
Peak memory 198388 kb
Host smart-45d942a2-6c3d-44ba-9f3a-0babedee1aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511169348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.1511169348
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.2806588585
Short name T991
Test name
Test status
Simulation time 48352583709 ps
CPU time 23.76 seconds
Started Jul 31 04:24:37 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 207876 kb
Host smart-93c806b2-4514-4e4e-b884-3ea713e47d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806588585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.2806588585
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3618859395
Short name T1147
Test name
Test status
Simulation time 23258410841 ps
CPU time 1162.66 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:44:05 PM PDT 24
Peak memory 199772 kb
Host smart-a15e4532-c1c3-49d9-b0db-3c8d640a87a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618859395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3618859395
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1381104763
Short name T406
Test name
Test status
Simulation time 4527742943 ps
CPU time 35.85 seconds
Started Jul 31 04:24:45 PM PDT 24
Finished Jul 31 04:25:21 PM PDT 24
Peak memory 198964 kb
Host smart-818a0840-bd2b-4e6a-abab-fc1061b8ba2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381104763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1381104763
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.2904615541
Short name T445
Test name
Test status
Simulation time 53754258156 ps
CPU time 70.97 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 199676 kb
Host smart-cdcb8aad-59b2-4c6c-9449-c4aa9883621d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904615541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.2904615541
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3708788007
Short name T579
Test name
Test status
Simulation time 42802076497 ps
CPU time 13.66 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:25:01 PM PDT 24
Peak memory 196056 kb
Host smart-9e692ad3-7ec8-4ef9-929a-10ebdb2ba8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708788007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3708788007
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.2504434357
Short name T301
Test name
Test status
Simulation time 108624924 ps
CPU time 0.82 seconds
Started Jul 31 04:24:36 PM PDT 24
Finished Jul 31 04:24:37 PM PDT 24
Peak memory 197104 kb
Host smart-aeb9fcd6-dde8-4c42-8511-00b22547cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504434357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.2504434357
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.3780984479
Short name T1175
Test name
Test status
Simulation time 57953397740 ps
CPU time 139.72 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:28:33 PM PDT 24
Peak memory 197684 kb
Host smart-410f6b05-288f-42e7-9861-429d53c38339
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780984479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3780984479
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.134022099
Short name T904
Test name
Test status
Simulation time 1432880815 ps
CPU time 2.2 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:24:45 PM PDT 24
Peak memory 198548 kb
Host smart-bb800073-d163-4cac-9b48-47b4e1cc3ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134022099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.134022099
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3862205171
Short name T843
Test name
Test status
Simulation time 80715364190 ps
CPU time 20.2 seconds
Started Jul 31 04:24:36 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 199696 kb
Host smart-de172a9b-01a1-411a-9397-7937d60e4277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862205171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3862205171
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.495249385
Short name T1086
Test name
Test status
Simulation time 138028541020 ps
CPU time 131.22 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:29:18 PM PDT 24
Peak memory 199772 kb
Host smart-e4352d11-4bb5-4653-bf70-8f726dec0ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495249385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.495249385
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3035948635
Short name T100
Test name
Test status
Simulation time 172709205360 ps
CPU time 71.46 seconds
Started Jul 31 04:27:06 PM PDT 24
Finished Jul 31 04:28:18 PM PDT 24
Peak memory 199780 kb
Host smart-e4eebd00-1ce9-4bbc-805f-3e9041df901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035948635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3035948635
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.2206276320
Short name T912
Test name
Test status
Simulation time 15632065108 ps
CPU time 25.41 seconds
Started Jul 31 04:27:10 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199800 kb
Host smart-a801a1bc-c34a-4fc6-9553-330c8116cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206276320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.2206276320
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1067232821
Short name T822
Test name
Test status
Simulation time 56560840773 ps
CPU time 22.3 seconds
Started Jul 31 04:27:08 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199720 kb
Host smart-6237e75f-f26f-448f-93db-284cde6cbd03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067232821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1067232821
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.4231095649
Short name T794
Test name
Test status
Simulation time 16158437388 ps
CPU time 3.64 seconds
Started Jul 31 04:27:05 PM PDT 24
Finished Jul 31 04:27:09 PM PDT 24
Peak memory 199624 kb
Host smart-07145be1-ed9e-45cd-a58b-82f58139ac27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231095649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.4231095649
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.2572362398
Short name T321
Test name
Test status
Simulation time 33326247413 ps
CPU time 21.69 seconds
Started Jul 31 04:27:05 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 199652 kb
Host smart-633ce9e8-f361-4f13-bac7-7aa4938facec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572362398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.2572362398
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.1423572264
Short name T305
Test name
Test status
Simulation time 103320607507 ps
CPU time 68.54 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:28:15 PM PDT 24
Peak memory 199832 kb
Host smart-4d5dfb7a-9ed0-4cb6-bacb-8cd08386993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423572264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.1423572264
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.682229234
Short name T961
Test name
Test status
Simulation time 104290373126 ps
CPU time 407.76 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:33:55 PM PDT 24
Peak memory 199644 kb
Host smart-98472eef-f46e-4e94-8b4a-00bb39cf4de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682229234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.682229234
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.240039083
Short name T802
Test name
Test status
Simulation time 8125720108 ps
CPU time 13.83 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:21 PM PDT 24
Peak memory 199460 kb
Host smart-a4efb453-1bac-45c3-aa2d-c1c97cffb67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240039083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.240039083
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.3333092173
Short name T1051
Test name
Test status
Simulation time 19441646 ps
CPU time 0.61 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 195408 kb
Host smart-475fd24a-b200-4bff-9ad2-5cca195c0b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333092173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.3333092173
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.3449171655
Short name T266
Test name
Test status
Simulation time 32825051540 ps
CPU time 46.34 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 199720 kb
Host smart-bf152420-38ae-48fd-b95e-d0fed3481111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449171655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.3449171655
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.2691698562
Short name T633
Test name
Test status
Simulation time 9429861605 ps
CPU time 15.95 seconds
Started Jul 31 04:24:48 PM PDT 24
Finished Jul 31 04:25:05 PM PDT 24
Peak memory 199536 kb
Host smart-1f7ca88c-781d-4174-853c-e6143d0258c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691698562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2691698562
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2660085663
Short name T173
Test name
Test status
Simulation time 281570421449 ps
CPU time 41.14 seconds
Started Jul 31 04:24:48 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 199684 kb
Host smart-de9fb25c-74be-4c87-bc30-f03fc603a86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660085663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2660085663
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.2143676426
Short name T922
Test name
Test status
Simulation time 57520751158 ps
CPU time 88.45 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:26:19 PM PDT 24
Peak memory 199796 kb
Host smart-906b59e5-0f30-4a57-91ac-6d1eb8b76cb5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143676426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.2143676426
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.3499727098
Short name T1090
Test name
Test status
Simulation time 64524298210 ps
CPU time 92.95 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:28:00 PM PDT 24
Peak memory 199676 kb
Host smart-c6d09d5d-9c33-4fff-83c1-66f201588670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3499727098 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.3499727098
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.3230525270
Short name T1025
Test name
Test status
Simulation time 5729647738 ps
CPU time 13.8 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 198864 kb
Host smart-11a64921-016e-4457-981f-e950573be3cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230525270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.3230525270
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.1316551598
Short name T384
Test name
Test status
Simulation time 50240742757 ps
CPU time 81.07 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 199916 kb
Host smart-f5ef9a0a-b51f-4bd4-a8c6-c97ac8c95813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316551598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1316551598
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.2736765927
Short name T798
Test name
Test status
Simulation time 19825180600 ps
CPU time 210.41 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:29:59 PM PDT 24
Peak memory 199684 kb
Host smart-64a7da3f-52fd-440f-86dc-22c9d04ec930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736765927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.2736765927
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1229989528
Short name T509
Test name
Test status
Simulation time 3550978190 ps
CPU time 24.32 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:25:15 PM PDT 24
Peak memory 197916 kb
Host smart-a5217b1c-a09f-4b0d-82d3-bf039933b798
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229989528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1229989528
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1819349668
Short name T784
Test name
Test status
Simulation time 133573237082 ps
CPU time 19.3 seconds
Started Jul 31 04:24:51 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 199800 kb
Host smart-e500a64b-3477-4330-9fc6-8d159a5e39dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819349668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1819349668
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.36333874
Short name T553
Test name
Test status
Simulation time 4223263864 ps
CPU time 3.54 seconds
Started Jul 31 04:24:50 PM PDT 24
Finished Jul 31 04:24:54 PM PDT 24
Peak memory 196020 kb
Host smart-a9d41c10-4bd1-4afe-adc0-b0db1fd7ee1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36333874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.36333874
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1672889826
Short name T667
Test name
Test status
Simulation time 89003043 ps
CPU time 0.84 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 194752 kb
Host smart-684595c9-7988-4c0b-a1b1-a64f93638859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672889826 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1672889826
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.1380400787
Short name T148
Test name
Test status
Simulation time 350167112095 ps
CPU time 1450.04 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:49:05 PM PDT 24
Peak memory 199828 kb
Host smart-7485d62a-8403-4bf8-871a-7c5eccff3969
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380400787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.1380400787
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.1774421440
Short name T39
Test name
Test status
Simulation time 45683667103 ps
CPU time 313.18 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:30:09 PM PDT 24
Peak memory 215232 kb
Host smart-31f818d9-4d96-4492-ade3-2cb70c279692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774421440 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.1774421440
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.868533244
Short name T436
Test name
Test status
Simulation time 1834552048 ps
CPU time 1.77 seconds
Started Jul 31 04:24:48 PM PDT 24
Finished Jul 31 04:24:50 PM PDT 24
Peak memory 198904 kb
Host smart-41ef45ba-d806-497b-9304-7bc4a7256aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868533244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.868533244
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.970917640
Short name T1148
Test name
Test status
Simulation time 69963760191 ps
CPU time 59.66 seconds
Started Jul 31 04:24:43 PM PDT 24
Finished Jul 31 04:25:43 PM PDT 24
Peak memory 199864 kb
Host smart-91ae7802-2f10-424b-9d19-59dfdf546f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970917640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.970917640
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.3398869125
Short name T811
Test name
Test status
Simulation time 70875170017 ps
CPU time 25.27 seconds
Started Jul 31 04:27:10 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199692 kb
Host smart-b2cdffd2-cc23-4ce4-8751-36ef4955ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398869125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.3398869125
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1780801315
Short name T259
Test name
Test status
Simulation time 193669840728 ps
CPU time 70.22 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:28:17 PM PDT 24
Peak memory 199704 kb
Host smart-3ca85077-e2ea-4a54-a40b-d507a30cd854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780801315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1780801315
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.4146323109
Short name T138
Test name
Test status
Simulation time 33296421729 ps
CPU time 26.32 seconds
Started Jul 31 04:27:11 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199732 kb
Host smart-76f57797-9050-4acd-92d0-9dff37ddceff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146323109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.4146323109
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2740812917
Short name T1085
Test name
Test status
Simulation time 63303523665 ps
CPU time 101.5 seconds
Started Jul 31 04:27:10 PM PDT 24
Finished Jul 31 04:28:52 PM PDT 24
Peak memory 199736 kb
Host smart-b2eb4d06-0182-445d-b6a2-a980c5901d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740812917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2740812917
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.2327201267
Short name T198
Test name
Test status
Simulation time 199403939582 ps
CPU time 78.47 seconds
Started Jul 31 04:27:04 PM PDT 24
Finished Jul 31 04:28:23 PM PDT 24
Peak memory 199696 kb
Host smart-fced5ec0-7a98-4ed9-94d9-9c74019d792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327201267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2327201267
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.2858630342
Short name T157
Test name
Test status
Simulation time 193809470572 ps
CPU time 66.59 seconds
Started Jul 31 04:27:04 PM PDT 24
Finished Jul 31 04:28:11 PM PDT 24
Peak memory 199624 kb
Host smart-955780db-4af4-4e7f-aa97-453d61cef8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858630342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.2858630342
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3681048178
Short name T323
Test name
Test status
Simulation time 34390699219 ps
CPU time 75.27 seconds
Started Jul 31 04:27:09 PM PDT 24
Finished Jul 31 04:28:24 PM PDT 24
Peak memory 199740 kb
Host smart-6aa3d344-0579-452a-9739-b60bf31f1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681048178 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3681048178
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.1533502617
Short name T720
Test name
Test status
Simulation time 36975846686 ps
CPU time 33.04 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:40 PM PDT 24
Peak memory 199840 kb
Host smart-93cdcc71-fe66-4c6b-a058-3924b2ff16ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533502617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.1533502617
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1893340667
Short name T1120
Test name
Test status
Simulation time 199581994407 ps
CPU time 65.7 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:26:03 PM PDT 24
Peak memory 199648 kb
Host smart-d2855dff-1cb8-4861-a8eb-4665f85759f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893340667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1893340667
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2207840685
Short name T964
Test name
Test status
Simulation time 3410330702 ps
CPU time 2.18 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 199552 kb
Host smart-5fe06c97-35c7-4af8-9b1b-7fd39778736c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207840685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2207840685
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.73517076
Short name T232
Test name
Test status
Simulation time 26919601900 ps
CPU time 12.48 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:26:42 PM PDT 24
Peak memory 199680 kb
Host smart-d2b85519-9928-4a37-a90c-9dd6bc5030e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73517076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.73517076
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.160682566
Short name T942
Test name
Test status
Simulation time 41414208347 ps
CPU time 34.1 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:25:31 PM PDT 24
Peak memory 199592 kb
Host smart-e9a1547b-f780-41e2-86c4-339e0ef1a284
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160682566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.160682566
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.94400170
Short name T1052
Test name
Test status
Simulation time 57861220918 ps
CPU time 202.13 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:28:24 PM PDT 24
Peak memory 199868 kb
Host smart-6325f3b2-a8fc-458f-8524-b0ee3997c815
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=94400170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.94400170
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.1947877458
Short name T892
Test name
Test status
Simulation time 1894593729 ps
CPU time 2.39 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:03 PM PDT 24
Peak memory 196764 kb
Host smart-05102f1b-c50d-4604-a28c-8aaad09ef191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947877458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.1947877458
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.275213204
Short name T306
Test name
Test status
Simulation time 58750080719 ps
CPU time 105.8 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:26:54 PM PDT 24
Peak memory 208136 kb
Host smart-4812d08d-b7ae-4e84-9b25-b691f0fc1ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275213204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.275213204
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.1059671882
Short name T685
Test name
Test status
Simulation time 20389360822 ps
CPU time 1049.66 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:42:35 PM PDT 24
Peak memory 199716 kb
Host smart-b2cdd609-315b-473b-aa24-617ed2dd72de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1059671882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.1059671882
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.3701387627
Short name T1
Test name
Test status
Simulation time 3284298017 ps
CPU time 13.35 seconds
Started Jul 31 04:24:57 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 198020 kb
Host smart-0f9a8337-8ca2-44cb-9ba2-f11c4bf91b09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3701387627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.3701387627
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.650176136
Short name T817
Test name
Test status
Simulation time 25505615383 ps
CPU time 12.36 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:25:18 PM PDT 24
Peak memory 199800 kb
Host smart-4066d550-1ef8-415e-bcc4-445f961279ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650176136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.650176136
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.3812204417
Short name T409
Test name
Test status
Simulation time 1822046031 ps
CPU time 2 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 195420 kb
Host smart-3c0f51b4-c07f-4356-84c1-29b5848c482e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812204417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3812204417
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.1935644278
Short name T836
Test name
Test status
Simulation time 723857559 ps
CPU time 1.27 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:24:56 PM PDT 24
Peak memory 198196 kb
Host smart-abfaed7b-5e34-4b67-a8d0-f35df085eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935644278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.1935644278
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.1058275317
Short name T282
Test name
Test status
Simulation time 470663590897 ps
CPU time 1504.13 seconds
Started Jul 31 04:25:09 PM PDT 24
Finished Jul 31 04:50:13 PM PDT 24
Peak memory 230228 kb
Host smart-b63d5aef-5565-4f4d-909d-05777d851cdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058275317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.1058275317
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2953871381
Short name T526
Test name
Test status
Simulation time 8346198419 ps
CPU time 10.09 seconds
Started Jul 31 04:25:06 PM PDT 24
Finished Jul 31 04:25:16 PM PDT 24
Peak memory 199736 kb
Host smart-e27ef0f9-b80b-41a9-96e4-b5d3b5ac4198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953871381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2953871381
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.2727345884
Short name T494
Test name
Test status
Simulation time 6304424236 ps
CPU time 10.25 seconds
Started Jul 31 04:24:55 PM PDT 24
Finished Jul 31 04:25:05 PM PDT 24
Peak memory 198524 kb
Host smart-3f20a9b5-31a5-4e1f-a304-c4226a05e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727345884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.2727345884
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.2302587508
Short name T448
Test name
Test status
Simulation time 26475556458 ps
CPU time 12.2 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199728 kb
Host smart-0da2fd02-c4b9-4cd9-bb3b-5e3ce5fdcd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302587508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2302587508
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.3405923058
Short name T868
Test name
Test status
Simulation time 37394717073 ps
CPU time 82.01 seconds
Started Jul 31 04:27:08 PM PDT 24
Finished Jul 31 04:28:30 PM PDT 24
Peak memory 199720 kb
Host smart-9d94f666-dc4f-49b7-b20d-bbc4abb424dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405923058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3405923058
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.911742359
Short name T189
Test name
Test status
Simulation time 32717410423 ps
CPU time 24.23 seconds
Started Jul 31 04:27:07 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199688 kb
Host smart-dba4e2db-99d1-45a6-a685-5d4a950234b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911742359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.911742359
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.243886348
Short name T850
Test name
Test status
Simulation time 39331089402 ps
CPU time 16.2 seconds
Started Jul 31 04:27:12 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199684 kb
Host smart-b9882853-733e-4cf3-b01f-35dcad9d8132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243886348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.243886348
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2622793888
Short name T1038
Test name
Test status
Simulation time 211745167752 ps
CPU time 106.9 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:29:00 PM PDT 24
Peak memory 199708 kb
Host smart-e61620f2-e88f-4ac7-b794-fb5215b6617e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622793888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2622793888
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.3659139908
Short name T858
Test name
Test status
Simulation time 37050387620 ps
CPU time 62.2 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:28:16 PM PDT 24
Peak memory 199712 kb
Host smart-3566d09c-e204-4030-9b4a-c23f1b0d8b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659139908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.3659139908
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3982466756
Short name T1121
Test name
Test status
Simulation time 41284771971 ps
CPU time 37.75 seconds
Started Jul 31 04:27:14 PM PDT 24
Finished Jul 31 04:27:51 PM PDT 24
Peak memory 199680 kb
Host smart-cb8b6049-2234-4ac9-820b-7c542743862d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982466756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3982466756
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3643686029
Short name T108
Test name
Test status
Simulation time 175883022468 ps
CPU time 256.45 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:31:29 PM PDT 24
Peak memory 199796 kb
Host smart-43767786-9071-497e-939a-200429a43fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643686029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3643686029
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.3278771457
Short name T864
Test name
Test status
Simulation time 41057568887 ps
CPU time 69.69 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:28:28 PM PDT 24
Peak memory 199712 kb
Host smart-8961e914-5c07-4f60-b077-1c62a7d344a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278771457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3278771457
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.1409363797
Short name T389
Test name
Test status
Simulation time 12434600 ps
CPU time 0.54 seconds
Started Jul 31 04:25:09 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 195052 kb
Host smart-1ac9cf4d-6f55-447e-b708-2aa93ab8bda9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409363797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1409363797
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.1404231893
Short name T592
Test name
Test status
Simulation time 97200310311 ps
CPU time 151.79 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:28:08 PM PDT 24
Peak memory 199848 kb
Host smart-75bef7c1-eb99-47f8-8015-3c1e6530ad3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404231893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1404231893
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.3958534246
Short name T275
Test name
Test status
Simulation time 101764831318 ps
CPU time 77.76 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:26:20 PM PDT 24
Peak memory 199740 kb
Host smart-783c984b-b870-4e78-9100-812b981841ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958534246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3958534246
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.598892005
Short name T472
Test name
Test status
Simulation time 142524960115 ps
CPU time 22.2 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:25:25 PM PDT 24
Peak memory 199756 kb
Host smart-6721eea1-2a5d-4554-b8d9-64dcd9b97279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598892005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.598892005
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.3943957499
Short name T439
Test name
Test status
Simulation time 27841970342 ps
CPU time 12.96 seconds
Started Jul 31 04:25:04 PM PDT 24
Finished Jul 31 04:25:17 PM PDT 24
Peak memory 199748 kb
Host smart-9a661b4b-79d7-4160-ba4e-a3de05893aec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943957499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.3943957499
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1540971149
Short name T654
Test name
Test status
Simulation time 137088049227 ps
CPU time 255 seconds
Started Jul 31 04:25:11 PM PDT 24
Finished Jul 31 04:29:26 PM PDT 24
Peak memory 199776 kb
Host smart-974df0a1-5707-4296-a149-82df7f6837f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540971149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1540971149
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.631791523
Short name T731
Test name
Test status
Simulation time 2560093910 ps
CPU time 2.01 seconds
Started Jul 31 04:25:11 PM PDT 24
Finished Jul 31 04:25:13 PM PDT 24
Peak memory 197424 kb
Host smart-a5a4f68f-fce9-47e4-ada3-b97631498e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631791523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.631791523
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.2075537937
Short name T838
Test name
Test status
Simulation time 41540790939 ps
CPU time 58.79 seconds
Started Jul 31 04:25:00 PM PDT 24
Finished Jul 31 04:25:59 PM PDT 24
Peak memory 199088 kb
Host smart-496ef1d8-f9d5-4870-8941-a6d5c812b5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075537937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.2075537937
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.2598202770
Short name T1162
Test name
Test status
Simulation time 5820198379 ps
CPU time 208.87 seconds
Started Jul 31 04:25:10 PM PDT 24
Finished Jul 31 04:28:39 PM PDT 24
Peak memory 199808 kb
Host smart-8e03f071-0865-4862-8e20-ee49d3d89940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2598202770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.2598202770
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.872169316
Short name T1012
Test name
Test status
Simulation time 6104384838 ps
CPU time 5.92 seconds
Started Jul 31 04:25:04 PM PDT 24
Finished Jul 31 04:25:10 PM PDT 24
Peak memory 198744 kb
Host smart-e36e9e0c-e28c-4690-bce1-e5edf1cf0c5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=872169316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.872169316
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.695723666
Short name T891
Test name
Test status
Simulation time 91472555786 ps
CPU time 145.73 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 200092 kb
Host smart-5e7fb552-93ad-4db0-81db-a32c5ba15b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695723666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.695723666
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.400843485
Short name T636
Test name
Test status
Simulation time 30165824477 ps
CPU time 23.14 seconds
Started Jul 31 04:25:01 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 195956 kb
Host smart-ce286b84-a7b8-434b-9dfa-f7577ca67b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400843485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.400843485
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.445979892
Short name T465
Test name
Test status
Simulation time 881395086 ps
CPU time 4.21 seconds
Started Jul 31 04:25:02 PM PDT 24
Finished Jul 31 04:25:06 PM PDT 24
Peak memory 199332 kb
Host smart-d31c67ca-6472-4a0f-a15f-d2981479a453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445979892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.445979892
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2769683894
Short name T572
Test name
Test status
Simulation time 91917916320 ps
CPU time 1149.15 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:44:18 PM PDT 24
Peak memory 232724 kb
Host smart-c7584d16-9853-4c50-b2f8-e3c1b6c3da4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769683894 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2769683894
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.1002749646
Short name T284
Test name
Test status
Simulation time 1675819137 ps
CPU time 3.07 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 198740 kb
Host smart-01c941c0-fbeb-4f9e-ab04-786fd7840ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002749646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.1002749646
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1369844714
Short name T875
Test name
Test status
Simulation time 33601919961 ps
CPU time 13.3 seconds
Started Jul 31 04:25:06 PM PDT 24
Finished Jul 31 04:25:19 PM PDT 24
Peak memory 199676 kb
Host smart-4be7517f-a1b6-4bcc-b5f6-b28a67c59bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369844714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1369844714
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.3767533916
Short name T175
Test name
Test status
Simulation time 116746407595 ps
CPU time 45.74 seconds
Started Jul 31 04:27:14 PM PDT 24
Finished Jul 31 04:27:59 PM PDT 24
Peak memory 199656 kb
Host smart-918b7120-1e9b-47d6-b9e6-f8272a36cca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767533916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.3767533916
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2371991234
Short name T1020
Test name
Test status
Simulation time 26175390569 ps
CPU time 40.45 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:27:54 PM PDT 24
Peak memory 199620 kb
Host smart-1c8a4787-2dca-46ed-be67-c674a89da1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371991234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2371991234
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.1491655526
Short name T830
Test name
Test status
Simulation time 45074348443 ps
CPU time 61.66 seconds
Started Jul 31 04:27:14 PM PDT 24
Finished Jul 31 04:28:16 PM PDT 24
Peak memory 199640 kb
Host smart-6c180220-4ecb-4d85-8a81-62cba73f14d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491655526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.1491655526
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3828418592
Short name T162
Test name
Test status
Simulation time 18518911087 ps
CPU time 27.98 seconds
Started Jul 31 04:27:17 PM PDT 24
Finished Jul 31 04:27:45 PM PDT 24
Peak memory 199748 kb
Host smart-0ec3afbc-7237-4566-9fb3-7dfb7dafb6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828418592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3828418592
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2480694517
Short name T556
Test name
Test status
Simulation time 129656487853 ps
CPU time 67.15 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:28:20 PM PDT 24
Peak memory 199784 kb
Host smart-4f225206-8a61-4148-87dd-edfcc19803a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480694517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2480694517
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3075886481
Short name T662
Test name
Test status
Simulation time 172609827848 ps
CPU time 136.36 seconds
Started Jul 31 04:27:17 PM PDT 24
Finished Jul 31 04:29:33 PM PDT 24
Peak memory 199708 kb
Host smart-86ea4935-069a-4260-8da3-b2213654066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075886481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3075886481
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1793026452
Short name T629
Test name
Test status
Simulation time 32225135535 ps
CPU time 44.59 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:27:57 PM PDT 24
Peak memory 199796 kb
Host smart-98dbbcb9-948f-4564-ba95-c154d70cc83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793026452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1793026452
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.4101166663
Short name T758
Test name
Test status
Simulation time 72472858572 ps
CPU time 31.19 seconds
Started Jul 31 04:27:15 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199704 kb
Host smart-063cb56b-7612-474a-bf89-f25b18166d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101166663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.4101166663
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.4032942551
Short name T728
Test name
Test status
Simulation time 9943118063 ps
CPU time 16.31 seconds
Started Jul 31 04:27:15 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199732 kb
Host smart-3cc24f90-936e-483b-93a6-44416c4c144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032942551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.4032942551
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2450128984
Short name T534
Test name
Test status
Simulation time 13981128 ps
CPU time 0.56 seconds
Started Jul 31 04:25:24 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 195468 kb
Host smart-1a17590a-afdc-4ed1-a00b-f87390f77a13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450128984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2450128984
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.1618562655
Short name T646
Test name
Test status
Simulation time 59362719278 ps
CPU time 22.52 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 199628 kb
Host smart-de3833b4-5486-4a24-ae7a-6f83104ae720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618562655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.1618562655
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.715151226
Short name T383
Test name
Test status
Simulation time 35850259076 ps
CPU time 21.79 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:25:51 PM PDT 24
Peak memory 199620 kb
Host smart-7906bf3f-a0bc-4da1-90b7-e07d1dada21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715151226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.715151226
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.3007991901
Short name T179
Test name
Test status
Simulation time 87801535854 ps
CPU time 69.75 seconds
Started Jul 31 04:25:16 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 199700 kb
Host smart-4adac99d-ed6e-406e-b08a-e89ff8d069aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007991901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.3007991901
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.3441652859
Short name T359
Test name
Test status
Simulation time 19480903793 ps
CPU time 19.31 seconds
Started Jul 31 04:25:13 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 199740 kb
Host smart-4ca14f40-63c7-43f7-8d5b-af743341218c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441652859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.3441652859
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.1528859899
Short name T998
Test name
Test status
Simulation time 123802272039 ps
CPU time 280.21 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:30:23 PM PDT 24
Peak memory 199644 kb
Host smart-bcbd6570-7933-4456-b6c3-39ba919eb53a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1528859899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.1528859899
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.1172830005
Short name T928
Test name
Test status
Simulation time 1247201111 ps
CPU time 2.31 seconds
Started Jul 31 04:25:16 PM PDT 24
Finished Jul 31 04:25:18 PM PDT 24
Peak memory 195356 kb
Host smart-f4ee8c9a-d2a6-4d86-9204-8526c99e6c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172830005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.1172830005
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3125725978
Short name T743
Test name
Test status
Simulation time 178453438548 ps
CPU time 180.74 seconds
Started Jul 31 04:25:14 PM PDT 24
Finished Jul 31 04:28:14 PM PDT 24
Peak memory 208144 kb
Host smart-0857588a-c990-44b9-a8e9-c330cdefa0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125725978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3125725978
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.759853495
Short name T908
Test name
Test status
Simulation time 21172667439 ps
CPU time 262.63 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:30:03 PM PDT 24
Peak memory 199708 kb
Host smart-8912b0ec-1b28-43a4-ac0b-a8d7a08e8170
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=759853495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.759853495
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.909234640
Short name T1057
Test name
Test status
Simulation time 6608248007 ps
CPU time 23.19 seconds
Started Jul 31 04:25:18 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 199088 kb
Host smart-f3b10330-dd54-4552-b03a-44ffa17cdf74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909234640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.909234640
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.2040072812
Short name T645
Test name
Test status
Simulation time 41583602673 ps
CPU time 83.91 seconds
Started Jul 31 04:25:14 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199704 kb
Host smart-373ec264-ab36-4ce4-8f5b-4727c5a23194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040072812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2040072812
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.424939108
Short name T72
Test name
Test status
Simulation time 3528409093 ps
CPU time 5.97 seconds
Started Jul 31 04:25:21 PM PDT 24
Finished Jul 31 04:25:27 PM PDT 24
Peak memory 196272 kb
Host smart-5d3e2c93-3f85-4ec4-b3b6-ef2e6a7225b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424939108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.424939108
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.162575150
Short name T616
Test name
Test status
Simulation time 860514307 ps
CPU time 2.24 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:25:25 PM PDT 24
Peak memory 198712 kb
Host smart-e80f92da-a3dc-46dc-ba79-aceff930a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162575150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.162575150
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.616364845
Short name T215
Test name
Test status
Simulation time 109797361238 ps
CPU time 95.1 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:27:11 PM PDT 24
Peak memory 216312 kb
Host smart-df89eb9b-e999-4fb6-a262-779ca4da8acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616364845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.616364845
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3365273913
Short name T1149
Test name
Test status
Simulation time 40524463253 ps
CPU time 411.47 seconds
Started Jul 31 04:25:19 PM PDT 24
Finished Jul 31 04:32:10 PM PDT 24
Peak memory 210592 kb
Host smart-508fcb73-8a83-439e-8fb9-9a2cbd1b0fe4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365273913 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3365273913
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1266211712
Short name T1054
Test name
Test status
Simulation time 6646419344 ps
CPU time 23.9 seconds
Started Jul 31 04:25:20 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 199720 kb
Host smart-351cd1ae-4ea3-4d36-a2a9-956143eb794c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266211712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1266211712
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.56655808
Short name T428
Test name
Test status
Simulation time 58346439200 ps
CPU time 89.04 seconds
Started Jul 31 04:25:12 PM PDT 24
Finished Jul 31 04:26:41 PM PDT 24
Peak memory 199712 kb
Host smart-b494927e-b179-4dee-b06c-1f45bc5dfbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56655808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.56655808
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.2210136672
Short name T497
Test name
Test status
Simulation time 32629067226 ps
CPU time 34.28 seconds
Started Jul 31 04:27:12 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199804 kb
Host smart-8a3871e4-bab9-4068-80ca-69d44a523f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210136672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.2210136672
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.3991073492
Short name T161
Test name
Test status
Simulation time 186022149523 ps
CPU time 127.96 seconds
Started Jul 31 04:27:20 PM PDT 24
Finished Jul 31 04:29:28 PM PDT 24
Peak memory 199780 kb
Host smart-1ea10bcf-a1b8-4b7e-a9fd-1f0c0d7ac244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991073492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.3991073492
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.4065197882
Short name T239
Test name
Test status
Simulation time 106039840673 ps
CPU time 160.08 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:29:53 PM PDT 24
Peak memory 199760 kb
Host smart-0f90600e-1b2d-4cf9-9ba8-c2768b15a521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065197882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.4065197882
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.1146227744
Short name T219
Test name
Test status
Simulation time 27407057970 ps
CPU time 44.99 seconds
Started Jul 31 04:27:13 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199752 kb
Host smart-c52b2f46-9568-4d7f-a974-1aa09859bcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146227744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.1146227744
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3593310082
Short name T227
Test name
Test status
Simulation time 144171383697 ps
CPU time 30.93 seconds
Started Jul 31 04:27:15 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199720 kb
Host smart-0a053508-bf56-4b40-8ccd-1a0b6eeecf5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593310082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3593310082
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.3181088446
Short name T1081
Test name
Test status
Simulation time 8664073255 ps
CPU time 14.84 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199712 kb
Host smart-6b9a4fa0-f1e3-41d7-8dd2-e96a42089590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181088446 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3181088446
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.1810543183
Short name T1123
Test name
Test status
Simulation time 7243231943 ps
CPU time 7.68 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:27:25 PM PDT 24
Peak memory 199780 kb
Host smart-75e177d0-cd26-48ef-ab26-b7153643cd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810543183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.1810543183
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.3227913441
Short name T997
Test name
Test status
Simulation time 24731358677 ps
CPU time 11.61 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199692 kb
Host smart-cab525fb-36ed-4f37-998e-4ada1d759dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227913441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3227913441
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.2407111983
Short name T903
Test name
Test status
Simulation time 27732990 ps
CPU time 0.59 seconds
Started Jul 31 04:25:20 PM PDT 24
Finished Jul 31 04:25:21 PM PDT 24
Peak memory 195188 kb
Host smart-42f30700-b406-4b5a-8e7b-0f4a89fb513a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407111983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.2407111983
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.216843616
Short name T732
Test name
Test status
Simulation time 50749732727 ps
CPU time 35.46 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:26:35 PM PDT 24
Peak memory 199756 kb
Host smart-e89755eb-cb79-4c4c-896e-2ae82a6e7c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216843616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.216843616
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.259460145
Short name T120
Test name
Test status
Simulation time 143206796265 ps
CPU time 56.76 seconds
Started Jul 31 04:25:21 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 199804 kb
Host smart-1e64c13b-eba9-4138-bd3f-775e4ea32252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259460145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.259460145
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.3145738008
Short name T832
Test name
Test status
Simulation time 29389088350 ps
CPU time 49.22 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:26:17 PM PDT 24
Peak memory 199644 kb
Host smart-65fa9201-7889-47d0-ad3b-aa08a9b19b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145738008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3145738008
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.895824966
Short name T96
Test name
Test status
Simulation time 42984755339 ps
CPU time 69.3 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 199780 kb
Host smart-31bf47c9-3018-433d-b137-19bbd71787a4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895824966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.895824966
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.1730194697
Short name T450
Test name
Test status
Simulation time 100890256085 ps
CPU time 312.65 seconds
Started Jul 31 04:25:21 PM PDT 24
Finished Jul 31 04:30:33 PM PDT 24
Peak memory 199668 kb
Host smart-b19175a0-c21a-472a-9d5a-a6f0118667e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1730194697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1730194697
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1939572090
Short name T404
Test name
Test status
Simulation time 7056216767 ps
CPU time 6.41 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 199604 kb
Host smart-175d6c90-a1bb-44bc-bea5-98ca7f496b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939572090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1939572090
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3895475442
Short name T240
Test name
Test status
Simulation time 60883502681 ps
CPU time 102.89 seconds
Started Jul 31 04:25:41 PM PDT 24
Finished Jul 31 04:27:24 PM PDT 24
Peak memory 199432 kb
Host smart-8ba43f6b-9b7a-4eba-bad2-6aba03d1f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895475442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3895475442
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.3860286813
Short name T1159
Test name
Test status
Simulation time 10208504967 ps
CPU time 514.24 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:34:03 PM PDT 24
Peak memory 199708 kb
Host smart-088052ac-ba51-43e4-a831-ee51c342b7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3860286813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.3860286813
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3591065031
Short name T369
Test name
Test status
Simulation time 3734529948 ps
CPU time 9.1 seconds
Started Jul 31 04:25:19 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 197880 kb
Host smart-e42ec065-fb13-407d-9f35-bcd794ffe37e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3591065031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3591065031
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.311243478
Short name T263
Test name
Test status
Simulation time 189354519303 ps
CPU time 249.23 seconds
Started Jul 31 04:25:22 PM PDT 24
Finished Jul 31 04:29:31 PM PDT 24
Peak memory 199792 kb
Host smart-8606fe1d-5c67-4ef2-be6b-d0ad237d8cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311243478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.311243478
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.3858501381
Short name T615
Test name
Test status
Simulation time 33552497044 ps
CPU time 10.51 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:35 PM PDT 24
Peak memory 195828 kb
Host smart-967407fb-ee2d-4d95-b397-d0707244aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858501381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.3858501381
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.497869571
Short name T280
Test name
Test status
Simulation time 10576905087 ps
CPU time 15.6 seconds
Started Jul 31 04:25:18 PM PDT 24
Finished Jul 31 04:25:34 PM PDT 24
Peak memory 199636 kb
Host smart-e50d5959-e94d-40c3-8bf4-36a591a14071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497869571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.497869571
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.2843010746
Short name T911
Test name
Test status
Simulation time 124170113805 ps
CPU time 241.31 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:30:25 PM PDT 24
Peak memory 199648 kb
Host smart-0b35266d-b4dc-4ea7-985e-82f35ab94876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843010746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.2843010746
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.2374172856
Short name T738
Test name
Test status
Simulation time 27286300705 ps
CPU time 298.35 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:31:23 PM PDT 24
Peak memory 215620 kb
Host smart-2e701b60-b573-419f-adc6-f5197066bf94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374172856 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.2374172856
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1580351372
Short name T390
Test name
Test status
Simulation time 2958058582 ps
CPU time 1.27 seconds
Started Jul 31 04:25:19 PM PDT 24
Finished Jul 31 04:25:21 PM PDT 24
Peak memory 198492 kb
Host smart-e3fac134-ea90-40e4-8386-0dd8df134d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580351372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1580351372
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.1275259017
Short name T558
Test name
Test status
Simulation time 67999126733 ps
CPU time 105.15 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:27:14 PM PDT 24
Peak memory 199712 kb
Host smart-5f919d79-aa17-4510-b888-1abea09ae16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275259017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.1275259017
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2506073663
Short name T252
Test name
Test status
Simulation time 29826132325 ps
CPU time 19.79 seconds
Started Jul 31 04:27:22 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199768 kb
Host smart-885595a9-c566-46ea-b3c0-889c97762b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506073663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2506073663
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3553181508
Short name T583
Test name
Test status
Simulation time 77803241527 ps
CPU time 185.15 seconds
Started Jul 31 04:27:19 PM PDT 24
Finished Jul 31 04:30:24 PM PDT 24
Peak memory 199708 kb
Host smart-350c0d95-8a80-40ab-bb29-7be0f0808049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553181508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3553181508
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1149473184
Short name T1150
Test name
Test status
Simulation time 23225605504 ps
CPU time 16.93 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199696 kb
Host smart-3aac02c2-5fd6-45c8-87fc-caaf6c3f996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149473184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1149473184
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1062934829
Short name T887
Test name
Test status
Simulation time 78346407582 ps
CPU time 22.47 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:39 PM PDT 24
Peak memory 199656 kb
Host smart-5539766b-9937-4bb9-bb08-013af0c69484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062934829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1062934829
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.3822032703
Short name T518
Test name
Test status
Simulation time 93904228024 ps
CPU time 41.52 seconds
Started Jul 31 04:27:17 PM PDT 24
Finished Jul 31 04:27:59 PM PDT 24
Peak memory 199752 kb
Host smart-1f0a8e26-04f0-48cc-affa-90f0a3f8c366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822032703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.3822032703
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.3055555917
Short name T782
Test name
Test status
Simulation time 176042102976 ps
CPU time 209.61 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:30:51 PM PDT 24
Peak memory 199744 kb
Host smart-85f3e516-19a5-47bf-948a-a203bc8d01ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055555917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.3055555917
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.1626157802
Short name T799
Test name
Test status
Simulation time 116078243636 ps
CPU time 49.29 seconds
Started Jul 31 04:27:19 PM PDT 24
Finished Jul 31 04:28:08 PM PDT 24
Peak memory 199728 kb
Host smart-665deef5-1df6-4eb4-a97e-3e5fce6fc287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626157802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.1626157802
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.521073921
Short name T1153
Test name
Test status
Simulation time 16191931164 ps
CPU time 13.55 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:30 PM PDT 24
Peak memory 199720 kb
Host smart-22ce855e-ce81-497c-b0dc-e3e74fc00bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521073921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.521073921
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.3681988951
Short name T488
Test name
Test status
Simulation time 166083827208 ps
CPU time 13.13 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:29 PM PDT 24
Peak memory 199704 kb
Host smart-9c97a467-c3d1-42fc-8def-fae7043eb485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681988951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.3681988951
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.970551669
Short name T1117
Test name
Test status
Simulation time 21254898 ps
CPU time 0.54 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 195112 kb
Host smart-6d865a53-1e8e-4b14-8b2a-d21d6c75ae03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970551669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.970551669
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.3734427487
Short name T845
Test name
Test status
Simulation time 36124732480 ps
CPU time 55.82 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 199676 kb
Host smart-64e161ef-36eb-47cd-8c44-bbbea2d43285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734427487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.3734427487
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2038916781
Short name T527
Test name
Test status
Simulation time 26785773349 ps
CPU time 11.35 seconds
Started Jul 31 04:25:20 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 199484 kb
Host smart-3c7bffe3-9748-49e1-af3b-1646967112cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038916781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2038916781
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.3806001099
Short name T1144
Test name
Test status
Simulation time 109629007102 ps
CPU time 44.79 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:26:12 PM PDT 24
Peak memory 199640 kb
Host smart-a33ea98b-52ea-4983-81f1-5c314f7b5dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806001099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.3806001099
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.3426610821
Short name T1049
Test name
Test status
Simulation time 25861717299 ps
CPU time 56.18 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:26:25 PM PDT 24
Peak memory 199432 kb
Host smart-7f9c7029-8ed4-4fdc-9947-2432325c6dd3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426610821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.3426610821
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2352172324
Short name T246
Test name
Test status
Simulation time 162923980356 ps
CPU time 301.38 seconds
Started Jul 31 04:25:26 PM PDT 24
Finished Jul 31 04:30:28 PM PDT 24
Peak memory 199660 kb
Host smart-c9529dfb-aa8b-4bfc-90da-6987717c52ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2352172324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2352172324
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.677918396
Short name T871
Test name
Test status
Simulation time 6988075987 ps
CPU time 3.99 seconds
Started Jul 31 04:25:21 PM PDT 24
Finished Jul 31 04:25:25 PM PDT 24
Peak memory 199692 kb
Host smart-e462df3f-9a1c-4a02-b3b0-f7401dda9df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677918396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.677918396
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4005295827
Short name T1062
Test name
Test status
Simulation time 95032381172 ps
CPU time 39.74 seconds
Started Jul 31 04:25:22 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 199260 kb
Host smart-2f9f7cc4-676b-414a-a8ca-3c807565fe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005295827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4005295827
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3275811151
Short name T956
Test name
Test status
Simulation time 18885460614 ps
CPU time 1080.83 seconds
Started Jul 31 04:25:26 PM PDT 24
Finished Jul 31 04:43:27 PM PDT 24
Peak memory 199708 kb
Host smart-25cda244-3702-4521-ad5e-c4b0dd5551b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275811151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3275811151
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.1287106821
Short name T660
Test name
Test status
Simulation time 4704062682 ps
CPU time 10.72 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:38 PM PDT 24
Peak memory 198368 kb
Host smart-40a7c7d5-47fd-45cd-9768-6b2938239528
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287106821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.1287106821
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.2589412708
Short name T599
Test name
Test status
Simulation time 222176782450 ps
CPU time 48.92 seconds
Started Jul 31 04:25:19 PM PDT 24
Finished Jul 31 04:26:08 PM PDT 24
Peak memory 199776 kb
Host smart-739c703f-e5b7-427b-94d6-7f2e4bdac51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589412708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2589412708
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.401743587
Short name T979
Test name
Test status
Simulation time 4058543553 ps
CPU time 1.53 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 195860 kb
Host smart-4f32abf4-487b-4fe4-b8cc-ce3642e42988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401743587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.401743587
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.2418806782
Short name T1136
Test name
Test status
Simulation time 268684101 ps
CPU time 1.45 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 197968 kb
Host smart-8f438a29-5cd0-4c34-b950-750118b483ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418806782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.2418806782
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3226791044
Short name T265
Test name
Test status
Simulation time 195388091666 ps
CPU time 95.12 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:27:16 PM PDT 24
Peak memory 199648 kb
Host smart-010655e9-b555-4571-88f3-4fc9b4063c0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226791044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3226791044
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4054881902
Short name T311
Test name
Test status
Simulation time 18535738951 ps
CPU time 212.84 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:29:00 PM PDT 24
Peak memory 215408 kb
Host smart-c18a8919-226e-46ff-a640-822cb03456fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054881902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4054881902
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.328292581
Short name T363
Test name
Test status
Simulation time 213985620 ps
CPU time 1.25 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:25:30 PM PDT 24
Peak memory 198100 kb
Host smart-833c9390-c289-4393-90bc-5b6d24e18921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328292581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.328292581
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.2127566646
Short name T31
Test name
Test status
Simulation time 44282444174 ps
CPU time 27.1 seconds
Started Jul 31 04:25:28 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 199712 kb
Host smart-2e9ede98-11e6-4af3-afaa-c1da9bd56f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127566646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.2127566646
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.4199880036
Short name T248
Test name
Test status
Simulation time 45890876009 ps
CPU time 205.48 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:30:43 PM PDT 24
Peak memory 199776 kb
Host smart-881a5e53-8ca1-4947-9e29-93d00a9ee487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199880036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.4199880036
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.3877757798
Short name T184
Test name
Test status
Simulation time 40065294047 ps
CPU time 26.01 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:27:45 PM PDT 24
Peak memory 199704 kb
Host smart-232fd90b-3840-48b5-865f-116090497daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877757798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.3877757798
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2905458180
Short name T994
Test name
Test status
Simulation time 105187049490 ps
CPU time 195.68 seconds
Started Jul 31 04:27:17 PM PDT 24
Finished Jul 31 04:30:33 PM PDT 24
Peak memory 199768 kb
Host smart-69abecc8-b425-4294-8875-c0c494bae2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905458180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2905458180
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.243527943
Short name T470
Test name
Test status
Simulation time 4938411041 ps
CPU time 7.18 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 199672 kb
Host smart-da2836e9-51ab-479d-acf6-c0991ef1748a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243527943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.243527943
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.3577986437
Short name T211
Test name
Test status
Simulation time 79658859362 ps
CPU time 21.03 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 199752 kb
Host smart-5aaa3272-0ced-448a-ab17-cedc0ab0b88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577986437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.3577986437
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.1221812957
Short name T107
Test name
Test status
Simulation time 60338856326 ps
CPU time 25.22 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199644 kb
Host smart-100750c1-471f-43ee-88dd-b09badac8df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221812957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.1221812957
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.756796396
Short name T197
Test name
Test status
Simulation time 6767837702 ps
CPU time 9.81 seconds
Started Jul 31 04:27:18 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 198660 kb
Host smart-393a5efb-e68b-4715-8f6a-432a3dbd5001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756796396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.756796396
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3752707230
Short name T1043
Test name
Test status
Simulation time 141479263330 ps
CPU time 187.06 seconds
Started Jul 31 04:27:17 PM PDT 24
Finished Jul 31 04:30:25 PM PDT 24
Peak memory 199712 kb
Host smart-9cf10dd3-7c3e-488c-b23b-f0c848c957b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752707230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3752707230
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.4123498946
Short name T610
Test name
Test status
Simulation time 57092313111 ps
CPU time 23.98 seconds
Started Jul 31 04:27:19 PM PDT 24
Finished Jul 31 04:27:43 PM PDT 24
Peak memory 199852 kb
Host smart-1f633cd6-b280-4f5b-946a-5903a51c458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123498946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4123498946
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3255894625
Short name T165
Test name
Test status
Simulation time 46692525142 ps
CPU time 29.22 seconds
Started Jul 31 04:27:16 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199864 kb
Host smart-82b9ac34-a1b2-4ece-b371-9bb0a0b1ed62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255894625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3255894625
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.2641597103
Short name T475
Test name
Test status
Simulation time 51597585 ps
CPU time 0.55 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 195096 kb
Host smart-ac857dfe-b3f1-4ee9-a1f4-23e5cfb71185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641597103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.2641597103
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2641253316
Short name T1027
Test name
Test status
Simulation time 38661666145 ps
CPU time 28.04 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:49 PM PDT 24
Peak memory 199400 kb
Host smart-f609bb71-285e-428d-9ff9-99f4c8062ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641253316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2641253316
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.1231695123
Short name T1131
Test name
Test status
Simulation time 94300283368 ps
CPU time 119.85 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:28:24 PM PDT 24
Peak memory 199644 kb
Host smart-c5aebca4-69e9-47be-850b-46febf25f140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231695123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.1231695123
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.1422620593
Short name T914
Test name
Test status
Simulation time 76508951697 ps
CPU time 145.21 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:28:47 PM PDT 24
Peak memory 199652 kb
Host smart-48e2e943-4a81-4ba6-9730-b0db94f79625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422620593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.1422620593
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.4099310168
Short name T508
Test name
Test status
Simulation time 61114401272 ps
CPU time 51.17 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:29 PM PDT 24
Peak memory 198996 kb
Host smart-d91f8ac8-5594-49f1-a590-500e91655c46
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099310168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.4099310168
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.983715107
Short name T686
Test name
Test status
Simulation time 96745726961 ps
CPU time 274.74 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:30:13 PM PDT 24
Peak memory 199716 kb
Host smart-1c4bb219-9eea-45cd-af34-1590d407f24c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983715107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.983715107
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.808115
Short name T473
Test name
Test status
Simulation time 3975554183 ps
CPU time 7.58 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:29 PM PDT 24
Peak memory 199708 kb
Host smart-71923080-9846-4853-aba6-9c2af9ae350b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.808115
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2779538194
Short name T408
Test name
Test status
Simulation time 19407384940 ps
CPU time 3.39 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 194584 kb
Host smart-020603c4-6475-47f3-b4bf-0f8d236b31ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779538194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2779538194
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.884629099
Short name T769
Test name
Test status
Simulation time 10404183471 ps
CPU time 470.73 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:34:15 PM PDT 24
Peak memory 199664 kb
Host smart-f7ee307c-3572-40bc-ae48-5bd1aed77590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884629099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.884629099
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.2904469394
Short name T840
Test name
Test status
Simulation time 3808691542 ps
CPU time 19.05 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:40 PM PDT 24
Peak memory 198704 kb
Host smart-72fbb3c3-b5e5-4ee9-9e20-65fb7ae2d879
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2904469394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.2904469394
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.4078457529
Short name T713
Test name
Test status
Simulation time 292422523167 ps
CPU time 28.14 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:25:58 PM PDT 24
Peak memory 199752 kb
Host smart-ead1e764-fc5b-4031-b576-5fe1153044a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078457529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.4078457529
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.709477671
Short name T612
Test name
Test status
Simulation time 4954791286 ps
CPU time 6.95 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:25:43 PM PDT 24
Peak memory 196188 kb
Host smart-c69c145f-645a-42a8-89f8-b97b2ac18155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709477671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.709477671
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.1359015214
Short name T1163
Test name
Test status
Simulation time 11588372958 ps
CPU time 29.65 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:51 PM PDT 24
Peak memory 199408 kb
Host smart-5ab0f64b-3c51-4341-b275-ddf5ae31f870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359015214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1359015214
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.4152788339
Short name T247
Test name
Test status
Simulation time 251469456194 ps
CPU time 93.23 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:27:04 PM PDT 24
Peak memory 208100 kb
Host smart-ded89696-e33d-42da-ad99-fa72c2a3ebab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152788339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.4152788339
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.209392721
Short name T901
Test name
Test status
Simulation time 80744182537 ps
CPU time 213.58 seconds
Started Jul 31 04:25:25 PM PDT 24
Finished Jul 31 04:28:58 PM PDT 24
Peak memory 216296 kb
Host smart-d11cfe5f-41a3-4bc3-905e-1b33d2701889
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209392721 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.209392721
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2735255633
Short name T1124
Test name
Test status
Simulation time 1052155317 ps
CPU time 4.22 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:32 PM PDT 24
Peak memory 198092 kb
Host smart-84ec5902-2cd0-4433-a160-46ce9f1ecca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735255633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2735255633
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1558479650
Short name T980
Test name
Test status
Simulation time 97629838039 ps
CPU time 40.3 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 199720 kb
Host smart-557ed4bd-1033-4dfb-80e8-34e39e83daeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558479650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1558479650
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.1057988174
Short name T691
Test name
Test status
Simulation time 58091829094 ps
CPU time 23.62 seconds
Started Jul 31 04:27:20 PM PDT 24
Finished Jul 31 04:27:44 PM PDT 24
Peak memory 199712 kb
Host smart-652c5c48-06d3-44a3-94d6-15a991787e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057988174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1057988174
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1539012628
Short name T563
Test name
Test status
Simulation time 129762553736 ps
CPU time 67.29 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:28:28 PM PDT 24
Peak memory 199660 kb
Host smart-53f90277-f9cc-43ba-a00d-e38be3e69c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539012628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1539012628
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.1711643812
Short name T155
Test name
Test status
Simulation time 76061730606 ps
CPU time 147.55 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:29:49 PM PDT 24
Peak memory 199660 kb
Host smart-86fbe880-2cc8-46a4-8df8-09f370177fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711643812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.1711643812
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.2279678415
Short name T201
Test name
Test status
Simulation time 20558754685 ps
CPU time 36.94 seconds
Started Jul 31 04:27:19 PM PDT 24
Finished Jul 31 04:27:56 PM PDT 24
Peak memory 199692 kb
Host smart-95d26fa5-bc95-45c2-80f5-982e256d7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279678415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.2279678415
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.1324842687
Short name T287
Test name
Test status
Simulation time 92219210503 ps
CPU time 23.93 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:27:45 PM PDT 24
Peak memory 199744 kb
Host smart-e239d32d-df34-4cf2-b960-64a7e97a0b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324842687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.1324842687
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2989779664
Short name T1009
Test name
Test status
Simulation time 209279032767 ps
CPU time 298.66 seconds
Started Jul 31 04:27:20 PM PDT 24
Finished Jul 31 04:32:19 PM PDT 24
Peak memory 199728 kb
Host smart-6b85f970-823a-492a-9673-494e5ff46e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989779664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2989779664
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.3876862529
Short name T947
Test name
Test status
Simulation time 19973596651 ps
CPU time 15.75 seconds
Started Jul 31 04:27:21 PM PDT 24
Finished Jul 31 04:27:37 PM PDT 24
Peak memory 199596 kb
Host smart-5eee83cc-0a39-4a2d-8c5c-10e1b1476d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876862529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.3876862529
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.2304709644
Short name T195
Test name
Test status
Simulation time 25332938975 ps
CPU time 10.97 seconds
Started Jul 31 04:27:30 PM PDT 24
Finished Jul 31 04:27:41 PM PDT 24
Peak memory 199716 kb
Host smart-883e2418-4b95-4c07-a938-b7c33eb7ceb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304709644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2304709644
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3897092043
Short name T600
Test name
Test status
Simulation time 35357505 ps
CPU time 0.53 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:38 PM PDT 24
Peak memory 195200 kb
Host smart-d5dfd936-6b75-4898-be2d-353963af2733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897092043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3897092043
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2917687306
Short name T590
Test name
Test status
Simulation time 214193721253 ps
CPU time 56.79 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:23:23 PM PDT 24
Peak memory 199640 kb
Host smart-7689c74c-5cbf-470b-9724-005ccd145338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917687306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2917687306
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.788502821
Short name T976
Test name
Test status
Simulation time 104513493251 ps
CPU time 207.14 seconds
Started Jul 31 04:22:40 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 200016 kb
Host smart-41dea373-71a7-4f82-ba06-f10d270a37eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788502821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.788502821
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.3730195695
Short name T461
Test name
Test status
Simulation time 25571234757 ps
CPU time 47.11 seconds
Started Jul 31 04:22:36 PM PDT 24
Finished Jul 31 04:23:23 PM PDT 24
Peak memory 199664 kb
Host smart-4f7702e3-3faa-4b8f-826a-82f8d2cd63b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730195695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.3730195695
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.1498215205
Short name T1058
Test name
Test status
Simulation time 254766387818 ps
CPU time 94.65 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:26:32 PM PDT 24
Peak memory 198172 kb
Host smart-94f37547-be9a-488c-923f-b03488df053f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498215205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.1498215205
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_loopback.598689677
Short name T330
Test name
Test status
Simulation time 3880263500 ps
CPU time 4.54 seconds
Started Jul 31 04:22:14 PM PDT 24
Finished Jul 31 04:22:19 PM PDT 24
Peak memory 198456 kb
Host smart-2090a707-c524-449c-992d-57f919534129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598689677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.598689677
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.4021253161
Short name T382
Test name
Test status
Simulation time 27315208401 ps
CPU time 9.74 seconds
Started Jul 31 04:21:43 PM PDT 24
Finished Jul 31 04:21:53 PM PDT 24
Peak memory 195296 kb
Host smart-aa3783a1-eff0-46a4-9cd4-349a9f566e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021253161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.4021253161
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3932654490
Short name T981
Test name
Test status
Simulation time 19777729336 ps
CPU time 336.42 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:30:18 PM PDT 24
Peak memory 198640 kb
Host smart-69ea95dd-47da-45cf-98b1-c126ca49aff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3932654490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3932654490
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.478441322
Short name T325
Test name
Test status
Simulation time 5271890107 ps
CPU time 12.62 seconds
Started Jul 31 04:25:09 PM PDT 24
Finished Jul 31 04:25:22 PM PDT 24
Peak memory 197836 kb
Host smart-f6f877d7-49a8-49aa-9b6c-88e73fbe91b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=478441322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.478441322
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1722993599
Short name T71
Test name
Test status
Simulation time 89136770255 ps
CPU time 24.33 seconds
Started Jul 31 04:21:46 PM PDT 24
Finished Jul 31 04:22:10 PM PDT 24
Peak memory 199728 kb
Host smart-66b1a5fa-a186-49cf-bbc6-d88bf90e5387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722993599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1722993599
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.2376830081
Short name T657
Test name
Test status
Simulation time 715912980 ps
CPU time 0.93 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:22:27 PM PDT 24
Peak memory 195344 kb
Host smart-c5bf923d-32a3-4104-93f9-2cb61b2f25ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376830081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.2376830081
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2503851062
Short name T70
Test name
Test status
Simulation time 234808668 ps
CPU time 0.91 seconds
Started Jul 31 04:24:47 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 216508 kb
Host smart-bf9c89dc-2540-4a9a-8555-78fff9c226c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503851062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2503851062
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.2743706262
Short name T1066
Test name
Test status
Simulation time 755012390 ps
CPU time 1.3 seconds
Started Jul 31 04:21:40 PM PDT 24
Finished Jul 31 04:21:41 PM PDT 24
Peak memory 198740 kb
Host smart-d9f0d56c-c82f-406a-92dd-6467e97866ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743706262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.2743706262
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2592261348
Short name T598
Test name
Test status
Simulation time 26385414912 ps
CPU time 30.43 seconds
Started Jul 31 04:21:56 PM PDT 24
Finished Jul 31 04:22:26 PM PDT 24
Peak memory 199608 kb
Host smart-7c3cb632-49dd-4407-b0b3-c4013fb19e44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592261348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2592261348
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3446608878
Short name T622
Test name
Test status
Simulation time 2756259540 ps
CPU time 2.48 seconds
Started Jul 31 04:24:42 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 198052 kb
Host smart-e800bb30-79e8-4408-84f0-175871e88639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446608878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3446608878
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3053199540
Short name T900
Test name
Test status
Simulation time 56302282749 ps
CPU time 57.08 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 198084 kb
Host smart-0aaf7c9e-9649-4b55-a183-daee984da95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053199540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3053199540
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.572583448
Short name T333
Test name
Test status
Simulation time 196649814 ps
CPU time 0.56 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:25:34 PM PDT 24
Peak memory 195428 kb
Host smart-664d174f-d094-4a5c-9fc5-109b3f1a5ef9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572583448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.572583448
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3412994304
Short name T377
Test name
Test status
Simulation time 8577292234 ps
CPU time 13.29 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199740 kb
Host smart-e9e39812-f62b-485e-bb89-605672c7655b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412994304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3412994304
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.2378975788
Short name T1069
Test name
Test status
Simulation time 17754146250 ps
CPU time 13.84 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 199828 kb
Host smart-9315402d-1c6e-424e-a560-9791b00f3bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378975788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.2378975788
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.782620604
Short name T829
Test name
Test status
Simulation time 172293208378 ps
CPU time 341.97 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:31:29 PM PDT 24
Peak memory 199832 kb
Host smart-152b1e20-34b7-417f-afdd-33b7474fd6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782620604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.782620604
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.2152238502
Short name T866
Test name
Test status
Simulation time 134707884907 ps
CPU time 82.5 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:26:54 PM PDT 24
Peak memory 199696 kb
Host smart-dc3473a9-207a-4ed1-9b8a-aa676ed0fa19
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152238502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2152238502
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.584573916
Short name T1065
Test name
Test status
Simulation time 118689229866 ps
CPU time 761.41 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:38:13 PM PDT 24
Peak memory 199756 kb
Host smart-05a8e073-d627-4e8e-a175-774b0813bc94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584573916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.584573916
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.822961662
Short name T393
Test name
Test status
Simulation time 7738878009 ps
CPU time 4.63 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 199280 kb
Host smart-6066adf4-912d-458d-b72f-2710bc0dd868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822961662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.822961662
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.382517133
Short name T523
Test name
Test status
Simulation time 73933381959 ps
CPU time 33.42 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:21 PM PDT 24
Peak memory 199872 kb
Host smart-d340d3bb-d5c6-4acd-a58b-a6ecb08f6f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382517133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.382517133
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3863619426
Short name T396
Test name
Test status
Simulation time 10676867272 ps
CPU time 157.46 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:28:07 PM PDT 24
Peak memory 199708 kb
Host smart-87992872-8f57-4c4f-99a4-3fec6ef74419
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3863619426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3863619426
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4254578340
Short name T1000
Test name
Test status
Simulation time 3815473996 ps
CPU time 7.95 seconds
Started Jul 31 04:25:26 PM PDT 24
Finished Jul 31 04:25:34 PM PDT 24
Peak memory 199412 kb
Host smart-55a31cbc-8cd7-47b6-80a2-a3a3c8b38e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254578340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4254578340
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.4160964470
Short name T1127
Test name
Test status
Simulation time 119762109813 ps
CPU time 44.8 seconds
Started Jul 31 04:25:30 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 199664 kb
Host smart-0a82e5a3-e140-45c7-b299-6836e65c0255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160964470 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.4160964470
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3961751951
Short name T861
Test name
Test status
Simulation time 48701573314 ps
CPU time 13.57 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 195748 kb
Host smart-6f1b0d3d-2a52-4d9a-a347-b6dd56b97eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961751951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3961751951
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.1199095855
Short name T986
Test name
Test status
Simulation time 894505764 ps
CPU time 1.87 seconds
Started Jul 31 04:25:26 PM PDT 24
Finished Jul 31 04:25:28 PM PDT 24
Peak memory 198748 kb
Host smart-650ca125-0829-4d36-9021-77f5c71dfbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199095855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.1199095855
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.2524913242
Short name T1125
Test name
Test status
Simulation time 12255762042 ps
CPU time 42.19 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199724 kb
Host smart-e5cba343-1f0a-48df-8e15-9aa535f96c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524913242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.2524913242
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.1441090070
Short name T1061
Test name
Test status
Simulation time 45629970131 ps
CPU time 84.43 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:26:56 PM PDT 24
Peak memory 199820 kb
Host smart-dd52df5e-9711-45e8-a36b-f9e441984126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441090070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.1441090070
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.1244470783
Short name T760
Test name
Test status
Simulation time 60606694 ps
CPU time 0.54 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:25:34 PM PDT 24
Peak memory 195136 kb
Host smart-dabb444d-3c48-4d54-b1df-3203426d0a12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244470783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.1244470783
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3222051326
Short name T585
Test name
Test status
Simulation time 55785774251 ps
CPU time 117.48 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:27:44 PM PDT 24
Peak memory 199832 kb
Host smart-92e7ee34-b13d-4a21-afd1-90985d37c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222051326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3222051326
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2496295048
Short name T418
Test name
Test status
Simulation time 42827406381 ps
CPU time 25.43 seconds
Started Jul 31 04:25:29 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 199696 kb
Host smart-50111d8a-30b4-48fe-913f-ef05326db512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496295048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2496295048
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.1947769367
Short name T1035
Test name
Test status
Simulation time 100352550996 ps
CPU time 38.01 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199820 kb
Host smart-96699710-cf7e-4cf0-a899-ddf736a4e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947769367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.1947769367
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.1103728196
Short name T427
Test name
Test status
Simulation time 37532942527 ps
CPU time 69.97 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:48 PM PDT 24
Peak memory 199848 kb
Host smart-29535da4-c77e-48b3-a91a-665a969d75c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103728196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.1103728196
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2478406083
Short name T936
Test name
Test status
Simulation time 87232004928 ps
CPU time 337.3 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:31:11 PM PDT 24
Peak memory 199692 kb
Host smart-ed535cd3-5be0-4e69-92dd-60cdfef0e3f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478406083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2478406083
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.4119592139
Short name T985
Test name
Test status
Simulation time 10304808811 ps
CPU time 17.33 seconds
Started Jul 31 04:25:30 PM PDT 24
Finished Jul 31 04:25:47 PM PDT 24
Peak memory 199748 kb
Host smart-3e6f59eb-7439-429d-b627-c2081ce2a5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119592139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.4119592139
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.2003267322
Short name T628
Test name
Test status
Simulation time 186900568756 ps
CPU time 80.55 seconds
Started Jul 31 04:25:27 PM PDT 24
Finished Jul 31 04:26:48 PM PDT 24
Peak memory 199892 kb
Host smart-5c5015ee-878c-49ec-8129-ee85da54806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003267322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.2003267322
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.2667861896
Short name T414
Test name
Test status
Simulation time 15601125523 ps
CPU time 802.5 seconds
Started Jul 31 04:25:31 PM PDT 24
Finished Jul 31 04:38:54 PM PDT 24
Peak memory 199700 kb
Host smart-06f9fdee-748a-420d-bc42-158cb0cd0d1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667861896 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.2667861896
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.1697412177
Short name T708
Test name
Test status
Simulation time 3590000524 ps
CPU time 12.1 seconds
Started Jul 31 04:25:26 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 198112 kb
Host smart-ef0bc247-3599-4228-9b20-44030dfe8fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697412177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.1697412177
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.3927767500
Short name T459
Test name
Test status
Simulation time 49445435573 ps
CPU time 36.49 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:26:12 PM PDT 24
Peak memory 198528 kb
Host smart-734a8ef2-db63-4a49-b064-fe7602724fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927767500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.3927767500
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.4025290022
Short name T403
Test name
Test status
Simulation time 6823410629 ps
CPU time 3.1 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 195912 kb
Host smart-7d2c1afa-c30a-48c9-963f-5bd35392cb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025290022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.4025290022
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.2379209090
Short name T74
Test name
Test status
Simulation time 703617431 ps
CPU time 1.43 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:33 PM PDT 24
Peak memory 199244 kb
Host smart-c0af8553-79f9-42f0-a326-f952f9e319c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379209090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.2379209090
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2057427944
Short name T1108
Test name
Test status
Simulation time 42627068523 ps
CPU time 1154.54 seconds
Started Jul 31 04:25:30 PM PDT 24
Finished Jul 31 04:44:45 PM PDT 24
Peak memory 215952 kb
Host smart-a1d84089-3afd-48a8-8913-951249b5b450
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057427944 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2057427944
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.1569436443
Short name T1114
Test name
Test status
Simulation time 7171000247 ps
CPU time 8.51 seconds
Started Jul 31 04:25:30 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 199144 kb
Host smart-95dd4246-ed2c-4de1-b184-03e60569b321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569436443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.1569436443
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.755021015
Short name T751
Test name
Test status
Simulation time 27607317732 ps
CPU time 18.4 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:26:06 PM PDT 24
Peak memory 199784 kb
Host smart-ff4f59b3-d5c2-41b4-b2be-92ef582a1d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755021015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.755021015
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.479423965
Short name T336
Test name
Test status
Simulation time 14015360 ps
CPU time 0.53 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 194776 kb
Host smart-6a61442a-3868-448c-bbb6-ddc09d594c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479423965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.479423965
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3854740206
Short name T540
Test name
Test status
Simulation time 72564024821 ps
CPU time 53.98 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 199536 kb
Host smart-8b1bc3c8-ee70-4333-acf0-a81433aae1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854740206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3854740206
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1886741988
Short name T640
Test name
Test status
Simulation time 111589701985 ps
CPU time 207.35 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:29:04 PM PDT 24
Peak memory 199620 kb
Host smart-d6a98469-3d41-4481-9d07-c7bbcf3465a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886741988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1886741988
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1652806817
Short name T950
Test name
Test status
Simulation time 27636580141 ps
CPU time 21.96 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 199664 kb
Host smart-e461efad-c0c4-4126-9091-03eb390131ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652806817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1652806817
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2165992566
Short name T943
Test name
Test status
Simulation time 67771708730 ps
CPU time 115.35 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:27:36 PM PDT 24
Peak memory 199684 kb
Host smart-32310e6d-d1a1-45da-815c-ca4ba475cb03
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165992566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2165992566
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.2400654081
Short name T827
Test name
Test status
Simulation time 89044114619 ps
CPU time 367.13 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:31:42 PM PDT 24
Peak memory 199680 kb
Host smart-6d5bc3ff-9a08-464e-ba96-f1a3fd5cdc92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400654081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.2400654081
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.833630946
Short name T374
Test name
Test status
Simulation time 6844934518 ps
CPU time 1.94 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 199556 kb
Host smart-5221448e-6932-4250-bc0f-34f5345fbf93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833630946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.833630946
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.4213105916
Short name T736
Test name
Test status
Simulation time 66311393638 ps
CPU time 31.52 seconds
Started Jul 31 04:25:33 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 199816 kb
Host smart-4bdd1861-d517-4459-849a-a801cd709579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213105916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4213105916
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2812039733
Short name T1122
Test name
Test status
Simulation time 7829657944 ps
CPU time 183.01 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:28:43 PM PDT 24
Peak memory 199680 kb
Host smart-64619673-8452-4fdc-833f-66b558636f65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2812039733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2812039733
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.4142772143
Short name T1109
Test name
Test status
Simulation time 4593915836 ps
CPU time 9.23 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 197796 kb
Host smart-f1f80def-999f-4b08-a94c-62deb1d9f049
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4142772143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.4142772143
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.1414269498
Short name T1003
Test name
Test status
Simulation time 704911194 ps
CPU time 1.72 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 195268 kb
Host smart-366515d0-7d7f-4308-80c5-eccec83b172f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414269498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1414269498
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2845258126
Short name T1140
Test name
Test status
Simulation time 6234616323 ps
CPU time 20.12 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:53 PM PDT 24
Peak memory 199736 kb
Host smart-f7504e69-9c59-42d7-814a-60f258fb7b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845258126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2845258126
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.3380650847
Short name T879
Test name
Test status
Simulation time 28113842591 ps
CPU time 47.95 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:26:33 PM PDT 24
Peak memory 199736 kb
Host smart-f20800ce-5070-4819-8c48-798135aef70f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380650847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.3380650847
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.199293089
Short name T151
Test name
Test status
Simulation time 81688578532 ps
CPU time 341.57 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:31:23 PM PDT 24
Peak memory 216188 kb
Host smart-216cfab2-e4d2-476e-83cd-a4ea80585784
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199293089 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.199293089
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.171512619
Short name T443
Test name
Test status
Simulation time 875401709 ps
CPU time 2.18 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 198988 kb
Host smart-05074685-87fa-4a9d-9288-17b32bb7061b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171512619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.171512619
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.3410911158
Short name T1063
Test name
Test status
Simulation time 58478227494 ps
CPU time 103.24 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:27:20 PM PDT 24
Peak memory 199720 kb
Host smart-f5371190-3646-4472-ab87-cd6adab02bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410911158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.3410911158
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.2278694259
Short name T68
Test name
Test status
Simulation time 11607335 ps
CPU time 0.55 seconds
Started Jul 31 04:25:34 PM PDT 24
Finished Jul 31 04:25:35 PM PDT 24
Peak memory 195124 kb
Host smart-c8f5b60b-5800-4545-8376-7726d5806234
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278694259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2278694259
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3470132690
Short name T926
Test name
Test status
Simulation time 115867427986 ps
CPU time 168.38 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:28:29 PM PDT 24
Peak memory 199756 kb
Host smart-5b0da26d-eab2-4a3a-9dc2-0c8a4f1d4363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470132690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3470132690
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.3872062787
Short name T882
Test name
Test status
Simulation time 86559049760 ps
CPU time 14.99 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 199668 kb
Host smart-102c0a2a-bad8-4b70-9661-4a15e76f3383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872062787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.3872062787
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.2893527798
Short name T917
Test name
Test status
Simulation time 29084155894 ps
CPU time 43.86 seconds
Started Jul 31 04:25:34 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 199652 kb
Host smart-e9fb0cf5-6512-48a8-bdd3-e1ba6a180ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893527798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.2893527798
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2807071555
Short name T456
Test name
Test status
Simulation time 55908847700 ps
CPU time 118.63 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:27:31 PM PDT 24
Peak memory 199676 kb
Host smart-d3e1a656-b006-48f1-9d25-25502333ef44
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807071555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2807071555
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2030861353
Short name T420
Test name
Test status
Simulation time 164735210100 ps
CPU time 513.65 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:34:08 PM PDT 24
Peak memory 199752 kb
Host smart-b4fbb30b-29ab-49bb-b2f4-5730999ccdae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030861353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2030861353
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.1424970916
Short name T386
Test name
Test status
Simulation time 7757404922 ps
CPU time 4.93 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:42 PM PDT 24
Peak memory 199448 kb
Host smart-e70d1d42-ea6f-444a-8baa-fa5aa4c1f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424970916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.1424970916
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.1341181200
Short name T750
Test name
Test status
Simulation time 73690692718 ps
CPU time 56.85 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:36 PM PDT 24
Peak memory 198828 kb
Host smart-4dd01181-abf4-424d-a00f-3cdf91bf5c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341181200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.1341181200
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.3769475066
Short name T401
Test name
Test status
Simulation time 28457690115 ps
CPU time 1387.91 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:48:55 PM PDT 24
Peak memory 199836 kb
Host smart-5a451825-8837-4bfe-8546-697f1d20608b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3769475066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.3769475066
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2965892808
Short name T452
Test name
Test status
Simulation time 4306270582 ps
CPU time 30.99 seconds
Started Jul 31 04:25:35 PM PDT 24
Finished Jul 31 04:26:06 PM PDT 24
Peak memory 197704 kb
Host smart-aa38572a-e85b-4c95-af25-8c058b2f8830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2965892808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2965892808
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.3544191001
Short name T709
Test name
Test status
Simulation time 31088915962 ps
CPU time 8.48 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199564 kb
Host smart-27affa59-f8d4-4d38-a74f-d212495b9758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544191001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3544191001
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2610482449
Short name T1134
Test name
Test status
Simulation time 47984239973 ps
CPU time 70.6 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:54 PM PDT 24
Peak memory 195616 kb
Host smart-45a03424-a4ff-4937-a3e6-4a4eb185cf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610482449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2610482449
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1036585658
Short name T966
Test name
Test status
Simulation time 772840776 ps
CPU time 1.27 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:25:37 PM PDT 24
Peak memory 198316 kb
Host smart-05246587-ffee-44c5-a453-26d91c730e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036585658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1036585658
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3907606888
Short name T785
Test name
Test status
Simulation time 241782547343 ps
CPU time 647.89 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:36:26 PM PDT 24
Peak memory 199652 kb
Host smart-513bd089-76d0-4472-804d-e51c66ab1610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907606888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3907606888
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.3911374970
Short name T910
Test name
Test status
Simulation time 12349521074 ps
CPU time 399.55 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:32:20 PM PDT 24
Peak memory 208052 kb
Host smart-bd40cfda-22e7-47c0-aaae-ec086cb02735
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911374970 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.3911374970
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2862888623
Short name T308
Test name
Test status
Simulation time 974849902 ps
CPU time 4.61 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 198772 kb
Host smart-9ef7e349-6116-4136-be42-a0a62e00ea82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862888623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2862888623
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2973060236
Short name T238
Test name
Test status
Simulation time 47231962198 ps
CPU time 70.63 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:53 PM PDT 24
Peak memory 199828 kb
Host smart-ac9221f0-e00a-450f-869a-038e3db708bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973060236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2973060236
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.831248949
Short name T1011
Test name
Test status
Simulation time 11249015 ps
CPU time 0.54 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:26:08 PM PDT 24
Peak memory 195136 kb
Host smart-3813728f-c7de-4886-ade5-828caba9db00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831248949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.831248949
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.908803933
Short name T126
Test name
Test status
Simulation time 159720905563 ps
CPU time 40.59 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 199736 kb
Host smart-44c2cead-f763-4d91-9b2b-4449c2d98211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908803933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.908803933
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.324857799
Short name T235
Test name
Test status
Simulation time 35935400069 ps
CPU time 14.72 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:58 PM PDT 24
Peak memory 199504 kb
Host smart-c638d786-2c11-41bb-b343-8ca0fb24b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324857799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.324857799
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.774905577
Short name T894
Test name
Test status
Simulation time 12841041765 ps
CPU time 9.35 seconds
Started Jul 31 04:25:40 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 199640 kb
Host smart-7cdfed13-fdf6-4298-a6fd-8d13f1d689e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774905577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.774905577
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.1917574555
Short name T13
Test name
Test status
Simulation time 69662317887 ps
CPU time 37.07 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199648 kb
Host smart-8c2a53fe-ea41-4552-b283-382fb79c0c91
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917574555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1917574555
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.957027970
Short name T397
Test name
Test status
Simulation time 85708703766 ps
CPU time 381.75 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:32:05 PM PDT 24
Peak memory 199688 kb
Host smart-bf55e59c-e699-4e1e-8682-6c3520f93b41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957027970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.957027970
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2058337087
Short name T1019
Test name
Test status
Simulation time 2612331191 ps
CPU time 4.83 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 196060 kb
Host smart-4fb35ac2-01d7-4180-a99f-cd73820dd986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058337087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2058337087
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1509080961
Short name T1152
Test name
Test status
Simulation time 39342570985 ps
CPU time 66.53 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 198796 kb
Host smart-cc846783-7aef-4990-b0c1-c0f4ed26758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509080961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1509080961
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.2418780878
Short name T788
Test name
Test status
Simulation time 7952495412 ps
CPU time 362.5 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:31:45 PM PDT 24
Peak memory 199676 kb
Host smart-8d01e206-5c2f-4fd3-9d62-60efb7783575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418780878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.2418780878
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.1362915215
Short name T364
Test name
Test status
Simulation time 1818201743 ps
CPU time 1.88 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 197888 kb
Host smart-e2b33b1d-2815-450b-9774-729d03bc9b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1362915215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1362915215
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.129262033
Short name T791
Test name
Test status
Simulation time 15534642161 ps
CPU time 28.78 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:08 PM PDT 24
Peak memory 199652 kb
Host smart-aad9ad69-eaf4-432f-8999-7ae785d360af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129262033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.129262033
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.498014804
Short name T286
Test name
Test status
Simulation time 37191248925 ps
CPU time 62.8 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:41 PM PDT 24
Peak memory 195524 kb
Host smart-0b949b41-2413-4b49-9a51-4f42fe4ff1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498014804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.498014804
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.3204160520
Short name T1143
Test name
Test status
Simulation time 5296913553 ps
CPU time 10.55 seconds
Started Jul 31 04:25:41 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 199688 kb
Host smart-336252c8-3f4b-4d13-b41f-ead75cb89b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204160520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.3204160520
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.1985782110
Short name T905
Test name
Test status
Simulation time 90160743466 ps
CPU time 604.44 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:35:53 PM PDT 24
Peak memory 199728 kb
Host smart-f40ac9c6-319e-4cd0-8448-c0bf1c063c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985782110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.1985782110
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1697670856
Short name T680
Test name
Test status
Simulation time 50482828378 ps
CPU time 303.76 seconds
Started Jul 31 04:26:03 PM PDT 24
Finished Jul 31 04:31:07 PM PDT 24
Peak memory 214188 kb
Host smart-4bd77c0e-3d93-4269-b82b-5fff33c002a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697670856 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1697670856
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.208306267
Short name T1006
Test name
Test status
Simulation time 663485673 ps
CPU time 2.34 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199332 kb
Host smart-2b3edf6e-ace5-4711-b111-e65aff044da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208306267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.208306267
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3043738296
Short name T506
Test name
Test status
Simulation time 93544595397 ps
CPU time 15.38 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 199676 kb
Host smart-39c797ab-cf18-47f6-8c1d-48d54e5b2059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043738296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3043738296
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4217291275
Short name T557
Test name
Test status
Simulation time 24474131 ps
CPU time 0.69 seconds
Started Jul 31 04:26:03 PM PDT 24
Finished Jul 31 04:26:04 PM PDT 24
Peak memory 195128 kb
Host smart-0865dddc-4fe9-4f32-b128-f9163a43e928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217291275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4217291275
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3856887916
Short name T714
Test name
Test status
Simulation time 75861508730 ps
CPU time 62.08 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:50 PM PDT 24
Peak memory 199824 kb
Host smart-ed4490fc-8cda-4581-90fc-8d620aa27c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856887916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3856887916
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.145227224
Short name T307
Test name
Test status
Simulation time 39003815256 ps
CPU time 30.49 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:26:20 PM PDT 24
Peak memory 199508 kb
Host smart-ec70ec5f-cdd0-49ac-ab8e-f8b32d14e14c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145227224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.145227224
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.1834843766
Short name T971
Test name
Test status
Simulation time 205553989207 ps
CPU time 127.47 seconds
Started Jul 31 04:26:04 PM PDT 24
Finished Jul 31 04:28:12 PM PDT 24
Peak memory 199700 kb
Host smart-e82d7bd5-c677-4c7d-a5b9-006d62b1755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834843766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1834843766
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3516352500
Short name T496
Test name
Test status
Simulation time 455608061 ps
CPU time 0.87 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 195428 kb
Host smart-194850d0-6660-444b-9b78-6fb7e937dfe8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516352500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3516352500
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.631573484
Short name T661
Test name
Test status
Simulation time 110338338560 ps
CPU time 308.95 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:31:10 PM PDT 24
Peak memory 199740 kb
Host smart-ccd14e6a-b12b-4de9-a2f4-7f68a50f8676
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631573484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.631573484
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.2172018994
Short name T973
Test name
Test status
Simulation time 7580244375 ps
CPU time 15.86 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:04 PM PDT 24
Peak memory 198668 kb
Host smart-5f40a56c-1269-4e0f-ace8-5b59cb6a517a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172018994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.2172018994
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.3547899579
Short name T698
Test name
Test status
Simulation time 22262781324 ps
CPU time 37.81 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 199068 kb
Host smart-2d809311-cc86-425e-9c08-838575d454fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547899579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.3547899579
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.2370954999
Short name T350
Test name
Test status
Simulation time 24299066678 ps
CPU time 1340.93 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:48:11 PM PDT 24
Peak memory 199756 kb
Host smart-22edaa7d-8128-42b9-9e86-e3c7a4663123
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2370954999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2370954999
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.3209741763
Short name T671
Test name
Test status
Simulation time 5713576869 ps
CPU time 11.47 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:26:00 PM PDT 24
Peak memory 197924 kb
Host smart-293d5a3f-8311-438e-818d-4b2c0ac84dff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3209741763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.3209741763
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.139256906
Short name T674
Test name
Test status
Simulation time 58650837455 ps
CPU time 72.06 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:27:07 PM PDT 24
Peak memory 199760 kb
Host smart-7a3248f0-2c49-4b52-9167-d18f57ee6b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139256906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.139256906
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.819532239
Short name T292
Test name
Test status
Simulation time 4507519044 ps
CPU time 8.07 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:26:34 PM PDT 24
Peak memory 196252 kb
Host smart-479cea99-84be-4a1b-adad-a935bb7fa292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819532239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.819532239
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.789959288
Short name T29
Test name
Test status
Simulation time 679432404 ps
CPU time 2.14 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 199188 kb
Host smart-fbb99b76-a890-4631-93cf-3e037995f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789959288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.789959288
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all.2991116097
Short name T970
Test name
Test status
Simulation time 147304682841 ps
CPU time 147.85 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:28:13 PM PDT 24
Peak memory 208152 kb
Host smart-fff762f5-cbec-43d1-be7f-1902b9579962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991116097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2991116097
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.644670550
Short name T1088
Test name
Test status
Simulation time 95533389153 ps
CPU time 896.31 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:40:42 PM PDT 24
Peak memory 216472 kb
Host smart-84094cc9-b8a9-43e1-966c-cecc1d87d67b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644670550 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.644670550
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.48212739
Short name T373
Test name
Test status
Simulation time 1810475435 ps
CPU time 2.39 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199352 kb
Host smart-9a4dc2e2-b5ee-48fa-9e9c-a473271faacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48212739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.48212739
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.917498051
Short name T623
Test name
Test status
Simulation time 99508593281 ps
CPU time 46.46 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:30 PM PDT 24
Peak memory 199700 kb
Host smart-fe4df5d0-a0bd-4b76-92e7-84bb1f66550d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917498051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.917498051
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2544525315
Short name T15
Test name
Test status
Simulation time 14415003 ps
CPU time 0.53 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 195124 kb
Host smart-cf05f577-eb4e-46a6-8f7b-8b0574991762
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544525315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2544525315
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2097659630
Short name T95
Test name
Test status
Simulation time 100353611277 ps
CPU time 102.83 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:27:25 PM PDT 24
Peak memory 199696 kb
Host smart-37b8698a-b490-4ef5-b8bf-c834fb1a884f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097659630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2097659630
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.3270263677
Short name T1032
Test name
Test status
Simulation time 12372941507 ps
CPU time 18.69 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:26:49 PM PDT 24
Peak memory 199192 kb
Host smart-bce1cb01-97a3-47f5-aa76-bd617a1d5aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270263677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.3270263677
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.1089527864
Short name T1037
Test name
Test status
Simulation time 24759676324 ps
CPU time 32.17 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:26:58 PM PDT 24
Peak memory 199628 kb
Host smart-d54f05b6-63f6-47ce-ad58-2073eb814fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089527864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.1089527864
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.440052283
Short name T945
Test name
Test status
Simulation time 26482256192 ps
CPU time 41.93 seconds
Started Jul 31 04:25:46 PM PDT 24
Finished Jul 31 04:26:28 PM PDT 24
Peak memory 196764 kb
Host smart-06332468-e3bb-49bb-9011-c1ee6cda6b2c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440052283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.440052283
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2020364737
Short name T285
Test name
Test status
Simulation time 46036655005 ps
CPU time 259.56 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:30:52 PM PDT 24
Peak memory 199700 kb
Host smart-dc07e094-424c-43cb-bb12-7abb2c6326cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2020364737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2020364737
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.3603246817
Short name T86
Test name
Test status
Simulation time 180528203 ps
CPU time 0.81 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 197024 kb
Host smart-b3c6182a-f03b-4e5d-91b8-d815b9647bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603246817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.3603246817
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.12410857
Short name T485
Test name
Test status
Simulation time 32360937739 ps
CPU time 48.18 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:31 PM PDT 24
Peak memory 197856 kb
Host smart-b8769c49-d340-47bd-a121-c6fa47d96e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12410857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.12410857
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1331303051
Short name T884
Test name
Test status
Simulation time 11145578021 ps
CPU time 715.06 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:38:16 PM PDT 24
Peak memory 199716 kb
Host smart-27030c9a-0784-4103-bc17-855ceaef4ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331303051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1331303051
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3817323644
Short name T329
Test name
Test status
Simulation time 5346417069 ps
CPU time 44.72 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:26:30 PM PDT 24
Peak memory 199208 kb
Host smart-c6c1c047-849a-41f4-b10a-a5c28753ad43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3817323644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3817323644
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.92916311
Short name T854
Test name
Test status
Simulation time 113463418867 ps
CPU time 46.07 seconds
Started Jul 31 04:26:02 PM PDT 24
Finished Jul 31 04:26:49 PM PDT 24
Peak memory 199744 kb
Host smart-6e442772-79da-431f-aeed-c48695b271ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92916311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.92916311
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.1374826679
Short name T735
Test name
Test status
Simulation time 2464801239 ps
CPU time 2.68 seconds
Started Jul 31 04:25:54 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 195740 kb
Host smart-6125b832-8dca-4cbd-8e27-a1b5314c52c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374826679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.1374826679
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.1281729846
Short name T649
Test name
Test status
Simulation time 6288001554 ps
CPU time 6.87 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 199740 kb
Host smart-e69cbf2e-ad26-4d9e-9cdb-34460089058f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281729846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.1281729846
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.3783584599
Short name T1077
Test name
Test status
Simulation time 91488232246 ps
CPU time 152.07 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:28:22 PM PDT 24
Peak memory 199748 kb
Host smart-a38bd359-0914-444e-b59b-5a325ce52e06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783584599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3783584599
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.3059731057
Short name T380
Test name
Test status
Simulation time 2360894598 ps
CPU time 2.2 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:25:45 PM PDT 24
Peak memory 198696 kb
Host smart-6459683b-e819-4ace-8ac0-c0984cc2336c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059731057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.3059731057
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.312388168
Short name T8
Test name
Test status
Simulation time 38519914200 ps
CPU time 28.67 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:26:57 PM PDT 24
Peak memory 199844 kb
Host smart-26b9f9eb-0b46-4370-87e4-de71a78d8559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312388168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.312388168
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.67676603
Short name T755
Test name
Test status
Simulation time 60953427 ps
CPU time 0.56 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:25:52 PM PDT 24
Peak memory 194544 kb
Host smart-0625e3a8-1112-44bb-bebc-6f063c0c79a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67676603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.67676603
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.439874669
Short name T1128
Test name
Test status
Simulation time 133078332197 ps
CPU time 49.98 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:26:33 PM PDT 24
Peak memory 199752 kb
Host smart-dcb51578-9c3a-4ba5-9033-36b29a5bfd46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439874669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.439874669
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.36806657
Short name T410
Test name
Test status
Simulation time 69656741154 ps
CPU time 102.67 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:28:09 PM PDT 24
Peak memory 199784 kb
Host smart-f24b04c0-a13a-46cd-99e4-4f94b7c5d9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36806657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.36806657
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.1030117638
Short name T164
Test name
Test status
Simulation time 36895260502 ps
CPU time 27.03 seconds
Started Jul 31 04:25:46 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 199648 kb
Host smart-603ee928-cdf9-4823-8a08-04cad76178f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030117638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.1030117638
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.1896510264
Short name T635
Test name
Test status
Simulation time 193903494285 ps
CPU time 312.74 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:31:00 PM PDT 24
Peak memory 199808 kb
Host smart-a5b1f3b1-cebf-4c7a-8106-ea28df2916e9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896510264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.1896510264
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.2866354690
Short name T477
Test name
Test status
Simulation time 79061213636 ps
CPU time 210.83 seconds
Started Jul 31 04:25:53 PM PDT 24
Finished Jul 31 04:29:24 PM PDT 24
Peak memory 199732 kb
Host smart-1524ae6c-5019-4d19-a46e-0570339c706f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866354690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.2866354690
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2222272103
Short name T387
Test name
Test status
Simulation time 145575278 ps
CPU time 0.65 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:00 PM PDT 24
Peak memory 195764 kb
Host smart-0f5026a6-7c8f-48ca-8ddc-220e8b73a5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222272103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2222272103
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2311694424
Short name T281
Test name
Test status
Simulation time 65969590490 ps
CPU time 25.53 seconds
Started Jul 31 04:25:43 PM PDT 24
Finished Jul 31 04:26:08 PM PDT 24
Peak memory 198120 kb
Host smart-1c39be55-47a2-4f2a-8c64-e58007eb00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311694424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2311694424
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.467813000
Short name T542
Test name
Test status
Simulation time 17205102894 ps
CPU time 897.09 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:40:53 PM PDT 24
Peak memory 199668 kb
Host smart-8ad07880-c290-4c0e-83b0-3e4e90b569b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=467813000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.467813000
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.461008317
Short name T1145
Test name
Test status
Simulation time 6979220114 ps
CPU time 35.13 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:26:35 PM PDT 24
Peak memory 197940 kb
Host smart-400ba958-fdfc-459f-9e9a-e839377c2dbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=461008317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.461008317
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.1296267157
Short name T1082
Test name
Test status
Simulation time 27264567428 ps
CPU time 10.94 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:26:00 PM PDT 24
Peak memory 199644 kb
Host smart-f7696a51-5eb7-4be8-ad41-2ee02d2aa8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296267157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.1296267157
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.4053800128
Short name T491
Test name
Test status
Simulation time 4793335660 ps
CPU time 4.59 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:25:59 PM PDT 24
Peak memory 195868 kb
Host smart-5fef6e7c-8042-4243-98c4-e48a1dc15ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053800128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4053800128
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1152829956
Short name T276
Test name
Test status
Simulation time 649561465 ps
CPU time 3.5 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:25:59 PM PDT 24
Peak memory 198084 kb
Host smart-6b71fc60-4be6-407d-9d93-ee819316d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152829956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1152829956
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.1331254146
Short name T990
Test name
Test status
Simulation time 143361703052 ps
CPU time 299.83 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:30:55 PM PDT 24
Peak memory 199728 kb
Host smart-fbcdfe77-9115-453b-9f23-a9e5671ffe4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331254146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.1331254146
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.276875774
Short name T796
Test name
Test status
Simulation time 7781697907 ps
CPU time 85.93 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 208056 kb
Host smart-077226fa-283a-4181-91d6-868f7f5cc29f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276875774 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.276875774
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.3817715984
Short name T1097
Test name
Test status
Simulation time 5022275159 ps
CPU time 2.18 seconds
Started Jul 31 04:25:46 PM PDT 24
Finished Jul 31 04:25:48 PM PDT 24
Peak memory 199560 kb
Host smart-eda3de64-7b41-49ad-9f2b-2dd24de223a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817715984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.3817715984
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2555549927
Short name T354
Test name
Test status
Simulation time 7961026064 ps
CPU time 12.77 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:25:58 PM PDT 24
Peak memory 199616 kb
Host smart-ce50f127-40af-4a3d-bfa3-6491751105f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555549927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2555549927
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.3864563712
Short name T734
Test name
Test status
Simulation time 43051255 ps
CPU time 0.55 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 195512 kb
Host smart-3239c502-053c-43d9-90fc-d8bda313f2da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864563712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.3864563712
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.2187003853
Short name T142
Test name
Test status
Simulation time 260216124113 ps
CPU time 355.7 seconds
Started Jul 31 04:25:48 PM PDT 24
Finished Jul 31 04:31:44 PM PDT 24
Peak memory 199668 kb
Host smart-031617e7-e722-469f-a457-c2eb51aee85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187003853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.2187003853
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2903975833
Short name T360
Test name
Test status
Simulation time 127792269917 ps
CPU time 26.03 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 199608 kb
Host smart-ee5c3b90-5882-4918-8c3d-98598d183079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903975833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2903975833
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.754478257
Short name T909
Test name
Test status
Simulation time 22795103109 ps
CPU time 36.7 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:26:22 PM PDT 24
Peak memory 199504 kb
Host smart-f8d4ea06-b535-497e-ac7f-7e0a90ddc706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754478257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.754478257
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2907506657
Short name T1028
Test name
Test status
Simulation time 7686007146 ps
CPU time 5.46 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 199748 kb
Host smart-cf6f1e2b-cd40-45db-aa66-8ed256180498
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907506657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2907506657
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3518204838
Short name T594
Test name
Test status
Simulation time 119502899002 ps
CPU time 161.68 seconds
Started Jul 31 04:25:54 PM PDT 24
Finished Jul 31 04:28:36 PM PDT 24
Peak memory 199672 kb
Host smart-5b5aa3e9-92a4-45e7-bbb2-2eebdaf0118b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518204838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3518204838
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.2598638481
Short name T1068
Test name
Test status
Simulation time 1309581510 ps
CPU time 3.7 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 198032 kb
Host smart-a9aa8f17-8bb7-467f-8647-eaf52720c2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598638481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.2598638481
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1858340957
Short name T862
Test name
Test status
Simulation time 165045279507 ps
CPU time 88.93 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:27:20 PM PDT 24
Peak memory 208060 kb
Host smart-76487306-4603-4030-b16d-0e93be3c371a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858340957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1858340957
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.1430002829
Short name T1099
Test name
Test status
Simulation time 10835010627 ps
CPU time 470.16 seconds
Started Jul 31 04:25:54 PM PDT 24
Finished Jul 31 04:33:44 PM PDT 24
Peak memory 199756 kb
Host smart-e60c67cf-b5eb-438a-b8ae-4ed832054e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430002829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1430002829
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.179166841
Short name T334
Test name
Test status
Simulation time 5850353245 ps
CPU time 50.16 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:26:38 PM PDT 24
Peak memory 199504 kb
Host smart-d4b89bb1-e051-43cf-8e3f-5a66b3fddc6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=179166841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.179166841
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.4255212040
Short name T378
Test name
Test status
Simulation time 30738913564 ps
CPU time 41.07 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:26:36 PM PDT 24
Peak memory 199692 kb
Host smart-a43b8ed3-6455-4aca-b6e9-1cd2fb07ebea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255212040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.4255212040
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.2536804977
Short name T87
Test name
Test status
Simulation time 31607126401 ps
CPU time 7.44 seconds
Started Jul 31 04:25:57 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 195556 kb
Host smart-db56e839-827f-4423-8bd2-6b7e0f86fc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536804977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.2536804977
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.3328584686
Short name T707
Test name
Test status
Simulation time 531913245 ps
CPU time 2.11 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:25:49 PM PDT 24
Peak memory 198152 kb
Host smart-2a842da1-e940-4abb-989c-e673b867e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328584686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3328584686
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.801175824
Short name T609
Test name
Test status
Simulation time 65649352174 ps
CPU time 243.1 seconds
Started Jul 31 04:25:52 PM PDT 24
Finished Jul 31 04:29:56 PM PDT 24
Peak memory 199732 kb
Host smart-0a7b2b6f-0e27-4ae3-a49a-ebaa696808ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801175824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.801175824
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1864755449
Short name T21
Test name
Test status
Simulation time 27273824466 ps
CPU time 233.42 seconds
Started Jul 31 04:25:52 PM PDT 24
Finished Jul 31 04:29:46 PM PDT 24
Peak memory 216256 kb
Host smart-dd90ce2d-dc16-42dc-ba2c-e1b5e62559e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864755449 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1864755449
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.1099591409
Short name T550
Test name
Test status
Simulation time 1305509914 ps
CPU time 3.73 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 198116 kb
Host smart-8b5c7fd1-3b03-43f9-b3f7-9413e7568673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099591409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1099591409
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.436696655
Short name T245
Test name
Test status
Simulation time 125338530937 ps
CPU time 44 seconds
Started Jul 31 04:25:52 PM PDT 24
Finished Jul 31 04:26:36 PM PDT 24
Peak memory 199796 kb
Host smart-7a1bfc78-34db-4539-8fb5-59b58fd011f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436696655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.436696655
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.2896954357
Short name T683
Test name
Test status
Simulation time 13175121 ps
CPU time 0.53 seconds
Started Jul 31 04:25:56 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 195112 kb
Host smart-de6795b2-b4a3-4a9b-928c-2164233fc826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896954357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2896954357
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3409257819
Short name T931
Test name
Test status
Simulation time 52482097368 ps
CPU time 21.35 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 199736 kb
Host smart-54a0fcb8-35e8-40aa-94a2-c312dd06080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409257819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3409257819
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2148852296
Short name T856
Test name
Test status
Simulation time 52727227612 ps
CPU time 18.16 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:17 PM PDT 24
Peak memory 198764 kb
Host smart-372cc1b4-6908-4db8-993c-aaa52a1c13ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148852296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2148852296
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2164519057
Short name T229
Test name
Test status
Simulation time 164832013440 ps
CPU time 61.23 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:26:50 PM PDT 24
Peak memory 199864 kb
Host smart-b8e4d953-ac5f-4a4e-bf0c-9f4bd96e0e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164519057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2164519057
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.799389313
Short name T627
Test name
Test status
Simulation time 14447359467 ps
CPU time 13.57 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:26:04 PM PDT 24
Peak memory 199704 kb
Host smart-266b6e1e-9d2c-4b97-a011-f871a7118746
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799389313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.799389313
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1613887907
Short name T484
Test name
Test status
Simulation time 235378853747 ps
CPU time 407.02 seconds
Started Jul 31 04:25:47 PM PDT 24
Finished Jul 31 04:32:35 PM PDT 24
Peak memory 199748 kb
Host smart-33e96cfe-0144-4812-93ed-b04c687cd151
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1613887907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1613887907
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.941692686
Short name T371
Test name
Test status
Simulation time 3629517391 ps
CPU time 7.68 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 198572 kb
Host smart-840a528d-a59e-4541-8ac3-b7138412d154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941692686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.941692686
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.1677151761
Short name T295
Test name
Test status
Simulation time 152717596694 ps
CPU time 107.43 seconds
Started Jul 31 04:25:45 PM PDT 24
Finished Jul 31 04:27:32 PM PDT 24
Peak memory 207940 kb
Host smart-e9e32b80-20d2-4bfc-9c5b-f47a20113d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677151761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1677151761
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.1697073496
Short name T498
Test name
Test status
Simulation time 4237873957 ps
CPU time 28.39 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:26:18 PM PDT 24
Peak memory 199736 kb
Host smart-3f9580af-8a6b-4018-964c-1c3b7aee4c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1697073496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.1697073496
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.950009482
Short name T571
Test name
Test status
Simulation time 6862420944 ps
CPU time 60.57 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:27:05 PM PDT 24
Peak memory 198004 kb
Host smart-f682bd27-616d-45a0-ae14-ab4e5ba0b25b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=950009482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.950009482
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.1447867109
Short name T885
Test name
Test status
Simulation time 262216721840 ps
CPU time 109.83 seconds
Started Jul 31 04:25:54 PM PDT 24
Finished Jul 31 04:27:44 PM PDT 24
Peak memory 199684 kb
Host smart-d23c7e52-a953-437b-af1e-825d689eb95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447867109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.1447867109
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.3800619348
Short name T889
Test name
Test status
Simulation time 30857926788 ps
CPU time 39.26 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:37 PM PDT 24
Peak memory 196552 kb
Host smart-8e98b5f6-2b5c-4e0b-b030-a161eda20901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800619348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.3800619348
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1584420008
Short name T1141
Test name
Test status
Simulation time 616200402 ps
CPU time 1.64 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 197768 kb
Host smart-aecc0ee8-8b73-443d-9189-0088dbb6cd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584420008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1584420008
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.1404317050
Short name T957
Test name
Test status
Simulation time 451089131325 ps
CPU time 303.5 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:31:03 PM PDT 24
Peak memory 199720 kb
Host smart-1bbf2f35-a488-4cd7-87e8-7691a963872a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404317050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.1404317050
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.69715061
Short name T1056
Test name
Test status
Simulation time 293739404468 ps
CPU time 420.55 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:33:08 PM PDT 24
Peak memory 216388 kb
Host smart-1b7a6a68-8c5e-49be-a542-afb47393c556
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69715061 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.69715061
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1218353744
Short name T343
Test name
Test status
Simulation time 337559173 ps
CPU time 0.83 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:25:50 PM PDT 24
Peak memory 197808 kb
Host smart-4146fe6e-478d-4fd6-9139-8de74144a854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218353744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1218353744
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4070297429
Short name T398
Test name
Test status
Simulation time 6367056477 ps
CPU time 2.04 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:46 PM PDT 24
Peak memory 196996 kb
Host smart-2b54e829-1e66-45b5-83c4-ef7e5807a757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070297429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4070297429
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.3008546018
Short name T1133
Test name
Test status
Simulation time 12859341 ps
CPU time 0.58 seconds
Started Jul 31 04:22:19 PM PDT 24
Finished Jul 31 04:22:20 PM PDT 24
Peak memory 194356 kb
Host smart-b594f904-e886-4ed9-9a7f-2d6f6d3ab1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008546018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3008546018
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.3284695266
Short name T893
Test name
Test status
Simulation time 87122184905 ps
CPU time 29.23 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:25:24 PM PDT 24
Peak memory 197724 kb
Host smart-7d7127b8-1d8f-4d54-9d25-f952e1ded05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284695266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.3284695266
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2304280769
Short name T687
Test name
Test status
Simulation time 46569639920 ps
CPU time 33.29 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:24:21 PM PDT 24
Peak memory 199656 kb
Host smart-a3d5859f-6c1c-42b5-b2e3-acd27ab50806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304280769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2304280769
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.1764832887
Short name T431
Test name
Test status
Simulation time 192532707420 ps
CPU time 43.18 seconds
Started Jul 31 04:25:42 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 199516 kb
Host smart-e8a0e52a-d236-4ea6-8f7e-c354ba1795d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764832887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.1764832887
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1154588528
Short name T502
Test name
Test status
Simulation time 281016165986 ps
CPU time 125.9 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:25:54 PM PDT 24
Peak memory 199748 kb
Host smart-116446b9-38a4-41d4-8bc5-042942169092
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154588528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1154588528
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.479656654
Short name T254
Test name
Test status
Simulation time 75932891655 ps
CPU time 715.99 seconds
Started Jul 31 04:23:34 PM PDT 24
Finished Jul 31 04:35:30 PM PDT 24
Peak memory 199344 kb
Host smart-d44060a9-051c-4ed5-919c-2c2b27b08529
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=479656654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.479656654
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.721722447
Short name T1060
Test name
Test status
Simulation time 676274351 ps
CPU time 1.88 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:25:46 PM PDT 24
Peak memory 197240 kb
Host smart-8df478d6-716a-4ffb-94c2-c33f195a4a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721722447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.721722447
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.452531765
Short name T982
Test name
Test status
Simulation time 149723436948 ps
CPU time 67.56 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 199628 kb
Host smart-6edeff08-50d3-4a04-aca8-0ca36ad659b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452531765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.452531765
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.824195445
Short name T447
Test name
Test status
Simulation time 17557076003 ps
CPU time 958.66 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:41:37 PM PDT 24
Peak memory 199612 kb
Host smart-e1c6568c-f7fb-4ac2-bd70-09e59941b255
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=824195445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.824195445
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.169895229
Short name T504
Test name
Test status
Simulation time 6968119655 ps
CPU time 10.89 seconds
Started Jul 31 04:23:39 PM PDT 24
Finished Jul 31 04:23:50 PM PDT 24
Peak memory 197628 kb
Host smart-d0c851e7-2047-4e26-979e-8b9e4eaef9b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169895229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.169895229
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.372405425
Short name T132
Test name
Test status
Simulation time 65300114078 ps
CPU time 28.45 seconds
Started Jul 31 04:21:52 PM PDT 24
Finished Jul 31 04:22:21 PM PDT 24
Peak memory 199740 kb
Host smart-3358eb20-b10e-4c67-a4f5-be76707d7264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372405425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.372405425
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1441701893
Short name T857
Test name
Test status
Simulation time 41559100343 ps
CPU time 16.76 seconds
Started Jul 31 04:23:38 PM PDT 24
Finished Jul 31 04:23:55 PM PDT 24
Peak memory 194720 kb
Host smart-3f6547ae-dbb3-4c9b-a49e-06199b9887e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441701893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1441701893
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2514701880
Short name T19
Test name
Test status
Simulation time 113891441 ps
CPU time 0.86 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 217748 kb
Host smart-5ebe1645-4834-41c4-8c8c-8c35e532e01f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514701880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2514701880
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.1664815437
Short name T554
Test name
Test status
Simulation time 443998116 ps
CPU time 2 seconds
Started Jul 31 04:22:36 PM PDT 24
Finished Jul 31 04:22:38 PM PDT 24
Peak memory 198148 kb
Host smart-95d9687b-a76d-412d-ba5d-8253aea072e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664815437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1664815437
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.3482575784
Short name T1169
Test name
Test status
Simulation time 1297336361761 ps
CPU time 601.06 seconds
Started Jul 31 04:21:57 PM PDT 24
Finished Jul 31 04:31:59 PM PDT 24
Peak memory 208092 kb
Host smart-a429f3c8-8fa7-42db-8066-a0566163e50c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482575784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3482575784
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.2941105243
Short name T80
Test name
Test status
Simulation time 109293770985 ps
CPU time 294.76 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:30:39 PM PDT 24
Peak memory 209224 kb
Host smart-1c4b3b23-c604-42b7-bfb6-d5fc6c717bde
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941105243 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.2941105243
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.2093913066
Short name T476
Test name
Test status
Simulation time 956661591 ps
CPU time 1.78 seconds
Started Jul 31 04:22:02 PM PDT 24
Finished Jul 31 04:22:04 PM PDT 24
Peak memory 199052 kb
Host smart-f4fcac22-8686-4de5-85af-169559572719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093913066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.2093913066
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.883444921
Short name T399
Test name
Test status
Simulation time 103115442534 ps
CPU time 54.44 seconds
Started Jul 31 04:22:28 PM PDT 24
Finished Jul 31 04:23:22 PM PDT 24
Peak memory 200104 kb
Host smart-75949826-15a5-435b-a0c1-7fcd0bd58041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883444921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.883444921
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.626738528
Short name T474
Test name
Test status
Simulation time 41270130 ps
CPU time 0.54 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:08 PM PDT 24
Peak memory 195136 kb
Host smart-606a5cee-9cd1-452c-81f5-f938232eb038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626738528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.626738528
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.624212334
Short name T143
Test name
Test status
Simulation time 86245857757 ps
CPU time 129.87 seconds
Started Jul 31 04:25:51 PM PDT 24
Finished Jul 31 04:28:01 PM PDT 24
Peak memory 199744 kb
Host smart-327dfd25-a2d4-4d9f-b47b-406f0b9d1aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624212334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.624212334
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.1264841969
Short name T274
Test name
Test status
Simulation time 37048016843 ps
CPU time 14.3 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:26:05 PM PDT 24
Peak memory 199704 kb
Host smart-f39e2545-c200-4c7e-92f7-94c1d8c64c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264841969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.1264841969
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1717153822
Short name T104
Test name
Test status
Simulation time 293835300879 ps
CPU time 124.55 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:28:00 PM PDT 24
Peak memory 199800 kb
Host smart-d03f56f0-c046-4dd6-b65d-0735a5a34475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717153822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1717153822
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.937248473
Short name T88
Test name
Test status
Simulation time 34540782945 ps
CPU time 15.2 seconds
Started Jul 31 04:25:54 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 199656 kb
Host smart-1a7f2fd8-bbae-4a0a-9473-222a7958254d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937248473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.937248473
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3914553247
Short name T675
Test name
Test status
Simulation time 156135954688 ps
CPU time 1562.45 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:51:58 PM PDT 24
Peak memory 199712 kb
Host smart-bde7bd81-f6a4-495b-914b-55f1cd561722
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3914553247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3914553247
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.753605668
Short name T821
Test name
Test status
Simulation time 948707808 ps
CPU time 0.81 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:26:09 PM PDT 24
Peak memory 197072 kb
Host smart-c5d1e106-8d1e-4efd-9458-4028562c0dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753605668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.753605668
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.2583667749
Short name T733
Test name
Test status
Simulation time 91904387706 ps
CPU time 70.55 seconds
Started Jul 31 04:26:04 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199916 kb
Host smart-95be2315-3edb-4061-a936-6c1bcffbfad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583667749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.2583667749
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.859081352
Short name T267
Test name
Test status
Simulation time 8710492263 ps
CPU time 119.51 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:28:00 PM PDT 24
Peak memory 199728 kb
Host smart-c960bef4-4f24-4e21-87ff-3cba07363595
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=859081352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.859081352
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.565201053
Short name T775
Test name
Test status
Simulation time 5842292918 ps
CPU time 54.2 seconds
Started Jul 31 04:25:52 PM PDT 24
Finished Jul 31 04:26:46 PM PDT 24
Peak memory 198460 kb
Host smart-2cf84e91-9ba6-4fe6-815f-df22613005b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=565201053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.565201053
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2170115207
Short name T993
Test name
Test status
Simulation time 24717106384 ps
CPU time 44.75 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 199628 kb
Host smart-145da33f-dead-4701-8700-a8c5b0f5873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170115207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2170115207
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2322883309
Short name T842
Test name
Test status
Simulation time 34967592998 ps
CPU time 29.15 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:28 PM PDT 24
Peak memory 196632 kb
Host smart-b638f54e-3fe8-4f2e-a6f5-f2c431e2143c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322883309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2322883309
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.1768272461
Short name T454
Test name
Test status
Simulation time 5383412011 ps
CPU time 14.76 seconds
Started Jul 31 04:26:06 PM PDT 24
Finished Jul 31 04:26:22 PM PDT 24
Peak memory 199128 kb
Host smart-6f1c7402-0d98-4697-87b1-43078d924f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768272461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.1768272461
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.3684739027
Short name T996
Test name
Test status
Simulation time 139002801958 ps
CPU time 267.28 seconds
Started Jul 31 04:25:50 PM PDT 24
Finished Jul 31 04:30:17 PM PDT 24
Peak memory 216200 kb
Host smart-2127f58c-0667-41fd-b04d-6d62c9e1ee56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684739027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3684739027
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1360938388
Short name T460
Test name
Test status
Simulation time 92858596583 ps
CPU time 394.64 seconds
Started Jul 31 04:25:49 PM PDT 24
Finished Jul 31 04:32:24 PM PDT 24
Peak memory 216272 kb
Host smart-d6efc8c3-e27b-4949-9a34-3b93a7470f0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360938388 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1360938388
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.2301483864
Short name T869
Test name
Test status
Simulation time 985274389 ps
CPU time 1.58 seconds
Started Jul 31 04:26:02 PM PDT 24
Finished Jul 31 04:26:04 PM PDT 24
Peak memory 199484 kb
Host smart-54918894-b632-4ca4-9ea4-b88a784bbffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301483864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.2301483864
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.1173163450
Short name T467
Test name
Test status
Simulation time 178443303423 ps
CPU time 68.44 seconds
Started Jul 31 04:26:00 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199500 kb
Host smart-562c234c-ae03-4942-b310-b734e0e71a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173163450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.1173163450
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.604972156
Short name T1119
Test name
Test status
Simulation time 176248719 ps
CPU time 0.54 seconds
Started Jul 31 04:25:56 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 195184 kb
Host smart-d3035e33-b4b6-4bf7-b87e-c8198394e19e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604972156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.604972156
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4082675295
Short name T1092
Test name
Test status
Simulation time 77634596544 ps
CPU time 33.5 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:33 PM PDT 24
Peak memory 199732 kb
Host smart-a2c5d1c1-d755-4792-89b4-e1d28e01351a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082675295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4082675295
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2669625649
Short name T739
Test name
Test status
Simulation time 52002401512 ps
CPU time 35.59 seconds
Started Jul 31 04:25:56 PM PDT 24
Finished Jul 31 04:26:31 PM PDT 24
Peak memory 199860 kb
Host smart-024d9bd1-49cd-4a6f-9349-d4a06d06e778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669625649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2669625649
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1577798168
Short name T199
Test name
Test status
Simulation time 20996987354 ps
CPU time 32.06 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:30 PM PDT 24
Peak memory 199448 kb
Host smart-ead8ae35-6511-4af9-9b77-e425e044d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577798168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1577798168
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.377226129
Short name T283
Test name
Test status
Simulation time 136196002628 ps
CPU time 243.94 seconds
Started Jul 31 04:26:01 PM PDT 24
Finished Jul 31 04:30:05 PM PDT 24
Peak memory 199716 kb
Host smart-ec8a275c-08d5-46ef-9703-c7174b3498ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377226129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.377226129
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.2481963505
Short name T792
Test name
Test status
Simulation time 92221924327 ps
CPU time 383.05 seconds
Started Jul 31 04:26:06 PM PDT 24
Finished Jul 31 04:32:29 PM PDT 24
Peak memory 199788 kb
Host smart-1772cb49-dacc-47f4-9383-81fb1634c1c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2481963505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.2481963505
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.517001651
Short name T855
Test name
Test status
Simulation time 6227611150 ps
CPU time 3.15 seconds
Started Jul 31 04:26:11 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 196296 kb
Host smart-7180c71b-c108-4c9b-a6a8-872e1c05a1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517001651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.517001651
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.4034865839
Short name T2
Test name
Test status
Simulation time 61138806076 ps
CPU time 11.17 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:09 PM PDT 24
Peak memory 198500 kb
Host smart-9fd1dae9-69fb-4b81-891a-e6812a01024f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034865839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.4034865839
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4043370419
Short name T367
Test name
Test status
Simulation time 7675910787 ps
CPU time 424.44 seconds
Started Jul 31 04:26:02 PM PDT 24
Finished Jul 31 04:33:07 PM PDT 24
Peak memory 199812 kb
Host smart-0fec5ce5-71a2-400a-80ee-1a856ac7e6b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4043370419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4043370419
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.1432104087
Short name T511
Test name
Test status
Simulation time 2459568809 ps
CPU time 4.19 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 198020 kb
Host smart-6855d114-60b2-4ac7-8510-e75ff59e92c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432104087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.1432104087
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.2518353116
Short name T434
Test name
Test status
Simulation time 27476021703 ps
CPU time 46.22 seconds
Started Jul 31 04:25:53 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199712 kb
Host smart-6a1ef25c-cbf8-46d2-a6b6-1630662e03fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518353116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.2518353116
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.652036496
Short name T772
Test name
Test status
Simulation time 1647012462 ps
CPU time 1.35 seconds
Started Jul 31 04:25:55 PM PDT 24
Finished Jul 31 04:25:56 PM PDT 24
Peak memory 195208 kb
Host smart-1fec09e5-c305-4fee-b105-02ddfd00956e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652036496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.652036496
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.83371565
Short name T76
Test name
Test status
Simulation time 5758780289 ps
CPU time 29.39 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:26:35 PM PDT 24
Peak memory 199648 kb
Host smart-b79e19fb-1298-4e6a-8b05-6d44822fbc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83371565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.83371565
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.1674848612
Short name T180
Test name
Test status
Simulation time 86893581470 ps
CPU time 1281.65 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:47:27 PM PDT 24
Peak memory 227776 kb
Host smart-d534a19c-fbb6-4c50-b038-de7d3399c024
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674848612 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.1674848612
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.726517403
Short name T1036
Test name
Test status
Simulation time 2378329049 ps
CPU time 1.8 seconds
Started Jul 31 04:25:53 PM PDT 24
Finished Jul 31 04:25:55 PM PDT 24
Peak memory 197996 kb
Host smart-ab7fa476-2f29-4268-941c-082f9c76fef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726517403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.726517403
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.2145287661
Short name T421
Test name
Test status
Simulation time 9584429383 ps
CPU time 14.45 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 199744 kb
Host smart-7b40ab87-f167-4f75-835d-3c2143c6f40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145287661 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.2145287661
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3107541252
Short name T512
Test name
Test status
Simulation time 18591569 ps
CPU time 0.52 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:26:16 PM PDT 24
Peak memory 195172 kb
Host smart-6e7e5b22-965e-47e5-9081-94640be4749f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107541252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3107541252
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.1264554720
Short name T1118
Test name
Test status
Simulation time 49132154268 ps
CPU time 37.44 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 199744 kb
Host smart-2ef3853c-a837-435b-b15c-21a578d24a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264554720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.1264554720
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1756340784
Short name T745
Test name
Test status
Simulation time 85522563895 ps
CPU time 36.67 seconds
Started Jul 31 04:26:03 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199828 kb
Host smart-0ee45bfc-6e79-4585-96e0-bfbecc0c4e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756340784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1756340784
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.3283110268
Short name T160
Test name
Test status
Simulation time 53037468516 ps
CPU time 27.2 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199704 kb
Host smart-1799024a-7c4a-4cd3-a48e-8961985cc450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283110268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.3283110268
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.874556475
Short name T844
Test name
Test status
Simulation time 301894244293 ps
CPU time 41.94 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:26:47 PM PDT 24
Peak memory 198052 kb
Host smart-d813af12-7ffa-4289-b7a3-6df5fd51d7a1
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874556475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.874556475
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2163241044
Short name T852
Test name
Test status
Simulation time 89582951009 ps
CPU time 390.89 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:32:44 PM PDT 24
Peak memory 199796 kb
Host smart-d840ba5c-5efd-43b5-adba-ee24afc1946b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163241044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2163241044
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.1333626092
Short name T992
Test name
Test status
Simulation time 1211606317 ps
CPU time 1.18 seconds
Started Jul 31 04:26:10 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 195896 kb
Host smart-bbcabdda-3d93-4b40-8984-c375411fab89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333626092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.1333626092
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3804785418
Short name T395
Test name
Test status
Simulation time 67118711410 ps
CPU time 261.21 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:30:27 PM PDT 24
Peak memory 198880 kb
Host smart-66b4bcba-4b69-4cbd-97d9-403d61e8c180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804785418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3804785418
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.4026525290
Short name T729
Test name
Test status
Simulation time 27357757041 ps
CPU time 181.75 seconds
Started Jul 31 04:26:10 PM PDT 24
Finished Jul 31 04:29:11 PM PDT 24
Peak memory 199792 kb
Host smart-40386afe-a08f-4fc8-a24a-2b4eb80fac54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4026525290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.4026525290
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.2985551448
Short name T813
Test name
Test status
Simulation time 2876578044 ps
CPU time 5.35 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 197828 kb
Host smart-f0810b1b-945e-4a3b-8d62-8481f046e89f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985551448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.2985551448
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2335804543
Short name T591
Test name
Test status
Simulation time 122052997771 ps
CPU time 31.66 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 199776 kb
Host smart-f8d1cbbd-b3d5-49c9-a74d-d967b2a70bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335804543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2335804543
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1537096440
Short name T370
Test name
Test status
Simulation time 32117242441 ps
CPU time 12.02 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:19 PM PDT 24
Peak memory 195856 kb
Host smart-0cd3eb6f-7f37-40ce-b8d3-41d539c4612a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537096440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1537096440
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.2921676513
Short name T653
Test name
Test status
Simulation time 501521117 ps
CPU time 1.24 seconds
Started Jul 31 04:26:05 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 198384 kb
Host smart-090b171c-c700-470b-a49d-40076bc8f1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921676513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.2921676513
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.3722409189
Short name T925
Test name
Test status
Simulation time 438492353583 ps
CPU time 195.76 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:29:24 PM PDT 24
Peak memory 199712 kb
Host smart-50f50d74-5909-4b20-81df-4daea11bd0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722409189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.3722409189
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.3866188669
Short name T264
Test name
Test status
Simulation time 90673813765 ps
CPU time 268.98 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:30:42 PM PDT 24
Peak memory 216468 kb
Host smart-957a51d1-d324-455a-ab74-d6afa71b1bf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866188669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.3866188669
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.4222101624
Short name T789
Test name
Test status
Simulation time 7248795098 ps
CPU time 7.93 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 199788 kb
Host smart-7646df1d-2d4d-4f95-8fc1-f2d583a1da9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222101624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.4222101624
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.1784510160
Short name T1115
Test name
Test status
Simulation time 591781135 ps
CPU time 0.82 seconds
Started Jul 31 04:25:56 PM PDT 24
Finished Jul 31 04:25:57 PM PDT 24
Peak memory 197024 kb
Host smart-9ada81c3-cdc9-4f1f-820f-59f85e158d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784510160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1784510160
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.3579744564
Short name T605
Test name
Test status
Simulation time 35047465 ps
CPU time 0.54 seconds
Started Jul 31 04:26:09 PM PDT 24
Finished Jul 31 04:26:10 PM PDT 24
Peak memory 195128 kb
Host smart-2b82cba1-cdf3-475a-b4e0-2d0bfc584dad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579744564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3579744564
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1387250308
Short name T150
Test name
Test status
Simulation time 131321911680 ps
CPU time 86 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199636 kb
Host smart-838f18a9-afad-4d64-beeb-deddc3c8a3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387250308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1387250308
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1247242179
Short name T222
Test name
Test status
Simulation time 39116001877 ps
CPU time 61.76 seconds
Started Jul 31 04:26:09 PM PDT 24
Finished Jul 31 04:27:11 PM PDT 24
Peak memory 199656 kb
Host smart-dc499655-6b59-4725-b1c5-e83047844a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247242179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1247242179
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.2201642697
Short name T1005
Test name
Test status
Simulation time 13198896128 ps
CPU time 31.95 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:14 PM PDT 24
Peak memory 199728 kb
Host smart-446df244-e9ee-4e20-830c-0e370fe5b1a5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201642697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2201642697
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.1756636525
Short name T290
Test name
Test status
Simulation time 138275933313 ps
CPU time 804.73 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:39:39 PM PDT 24
Peak memory 199660 kb
Host smart-fbbc8435-b777-404a-a209-589dc606258a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756636525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.1756636525
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.3502802803
Short name T921
Test name
Test status
Simulation time 4596562682 ps
CPU time 4.86 seconds
Started Jul 31 04:26:04 PM PDT 24
Finished Jul 31 04:26:09 PM PDT 24
Peak memory 199212 kb
Host smart-f5b9a9de-6b15-4ae9-b50b-2eaf4961e887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502802803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.3502802803
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.813398815
Short name T721
Test name
Test status
Simulation time 185036852156 ps
CPU time 96.15 seconds
Started Jul 31 04:26:11 PM PDT 24
Finished Jul 31 04:27:47 PM PDT 24
Peak memory 208000 kb
Host smart-f6d48d26-bc94-4904-91e0-30ac023e09b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813398815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.813398815
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.189501418
Short name T983
Test name
Test status
Simulation time 25650757071 ps
CPU time 1259.77 seconds
Started Jul 31 04:26:15 PM PDT 24
Finished Jul 31 04:47:15 PM PDT 24
Peak memory 199716 kb
Host smart-0ce95113-72d7-4c09-a2d6-a760f3f2a162
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=189501418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.189501418
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.2519054044
Short name T328
Test name
Test status
Simulation time 4634080698 ps
CPU time 30.41 seconds
Started Jul 31 04:26:15 PM PDT 24
Finished Jul 31 04:26:46 PM PDT 24
Peak memory 199084 kb
Host smart-b56035a2-3222-4903-84a3-f47e2c1b2491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519054044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.2519054044
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.880879301
Short name T375
Test name
Test status
Simulation time 34710205502 ps
CPU time 14.89 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 198556 kb
Host smart-97d2b547-6723-4dfa-8df4-03e352bc5711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880879301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.880879301
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3989893211
Short name T848
Test name
Test status
Simulation time 4819135858 ps
CPU time 7.64 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:26 PM PDT 24
Peak memory 195948 kb
Host smart-759dc8f9-34c0-4d51-8d60-0605bdd27dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989893211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3989893211
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3831563746
Short name T544
Test name
Test status
Simulation time 880973380 ps
CPU time 3.77 seconds
Started Jul 31 04:26:09 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 198680 kb
Host smart-6648c2ca-84a9-443a-850c-32d2dced9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831563746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3831563746
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.4056077269
Short name T853
Test name
Test status
Simulation time 429363212689 ps
CPU time 469.86 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:34:02 PM PDT 24
Peak memory 208112 kb
Host smart-63e579f4-7771-4fcb-ad14-691bc8742458
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056077269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.4056077269
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.1203957573
Short name T1067
Test name
Test status
Simulation time 1935065694 ps
CPU time 2.36 seconds
Started Jul 31 04:26:11 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 198696 kb
Host smart-4c96f790-7ea5-4deb-a461-97c708209c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203957573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1203957573
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1118775634
Short name T863
Test name
Test status
Simulation time 90470242720 ps
CPU time 137.89 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:28:30 PM PDT 24
Peak memory 199612 kb
Host smart-438690ac-5ae3-44cb-a60f-3b2083d52745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118775634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1118775634
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.4118038401
Short name T536
Test name
Test status
Simulation time 10902124 ps
CPU time 0.54 seconds
Started Jul 31 04:26:11 PM PDT 24
Finished Jul 31 04:26:11 PM PDT 24
Peak memory 194028 kb
Host smart-af537ae2-ff7f-4271-91db-4a31827b49e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118038401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.4118038401
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.259962588
Short name T7
Test name
Test status
Simulation time 35873373612 ps
CPU time 32.74 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:26:40 PM PDT 24
Peak memory 199720 kb
Host smart-2ffa7988-b546-4c6f-9348-ce3df0ba7e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259962588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.259962588
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.1297018005
Short name T272
Test name
Test status
Simulation time 110275932658 ps
CPU time 220.76 seconds
Started Jul 31 04:26:35 PM PDT 24
Finished Jul 31 04:30:16 PM PDT 24
Peak memory 199792 kb
Host smart-9099c9b1-b036-4c97-bc28-c1ca3642639b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297018005 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.1297018005
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.4002201508
Short name T1171
Test name
Test status
Simulation time 67741352756 ps
CPU time 104.06 seconds
Started Jul 31 04:26:07 PM PDT 24
Finished Jul 31 04:27:51 PM PDT 24
Peak memory 199760 kb
Host smart-8435193d-c7bc-4229-965c-9720702d670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002201508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.4002201508
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.176183434
Short name T641
Test name
Test status
Simulation time 24859792354 ps
CPU time 11.24 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 199732 kb
Host smart-2ad4f5cd-54a8-4e99-9e5b-b89418675796
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176183434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.176183434
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2282621882
Short name T643
Test name
Test status
Simulation time 71825084237 ps
CPU time 141.04 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:28:34 PM PDT 24
Peak memory 199844 kb
Host smart-686bb3a0-04ef-4610-b6f9-78d4499c5bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282621882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2282621882
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.704426776
Short name T823
Test name
Test status
Simulation time 4618013245 ps
CPU time 9.62 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:23 PM PDT 24
Peak memory 198664 kb
Host smart-6bb8860a-e8ef-497f-ab53-9de6fb558d59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704426776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.704426776
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_perf.1271403675
Short name T302
Test name
Test status
Simulation time 6529086720 ps
CPU time 92.5 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:27:49 PM PDT 24
Peak memory 199744 kb
Host smart-ec0f0c57-f841-45b4-9989-ee28dd773a37
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1271403675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.1271403675
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.778321219
Short name T1154
Test name
Test status
Simulation time 4031537594 ps
CPU time 8.07 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:32 PM PDT 24
Peak memory 197848 kb
Host smart-f441cdbd-b00c-4c3b-be3e-0841162e7017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778321219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.778321219
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.660827656
Short name T1071
Test name
Test status
Simulation time 8523919682 ps
CPU time 13.24 seconds
Started Jul 31 04:26:20 PM PDT 24
Finished Jul 31 04:26:34 PM PDT 24
Peak memory 198908 kb
Host smart-d819fdc1-fa09-46d5-b8fd-79c401e6cd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660827656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.660827656
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2210364775
Short name T611
Test name
Test status
Simulation time 41921951443 ps
CPU time 63.97 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:27:28 PM PDT 24
Peak memory 196572 kb
Host smart-8e3eb76c-ca21-4c52-958b-4356c2ebc4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210364775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2210364775
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.3597754853
Short name T253
Test name
Test status
Simulation time 6054238083 ps
CPU time 11.55 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:26:46 PM PDT 24
Peak memory 199700 kb
Host smart-8500c8bc-211d-4b4d-98fc-42a3bd0d58b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597754853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.3597754853
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.2922752468
Short name T870
Test name
Test status
Simulation time 102422762387 ps
CPU time 42 seconds
Started Jul 31 04:26:15 PM PDT 24
Finished Jul 31 04:26:57 PM PDT 24
Peak memory 199780 kb
Host smart-1ab5c530-7fdf-459e-a841-def0ebfc1efb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922752468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.2922752468
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.412443438
Short name T1018
Test name
Test status
Simulation time 1172904141 ps
CPU time 1.74 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 198756 kb
Host smart-942654d5-7fe7-4e21-aa30-e1948158fcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412443438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.412443438
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.1292205146
Short name T965
Test name
Test status
Simulation time 107265376016 ps
CPU time 174.22 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:29:37 PM PDT 24
Peak memory 199744 kb
Host smart-1806b080-1916-4393-9023-60942bdc5820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292205146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1292205146
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3997595410
Short name T327
Test name
Test status
Simulation time 36362000 ps
CPU time 0.54 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:19 PM PDT 24
Peak memory 194104 kb
Host smart-510a1b80-d34b-40f6-af90-0165dc3c775e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997595410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3997595410
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.3593556094
Short name T568
Test name
Test status
Simulation time 55320150402 ps
CPU time 25.88 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:26:52 PM PDT 24
Peak memory 199684 kb
Host smart-27f4fa66-8ef6-4ca0-a198-02e25383a7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593556094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.3593556094
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.807617325
Short name T433
Test name
Test status
Simulation time 44043159913 ps
CPU time 47.6 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:26:56 PM PDT 24
Peak memory 199796 kb
Host smart-f2f2dc78-063d-49c7-9d23-11b20a8ba1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807617325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.807617325
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.935597961
Short name T110
Test name
Test status
Simulation time 33534020226 ps
CPU time 58.75 seconds
Started Jul 31 04:26:15 PM PDT 24
Finished Jul 31 04:27:13 PM PDT 24
Peak memory 199788 kb
Host smart-88fd96de-0ebe-40b2-acd4-e9b34fdef4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935597961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.935597961
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.304393474
Short name T804
Test name
Test status
Simulation time 3293077216 ps
CPU time 2.14 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:26:14 PM PDT 24
Peak memory 196244 kb
Host smart-3ad5bb76-b780-41ad-81d2-eb8ee3e8acfd
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304393474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.304393474
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.4259246130
Short name T236
Test name
Test status
Simulation time 113329365076 ps
CPU time 467 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:33:59 PM PDT 24
Peak memory 199616 kb
Host smart-77759527-7a96-47d4-9896-4da739a73294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4259246130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.4259246130
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.2539559205
Short name T313
Test name
Test status
Simulation time 4432740766 ps
CPU time 8.58 seconds
Started Jul 31 04:26:08 PM PDT 24
Finished Jul 31 04:26:17 PM PDT 24
Peak memory 199712 kb
Host smart-8544ecb6-364e-477f-81c1-d8b57b718b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539559205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.2539559205
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.338967069
Short name T770
Test name
Test status
Simulation time 158254142908 ps
CPU time 78.2 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:27:32 PM PDT 24
Peak memory 199940 kb
Host smart-895895c1-a0e6-4c17-b442-dfb2682f8a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338967069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.338967069
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.3966962928
Short name T278
Test name
Test status
Simulation time 23161297882 ps
CPU time 121.43 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:28:17 PM PDT 24
Peak memory 199736 kb
Host smart-4ae0968f-091e-4f41-acad-3b409452a342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3966962928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.3966962928
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.3683347345
Short name T648
Test name
Test status
Simulation time 5892615918 ps
CPU time 9.58 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:23 PM PDT 24
Peak memory 198804 kb
Host smart-72aae7de-463b-49dc-8b0c-57304d85d98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3683347345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.3683347345
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.2171320376
Short name T109
Test name
Test status
Simulation time 82062793523 ps
CPU time 76.39 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:27:30 PM PDT 24
Peak memory 199744 kb
Host smart-cd0c8a0f-6f57-4840-9613-78fc166fa3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171320376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2171320376
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.3307372070
Short name T92
Test name
Test status
Simulation time 2822923016 ps
CPU time 1.67 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 196252 kb
Host smart-2aa02065-b806-4479-b8e9-fff1039b4415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307372070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.3307372070
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.507361633
Short name T355
Test name
Test status
Simulation time 262039246 ps
CPU time 1.81 seconds
Started Jul 31 04:26:12 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 197988 kb
Host smart-2b70d92e-02a7-4d3d-a380-48b98928e8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507361633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.507361633
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2505758347
Short name T149
Test name
Test status
Simulation time 255082021300 ps
CPU time 635.94 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:36:49 PM PDT 24
Peak memory 199776 kb
Host smart-4aa2485f-9107-4922-8400-d32fe7386abe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505758347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2505758347
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.1641164241
Short name T1039
Test name
Test status
Simulation time 133559315363 ps
CPU time 508.56 seconds
Started Jul 31 04:26:16 PM PDT 24
Finished Jul 31 04:34:45 PM PDT 24
Peak memory 216248 kb
Host smart-8f0dc722-e5a9-420a-9758-9cfacf14843f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641164241 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.1641164241
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.1296098605
Short name T588
Test name
Test status
Simulation time 1936972852 ps
CPU time 2.07 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:26:16 PM PDT 24
Peak memory 198600 kb
Host smart-62c614f1-2e25-473b-8eea-19151a0c02a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296098605 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.1296098605
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.521999722
Short name T1008
Test name
Test status
Simulation time 37063232553 ps
CPU time 15.22 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:34 PM PDT 24
Peak memory 199804 kb
Host smart-59070e2a-148c-46db-b5b2-4010c6485e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521999722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.521999722
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.854816502
Short name T524
Test name
Test status
Simulation time 36297458 ps
CPU time 0.55 seconds
Started Jul 31 04:26:18 PM PDT 24
Finished Jul 31 04:26:19 PM PDT 24
Peak memory 195372 kb
Host smart-7fc0a546-f648-451f-a4fb-3c229bf43438
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854816502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.854816502
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.1794006391
Short name T723
Test name
Test status
Simulation time 89384873905 ps
CPU time 136.18 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:28:40 PM PDT 24
Peak memory 199744 kb
Host smart-ff846db6-4118-410f-a7e8-a27ca62fbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794006391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1794006391
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.415538502
Short name T771
Test name
Test status
Simulation time 9984115664 ps
CPU time 15.36 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 198084 kb
Host smart-8546a6eb-aa1d-4976-a7c8-4825942ce062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415538502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.415538502
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.715080369
Short name T1021
Test name
Test status
Simulation time 13312748167 ps
CPU time 23.22 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:26:55 PM PDT 24
Peak memory 199676 kb
Host smart-207e5b0e-6996-4b32-b69b-1351150303d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715080369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.715080369
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4189339044
Short name T682
Test name
Test status
Simulation time 8703604174 ps
CPU time 11.65 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:33 PM PDT 24
Peak memory 195620 kb
Host smart-607694b7-a434-4520-824c-da0f5e6c42be
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189339044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4189339044
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.463865501
Short name T634
Test name
Test status
Simulation time 107777796965 ps
CPU time 283.8 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:31:26 PM PDT 24
Peak memory 199788 kb
Host smart-b6d1332f-5b14-4958-a390-cf3250f0c5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=463865501 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.463865501
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.1123382743
Short name T1142
Test name
Test status
Simulation time 558233524 ps
CPU time 0.84 seconds
Started Jul 31 04:26:23 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 196000 kb
Host smart-48e12c90-d20d-4e7d-bd77-a3a2300ea865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123382743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.1123382743
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.2225801307
Short name T1014
Test name
Test status
Simulation time 177751314874 ps
CPU time 38.9 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 207564 kb
Host smart-2f1a4144-e332-418f-8146-7f059ab32c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225801307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.2225801307
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1082016663
Short name T655
Test name
Test status
Simulation time 12358839352 ps
CPU time 471.29 seconds
Started Jul 31 04:26:23 PM PDT 24
Finished Jul 31 04:34:14 PM PDT 24
Peak memory 199836 kb
Host smart-4d1f1440-b61e-4024-a4e1-29489f93ca35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082016663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1082016663
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.2402947026
Short name T1072
Test name
Test status
Simulation time 2737484887 ps
CPU time 10.68 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:26:40 PM PDT 24
Peak memory 198688 kb
Host smart-c4d806f6-c9c4-4577-bdeb-14c12cb1bb9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2402947026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.2402947026
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2695208652
Short name T860
Test name
Test status
Simulation time 146330742032 ps
CPU time 76.26 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:27:48 PM PDT 24
Peak memory 199736 kb
Host smart-ac9cb518-9bc8-41ba-81f5-40393fbf4107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695208652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2695208652
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.3016759479
Short name T937
Test name
Test status
Simulation time 41175835490 ps
CPU time 46.47 seconds
Started Jul 31 04:26:13 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 195532 kb
Host smart-dc569ac5-4835-4927-bf0c-ed921c681e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016759479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.3016759479
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2638517679
Short name T258
Test name
Test status
Simulation time 5530448546 ps
CPU time 24.68 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:46 PM PDT 24
Peak memory 199512 kb
Host smart-06074643-7e2f-4434-9f96-2d98360672b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638517679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2638517679
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.302845910
Short name T933
Test name
Test status
Simulation time 82352041546 ps
CPU time 1129.94 seconds
Started Jul 31 04:26:17 PM PDT 24
Finished Jul 31 04:45:07 PM PDT 24
Peak memory 199744 kb
Host smart-12868008-6942-4f8e-a720-721b22e3c634
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302845910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.302845910
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2984939564
Short name T602
Test name
Test status
Simulation time 66203932706 ps
CPU time 1758.82 seconds
Started Jul 31 04:26:39 PM PDT 24
Finished Jul 31 04:55:58 PM PDT 24
Peak memory 224612 kb
Host smart-afa8637f-ac05-4779-8606-29ef345784da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984939564 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2984939564
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.833618194
Short name T537
Test name
Test status
Simulation time 639740896 ps
CPU time 1.82 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:23 PM PDT 24
Peak memory 199072 kb
Host smart-7623724b-24d4-4e45-bbdc-db07819a8758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833618194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.833618194
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1257707752
Short name T582
Test name
Test status
Simulation time 35946385840 ps
CPU time 16.67 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 199772 kb
Host smart-159bdb94-cfde-462d-a33e-d9923722f891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257707752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1257707752
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1796680972
Short name T480
Test name
Test status
Simulation time 23875431 ps
CPU time 0.57 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:26:28 PM PDT 24
Peak memory 195152 kb
Host smart-dc80a445-de35-4d03-881b-6fadaca26a6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796680972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1796680972
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3301347692
Short name T878
Test name
Test status
Simulation time 88921956724 ps
CPU time 45.3 seconds
Started Jul 31 04:26:20 PM PDT 24
Finished Jul 31 04:27:06 PM PDT 24
Peak memory 199744 kb
Host smart-a2ced68d-b90a-4e66-b664-fb7d09ec9778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301347692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3301347692
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.2014680186
Short name T664
Test name
Test status
Simulation time 33327231368 ps
CPU time 53.24 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:27:18 PM PDT 24
Peak memory 199676 kb
Host smart-d44d598e-f23e-4f59-af8f-1ceabce64c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014680186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.2014680186
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.2383068369
Short name T701
Test name
Test status
Simulation time 71219694812 ps
CPU time 28.21 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:26:56 PM PDT 24
Peak memory 199800 kb
Host smart-58fbb75c-5d88-42ad-b5e9-82a3be75229c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383068369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.2383068369
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.2483569709
Short name T899
Test name
Test status
Simulation time 13868801206 ps
CPU time 26.38 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:51 PM PDT 24
Peak memory 199608 kb
Host smart-6d1a7eb2-a67f-4e69-8a46-7959242f2844
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483569709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2483569709
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2586573288
Short name T490
Test name
Test status
Simulation time 86004483282 ps
CPU time 63.45 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:27:30 PM PDT 24
Peak memory 199744 kb
Host smart-2d0f01e8-2eb1-4c4e-8ba4-39d2eecb31e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2586573288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2586573288
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2389150644
Short name T652
Test name
Test status
Simulation time 3389412998 ps
CPU time 2.46 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:26:32 PM PDT 24
Peak memory 198256 kb
Host smart-249ee2ef-384a-4632-8f92-51d4dbadefcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389150644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2389150644
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.3341840950
Short name T586
Test name
Test status
Simulation time 35634308259 ps
CPU time 58.59 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:27:26 PM PDT 24
Peak memory 199900 kb
Host smart-91eb657c-36c2-46f6-821b-da1a33508942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341840950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.3341840950
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.261999828
Short name T260
Test name
Test status
Simulation time 22579036483 ps
CPU time 236.44 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:30:22 PM PDT 24
Peak memory 199812 kb
Host smart-0676579f-3040-46a9-a583-6b7d8e1b3429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261999828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.261999828
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2811191667
Short name T90
Test name
Test status
Simulation time 5472701046 ps
CPU time 23.81 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:48 PM PDT 24
Peak memory 197700 kb
Host smart-325667b8-d46a-438d-b760-ba55a1aebe92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2811191667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2811191667
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3711048386
Short name T984
Test name
Test status
Simulation time 44285380896 ps
CPU time 64.01 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:27:35 PM PDT 24
Peak memory 199684 kb
Host smart-30b413a9-dd94-4ff4-a8b4-51649d5ea79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711048386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3711048386
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.827500576
Short name T806
Test name
Test status
Simulation time 3820297710 ps
CPU time 3.36 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:26:35 PM PDT 24
Peak memory 196340 kb
Host smart-937f4c3d-5cf1-4588-a5cf-42e23aa9bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827500576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.827500576
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.275510823
Short name T531
Test name
Test status
Simulation time 492517250 ps
CPU time 1.64 seconds
Started Jul 31 04:26:23 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 198148 kb
Host smart-bb44681c-57a0-439f-8341-fc7c05613629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275510823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.275510823
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.1487300387
Short name T953
Test name
Test status
Simulation time 78477759132 ps
CPU time 602.02 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:36:29 PM PDT 24
Peak memory 199776 kb
Host smart-5a8c576d-1779-41c5-9acc-043821ffc853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487300387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.1487300387
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.596603272
Short name T774
Test name
Test status
Simulation time 39465765629 ps
CPU time 173.2 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:29:14 PM PDT 24
Peak memory 211444 kb
Host smart-fd4b2c16-d6cd-463b-b4ab-3325180cd709
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596603272 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.596603272
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.4247420627
Short name T513
Test name
Test status
Simulation time 6922821426 ps
CPU time 19.91 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:41 PM PDT 24
Peak memory 199720 kb
Host smart-75667d8c-fc07-49f0-8ccd-df078097ac4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247420627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.4247420627
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1982694629
Short name T809
Test name
Test status
Simulation time 9053282016 ps
CPU time 14.09 seconds
Started Jul 31 04:26:25 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199816 kb
Host smart-869aca98-d827-4333-ab81-d6469b94a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982694629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1982694629
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.2772032657
Short name T417
Test name
Test status
Simulation time 30037936 ps
CPU time 0.54 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:26:34 PM PDT 24
Peak memory 195088 kb
Host smart-90cf1e75-deab-4ae5-999c-487285bb67e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772032657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.2772032657
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.1829012586
Short name T1079
Test name
Test status
Simulation time 51938597609 ps
CPU time 43.27 seconds
Started Jul 31 04:26:25 PM PDT 24
Finished Jul 31 04:27:08 PM PDT 24
Peak memory 199828 kb
Host smart-7ee9595c-8823-406a-8942-bc41b15b39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829012586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.1829012586
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1703963300
Short name T608
Test name
Test status
Simulation time 128567758630 ps
CPU time 234.15 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:30:22 PM PDT 24
Peak memory 199756 kb
Host smart-e4dee952-5d45-4e03-b22e-fec6693f9420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703963300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1703963300
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_intr.409635242
Short name T584
Test name
Test status
Simulation time 30584063751 ps
CPU time 11.58 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:26:44 PM PDT 24
Peak memory 199760 kb
Host smart-b02adfd5-4e3c-47a9-959b-e072a8a67c96
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409635242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.409635242
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.797432878
Short name T1070
Test name
Test status
Simulation time 57073797484 ps
CPU time 98.97 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:28:03 PM PDT 24
Peak memory 199804 kb
Host smart-e11b4cfe-212d-4496-afea-74f5c6d4072a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=797432878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.797432878
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.2464466528
Short name T587
Test name
Test status
Simulation time 5808907699 ps
CPU time 10.39 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:26:38 PM PDT 24
Peak memory 199444 kb
Host smart-60cce667-627a-4722-8aae-7db5cd80b7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464466528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.2464466528
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.872969859
Short name T538
Test name
Test status
Simulation time 91486818305 ps
CPU time 198.38 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:29:48 PM PDT 24
Peak memory 199924 kb
Host smart-68d1c02a-03fb-43eb-9c86-988dce867f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872969859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.872969859
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.4084954818
Short name T366
Test name
Test status
Simulation time 3720559359 ps
CPU time 196.34 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:29:51 PM PDT 24
Peak memory 199680 kb
Host smart-b9a1cd19-0baf-44e4-8c7c-2af9d5e6cad2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084954818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.4084954818
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3737472338
Short name T326
Test name
Test status
Simulation time 6848489899 ps
CPU time 64.07 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:27:33 PM PDT 24
Peak memory 197932 kb
Host smart-856e50db-8365-4e11-a768-25192773e4e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3737472338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3737472338
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.2268949329
Short name T426
Test name
Test status
Simulation time 31688909999 ps
CPU time 15.83 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:26:49 PM PDT 24
Peak memory 199640 kb
Host smart-90544108-50cf-46c2-8e39-c46f7bc66357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268949329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2268949329
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.2650323305
Short name T365
Test name
Test status
Simulation time 4232409283 ps
CPU time 6.63 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:26:38 PM PDT 24
Peak memory 195996 kb
Host smart-b4f61960-6c00-4706-a87e-c97e568c3caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650323305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.2650323305
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.1502352042
Short name T89
Test name
Test status
Simulation time 5587621427 ps
CPU time 4.55 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:26:36 PM PDT 24
Peak memory 199540 kb
Host smart-653eaf40-3fbf-409a-b3a4-283bc707e9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502352042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1502352042
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.3468785340
Short name T569
Test name
Test status
Simulation time 819487609839 ps
CPU time 155.63 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:29:07 PM PDT 24
Peak memory 199724 kb
Host smart-85875ea3-36cb-48f4-bacf-7eb47eea2646
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468785340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.3468785340
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3883529920
Short name T1047
Test name
Test status
Simulation time 146958933334 ps
CPU time 609.28 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:36:30 PM PDT 24
Peak memory 210656 kb
Host smart-1f4ef624-53dd-4233-8c68-24fb3857cbdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883529920 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3883529920
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1604435787
Short name T581
Test name
Test status
Simulation time 6407005563 ps
CPU time 16.4 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:26:40 PM PDT 24
Peak memory 199684 kb
Host smart-2d409294-e9d3-41d2-889e-670c6fa53805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604435787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1604435787
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.479516835
Short name T783
Test name
Test status
Simulation time 4721046278 ps
CPU time 8.04 seconds
Started Jul 31 04:26:39 PM PDT 24
Finished Jul 31 04:26:47 PM PDT 24
Peak memory 199656 kb
Host smart-6f1c3608-c5e7-47c2-b9c4-5cc593ff6ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479516835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.479516835
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.638047909
Short name T346
Test name
Test status
Simulation time 16543649 ps
CPU time 0.54 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:26:33 PM PDT 24
Peak memory 195168 kb
Host smart-9388c119-7a17-4e24-921f-4627fee09dc4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638047909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.638047909
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.234274566
Short name T786
Test name
Test status
Simulation time 116249426739 ps
CPU time 90.44 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:27:57 PM PDT 24
Peak memory 199864 kb
Host smart-593c9e4b-7c6c-4890-b299-76724f5f5591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234274566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.234274566
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1603395853
Short name T1084
Test name
Test status
Simulation time 40750791573 ps
CPU time 30.72 seconds
Started Jul 31 04:26:46 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 199548 kb
Host smart-9508c487-5e52-4c1e-b94c-fef5ee319999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603395853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1603395853
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.619760767
Short name T816
Test name
Test status
Simulation time 185677246298 ps
CPU time 101.69 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:28:13 PM PDT 24
Peak memory 199688 kb
Host smart-34e86d2d-ed7c-4464-9c03-fb7affd3b57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619760767 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.619760767
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.313264894
Short name T624
Test name
Test status
Simulation time 195525776312 ps
CPU time 67.52 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:51 PM PDT 24
Peak memory 199372 kb
Host smart-43e6e895-8f1c-4cc3-8665-afac7bc279da
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313264894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.313264894
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3258974580
Short name T391
Test name
Test status
Simulation time 327984109381 ps
CPU time 465 seconds
Started Jul 31 04:26:24 PM PDT 24
Finished Jul 31 04:34:09 PM PDT 24
Peak memory 199652 kb
Host smart-2a031c06-656a-40ba-933a-19a2d016c30f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3258974580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3258974580
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1255989881
Short name T647
Test name
Test status
Simulation time 7023321413 ps
CPU time 11.97 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 197592 kb
Host smart-8913fcce-46d0-4377-9466-26577970ed54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255989881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1255989881
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.4082511986
Short name T528
Test name
Test status
Simulation time 74600663968 ps
CPU time 191.51 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:29:40 PM PDT 24
Peak memory 199864 kb
Host smart-7047e5c5-aad3-4106-99ce-4dcd978a1e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082511986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.4082511986
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.3036391894
Short name T310
Test name
Test status
Simulation time 22663788487 ps
CPU time 331.4 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:31:59 PM PDT 24
Peak memory 199692 kb
Host smart-97fb3615-3c0f-4359-b1b8-ce5a6cfba9e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3036391894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.3036391894
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.2372017171
Short name T32
Test name
Test status
Simulation time 5973373204 ps
CPU time 13.51 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:26:45 PM PDT 24
Peak memory 198464 kb
Host smart-d2c35262-8606-42ef-8213-82b6aee3f75d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2372017171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2372017171
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.71376385
Short name T642
Test name
Test status
Simulation time 33134284814 ps
CPU time 26.65 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:26:55 PM PDT 24
Peak memory 199796 kb
Host smart-9dfe30b0-dd4e-445c-baba-cb021271d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71376385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.71376385
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1819061222
Short name T1164
Test name
Test status
Simulation time 2969827751 ps
CPU time 5.28 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:26:27 PM PDT 24
Peak memory 196304 kb
Host smart-98aa8802-b78e-427f-9c39-564ab21d36c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819061222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1819061222
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.3628942287
Short name T725
Test name
Test status
Simulation time 5690535415 ps
CPU time 19.83 seconds
Started Jul 31 04:26:21 PM PDT 24
Finished Jul 31 04:26:40 PM PDT 24
Peak memory 199492 kb
Host smart-4de89e6b-d8b5-4106-a0b9-2749e0e983f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628942287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.3628942287
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3111824097
Short name T696
Test name
Test status
Simulation time 295553493734 ps
CPU time 84.7 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:28:07 PM PDT 24
Peak memory 208000 kb
Host smart-3dfb62b7-a3ec-498c-94d2-54b4cf89f94d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111824097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3111824097
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1884385362
Short name T766
Test name
Test status
Simulation time 70172197749 ps
CPU time 691.56 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:38:18 PM PDT 24
Peak memory 216292 kb
Host smart-1b8dc390-b673-4b96-9095-f1dc1bfd4a53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884385362 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1884385362
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2596575521
Short name T596
Test name
Test status
Simulation time 7660614265 ps
CPU time 13.55 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 199256 kb
Host smart-5c3d2920-1666-4419-8ef0-a47ddb764178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596575521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2596575521
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.3492337766
Short name T719
Test name
Test status
Simulation time 46748404535 ps
CPU time 79.21 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:27:46 PM PDT 24
Peak memory 199792 kb
Host smart-42d46c2f-2d20-4591-b541-39ebeb150f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492337766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.3492337766
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.4079082830
Short name T17
Test name
Test status
Simulation time 88541079 ps
CPU time 0.58 seconds
Started Jul 31 04:22:07 PM PDT 24
Finished Jul 31 04:22:07 PM PDT 24
Peak memory 195152 kb
Host smart-83f6e513-6f7f-4c7e-877c-6712975b1796
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079082830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.4079082830
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3914744566
Short name T712
Test name
Test status
Simulation time 44158449662 ps
CPU time 70.26 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 198380 kb
Host smart-2032397f-0278-458e-b778-cd4513e8d68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914744566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3914744566
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.3149359902
Short name T790
Test name
Test status
Simulation time 20735986747 ps
CPU time 33.79 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:13 PM PDT 24
Peak memory 199656 kb
Host smart-7a2f0309-96e1-4525-9302-3a217ecdb91a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149359902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.3149359902
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.4121944483
Short name T111
Test name
Test status
Simulation time 63324596391 ps
CPU time 33.57 seconds
Started Jul 31 04:23:48 PM PDT 24
Finished Jul 31 04:24:21 PM PDT 24
Peak memory 199664 kb
Host smart-2ca8f029-91dd-4689-bda7-ff19a78038c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121944483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.4121944483
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.1234486232
Short name T97
Test name
Test status
Simulation time 55838083063 ps
CPU time 23.31 seconds
Started Jul 31 04:25:36 PM PDT 24
Finished Jul 31 04:26:00 PM PDT 24
Peak memory 197956 kb
Host smart-41862654-7a36-41e1-bfa2-785bbb342e04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234486232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.1234486232
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.2262868783
Short name T724
Test name
Test status
Simulation time 222688285359 ps
CPU time 272.32 seconds
Started Jul 31 04:22:07 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 199704 kb
Host smart-7b3ffb4b-99fc-4e0d-899c-493f294dff78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262868783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2262868783
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3342441586
Short name T1100
Test name
Test status
Simulation time 9829068049 ps
CPU time 7.24 seconds
Started Jul 31 04:22:07 PM PDT 24
Finished Jul 31 04:22:15 PM PDT 24
Peak memory 198580 kb
Host smart-b6881132-6bca-41c1-ae3f-e77e13964cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342441586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3342441586
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.3827643025
Short name T481
Test name
Test status
Simulation time 129539222310 ps
CPU time 61.02 seconds
Started Jul 31 04:25:38 PM PDT 24
Finished Jul 31 04:26:39 PM PDT 24
Peak memory 207936 kb
Host smart-3b6acbd4-6182-4840-8ad7-6578fb46becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827643025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3827643025
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.330268595
Short name T469
Test name
Test status
Simulation time 11857314097 ps
CPU time 341.95 seconds
Started Jul 31 04:24:40 PM PDT 24
Finished Jul 31 04:30:23 PM PDT 24
Peak memory 198320 kb
Host smart-1f5dab8f-7c38-4266-b384-3bfcabd59f48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=330268595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.330268595
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1452104092
Short name T507
Test name
Test status
Simulation time 7097203462 ps
CPU time 59.24 seconds
Started Jul 31 04:25:07 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 198608 kb
Host smart-1fef9766-2ff5-46d2-81fd-81da6c175a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1452104092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1452104092
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1995935924
Short name T437
Test name
Test status
Simulation time 16431038415 ps
CPU time 34.48 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:43 PM PDT 24
Peak memory 199860 kb
Host smart-1d206d71-0db3-44ae-bc59-8c0da174808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995935924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1995935924
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.3775192316
Short name T1095
Test name
Test status
Simulation time 5219450153 ps
CPU time 2.65 seconds
Started Jul 31 04:22:51 PM PDT 24
Finished Jul 31 04:22:54 PM PDT 24
Peak memory 196276 kb
Host smart-6104b157-d9d8-424c-a695-81252b30cabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775192316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.3775192316
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.3293691717
Short name T1156
Test name
Test status
Simulation time 6029625318 ps
CPU time 10.81 seconds
Started Jul 31 04:24:58 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 199384 kb
Host smart-a4953d47-ffdb-4781-861b-dd2fb3d7af3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293691717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.3293691717
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.3676826044
Short name T529
Test name
Test status
Simulation time 300058851197 ps
CPU time 1054.84 seconds
Started Jul 31 04:22:12 PM PDT 24
Finished Jul 31 04:39:47 PM PDT 24
Peak memory 199696 kb
Host smart-9539b531-b78b-409d-a5cc-147e5b74b8b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676826044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3676826044
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4111000843
Short name T923
Test name
Test status
Simulation time 148040967421 ps
CPU time 564.43 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:35:04 PM PDT 24
Peak memory 224384 kb
Host smart-817964e1-39a0-49c7-b6ca-bc554c613d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111000843 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4111000843
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.981164803
Short name T693
Test name
Test status
Simulation time 518176725 ps
CPU time 2.1 seconds
Started Jul 31 04:25:10 PM PDT 24
Finished Jul 31 04:25:13 PM PDT 24
Peak memory 197836 kb
Host smart-c27a3131-ae44-4a8b-9caa-05d9a710c4c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981164803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.981164803
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.220684514
Short name T580
Test name
Test status
Simulation time 34126366049 ps
CPU time 12.69 seconds
Started Jul 31 04:22:00 PM PDT 24
Finished Jul 31 04:22:13 PM PDT 24
Peak memory 199512 kb
Host smart-2d51e31d-e1f0-4baa-86b0-bb65cd96ff45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220684514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.220684514
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.3678185448
Short name T543
Test name
Test status
Simulation time 18268851745 ps
CPU time 18.08 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:26:50 PM PDT 24
Peak memory 199760 kb
Host smart-d4bea831-a29c-4075-9897-c85c6fb46e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678185448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.3678185448
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.3693858094
Short name T183
Test name
Test status
Simulation time 108490254189 ps
CPU time 596.15 seconds
Started Jul 31 04:26:23 PM PDT 24
Finished Jul 31 04:36:19 PM PDT 24
Peak memory 224588 kb
Host smart-2c6d99e9-c879-4ba3-83ab-9c81e0d96ddd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693858094 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.3693858094
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.978239069
Short name T975
Test name
Test status
Simulation time 13657022787 ps
CPU time 179.88 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:29:45 PM PDT 24
Peak memory 209304 kb
Host smart-90d32147-a673-4e55-971f-2f91f02b98fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978239069 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.978239069
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2928185617
Short name T145
Test name
Test status
Simulation time 89977984143 ps
CPU time 122.01 seconds
Started Jul 31 04:26:46 PM PDT 24
Finished Jul 31 04:28:48 PM PDT 24
Peak memory 212780 kb
Host smart-6a288db7-fbae-4984-830f-52cbf203d8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928185617 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2928185617
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1588191631
Short name T672
Test name
Test status
Simulation time 14194249577 ps
CPU time 27.11 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:26:56 PM PDT 24
Peak memory 199740 kb
Host smart-9f29dfea-1e04-4c80-a72d-1587eb1e6a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588191631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1588191631
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3803249732
Short name T555
Test name
Test status
Simulation time 85755312001 ps
CPU time 451.72 seconds
Started Jul 31 04:26:22 PM PDT 24
Finished Jul 31 04:33:54 PM PDT 24
Peak memory 225364 kb
Host smart-1ef6bb9d-c0d6-4501-beee-feb3fd140122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803249732 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3803249732
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.1895313216
Short name T607
Test name
Test status
Simulation time 258957429679 ps
CPU time 36.06 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:27:05 PM PDT 24
Peak memory 199824 kb
Host smart-aad1f05a-6998-4dc4-b769-2725b791acb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895313216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.1895313216
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1010629405
Short name T204
Test name
Test status
Simulation time 38999167886 ps
CPU time 384.74 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:32:54 PM PDT 24
Peak memory 216324 kb
Host smart-c857c874-1446-4f0c-b0a7-6c4b00e9d328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010629405 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1010629405
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2568436434
Short name T695
Test name
Test status
Simulation time 148256329120 ps
CPU time 77.92 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:27:44 PM PDT 24
Peak memory 199728 kb
Host smart-306a3d3b-e5fa-46a6-930d-db0018a7917f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568436434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2568436434
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.2617433719
Short name T570
Test name
Test status
Simulation time 44645056066 ps
CPU time 41.47 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:25 PM PDT 24
Peak memory 199708 kb
Host smart-4fa83f83-565e-4250-981c-bd475e70005f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617433719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.2617433719
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.765758567
Short name T741
Test name
Test status
Simulation time 149523438924 ps
CPU time 445.11 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:34:12 PM PDT 24
Peak memory 216196 kb
Host smart-22033079-e5b3-4500-af86-10f7acaa6ad1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765758567 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.765758567
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.3838729821
Short name T847
Test name
Test status
Simulation time 28858578020 ps
CPU time 40.78 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199804 kb
Host smart-41165c94-c114-4493-942b-76c796f57e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838729821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.3838729821
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1559353041
Short name T776
Test name
Test status
Simulation time 6997024999 ps
CPU time 67.96 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:27:38 PM PDT 24
Peak memory 216208 kb
Host smart-5b03470a-6466-4b74-80ff-901749463c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559353041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1559353041
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.1684879343
Short name T1146
Test name
Test status
Simulation time 53064713912 ps
CPU time 34.92 seconds
Started Jul 31 04:26:25 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 199680 kb
Host smart-c11fdcdb-0d40-4774-84ac-140215e349f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684879343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.1684879343
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2325019517
Short name T316
Test name
Test status
Simulation time 208399620553 ps
CPU time 1030.85 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:43:39 PM PDT 24
Peak memory 224636 kb
Host smart-21badf37-26c8-48eb-847a-7f557f58e2a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325019517 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2325019517
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.74308120
Short name T589
Test name
Test status
Simulation time 101090070551 ps
CPU time 210.55 seconds
Started Jul 31 04:26:37 PM PDT 24
Finished Jul 31 04:30:08 PM PDT 24
Peak memory 199708 kb
Host smart-0176d11f-a7d4-4eee-9ce2-e81302056436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74308120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.74308120
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1866100981
Short name T438
Test name
Test status
Simulation time 231245277510 ps
CPU time 604.73 seconds
Started Jul 31 04:26:25 PM PDT 24
Finished Jul 31 04:36:30 PM PDT 24
Peak memory 224580 kb
Host smart-f45a52e2-0910-4ca9-8200-1e2ad4d1f7ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866100981 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1866100981
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.2052297875
Short name T462
Test name
Test status
Simulation time 67238923 ps
CPU time 0.53 seconds
Started Jul 31 04:23:26 PM PDT 24
Finished Jul 31 04:23:27 PM PDT 24
Peak memory 192316 kb
Host smart-12ba7108-91d5-4ce0-bc73-19417b36f31e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052297875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.2052297875
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.3128927260
Short name T358
Test name
Test status
Simulation time 21058273576 ps
CPU time 35.32 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:24:16 PM PDT 24
Peak memory 199648 kb
Host smart-52422031-ac61-4477-83ba-60485dbd8aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128927260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.3128927260
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.503199110
Short name T898
Test name
Test status
Simulation time 10287931050 ps
CPU time 16.3 seconds
Started Jul 31 04:23:32 PM PDT 24
Finished Jul 31 04:23:49 PM PDT 24
Peak memory 199544 kb
Host smart-7eb71364-36ab-44f3-a5a4-d85455325162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503199110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.503199110
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.1938457860
Short name T216
Test name
Test status
Simulation time 22273504728 ps
CPU time 47.5 seconds
Started Jul 31 04:23:40 PM PDT 24
Finished Jul 31 04:24:28 PM PDT 24
Peak memory 199640 kb
Host smart-8d58221b-0568-4ce8-afa0-bd3ff5d8741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938457860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.1938457860
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.1228735166
Short name T837
Test name
Test status
Simulation time 23336083762 ps
CPU time 8.61 seconds
Started Jul 31 04:24:56 PM PDT 24
Finished Jul 31 04:25:05 PM PDT 24
Peak memory 196864 kb
Host smart-86c5a267-18a4-4fa4-ad88-65ed2e6ab169
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228735166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.1228735166
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.1306861274
Short name T249
Test name
Test status
Simulation time 102979953907 ps
CPU time 195.07 seconds
Started Jul 31 04:23:25 PM PDT 24
Finished Jul 31 04:26:41 PM PDT 24
Peak memory 197868 kb
Host smart-4f26d9c5-57de-43ea-9095-18d6dfdf833a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1306861274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.1306861274
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.3054316637
Short name T349
Test name
Test status
Simulation time 4262662529 ps
CPU time 7.76 seconds
Started Jul 31 04:23:36 PM PDT 24
Finished Jul 31 04:23:44 PM PDT 24
Peak memory 197884 kb
Host smart-75cb7adb-bc09-4283-815b-c6f53ccab6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054316637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.3054316637
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3556663819
Short name T392
Test name
Test status
Simulation time 65513366525 ps
CPU time 103.42 seconds
Started Jul 31 04:23:25 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 196416 kb
Host smart-698d8894-660e-4f7e-b56f-f7432fec858b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556663819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3556663819
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.501618112
Short name T468
Test name
Test status
Simulation time 9291395749 ps
CPU time 256.17 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:27:58 PM PDT 24
Peak memory 199716 kb
Host smart-617d1f27-4dc8-49f7-b488-27b8d97f5c35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=501618112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.501618112
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.398796830
Short name T1138
Test name
Test status
Simulation time 6733464541 ps
CPU time 18.53 seconds
Started Jul 31 04:25:18 PM PDT 24
Finished Jul 31 04:25:37 PM PDT 24
Peak memory 197844 kb
Host smart-ffebfe42-d868-4b84-9574-52b341f8de0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398796830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.398796830
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.2452069007
Short name T116
Test name
Test status
Simulation time 14857643035 ps
CPU time 22.53 seconds
Started Jul 31 04:25:08 PM PDT 24
Finished Jul 31 04:25:31 PM PDT 24
Peak memory 198672 kb
Host smart-a2482256-fe45-4191-abff-6629259153d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452069007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2452069007
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.2308988482
Short name T505
Test name
Test status
Simulation time 33816765480 ps
CPU time 50.46 seconds
Started Jul 31 04:23:41 PM PDT 24
Finished Jul 31 04:24:32 PM PDT 24
Peak memory 195580 kb
Host smart-6b4bac2a-0f31-4090-85e0-24fd84fe2c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308988482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.2308988482
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.4011165967
Short name T294
Test name
Test status
Simulation time 103141974 ps
CPU time 1.01 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:25:41 PM PDT 24
Peak memory 198192 kb
Host smart-b66298c4-e5df-4736-8dbe-91ac67ea35f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011165967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.4011165967
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.2953782254
Short name T123
Test name
Test status
Simulation time 384043571661 ps
CPU time 290.58 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:28:32 PM PDT 24
Peak memory 208040 kb
Host smart-e02524aa-ba84-4847-8912-1c84deb51c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953782254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.2953782254
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.621573390
Short name T952
Test name
Test status
Simulation time 1587842493 ps
CPU time 2.08 seconds
Started Jul 31 04:22:15 PM PDT 24
Finished Jul 31 04:22:17 PM PDT 24
Peak memory 198744 kb
Host smart-ea82eee6-fa72-4f2b-b620-18f61970a74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621573390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.621573390
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.3766127500
Short name T1078
Test name
Test status
Simulation time 36874097862 ps
CPU time 14.36 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:25:09 PM PDT 24
Peak memory 198208 kb
Host smart-4928a3a5-6a2c-41cf-b005-8c2166d155a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766127500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.3766127500
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.686868855
Short name T1112
Test name
Test status
Simulation time 79654326964 ps
CPU time 35.89 seconds
Started Jul 31 04:26:27 PM PDT 24
Finished Jul 31 04:27:03 PM PDT 24
Peak memory 199740 kb
Host smart-86433aef-48c9-49e3-a0e8-08970ebdee2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686868855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.686868855
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.67421012
Short name T1050
Test name
Test status
Simulation time 171524013933 ps
CPU time 995.07 seconds
Started Jul 31 04:26:44 PM PDT 24
Finished Jul 31 04:43:20 PM PDT 24
Peak memory 230468 kb
Host smart-59b5f340-0761-4058-a8dd-446bdc8cb122
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67421012 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.67421012
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.4272589963
Short name T187
Test name
Test status
Simulation time 12832382656 ps
CPU time 29.16 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:27:03 PM PDT 24
Peak memory 199768 kb
Host smart-a6121c3c-1a73-400e-a73a-b190838c7a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272589963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.4272589963
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2544554099
Short name T1044
Test name
Test status
Simulation time 34351070425 ps
CPU time 211.73 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:30:05 PM PDT 24
Peak memory 211704 kb
Host smart-0e9d4d80-b753-4d9a-943e-ae854b38a013
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544554099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2544554099
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.1252036967
Short name T495
Test name
Test status
Simulation time 8761474786 ps
CPU time 13.84 seconds
Started Jul 31 04:26:29 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 198472 kb
Host smart-e1d17933-93a6-41a9-9746-ae20d294aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252036967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.1252036967
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1512966308
Short name T1089
Test name
Test status
Simulation time 74647147264 ps
CPU time 156.5 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:29:08 PM PDT 24
Peak memory 215360 kb
Host smart-5f9aad90-4302-4b42-9fb1-306617294257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512966308 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1512966308
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.1183736800
Short name T1048
Test name
Test status
Simulation time 70865159551 ps
CPU time 89.81 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:28:03 PM PDT 24
Peak memory 199740 kb
Host smart-e61d4f75-abb3-40cf-a3d9-8d8b6c5db23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183736800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.1183736800
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.2179935665
Short name T1033
Test name
Test status
Simulation time 50882469609 ps
CPU time 602.22 seconds
Started Jul 31 04:26:35 PM PDT 24
Finished Jul 31 04:36:38 PM PDT 24
Peak memory 216268 kb
Host smart-bac48ca2-b248-47ee-8ae8-9950f627dec5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179935665 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.2179935665
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.3143194900
Short name T1155
Test name
Test status
Simulation time 9198930332 ps
CPU time 5.13 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:26:37 PM PDT 24
Peak memory 199796 kb
Host smart-19d4b330-ecba-4353-93a0-1142516e3e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143194900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.3143194900
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.1641451926
Short name T780
Test name
Test status
Simulation time 121665413982 ps
CPU time 333.64 seconds
Started Jul 31 04:26:39 PM PDT 24
Finished Jul 31 04:32:12 PM PDT 24
Peak memory 216524 kb
Host smart-cbd12542-76ca-4cca-9eb7-71296905d0b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641451926 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.1641451926
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.3364286694
Short name T159
Test name
Test status
Simulation time 10276458435 ps
CPU time 14.63 seconds
Started Jul 31 04:26:28 PM PDT 24
Finished Jul 31 04:26:43 PM PDT 24
Peak memory 199716 kb
Host smart-ce9915b6-244d-4515-bf2e-995c80d854e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364286694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.3364286694
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.2468033123
Short name T759
Test name
Test status
Simulation time 58646175564 ps
CPU time 796.93 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:39:50 PM PDT 24
Peak memory 216408 kb
Host smart-44c09af1-efee-4a11-8baa-078f5d89069e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468033123 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.2468033123
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.400895036
Short name T1031
Test name
Test status
Simulation time 70570265293 ps
CPU time 143.54 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:28:55 PM PDT 24
Peak memory 199688 kb
Host smart-50f41789-31b6-4bcc-ad98-24225ad9f963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400895036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.400895036
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.2213706878
Short name T25
Test name
Test status
Simulation time 24274054401 ps
CPU time 277.42 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:31:08 PM PDT 24
Peak memory 215584 kb
Host smart-b4842af0-3b62-4460-aeaf-a212fc6f81b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213706878 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.2213706878
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3110864531
Short name T130
Test name
Test status
Simulation time 23203421948 ps
CPU time 22.02 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:26:55 PM PDT 24
Peak memory 199740 kb
Host smart-d3112384-5147-4101-b53b-c006f4b46e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110864531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3110864531
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1094171854
Short name T768
Test name
Test status
Simulation time 25010579642 ps
CPU time 285.62 seconds
Started Jul 31 04:26:26 PM PDT 24
Finished Jul 31 04:31:11 PM PDT 24
Peak memory 215360 kb
Host smart-8a6b13ac-ecb5-4690-a275-15f5d1d93411
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094171854 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1094171854
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.1114350410
Short name T1135
Test name
Test status
Simulation time 22463211461 ps
CPU time 17.68 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:26:48 PM PDT 24
Peak memory 199780 kb
Host smart-fb11e4f9-fba7-44d5-9945-60591b86ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114350410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.1114350410
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.904199036
Short name T880
Test name
Test status
Simulation time 78979120365 ps
CPU time 15.23 seconds
Started Jul 31 04:26:38 PM PDT 24
Finished Jul 31 04:26:53 PM PDT 24
Peak memory 199692 kb
Host smart-5a44a0ea-5514-47d4-ac59-0a6529ba0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904199036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.904199036
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.2319268935
Short name T98
Test name
Test status
Simulation time 192381293779 ps
CPU time 605.55 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:36:36 PM PDT 24
Peak memory 228724 kb
Host smart-6263ec41-8310-4725-a915-8ac865791177
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319268935 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.2319268935
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2324332923
Short name T565
Test name
Test status
Simulation time 12319207 ps
CPU time 0.57 seconds
Started Jul 31 04:22:37 PM PDT 24
Finished Jul 31 04:22:37 PM PDT 24
Peak memory 195052 kb
Host smart-92c048c6-3c3e-4cde-896c-5f9d10f6ba6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324332923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2324332923
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.1770465067
Short name T435
Test name
Test status
Simulation time 32486163642 ps
CPU time 35.99 seconds
Started Jul 31 04:25:25 PM PDT 24
Finished Jul 31 04:26:02 PM PDT 24
Peak memory 198392 kb
Host smart-c7e82052-6e82-4186-94f4-2cff04765160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770465067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.1770465067
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.4014177592
Short name T740
Test name
Test status
Simulation time 92227405237 ps
CPU time 30.72 seconds
Started Jul 31 04:25:44 PM PDT 24
Finished Jul 31 04:26:15 PM PDT 24
Peak memory 199660 kb
Host smart-1dda6cb1-0d66-411c-ad3b-f2056ebe5409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014177592 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.4014177592
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.3708457118
Short name T237
Test name
Test status
Simulation time 51974073542 ps
CPU time 49.36 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:29 PM PDT 24
Peak memory 199644 kb
Host smart-6bcaa083-b309-4579-b68f-d2d93be4392e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708457118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.3708457118
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.1120817761
Short name T1172
Test name
Test status
Simulation time 55157508356 ps
CPU time 29.26 seconds
Started Jul 31 04:25:39 PM PDT 24
Finished Jul 31 04:26:09 PM PDT 24
Peak memory 199692 kb
Host smart-13dcb0cc-2aa7-4075-990b-40d98a350bc9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120817761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.1120817761
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.3466612359
Short name T242
Test name
Test status
Simulation time 56358288114 ps
CPU time 261.66 seconds
Started Jul 31 04:26:14 PM PDT 24
Finished Jul 31 04:30:36 PM PDT 24
Peak memory 199676 kb
Host smart-4b6119a5-3914-41a2-93e6-dae1b2456622
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466612359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.3466612359
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.1136585853
Short name T1167
Test name
Test status
Simulation time 3625598635 ps
CPU time 3.22 seconds
Started Jul 31 04:22:36 PM PDT 24
Finished Jul 31 04:22:39 PM PDT 24
Peak memory 199364 kb
Host smart-8d95d914-108d-43f3-b24c-28577fc751e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136585853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.1136585853
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.3687680104
Short name T532
Test name
Test status
Simulation time 13826668202 ps
CPU time 20.7 seconds
Started Jul 31 04:22:26 PM PDT 24
Finished Jul 31 04:22:47 PM PDT 24
Peak memory 199860 kb
Host smart-1955ab67-ce05-4659-a050-96409f58a781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687680104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.3687680104
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.182075809
Short name T658
Test name
Test status
Simulation time 6429898852 ps
CPU time 260.96 seconds
Started Jul 31 04:24:46 PM PDT 24
Finished Jul 31 04:29:07 PM PDT 24
Peak memory 198768 kb
Host smart-293f9a9d-c68e-4bd4-9b58-8b7891a72272
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=182075809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.182075809
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1830462804
Short name T1173
Test name
Test status
Simulation time 3400696583 ps
CPU time 12.54 seconds
Started Jul 31 04:22:27 PM PDT 24
Finished Jul 31 04:22:40 PM PDT 24
Peak memory 197556 kb
Host smart-671f4ddf-c10d-4e55-baa5-fe00c5ed3483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830462804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1830462804
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1892241170
Short name T1015
Test name
Test status
Simulation time 42458620660 ps
CPU time 21.72 seconds
Started Jul 31 04:22:20 PM PDT 24
Finished Jul 31 04:22:42 PM PDT 24
Peak memory 199644 kb
Host smart-6d704663-d0e2-446f-b4d5-598492c322b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892241170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1892241170
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.1687315916
Short name T482
Test name
Test status
Simulation time 1950987367 ps
CPU time 3.52 seconds
Started Jul 31 04:23:13 PM PDT 24
Finished Jul 31 04:23:17 PM PDT 24
Peak memory 195240 kb
Host smart-328e7b63-a4cf-4445-b83f-aca092ab2eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687315916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.1687315916
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.3175545689
Short name T402
Test name
Test status
Simulation time 306147089 ps
CPU time 2.32 seconds
Started Jul 31 04:23:25 PM PDT 24
Finished Jul 31 04:23:28 PM PDT 24
Peak memory 195676 kb
Host smart-852d7037-894a-4e5c-bd66-18c372d91b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175545689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.3175545689
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2546188036
Short name T464
Test name
Test status
Simulation time 47389841838 ps
CPU time 71.34 seconds
Started Jul 31 04:23:15 PM PDT 24
Finished Jul 31 04:24:26 PM PDT 24
Peak memory 199800 kb
Host smart-04496ef9-1b29-4d38-adc1-db0834f91997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546188036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2546188036
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.3447963554
Short name T37
Test name
Test status
Simulation time 171866749826 ps
CPU time 1564.05 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:48:39 PM PDT 24
Peak memory 226164 kb
Host smart-cdade631-cf1a-4cd5-b0b0-1fa382abebd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447963554 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.3447963554
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.4013090286
Short name T549
Test name
Test status
Simulation time 6897069328 ps
CPU time 18.01 seconds
Started Jul 31 04:22:34 PM PDT 24
Finished Jul 31 04:22:52 PM PDT 24
Peak memory 199532 kb
Host smart-094c8045-3f94-4b8f-8233-542c100b5a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013090286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.4013090286
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3900058311
Short name T1017
Test name
Test status
Simulation time 41505698999 ps
CPU time 26.15 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:24:08 PM PDT 24
Peak memory 199700 kb
Host smart-48dffa36-bbbf-4691-a18b-f14a64b1c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900058311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3900058311
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.3442242841
Short name T270
Test name
Test status
Simulation time 24067016705 ps
CPU time 31.78 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:27:03 PM PDT 24
Peak memory 199492 kb
Host smart-3586fb87-f024-49fa-afab-2ccb86776745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442242841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.3442242841
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2770865789
Short name T413
Test name
Test status
Simulation time 6342852062 ps
CPU time 70.02 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:27:40 PM PDT 24
Peak memory 208216 kb
Host smart-3ab8c45d-3a4a-43e5-be17-e2e6e930ef00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770865789 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2770865789
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.2768843561
Short name T761
Test name
Test status
Simulation time 75885609547 ps
CPU time 32.45 seconds
Started Jul 31 04:26:25 PM PDT 24
Finished Jul 31 04:26:57 PM PDT 24
Peak memory 199744 kb
Host smart-94076bf8-0a35-4f26-842c-3ad829811881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768843561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.2768843561
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3747635162
Short name T41
Test name
Test status
Simulation time 9978509555 ps
CPU time 130.09 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:28:44 PM PDT 24
Peak memory 216488 kb
Host smart-131ac62c-55fc-4d65-b13c-1b15470b7570
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747635162 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3747635162
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1702741639
Short name T593
Test name
Test status
Simulation time 121955125378 ps
CPU time 43.78 seconds
Started Jul 31 04:26:35 PM PDT 24
Finished Jul 31 04:27:19 PM PDT 24
Peak memory 199784 kb
Host smart-5f135743-60b7-4d44-949c-721a0c874390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702741639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1702741639
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3741774984
Short name T82
Test name
Test status
Simulation time 60508937781 ps
CPU time 195.17 seconds
Started Jul 31 04:26:40 PM PDT 24
Finished Jul 31 04:29:55 PM PDT 24
Peak memory 208016 kb
Host smart-9edf519e-711d-46f3-b339-0884780de436
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741774984 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3741774984
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2571205796
Short name T968
Test name
Test status
Simulation time 17139669337 ps
CPU time 32.96 seconds
Started Jul 31 04:26:44 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 199616 kb
Host smart-bf64aa69-71f8-4b6b-bff4-073f4118f075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571205796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2571205796
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.1854541119
Short name T344
Test name
Test status
Simulation time 56708135079 ps
CPU time 88.54 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:28:00 PM PDT 24
Peak memory 199764 kb
Host smart-c105dbfe-f1c1-4e64-b453-caf5a43bb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854541119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.1854541119
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.1962738579
Short name T1170
Test name
Test status
Simulation time 44540904455 ps
CPU time 11.15 seconds
Started Jul 31 04:26:31 PM PDT 24
Finished Jul 31 04:26:42 PM PDT 24
Peak memory 198236 kb
Host smart-31303cec-ab67-4529-ad88-f05a46c79cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962738579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1962738579
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2793448419
Short name T510
Test name
Test status
Simulation time 19178693336 ps
CPU time 101.1 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:28:26 PM PDT 24
Peak memory 208156 kb
Host smart-e9647930-e434-4051-bf46-cd15b2ab64e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793448419 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2793448419
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.3018230488
Short name T117
Test name
Test status
Simulation time 110553688771 ps
CPU time 29.76 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:12 PM PDT 24
Peak memory 199792 kb
Host smart-8cd2e3e3-c8e9-4d8b-b302-7554dc566d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018230488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.3018230488
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.2233803670
Short name T626
Test name
Test status
Simulation time 257402740103 ps
CPU time 291.94 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:31:34 PM PDT 24
Peak memory 215944 kb
Host smart-27a63d8d-3544-4b65-986e-31f07acfcbab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233803670 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.2233803670
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.3903621215
Short name T1165
Test name
Test status
Simulation time 19126326464 ps
CPU time 8.27 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:26:51 PM PDT 24
Peak memory 199740 kb
Host smart-daa7230a-08bc-4e86-9b1e-d7626921191d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903621215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.3903621215
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3774053109
Short name T575
Test name
Test status
Simulation time 50892876188 ps
CPU time 443.15 seconds
Started Jul 31 04:26:38 PM PDT 24
Finished Jul 31 04:34:01 PM PDT 24
Peak memory 216396 kb
Host smart-7e7087d6-16a4-4704-ae88-71aeba600ef6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774053109 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3774053109
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3587692357
Short name T631
Test name
Test status
Simulation time 182329970037 ps
CPU time 137.56 seconds
Started Jul 31 04:26:39 PM PDT 24
Finished Jul 31 04:28:56 PM PDT 24
Peak memory 199804 kb
Host smart-e2b44b60-7199-4bec-bff9-d78815d344ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587692357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3587692357
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2033338723
Short name T36
Test name
Test status
Simulation time 31421356238 ps
CPU time 194.16 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:29:57 PM PDT 24
Peak memory 215896 kb
Host smart-3b3893a0-bbf0-406a-811f-bceba1d9bc55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033338723 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2033338723
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.2936642084
Short name T298
Test name
Test status
Simulation time 152677407003 ps
CPU time 139.9 seconds
Started Jul 31 04:26:46 PM PDT 24
Finished Jul 31 04:29:06 PM PDT 24
Peak memory 199800 kb
Host smart-43d0f4ae-93bd-456c-8e2b-2918c93a7e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936642084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2936642084
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.3663045231
Short name T40
Test name
Test status
Simulation time 170869028138 ps
CPU time 130.55 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:28:43 PM PDT 24
Peak memory 208240 kb
Host smart-5abd752e-dfce-4b76-bf1d-d9b8f557b14e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663045231 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.3663045231
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.1516449204
Short name T1073
Test name
Test status
Simulation time 12457381 ps
CPU time 0.57 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:55 PM PDT 24
Peak memory 193244 kb
Host smart-5beaad5b-0552-4688-b075-5df7812d7c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516449204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.1516449204
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3920107467
Short name T250
Test name
Test status
Simulation time 175425482225 ps
CPU time 308.43 seconds
Started Jul 31 04:23:36 PM PDT 24
Finished Jul 31 04:28:44 PM PDT 24
Peak memory 199656 kb
Host smart-17b671c7-7f24-4fdf-a4c3-e3f854cfc85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920107467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3920107467
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.2692943174
Short name T486
Test name
Test status
Simulation time 23946280266 ps
CPU time 20.62 seconds
Started Jul 31 04:22:25 PM PDT 24
Finished Jul 31 04:22:46 PM PDT 24
Peak memory 200064 kb
Host smart-7ee1dbd7-fa33-461e-b32d-4b0eb319ff11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692943174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.2692943174
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.1790396217
Short name T820
Test name
Test status
Simulation time 249668995749 ps
CPU time 30.72 seconds
Started Jul 31 04:22:36 PM PDT 24
Finished Jul 31 04:23:07 PM PDT 24
Peak memory 199636 kb
Host smart-b0445e7f-1b74-4cb9-912d-2484dfadcd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790396217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1790396217
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.395479591
Short name T639
Test name
Test status
Simulation time 8256525774 ps
CPU time 12.48 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:54 PM PDT 24
Peak memory 197680 kb
Host smart-37b7977b-8110-4030-8f8c-abba164da778
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395479591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.395479591
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_loopback.112548196
Short name T499
Test name
Test status
Simulation time 1936511785 ps
CPU time 1.88 seconds
Started Jul 31 04:25:37 PM PDT 24
Finished Jul 31 04:25:39 PM PDT 24
Peak memory 195168 kb
Host smart-f2ac8482-41fc-4a48-9188-d00203a2a7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112548196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.112548196
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1734358548
Short name T1075
Test name
Test status
Simulation time 21411208173 ps
CPU time 7.83 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:40 PM PDT 24
Peak memory 199752 kb
Host smart-51f07542-e51d-41af-b29b-e1733948ae8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734358548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1734358548
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2023104989
Short name T318
Test name
Test status
Simulation time 11750373027 ps
CPU time 160.4 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:27:35 PM PDT 24
Peak memory 198260 kb
Host smart-ef437aa6-c2ef-4380-ae83-e476804efaed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2023104989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2023104989
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.1236493180
Short name T1041
Test name
Test status
Simulation time 2187234295 ps
CPU time 10.06 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:43 PM PDT 24
Peak memory 198380 kb
Host smart-0a456fea-fceb-4ec4-a697-a4f450124d82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1236493180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.1236493180
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.4246383156
Short name T934
Test name
Test status
Simulation time 39566944832 ps
CPU time 29.31 seconds
Started Jul 31 04:25:14 PM PDT 24
Finished Jul 31 04:25:44 PM PDT 24
Peak memory 199520 kb
Host smart-c9498135-ee3f-4509-b89f-a3c7da7e4f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246383156 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.4246383156
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1260651332
Short name T419
Test name
Test status
Simulation time 1473759506 ps
CPU time 3.02 seconds
Started Jul 31 04:24:41 PM PDT 24
Finished Jul 31 04:24:44 PM PDT 24
Peak memory 195256 kb
Host smart-91b02617-e513-46b2-aaad-75112b5ed2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260651332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1260651332
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.2245538215
Short name T503
Test name
Test status
Simulation time 5906863117 ps
CPU time 39.32 seconds
Started Jul 31 04:25:12 PM PDT 24
Finished Jul 31 04:25:51 PM PDT 24
Peak memory 199000 kb
Host smart-e5537ce3-2ee4-416e-8930-cb3150f5561a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245538215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.2245538215
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.1326165047
Short name T171
Test name
Test status
Simulation time 49617105246 ps
CPU time 54.96 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:24:37 PM PDT 24
Peak memory 199820 kb
Host smart-d59fc3d3-77b5-44e8-a33d-0b0d31cad217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326165047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1326165047
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.636339483
Short name T356
Test name
Test status
Simulation time 3804636594 ps
CPU time 2.15 seconds
Started Jul 31 04:25:05 PM PDT 24
Finished Jul 31 04:25:08 PM PDT 24
Peak memory 198364 kb
Host smart-72f17257-5e72-4e24-9a87-53f22181c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636339483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.636339483
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.1732106257
Short name T309
Test name
Test status
Simulation time 3868117950 ps
CPU time 3.14 seconds
Started Jul 31 04:25:32 PM PDT 24
Finished Jul 31 04:25:36 PM PDT 24
Peak memory 197096 kb
Host smart-d50f075c-c134-4d51-8648-64f6fdf483ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732106257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.1732106257
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4117960846
Short name T27
Test name
Test status
Simulation time 15130536947 ps
CPU time 40.34 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:27:25 PM PDT 24
Peak memory 199756 kb
Host smart-1cc4170e-90cf-4f4c-ad6b-c0432c347a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117960846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4117960846
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4057839791
Short name T946
Test name
Test status
Simulation time 37071948586 ps
CPU time 30.22 seconds
Started Jul 31 04:26:44 PM PDT 24
Finished Jul 31 04:27:15 PM PDT 24
Peak memory 199688 kb
Host smart-f3159e38-4bdb-4a67-93da-2c387a63411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057839791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4057839791
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.353860999
Short name T918
Test name
Test status
Simulation time 70408010280 ps
CPU time 733.49 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:38:46 PM PDT 24
Peak memory 216260 kb
Host smart-b7b6dbe9-51c2-49ec-ab4b-0e6f0f11d45f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353860999 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.353860999
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.3156053525
Short name T915
Test name
Test status
Simulation time 300093410729 ps
CPU time 176.76 seconds
Started Jul 31 04:26:33 PM PDT 24
Finished Jul 31 04:29:30 PM PDT 24
Peak memory 199792 kb
Host smart-62abcaf8-4c24-42e4-9e20-f6c2574c8543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156053525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.3156053525
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3265822477
Short name T1001
Test name
Test status
Simulation time 152230535682 ps
CPU time 235.65 seconds
Started Jul 31 04:26:36 PM PDT 24
Finished Jul 31 04:30:32 PM PDT 24
Peak memory 216408 kb
Host smart-f7afae32-e53d-40cf-ae5e-b3fdf7e72350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265822477 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3265822477
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1505597708
Short name T163
Test name
Test status
Simulation time 25003053280 ps
CPU time 42.27 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:27:17 PM PDT 24
Peak memory 199768 kb
Host smart-8640dd2f-3597-4d54-9cc1-68a2af266bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505597708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1505597708
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2874914255
Short name T81
Test name
Test status
Simulation time 51979115501 ps
CPU time 327.73 seconds
Started Jul 31 04:26:34 PM PDT 24
Finished Jul 31 04:32:02 PM PDT 24
Peak memory 216424 kb
Host smart-f894e2ef-bd25-4dfd-9845-e62b13c01cf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874914255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2874914255
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.4035135264
Short name T170
Test name
Test status
Simulation time 29757866279 ps
CPU time 43.35 seconds
Started Jul 31 04:26:30 PM PDT 24
Finished Jul 31 04:27:13 PM PDT 24
Peak memory 199624 kb
Host smart-80e199d1-f51c-4595-81a1-6edca2e40c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035135264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.4035135264
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.1154589498
Short name T33
Test name
Test status
Simulation time 89513009909 ps
CPU time 951.97 seconds
Started Jul 31 04:26:40 PM PDT 24
Finished Jul 31 04:42:33 PM PDT 24
Peak memory 225300 kb
Host smart-26f7334d-e796-43af-9dcb-9d23071bc067
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154589498 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.1154589498
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.2843446257
Short name T676
Test name
Test status
Simulation time 118111147988 ps
CPU time 380.73 seconds
Started Jul 31 04:26:35 PM PDT 24
Finished Jul 31 04:32:55 PM PDT 24
Peak memory 216380 kb
Host smart-e03a809d-44a7-4fd0-8d18-99e1bd7f85dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843446257 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.2843446257
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.1764192383
Short name T218
Test name
Test status
Simulation time 38126018434 ps
CPU time 80.1 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:28:02 PM PDT 24
Peak memory 199800 kb
Host smart-0a33c994-ec1a-45fc-9bc3-83475fa01d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764192383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1764192383
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3921653804
Short name T83
Test name
Test status
Simulation time 43219264044 ps
CPU time 425.8 seconds
Started Jul 31 04:26:47 PM PDT 24
Finished Jul 31 04:33:53 PM PDT 24
Peak memory 216288 kb
Host smart-2ff4d0a6-09d0-4a00-a10e-85dcb3a0e680
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921653804 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3921653804
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2726877121
Short name T1101
Test name
Test status
Simulation time 50696550217 ps
CPU time 40.45 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:27:22 PM PDT 24
Peak memory 199740 kb
Host smart-dc624569-91f0-423b-b988-e421210d6d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726877121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2726877121
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.119975817
Short name T185
Test name
Test status
Simulation time 120412211135 ps
CPU time 416.54 seconds
Started Jul 31 04:26:40 PM PDT 24
Finished Jul 31 04:33:36 PM PDT 24
Peak memory 216408 kb
Host smart-ab5d00e6-d95c-4147-803e-9f29dd3eaeab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119975817 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.119975817
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2674221130
Short name T320
Test name
Test status
Simulation time 36063555882 ps
CPU time 12.23 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:26:55 PM PDT 24
Peak memory 199744 kb
Host smart-bc136d65-bea1-45c1-8370-3b42e1a6922d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674221130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2674221130
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.4242471575
Short name T1091
Test name
Test status
Simulation time 56598509962 ps
CPU time 198.71 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:29:50 PM PDT 24
Peak memory 208088 kb
Host smart-d7f79ed9-f980-47d0-8cb9-d06f2f267f19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242471575 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.4242471575
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.107049255
Short name T1053
Test name
Test status
Simulation time 136083492422 ps
CPU time 54.23 seconds
Started Jul 31 04:26:32 PM PDT 24
Finished Jul 31 04:27:26 PM PDT 24
Peak memory 199748 kb
Host smart-a8953678-697a-4e59-ab80-410fc6ef1d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107049255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.107049255
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.3000671029
Short name T493
Test name
Test status
Simulation time 40055133 ps
CPU time 0.61 seconds
Started Jul 31 04:22:46 PM PDT 24
Finished Jul 31 04:22:46 PM PDT 24
Peak memory 195092 kb
Host smart-d5ddb2dd-8c01-4090-b5dd-2039af473f87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000671029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.3000671029
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.939619210
Short name T1098
Test name
Test status
Simulation time 23534988759 ps
CPU time 44.43 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:26:07 PM PDT 24
Peak memory 199540 kb
Host smart-50852a8f-a71f-43d3-950e-53196dd62268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939619210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.939619210
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.884253253
Short name T140
Test name
Test status
Simulation time 27664226869 ps
CPU time 34.23 seconds
Started Jul 31 04:24:52 PM PDT 24
Finished Jul 31 04:25:26 PM PDT 24
Peak memory 198936 kb
Host smart-460f6fd6-8500-42a2-8913-0c5408a72894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884253253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.884253253
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.117143030
Short name T825
Test name
Test status
Simulation time 3934946984 ps
CPU time 7.29 seconds
Started Jul 31 04:22:39 PM PDT 24
Finished Jul 31 04:22:47 PM PDT 24
Peak memory 197060 kb
Host smart-63c69e8c-8a61-4306-a715-5ae50c6a2f89
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117143030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.117143030
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.4039256601
Short name T566
Test name
Test status
Simulation time 82354003882 ps
CPU time 162.03 seconds
Started Jul 31 04:25:58 PM PDT 24
Finished Jul 31 04:28:40 PM PDT 24
Peak memory 199508 kb
Host smart-a93a1000-e32c-4ac4-9d45-6ba1b39aa020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4039256601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.4039256601
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.1924574203
Short name T765
Test name
Test status
Simulation time 4001467611 ps
CPU time 2.64 seconds
Started Jul 31 04:23:56 PM PDT 24
Finished Jul 31 04:23:59 PM PDT 24
Peak memory 198328 kb
Host smart-01ded782-0117-4965-8307-eb167b094414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924574203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1924574203
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.3131607964
Short name T296
Test name
Test status
Simulation time 100720963467 ps
CPU time 127.19 seconds
Started Jul 31 04:25:23 PM PDT 24
Finished Jul 31 04:27:30 PM PDT 24
Peak memory 199680 kb
Host smart-d4fb00b4-4294-4fd6-a898-f9b20a7426f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131607964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.3131607964
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1422258859
Short name T614
Test name
Test status
Simulation time 8381120764 ps
CPU time 96.18 seconds
Started Jul 31 04:23:56 PM PDT 24
Finished Jul 31 04:25:33 PM PDT 24
Peak memory 199832 kb
Host smart-fa776bfd-7a18-4ba8-b480-807da538b309
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1422258859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1422258859
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.1705602190
Short name T1022
Test name
Test status
Simulation time 4151892970 ps
CPU time 17.91 seconds
Started Jul 31 04:22:35 PM PDT 24
Finished Jul 31 04:22:53 PM PDT 24
Peak memory 198664 kb
Host smart-603f663a-5737-4baf-a9bf-f30e0d559057
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1705602190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.1705602190
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.3974163761
Short name T718
Test name
Test status
Simulation time 332270291247 ps
CPU time 223.05 seconds
Started Jul 31 04:23:15 PM PDT 24
Finished Jul 31 04:26:58 PM PDT 24
Peak memory 199804 kb
Host smart-29c33096-4346-4059-9e25-f21a97df6e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974163761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.3974163761
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1187979647
Short name T458
Test name
Test status
Simulation time 49693177378 ps
CPU time 69.07 seconds
Started Jul 31 04:25:14 PM PDT 24
Finished Jul 31 04:26:24 PM PDT 24
Peak memory 194828 kb
Host smart-9cbee078-597a-429e-8042-82a90a2ff2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187979647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1187979647
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.59882680
Short name T617
Test name
Test status
Simulation time 622387824 ps
CPU time 2.33 seconds
Started Jul 31 04:24:54 PM PDT 24
Finished Jul 31 04:24:57 PM PDT 24
Peak memory 196988 kb
Host smart-da80392f-bffb-4b10-afdd-7d5924e9279b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59882680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.59882680
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.4715836
Short name T94
Test name
Test status
Simulation time 139432727510 ps
CPU time 111.07 seconds
Started Jul 31 04:22:40 PM PDT 24
Finished Jul 31 04:24:31 PM PDT 24
Peak memory 199564 kb
Host smart-e6ac2528-23c3-4821-b559-b58410bfdae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4715836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.4715836
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.1007601140
Short name T153
Test name
Test status
Simulation time 313739566587 ps
CPU time 1183.4 seconds
Started Jul 31 04:25:59 PM PDT 24
Finished Jul 31 04:45:42 PM PDT 24
Peak memory 216436 kb
Host smart-fac12e28-d9d1-4015-9a81-01873f12cf2a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007601140 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.1007601140
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2959445172
Short name T1168
Test name
Test status
Simulation time 6577057372 ps
CPU time 8.31 seconds
Started Jul 31 04:23:55 PM PDT 24
Finished Jul 31 04:24:03 PM PDT 24
Peak memory 199640 kb
Host smart-d8b338d9-cfe2-4569-a9ca-77dc33a4b29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959445172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2959445172
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2983867298
Short name T1023
Test name
Test status
Simulation time 291874708873 ps
CPU time 66.13 seconds
Started Jul 31 04:23:42 PM PDT 24
Finished Jul 31 04:24:48 PM PDT 24
Peak memory 199864 kb
Host smart-f8239ebf-f671-4d5f-b548-82761509dbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983867298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2983867298
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.1641263298
Short name T206
Test name
Test status
Simulation time 70461024150 ps
CPU time 45.33 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 199536 kb
Host smart-af455d1c-dc7e-4bbf-87d1-5e3d8e8b9281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641263298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.1641263298
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.2031230909
Short name T716
Test name
Test status
Simulation time 122169742246 ps
CPU time 277.79 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:31:23 PM PDT 24
Peak memory 215856 kb
Host smart-27a14d84-6d42-4b30-ac35-44a2a341c429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031230909 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.2031230909
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.777964287
Short name T867
Test name
Test status
Simulation time 99827299400 ps
CPU time 27.93 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:11 PM PDT 24
Peak memory 199728 kb
Host smart-4f84b956-3ab3-4f11-b8d0-2d3aa14af3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777964287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.777964287
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.3284767878
Short name T678
Test name
Test status
Simulation time 11116491457 ps
CPU time 13.67 seconds
Started Jul 31 04:26:45 PM PDT 24
Finished Jul 31 04:26:59 PM PDT 24
Peak memory 199660 kb
Host smart-40a3b124-7bb6-40d1-ade5-6d66721c70cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284767878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.3284767878
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.2272312629
Short name T561
Test name
Test status
Simulation time 38219695200 ps
CPU time 322.5 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:32:03 PM PDT 24
Peak memory 215456 kb
Host smart-9ffe4e34-ee28-4b8e-ada8-bdd01562fe22
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272312629 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.2272312629
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3339954909
Short name T754
Test name
Test status
Simulation time 33549323327 ps
CPU time 54.38 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:37 PM PDT 24
Peak memory 199640 kb
Host smart-fd64d038-110b-498b-8ebe-3065881b924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339954909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3339954909
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1224707065
Short name T289
Test name
Test status
Simulation time 298152986230 ps
CPU time 40.98 seconds
Started Jul 31 04:26:51 PM PDT 24
Finished Jul 31 04:27:32 PM PDT 24
Peak memory 199724 kb
Host smart-f7bc0bdc-be3d-4a77-959b-8d7b7b941775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224707065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1224707065
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.1093756639
Short name T752
Test name
Test status
Simulation time 88966762304 ps
CPU time 251.04 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:30:54 PM PDT 24
Peak memory 213988 kb
Host smart-189d22ef-5c54-4bf0-92b3-120936685244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093756639 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.1093756639
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.407175007
Short name T1013
Test name
Test status
Simulation time 12306595809 ps
CPU time 6.8 seconds
Started Jul 31 04:26:37 PM PDT 24
Finished Jul 31 04:26:44 PM PDT 24
Peak memory 199516 kb
Host smart-2b3ef7d7-14bf-4101-9834-b57b9fd1fbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407175007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.407175007
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.1143259874
Short name T203
Test name
Test status
Simulation time 65979542587 ps
CPU time 45.09 seconds
Started Jul 31 04:26:42 PM PDT 24
Finished Jul 31 04:27:27 PM PDT 24
Peak memory 199760 kb
Host smart-611197e6-75b2-4df1-a4b8-d8fe92df0794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143259874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1143259874
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3350263088
Short name T684
Test name
Test status
Simulation time 59058809318 ps
CPU time 533.7 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:35:35 PM PDT 24
Peak memory 225408 kb
Host smart-bf34bd6a-dc63-4117-b7c9-e320bba1d16e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350263088 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3350263088
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.1540542409
Short name T551
Test name
Test status
Simulation time 128938170924 ps
CPU time 109.28 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:28:30 PM PDT 24
Peak memory 199780 kb
Host smart-084bb0c0-1ef0-4cbc-946c-9858aca83346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540542409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.1540542409
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2060170070
Short name T876
Test name
Test status
Simulation time 40326386025 ps
CPU time 376.46 seconds
Started Jul 31 04:26:36 PM PDT 24
Finished Jul 31 04:32:53 PM PDT 24
Peak memory 215428 kb
Host smart-52d4bf3e-2823-43b9-afb3-dc03832306e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060170070 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2060170070
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.4189218523
Short name T487
Test name
Test status
Simulation time 33679690467 ps
CPU time 16.17 seconds
Started Jul 31 04:26:44 PM PDT 24
Finished Jul 31 04:27:00 PM PDT 24
Peak memory 199824 kb
Host smart-b7a792da-d082-4cf1-ae37-ccce80f743c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189218523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.4189218523
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.1028792138
Short name T38
Test name
Test status
Simulation time 122230556240 ps
CPU time 1258.37 seconds
Started Jul 31 04:26:41 PM PDT 24
Finished Jul 31 04:47:40 PM PDT 24
Peak memory 224940 kb
Host smart-63c3148c-2631-4cf5-9574-6b0c2ff2b533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028792138 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.1028792138
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1854028706
Short name T174
Test name
Test status
Simulation time 50414138672 ps
CPU time 30.16 seconds
Started Jul 31 04:26:43 PM PDT 24
Finished Jul 31 04:27:13 PM PDT 24
Peak memory 199800 kb
Host smart-875b623a-d9de-4aa0-94de-362f6cd7e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854028706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1854028706
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.911402279
Short name T34
Test name
Test status
Simulation time 148714987260 ps
CPU time 853.62 seconds
Started Jul 31 04:26:46 PM PDT 24
Finished Jul 31 04:41:00 PM PDT 24
Peak memory 224568 kb
Host smart-d2de800b-e429-4a99-aa35-96ce46a7f9b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911402279 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.911402279
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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