Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	107331	1			T1	5		T2	21		T3	54
all_values[1]	107331	1			T1	5		T2	21		T3	54
all_values[2]	107331	1			T1	5		T2	21		T3	54
all_values[3]	107331	1			T1	5		T2	21		T3	54
all_values[4]	107331	1			T1	5		T2	21		T3	54
all_values[5]	107331	1			T1	5		T2	21		T3	54
all_values[6]	107331	1			T1	5		T2	21		T3	54
all_values[7]	107331	1			T1	5		T2	21		T3	54
all_values[8]	107331	1			T1	5		T2	21		T3	54

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

485536

1

T1

23

T2

109

T3

108

auto[1]

480443

1

T1

22

T2

80

T3

378

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

874938

1

T1

38

T2

147

T3

463

auto[1]

91041

1

T1

7

T2

42

T3

23

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	31402	1			T3	45		T7	2		T8	2
all_values[0]	auto[0]	auto[1]	23157	1			T1	1		T2	19		T3	9
all_values[0]	auto[1]	auto[0]	30471	1			T1	3		T8	12		T9	24
all_values[0]	auto[1]	auto[1]	22301	1			T1	1		T2	2		T7	1
all_values[1]	auto[0]	auto[0]	51780	1			T1	1		T2	1		T4	2
all_values[1]	auto[0]	auto[1]	1543	1			T7	2		T8	2		T36	7
all_values[1]	auto[1]	auto[0]	52374	1			T1	4		T2	18		T3	54
all_values[1]	auto[1]	auto[1]	1634	1			T2	2		T9	15		T87	4
all_values[2]	auto[0]	auto[0]	53034	1			T1	1		T2	2		T3	48
all_values[2]	auto[0]	auto[1]	2733	1			T1	2		T2	1		T3	4
all_values[2]	auto[1]	auto[0]	49293	1			T1	1		T2	13		T3	1
all_values[2]	auto[1]	auto[1]	2271	1			T1	1		T2	5		T3	1
all_values[3]	auto[0]	auto[0]	51668	1			T1	1		T2	6		T4	2
all_values[3]	auto[0]	auto[1]	285	1			T13	1		T16	3		T17	2
all_values[3]	auto[1]	auto[0]	55088	1			T1	4		T2	15		T3	54
all_values[3]	auto[1]	auto[1]	290	1			T8	1		T14	1		T87	1
all_values[4]	auto[0]	auto[0]	52162	1			T1	3		T2	16		T3	2
all_values[4]	auto[0]	auto[1]	412	1			T8	3		T16	1		T17	3
all_values[4]	auto[1]	auto[0]	54396	1			T1	2		T2	5		T3	52
all_values[4]	auto[1]	auto[1]	361	1			T16	5		T17	2		T18	1
all_values[5]	auto[0]	auto[0]	52862	1			T1	2		T2	14		T4	2
all_values[5]	auto[0]	auto[1]	156	1			T16	1		T17	6		T18	2
all_values[5]	auto[1]	auto[0]	54161	1			T1	3		T2	7		T3	54
all_values[5]	auto[1]	auto[1]	152	1			T16	4		T17	6		T20	1
all_values[6]	auto[0]	auto[0]	53326	1			T1	4		T2	16		T4	2
all_values[6]	auto[0]	auto[1]	177	1			T16	2		T17	5		T18	1
all_values[6]	auto[1]	auto[0]	53668	1			T1	1		T2	5		T3	54
all_values[6]	auto[1]	auto[1]	160	1			T16	3		T17	2		T18	3
all_values[7]	auto[0]	auto[0]	53496	1			T1	4		T2	19		T4	2
all_values[7]	auto[0]	auto[1]	291	1			T8	2		T16	5		T17	1
all_values[7]	auto[1]	auto[0]	53200	1			T1	1		T2	2		T3	54
all_values[7]	auto[1]	auto[1]	344	1			T9	6		T88	3		T16	5
all_values[8]	auto[0]	auto[0]	38425	1			T1	3		T2	8		T9	29
all_values[8]	auto[0]	auto[1]	18627	1			T1	1		T2	7		T4	2
all_values[8]	auto[1]	auto[0]	34132	1			T3	45		T7	2		T8	14
all_values[8]	auto[1]	auto[1]	16147	1			T1	1		T2	6		T3	9