Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2269	1			T2	2		T3	1		T4	1
auto[BaudRate115200]	2023	1			T2	1		T3	1		T6	2
auto[BaudRate230400]	1902	1			T2	2		T9	12		T11	15
auto[BaudRate128Kbps]	1990	1			T2	1		T3	1		T4	1
auto[BaudRate256Kbps]	2148	1			T1	3		T3	2		T7	1
auto[BaudRate1Mbps]	1894	1			T1	1		T8	3		T9	4
auto[BaudRate1p5Mbps]	1338	1			T1	4		T2	2		T3	4

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1350	1			T12	16		T39	9		T274	5
freqs[25]	1405	1			T1	8		T4	2		T9	55
freqs[48]	494	1			T40	10		T276	5		T312	5
freqs[50]	615	1			T13	7		T24	14		T280	9
freqs[100]	1315	1			T2	8		T37	6		T38	9

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	262	1			T12	1		T327	2		T183	4
auto[BaudRate9600]	freqs[25]	211	1			T4	1		T9	14		T14	2
auto[BaudRate9600]	freqs[48]	73	1			T276	1		T272	2		T206	1
auto[BaudRate9600]	freqs[50]	79	1			T24	1		T280	1		T319	1
auto[BaudRate9600]	freqs[100]	205	1			T2	2		T38	1		T112	1
auto[BaudRate115200]	freqs[24]	202	1			T12	3		T274	2		T183	1
auto[BaudRate115200]	freqs[25]	233	1			T9	12		T14	1		T30	6
auto[BaudRate115200]	freqs[48]	71	1			T276	2		T133	2		T272	1
auto[BaudRate115200]	freqs[50]	120	1			T24	1		T280	1		T294	1
auto[BaudRate115200]	freqs[100]	167	1			T2	1		T37	1		T112	1
auto[BaudRate230400]	freqs[24]	190	1			T12	3		T39	1		T18	4
auto[BaudRate230400]	freqs[25]	197	1			T9	12		T14	1		T87	1
auto[BaudRate230400]	freqs[48]	71	1			T133	2		T272	2		T206	2
auto[BaudRate230400]	freqs[50]	98	1			T13	1		T24	2		T311	1
auto[BaudRate230400]	freqs[100]	173	1			T2	2		T37	1		T38	1
auto[BaudRate128Kbps]	freqs[24]	186	1			T12	3		T290	2		T18	1
auto[BaudRate128Kbps]	freqs[25]	203	1			T4	1		T9	3		T14	1
auto[BaudRate128Kbps]	freqs[48]	71	1			T276	1		T133	1		T272	4
auto[BaudRate128Kbps]	freqs[50]	87	1			T13	3		T24	1		T280	2
auto[BaudRate128Kbps]	freqs[100]	175	1			T2	1		T37	1		T38	1
auto[BaudRate256Kbps]	freqs[24]	213	1			T12	2		T39	1		T274	2
auto[BaudRate256Kbps]	freqs[25]	209	1			T1	3		T9	6		T14	2
auto[BaudRate256Kbps]	freqs[48]	68	1			T40	3		T133	2		T272	2
auto[BaudRate256Kbps]	freqs[50]	86	1			T13	1		T24	4		T280	1
auto[BaudRate256Kbps]	freqs[100]	215	1			T37	1		T38	5		T112	1
auto[BaudRate1Mbps]	freqs[24]	208	1			T12	2		T39	7		T274	1
auto[BaudRate1Mbps]	freqs[25]	229	1			T1	1		T9	4		T14	2
auto[BaudRate1Mbps]	freqs[48]	67	1			T40	3		T312	2		T133	2
auto[BaudRate1Mbps]	freqs[50]	89	1			T13	1		T24	2		T280	2
auto[BaudRate1Mbps]	freqs[100]	175	1			T37	1		T38	1		T112	1
auto[BaudRate1p5Mbps]	freqs[25]	123	1			T1	4		T9	4		T14	1
auto[BaudRate1p5Mbps]	freqs[48]	73	1			T40	4		T276	1		T312	3
auto[BaudRate1p5Mbps]	freqs[50]	56	1			T13	1		T24	3		T280	2
auto[BaudRate1p5Mbps]	freqs[100]	205	1			T2	2		T37	1		T266	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded