Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	28442944	1			T1	35716		T2	377		T3	29
all_levels[1]	175432	1			T1	2353		T2	34		T8	241
all_levels[2]	2474	1			T1	17		T2	3		T7	1
all_levels[3]	1058	1			T7	1		T9	4		T11	1
all_levels[4]	689	1			T7	3		T9	4		T11	2
all_levels[5]	520	1			T7	1		T8	2		T9	4
all_levels[6]	420	1			T7	2		T9	3		T12	1
all_levels[7]	332	1			T9	3		T35	1		T13	2
all_levels[8]	301	1			T9	1		T12	1		T35	1
all_levels[9]	258	1			T7	1		T9	1		T35	1
all_levels[10]	175	1			T7	1		T113	1		T114	1
all_levels[11]	176	1			T9	2		T102	1		T14	1
all_levels[12]	152	1			T13	1		T38	1		T113	1
all_levels[13]	157	1			T9	1		T13	1		T102	1
all_levels[14]	139	1			T9	1		T13	1		T102	1
all_levels[15]	132	1			T114	1		T123	1		T129	2
all_levels[16]	100	1			T9	1		T38	1		T130	1
all_levels[17]	100	1			T38	1		T88	1		T117	1
all_levels[18]	83	1			T9	2		T114	1		T131	2
all_levels[19]	96	1			T87	2		T113	1		T131	1
all_levels[20]	90	1			T14	1		T38	1		T117	1
all_levels[21]	63	1			T132	1		T133	1		T33	1
all_levels[22]	60	1			T123	1		T117	1		T131	1
all_levels[23]	55	1			T13	1		T39	1		T113	1
all_levels[24]	68	1			T7	2		T9	1		T30	1
all_levels[25]	57	1			T7	2		T114	1		T16	1
all_levels[26]	51	1			T7	1		T38	1		T16	1
all_levels[27]	50	1			T9	1		T38	1		T132	1
all_levels[28]	30	1			T134	2		T50	1		T135	1
all_levels[29]	39	1			T120	1		T136	1		T115	1
all_levels[30]	50	1			T9	1		T14	1		T114	1
all_levels[31]	35	1			T9	1		T39	4		T131	1
all_levels[32]	34	1			T13	1		T88	1		T137	1
all_levels[33]	26	1			T129	1		T137	1		T138	1
all_levels[34]	20	1			T139	1		T140	1		T141	1
all_levels[35]	26	1			T142	2		T143	1		T140	1
all_levels[36]	30	1			T131	1		T144	1		T145	1
all_levels[37]	15	1			T146	1		T147	1		T125	1
all_levels[38]	20	1			T136	1		T145	1		T138	2
all_levels[39]	16	1			T48	1		T148	2		T149	1
all_levels[40]	26	1			T126	1		T135	1		T150	1
all_levels[41]	23	1			T123	1		T120	1		T151	1
all_levels[42]	20	1			T114	1		T115	1		T143	2
all_levels[43]	22	1			T152	3		T132	1		T153	1
all_levels[44]	14	1			T150	1		T154	1		T153	1
all_levels[45]	16	1			T48	1		T155	1		T125	1
all_levels[46]	6	1			T7	1		T156	1		T157	1
all_levels[47]	27	1			T158	1		T146	2		T151	1
all_levels[48]	18	1			T102	1		T87	1		T145	2
all_levels[49]	18	1			T114	1		T159	1		T160	1
all_levels[50]	5	1			T161	1		T162	1		T163	1
all_levels[51]	10	1			T30	1		T159	1		T164	1
all_levels[52]	8	1			T30	1		T145	1		T156	1
all_levels[53]	9	1			T165	1		T166	1		T167	1
all_levels[54]	8	1			T123	1		T159	1		T168	1
all_levels[55]	15	1			T158	1		T169	1		T170	1
all_levels[56]	14	1			T9	1		T21	1		T171	1
all_levels[57]	7	1			T172	1		T173	1		T174	1
all_levels[58]	13	1			T138	3		T175	3		T169	1
all_levels[59]	5	1			T169	1		T176	1		T177	1
all_levels[60]	5	1			T178	1		T179	1		T180	1
all_levels[61]	8	1			T142	1		T181	2		T182	1
all_levels[62]	10	1			T117	1		T170	1		T173	1
all_levels[63]	11	1			T13	1		T123	1		T43	1
all_levels[64]	101	1			T13	1		T14	1		T87	2

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28622361

1

T1

38086

T2

414

T3

22

auto[1]

4631

1

T3

7

T5

1

T7

5

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[33]]	[auto[1]]	0	1	1
[all_levels[46]]	[auto[1]]	0	1	1
[all_levels[50] , all_levels[51] , all_levels[52] , all_levels[53] , all_levels[54]]	[auto[1]]	--	--	5
[all_levels[59] , all_levels[60]]	[auto[1]]	--	--	2
[all_levels[63]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	28438755	1			T1	35716		T2	377		T3	22
all_levels[0]	auto[1]	4189	1			T3	7		T5	1		T7	2
all_levels[1]	auto[0]	175364	1			T1	2353		T2	34		T8	241
all_levels[1]	auto[1]	68	1			T14	1		T87	1		T183	2
all_levels[2]	auto[0]	2451	1			T1	17		T2	3		T7	1
all_levels[2]	auto[1]	23	1			T130	1		T165	3		T184	1
all_levels[3]	auto[0]	1023	1			T7	1		T9	4		T11	1
all_levels[3]	auto[1]	35	1			T116	1		T132	1		T185	2
all_levels[4]	auto[0]	675	1			T7	1		T9	4		T11	2
all_levels[4]	auto[1]	14	1			T7	2		T118	2		T186	1
all_levels[5]	auto[0]	507	1			T7	1		T8	2		T9	4
all_levels[5]	auto[1]	13	1			T137	2		T187	1		T188	1
all_levels[6]	auto[0]	412	1			T7	2		T9	3		T12	1
all_levels[6]	auto[1]	8	1			T189	2		T190	1		T162	1
all_levels[7]	auto[0]	325	1			T9	3		T35	1		T13	2
all_levels[7]	auto[1]	7	1			T38	1		T191	1		T192	1
all_levels[8]	auto[0]	284	1			T9	1		T12	1		T35	1
all_levels[8]	auto[1]	17	1			T152	1		T137	2		T193	2
all_levels[9]	auto[0]	244	1			T7	1		T9	1		T35	1
all_levels[9]	auto[1]	14	1			T194	1		T119	4		T141	2
all_levels[10]	auto[0]	166	1			T7	1		T113	1		T114	1
all_levels[10]	auto[1]	9	1			T191	1		T195	1		T196	1
all_levels[11]	auto[0]	161	1			T9	2		T102	1		T14	1
all_levels[11]	auto[1]	15	1			T20	1		T50	2		T197	1
all_levels[12]	auto[0]	146	1			T13	1		T38	1		T113	1
all_levels[12]	auto[1]	6	1			T198	2		T199	1		T200	1
all_levels[13]	auto[0]	149	1			T9	1		T13	1		T102	1
all_levels[13]	auto[1]	8	1			T201	2		T169	1		T202	1
all_levels[14]	auto[0]	123	1			T9	1		T13	1		T102	1
all_levels[14]	auto[1]	16	1			T130	1		T203	1		T196	1
all_levels[15]	auto[0]	111	1			T114	1		T123	1		T129	2
all_levels[15]	auto[1]	21	1			T204	1		T188	2		T205	2
all_levels[16]	auto[0]	90	1			T9	1		T38	1		T130	1
all_levels[16]	auto[1]	10	1			T206	1		T207	1		T208	3
all_levels[17]	auto[0]	93	1			T38	1		T88	1		T117	1
all_levels[17]	auto[1]	7	1			T155	1		T209	1		T210	1
all_levels[18]	auto[0]	77	1			T9	2		T114	1		T131	2
all_levels[18]	auto[1]	6	1			T31	1		T211	1		T212	1
all_levels[19]	auto[0]	90	1			T87	1		T113	1		T131	1
all_levels[19]	auto[1]	6	1			T87	1		T213	1		T214	2
all_levels[20]	auto[0]	78	1			T14	1		T38	1		T117	1
all_levels[20]	auto[1]	12	1			T215	1		T216	2		T217	1
all_levels[21]	auto[0]	58	1			T132	1		T133	1		T33	1
all_levels[21]	auto[1]	5	1			T218	1		T219	2		T220	1
all_levels[22]	auto[0]	51	1			T123	1		T117	1		T131	1
all_levels[22]	auto[1]	9	1			T221	1		T206	1		T212	1
all_levels[23]	auto[0]	53	1			T13	1		T39	1		T113	1
all_levels[23]	auto[1]	2	1			T202	1		T222	1		-	-
all_levels[24]	auto[0]	63	1			T7	1		T9	1		T30	1
all_levels[24]	auto[1]	5	1			T7	1		T223	2		T224	1
all_levels[25]	auto[0]	55	1			T7	2		T114	1		T16	1
all_levels[25]	auto[1]	2	1			T118	1		T202	1		-	-
all_levels[26]	auto[0]	48	1			T7	1		T38	1		T16	1
all_levels[26]	auto[1]	3	1			T225	1		T226	1		T227	1
all_levels[27]	auto[0]	39	1			T9	1		T38	1		T132	1
all_levels[27]	auto[1]	11	1			T218	2		T228	2		T229	2
all_levels[28]	auto[0]	28	1			T134	1		T50	1		T135	1
all_levels[28]	auto[1]	2	1			T134	1		T230	1		-	-
all_levels[29]	auto[0]	36	1			T120	1		T136	1		T115	1
all_levels[29]	auto[1]	3	1			T231	3		-	-		-	-
all_levels[30]	auto[0]	44	1			T9	1		T14	1		T114	1
all_levels[30]	auto[1]	6	1			T30	1		T232	1		T233	1
all_levels[31]	auto[0]	28	1			T9	1		T39	1		T131	1
all_levels[31]	auto[1]	7	1			T39	3		T163	1		T234	2
all_levels[32]	auto[0]	28	1			T13	1		T88	1		T137	1
all_levels[32]	auto[1]	6	1			T235	2		T236	2		T237	2
all_levels[33]	auto[0]	26	1			T129	1		T137	1		T138	1
all_levels[34]	auto[0]	19	1			T139	1		T140	1		T141	1
all_levels[34]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[35]	auto[0]	25	1			T142	2		T143	1		T140	1
all_levels[35]	auto[1]	1	1			T239	1		-	-		-	-
all_levels[36]	auto[0]	28	1			T131	1		T144	1		T145	1
all_levels[36]	auto[1]	2	1			T199	1		T240	1		-	-
all_levels[37]	auto[0]	14	1			T146	1		T147	1		T125	1
all_levels[37]	auto[1]	1	1			T241	1		-	-		-	-
all_levels[38]	auto[0]	16	1			T136	1		T145	1		T138	1
all_levels[38]	auto[1]	4	1			T138	1		T169	1		T163	1
all_levels[39]	auto[0]	14	1			T48	1		T148	1		T149	1
all_levels[39]	auto[1]	2	1			T148	1		T242	1		-	-
all_levels[40]	auto[0]	21	1			T126	1		T135	1		T150	1
all_levels[40]	auto[1]	5	1			T243	1		T244	4		-	-
all_levels[41]	auto[0]	19	1			T123	1		T120	1		T151	1
all_levels[41]	auto[1]	4	1			T243	1		T245	2		T246	1
all_levels[42]	auto[0]	17	1			T114	1		T115	1		T143	1
all_levels[42]	auto[1]	3	1			T143	1		T247	2		-	-
all_levels[43]	auto[0]	20	1			T152	1		T132	1		T153	1
all_levels[43]	auto[1]	2	1			T152	2		-	-		-	-
all_levels[44]	auto[0]	13	1			T150	1		T154	1		T153	1
all_levels[44]	auto[1]	1	1			T155	1		-	-		-	-
all_levels[45]	auto[0]	14	1			T48	1		T155	1		T125	1
all_levels[45]	auto[1]	2	1			T248	2		-	-		-	-
all_levels[46]	auto[0]	6	1			T7	1		T156	1		T157	1
all_levels[47]	auto[0]	20	1			T158	1		T146	2		T151	1
all_levels[47]	auto[1]	7	1			T215	1		T196	1		T198	1
all_levels[48]	auto[0]	17	1			T102	1		T87	1		T145	1
all_levels[48]	auto[1]	1	1			T145	1		-	-		-	-
all_levels[49]	auto[0]	15	1			T114	1		T159	1		T160	1
all_levels[49]	auto[1]	3	1			T249	1		T250	1		T251	1
all_levels[50]	auto[0]	5	1			T161	1		T162	1		T163	1
all_levels[51]	auto[0]	10	1			T30	1		T159	1		T164	1
all_levels[52]	auto[0]	8	1			T30	1		T145	1		T156	1
all_levels[53]	auto[0]	9	1			T165	1		T166	1		T167	1
all_levels[54]	auto[0]	8	1			T123	1		T159	1		T168	1
all_levels[55]	auto[0]	9	1			T158	1		T169	1		T170	1
all_levels[55]	auto[1]	6	1			T252	3		T253	2		T226	1
all_levels[56]	auto[0]	12	1			T9	1		T21	1		T171	1
all_levels[56]	auto[1]	2	1			T254	1		T255	1		-	-
all_levels[57]	auto[0]	6	1			T172	1		T173	1		T174	1
all_levels[57]	auto[1]	1	1			T256	1		-	-		-	-
all_levels[58]	auto[0]	8	1			T138	1		T175	1		T169	1
all_levels[58]	auto[1]	5	1			T138	2		T175	2		T243	1
all_levels[59]	auto[0]	5	1			T169	1		T176	1		T177	1
all_levels[60]	auto[0]	5	1			T178	1		T179	1		T180	1
all_levels[61]	auto[0]	6	1			T142	1		T181	1		T182	1
all_levels[61]	auto[1]	2	1			T181	1		T257	1		-	-
all_levels[62]	auto[0]	8	1			T117	1		T170	1		T173	1
all_levels[62]	auto[1]	2	1			T258	2		-	-		-	-
all_levels[63]	auto[0]	11	1			T13	1		T123	1		T43	1
all_levels[64]	auto[0]	92	1			T13	1		T14	1		T87	2
all_levels[64]	auto[1]	9	1			T259	1		T141	1		T51	2