Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	107331	1			T1	5		T2	21		T3	54
all_pins[1]	107331	1			T1	5		T2	21		T3	54
all_pins[2]	107331	1			T1	5		T2	21		T3	54
all_pins[3]	107331	1			T1	5		T2	21		T3	54
all_pins[4]	107331	1			T1	5		T2	21		T3	54
all_pins[5]	107331	1			T1	5		T2	21		T3	54
all_pins[6]	107331	1			T1	5		T2	21		T3	54
all_pins[7]	107331	1			T1	5		T2	21		T3	54
all_pins[8]	107331	1			T1	5		T2	21		T3	54

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	921374	1			T1	42		T2	174		T3	476
values[0x1]	44605	1			T1	3		T2	15		T3	10
transitions[0x0=>0x1]	36119	1			T1	3		T2	13		T3	10
transitions[0x1=>0x0]	35945	1			T1	3		T2	13		T3	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84955	1			T1	4		T2	19		T3	54
all_pins[0]	values[0x1]	22376	1			T1	1		T2	2		T7	1
all_pins[0]	transitions[0x0=>0x1]	21764	1			T1	1		T2	2		T7	1
all_pins[0]	transitions[0x1=>0x0]	1019	1			T2	2		T9	15		T16	1
all_pins[1]	values[0x0]	105700	1			T1	5		T2	19		T3	54
all_pins[1]	values[0x1]	1631	1			T2	2		T9	15		T87	4
all_pins[1]	transitions[0x0=>0x1]	1506	1			T2	1		T9	13		T87	4
all_pins[1]	transitions[0x1=>0x0]	2194	1			T1	1		T2	4		T3	1
all_pins[2]	values[0x0]	105012	1			T1	4		T2	16		T3	53
all_pins[2]	values[0x1]	2319	1			T1	1		T2	5		T3	1
all_pins[2]	transitions[0x0=>0x1]	2248	1			T1	1		T2	5		T3	1
all_pins[2]	transitions[0x1=>0x0]	219	1			T8	1		T14	1		T16	3
all_pins[3]	values[0x0]	107041	1			T1	5		T2	21		T3	54
all_pins[3]	values[0x1]	290	1			T8	1		T14	1		T87	1
all_pins[3]	transitions[0x0=>0x1]	257	1			T8	1		T14	1		T87	1
all_pins[3]	transitions[0x1=>0x0]	328	1			T16	3		T17	2		T20	8
all_pins[4]	values[0x0]	106970	1			T1	5		T2	21		T3	54
all_pins[4]	values[0x1]	361	1			T16	5		T17	2		T18	1
all_pins[4]	transitions[0x0=>0x1]	302	1			T16	2		T18	1		T20	6
all_pins[4]	transitions[0x1=>0x0]	135	1			T16	1		T17	4		T31	1
all_pins[5]	values[0x0]	107137	1			T1	5		T2	21		T3	54
all_pins[5]	values[0x1]	194	1			T16	4		T17	6		T20	2
all_pins[5]	transitions[0x0=>0x1]	148	1			T16	3		T17	5		T20	2
all_pins[5]	transitions[0x1=>0x0]	833	1			T7	2		T9	5		T11	12
all_pins[6]	values[0x0]	106452	1			T1	5		T2	21		T3	54
all_pins[6]	values[0x1]	879	1			T7	2		T9	5		T11	12
all_pins[6]	transitions[0x0=>0x1]	833	1			T7	2		T9	5		T11	12
all_pins[6]	transitions[0x1=>0x0]	298	1			T9	6		T88	3		T16	4
all_pins[7]	values[0x0]	106987	1			T1	5		T2	21		T3	54
all_pins[7]	values[0x1]	344	1			T9	6		T88	3		T16	5
all_pins[7]	transitions[0x0=>0x1]	215	1			T9	6		T16	5		T17	1
all_pins[7]	transitions[0x1=>0x0]	16082	1			T1	1		T2	6		T3	9
all_pins[8]	values[0x0]	91120	1			T1	4		T2	15		T3	45
all_pins[8]	values[0x1]	16211	1			T1	1		T2	6		T3	9
all_pins[8]	transitions[0x0=>0x1]	8846	1			T1	1		T2	5		T3	9
all_pins[8]	transitions[0x1=>0x0]	14837	1			T1	1		T2	1		T7	1