Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8008716	1			T1	4571		T2	252		T3	8
all_levels[1]	1875474	1			T1	14		T2	78		T8	7
all_levels[2]	469549	1			T1	11		T2	36		T7	1
all_levels[3]	193816	1			T1	17		T2	2		T3	2
all_levels[4]	296391	1			T1	15		T2	6		T8	4
all_levels[5]	415606	1			T1	14		T3	1		T8	2
all_levels[6]	187298	1			T1	13		T2	12		T8	2
all_levels[7]	247060	1			T1	13		T2	3		T8	2
all_levels[8]	338345	1			T1	13		T2	2		T3	1
all_levels[9]	202120	1			T1	16		T8	4		T9	2
all_levels[10]	305165	1			T1	17		T2	1		T8	2
all_levels[11]	185314	1			T1	17		T8	4		T11	22
all_levels[12]	404022	1			T1	15		T2	2		T8	2
all_levels[13]	251790	1			T1	16		T8	3		T9	2
all_levels[14]	171212	1			T1	16		T2	2		T8	2
all_levels[15]	237759	1			T1	11		T2	13		T8	2
all_levels[16]	275709	1			T1	14		T2	2		T8	14
all_levels[17]	213075	1			T1	12		T2	3		T3	3
all_levels[18]	431002	1			T1	21		T8	2		T9	10
all_levels[19]	228120	1			T1	16		T8	3		T11	3
all_levels[20]	181545	1			T1	17		T3	2		T8	6
all_levels[21]	179853	1			T1	14		T8	3		T9	1
all_levels[22]	159568	1			T1	14		T3	4		T8	2
all_levels[23]	151575	1			T1	16		T8	2		T9	2
all_levels[24]	148032	1			T1	12		T8	2		T12	9
all_levels[25]	196719	1			T1	16		T3	2		T8	2
all_levels[26]	150700	1			T1	13		T8	2		T9	5
all_levels[27]	238907	1			T1	12		T8	2		T9	1
all_levels[28]	142397	1			T1	9		T8	2		T12	3
all_levels[29]	189822	1			T1	15		T8	2		T36	35988
all_levels[30]	229293	1			T1	16		T8	3		T36	2513
all_levels[31]	753926	1			T1	421		T3	2		T8	207
all_levels[32]	10966739	1			T1	32659		T3	5		T7	8

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28622361

1

T1

38086

T2

414

T3

22

auto[1]

4258

1

T3

8

T7

6

T8

5

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8006245	1			T1	4571		T2	252		T3	6
all_levels[0]	auto[1]	2471	1			T3	2		T7	3		T8	5
all_levels[1]	auto[0]	1875176	1			T1	14		T2	78		T8	7
all_levels[1]	auto[1]	298	1			T37	1		T14	1		T274	1
all_levels[2]	auto[0]	469504	1			T1	11		T2	36		T7	1
all_levels[2]	auto[1]	45	1			T260	2		T20	1		T221	2
all_levels[3]	auto[0]	193689	1			T1	17		T2	2		T3	2
all_levels[3]	auto[1]	127	1			T152	1		T119	1		T50	1
all_levels[4]	auto[0]	296368	1			T1	15		T2	6		T8	4
all_levels[4]	auto[1]	23	1			T194	1		T279	1		T148	1
all_levels[5]	auto[0]	415580	1			T1	14		T3	1		T8	2
all_levels[5]	auto[1]	26	1			T223	1		T50	1		T206	1
all_levels[6]	auto[0]	187275	1			T1	13		T2	12		T8	2
all_levels[6]	auto[1]	23	1			T38	1		T165	3		T223	1
all_levels[7]	auto[0]	246945	1			T1	13		T2	3		T8	2
all_levels[7]	auto[1]	115	1			T111	16		T263	1		T182	1
all_levels[8]	auto[0]	338313	1			T1	13		T2	2		T3	1
all_levels[8]	auto[1]	32	1			T259	2		T329	3		T203	1
all_levels[9]	auto[0]	202081	1			T1	16		T8	4		T9	2
all_levels[9]	auto[1]	39	1			T39	3		T150	1		T153	1
all_levels[10]	auto[0]	305128	1			T1	17		T2	1		T8	2
all_levels[10]	auto[1]	37	1			T281	1		T330	2		T329	1
all_levels[11]	auto[0]	185282	1			T1	17		T8	4		T11	22
all_levels[11]	auto[1]	32	1			T120	2		T134	5		T298	3
all_levels[12]	auto[0]	403992	1			T1	15		T2	2		T8	2
all_levels[12]	auto[1]	30	1			T35	1		T154	1		T206	1
all_levels[13]	auto[0]	251762	1			T1	16		T8	3		T9	2
all_levels[13]	auto[1]	28	1			T268	2		T138	1		T143	1
all_levels[14]	auto[0]	171185	1			T1	16		T2	2		T8	2
all_levels[14]	auto[1]	27	1			T138	1		T197	1		T331	2
all_levels[15]	auto[0]	237692	1			T1	11		T2	13		T8	2
all_levels[15]	auto[1]	67	1			T263	8		T194	1		T232	1
all_levels[16]	auto[0]	275688	1			T1	14		T2	2		T8	14
all_levels[16]	auto[1]	21	1			T13	1		T144	3		T132	2
all_levels[17]	auto[0]	213045	1			T1	12		T2	3		T3	3
all_levels[17]	auto[1]	30	1			T11	1		T118	1		T268	1
all_levels[18]	auto[0]	430990	1			T1	21		T8	2		T9	10
all_levels[18]	auto[1]	12	1			T332	2		T333	1		T334	1
all_levels[19]	auto[0]	228099	1			T1	16		T8	3		T11	3
all_levels[19]	auto[1]	21	1			T31	3		T145	1		T139	1
all_levels[20]	auto[0]	181529	1			T1	17		T3	2		T8	6
all_levels[20]	auto[1]	16	1			T88	1		T206	1		T335	1
all_levels[21]	auto[0]	179827	1			T1	14		T8	3		T9	1
all_levels[21]	auto[1]	26	1			T311	2		T301	1		T203	2
all_levels[22]	auto[0]	159553	1			T1	14		T3	2		T8	2
all_levels[22]	auto[1]	15	1			T3	2		T309	3		T336	2
all_levels[23]	auto[0]	151563	1			T1	16		T8	2		T9	2
all_levels[23]	auto[1]	12	1			T123	1		T206	1		T337	2
all_levels[24]	auto[0]	148021	1			T1	12		T8	2		T12	9
all_levels[24]	auto[1]	11	1			T310	1		T338	1		T203	1
all_levels[25]	auto[0]	196697	1			T1	16		T3	2		T8	2
all_levels[25]	auto[1]	22	1			T30	2		T194	3		T145	2
all_levels[26]	auto[0]	150685	1			T1	13		T8	2		T9	5
all_levels[26]	auto[1]	15	1			T339	1		T340	3		T215	1
all_levels[27]	auto[0]	238882	1			T1	12		T8	2		T9	1
all_levels[27]	auto[1]	25	1			T183	2		T323	1		T212	1
all_levels[28]	auto[0]	142383	1			T1	9		T8	2		T12	3
all_levels[28]	auto[1]	14	1			T341	2		T51	1		T342	1
all_levels[29]	auto[0]	189811	1			T1	15		T8	2		T36	35988
all_levels[29]	auto[1]	11	1			T119	2		T308	1		T335	1
all_levels[30]	auto[0]	229268	1			T1	16		T8	3		T36	2513
all_levels[30]	auto[1]	25	1			T103	1		T24	1		T87	1
all_levels[31]	auto[0]	753906	1			T1	421		T3	2		T8	207
all_levels[31]	auto[1]	20	1			T20	1		T197	1		T343	1
all_levels[32]	auto[0]	10966197	1			T1	32659		T3	1		T7	5
all_levels[32]	auto[1]	542	1			T3	4		T7	3		T9	1