Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	677	1			T16	11		T17	15		T18	4
all_values[1]	677	1			T16	11		T17	15		T18	4
all_values[2]	677	1			T16	11		T17	15		T18	4
all_values[3]	677	1			T16	11		T17	15		T18	4
all_values[4]	677	1			T16	11		T17	15		T18	4
all_values[5]	677	1			T16	11		T17	15		T18	4
all_values[6]	677	1			T16	11		T17	15		T18	4
all_values[7]	677	1			T16	11		T17	15		T18	4
all_values[8]	677	1			T16	11		T17	15		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3252

1

T16

52

T17

66

T18

11

auto[1]

2841

1

T16

47

T17

69

T18

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1979

1

T16

31

T17

52

T18

7

auto[1]

4114

1

T16

68

T17

83

T18

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3606

1

T16

60

T17

83

T18

23

auto[1]

2487

1

T16

39

T17

52

T18

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	220	1			T16	5		T17	7		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	186	1			T16	3		T17	2		T20	5
all_values[0]	auto[1]	auto[0]	auto[1]	153	1			T16	2		T17	3		T126	2
all_values[0]	auto[1]	auto[1]	auto[1]	118	1			T16	1		T17	3		T18	2
all_values[1]	auto[0]	auto[0]	auto[0]	211	1			T16	7		T17	5		T20	2
all_values[1]	auto[0]	auto[1]	auto[0]	193	1			T16	3		T17	4		T18	4
all_values[1]	auto[1]	auto[0]	auto[1]	149	1			T16	1		T17	4		T32	2
all_values[1]	auto[1]	auto[1]	auto[1]	124	1			T17	2		T20	1		T126	1
all_values[2]	auto[0]	auto[0]	auto[0]	146	1			T16	2		T17	3		T20	2
all_values[2]	auto[0]	auto[0]	auto[1]	58	1			T16	2		T18	1		T115	1
all_values[2]	auto[0]	auto[1]	auto[0]	121	1			T16	1		T17	5		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	68	1			T16	1		T17	1		T20	3
all_values[2]	auto[1]	auto[0]	auto[1]	134	1			T16	2		T17	2		T126	1
all_values[2]	auto[1]	auto[1]	auto[1]	150	1			T16	3		T17	4		T18	3
all_values[3]	auto[0]	auto[0]	auto[0]	144	1			T16	2		T17	6		T20	1
all_values[3]	auto[0]	auto[0]	auto[1]	65	1			T17	1		T18	1		T115	2
all_values[3]	auto[0]	auto[1]	auto[0]	104	1			T16	3		T17	2		T20	1
all_values[3]	auto[0]	auto[1]	auto[1]	73	1			T16	3		T18	1		T33	1
all_values[3]	auto[1]	auto[0]	auto[1]	159	1			T16	3		T17	3		T20	3
all_values[3]	auto[1]	auto[1]	auto[1]	132	1			T17	3		T18	2		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	151	1			T17	4		T31	2		T115	1
all_values[4]	auto[0]	auto[0]	auto[1]	60	1			T16	1		T18	1		T33	1
all_values[4]	auto[0]	auto[1]	auto[0]	123	1			T16	3		T17	5		T20	1
all_values[4]	auto[0]	auto[1]	auto[1]	68	1			T16	2		T17	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	139	1			T16	2		T17	3		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	136	1			T16	3		T17	2		T18	1
all_values[5]	auto[0]	auto[0]	auto[0]	144	1			T16	1		T17	1		T20	2
all_values[5]	auto[0]	auto[0]	auto[1]	63	1			T16	2		T17	3		T18	1
all_values[5]	auto[0]	auto[1]	auto[0]	136	1			T16	4		T17	2		T18	2
all_values[5]	auto[0]	auto[1]	auto[1]	60	1			T16	1		T17	2		T20	1
all_values[5]	auto[1]	auto[0]	auto[1]	141	1			T17	2		T20	2		T126	2
all_values[5]	auto[1]	auto[1]	auto[1]	133	1			T16	3		T17	5		T18	1
all_values[6]	auto[0]	auto[0]	auto[0]	134	1			T16	3		T31	3		T115	2
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T16	1		T17	1		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	97	1			T16	1		T17	6		T20	1
all_values[6]	auto[0]	auto[1]	auto[1]	72	1			T17	2		T18	2		T31	1
all_values[6]	auto[1]	auto[0]	auto[1]	153	1			T16	3		T17	6		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T16	3		T18	1		T20	1
all_values[7]	auto[0]	auto[0]	auto[0]	157	1			T16	1		T17	4		T20	2
all_values[7]	auto[0]	auto[0]	auto[1]	61	1			T16	2		T18	1		T31	1
all_values[7]	auto[0]	auto[1]	auto[0]	118	1			T17	5		T18	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[1]	68	1			T16	2		T17	2		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	153	1			T16	3		T17	1		T20	3
all_values[7]	auto[1]	auto[1]	auto[1]	120	1			T16	3		T17	3		T18	1
all_values[8]	auto[0]	auto[0]	auto[1]	230	1			T16	2		T17	4		T18	2
all_values[8]	auto[0]	auto[1]	auto[1]	197	1			T16	2		T17	5		T18	2
all_values[8]	auto[1]	auto[0]	auto[1]	149	1			T16	5		T17	3		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	101	1			T16	2		T17	3		T126	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal