| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 99.11 | 99.10 | 97.65 | 100.00 | 98.38 | 100.00 | 99.55 |
| T1252 | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2023754192 | Aug 01 04:52:57 PM PDT 24 | Aug 01 04:52:58 PM PDT 24 | 27170272 ps | ||
| T1253 | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3559421266 | Aug 01 04:53:09 PM PDT 24 | Aug 01 04:53:10 PM PDT 24 | 207970783 ps | ||
| T1254 | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3055869765 | Aug 01 04:52:46 PM PDT 24 | Aug 01 04:52:47 PM PDT 24 | 82761473 ps | ||
| T1255 | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2338970041 | Aug 01 04:53:39 PM PDT 24 | Aug 01 04:53:40 PM PDT 24 | 31119488 ps | ||
| T1256 | /workspace/coverage/cover_reg_top/0.uart_csr_rw.2388473774 | Aug 01 04:52:30 PM PDT 24 | Aug 01 04:52:31 PM PDT 24 | 65292756 ps | ||
| T1257 | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2959212014 | Aug 01 04:53:36 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 117493111 ps | ||
| T1258 | /workspace/coverage/cover_reg_top/33.uart_intr_test.702659272 | Aug 01 04:53:49 PM PDT 24 | Aug 01 04:53:50 PM PDT 24 | 14476289 ps | ||
| T1259 | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.527510140 | Aug 01 04:53:11 PM PDT 24 | Aug 01 04:53:12 PM PDT 24 | 90405460 ps | ||
| T1260 | /workspace/coverage/cover_reg_top/17.uart_intr_test.4139655310 | Aug 01 04:53:39 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 39002881 ps | ||
| T1261 | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1218308622 | Aug 01 04:53:25 PM PDT 24 | Aug 01 04:53:26 PM PDT 24 | 101138398 ps | ||
| T68 | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3006413779 | Aug 01 04:52:44 PM PDT 24 | Aug 01 04:52:45 PM PDT 24 | 13813089 ps | ||
| T1262 | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4290320660 | Aug 01 04:53:37 PM PDT 24 | Aug 01 04:53:38 PM PDT 24 | 285270702 ps | ||
| T1263 | /workspace/coverage/cover_reg_top/12.uart_csr_rw.1131145963 | Aug 01 04:53:22 PM PDT 24 | Aug 01 04:53:23 PM PDT 24 | 13364136 ps | ||
| T1264 | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3062228258 | Aug 01 04:53:24 PM PDT 24 | Aug 01 04:53:25 PM PDT 24 | 63668475 ps | ||
| T1265 | /workspace/coverage/cover_reg_top/0.uart_intr_test.3894975056 | Aug 01 04:52:31 PM PDT 24 | Aug 01 04:52:32 PM PDT 24 | 84524932 ps | ||
| T1266 | /workspace/coverage/cover_reg_top/18.uart_csr_rw.1178378286 | Aug 01 04:53:38 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 11288178 ps | ||
| T1267 | /workspace/coverage/cover_reg_top/1.uart_intr_test.3884977917 | Aug 01 04:52:32 PM PDT 24 | Aug 01 04:52:33 PM PDT 24 | 28456735 ps | ||
| T1268 | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4261857342 | Aug 01 04:52:33 PM PDT 24 | Aug 01 04:52:34 PM PDT 24 | 115783911 ps | ||
| T1269 | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.417219519 | Aug 01 04:52:43 PM PDT 24 | Aug 01 04:52:44 PM PDT 24 | 61983457 ps | ||
| T1270 | /workspace/coverage/cover_reg_top/3.uart_tl_errors.867259324 | Aug 01 04:52:44 PM PDT 24 | Aug 01 04:52:46 PM PDT 24 | 75975727 ps | ||
| T1271 | /workspace/coverage/cover_reg_top/41.uart_intr_test.3407896758 | Aug 01 04:53:50 PM PDT 24 | Aug 01 04:53:51 PM PDT 24 | 15372145 ps | ||
| T1272 | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2259610748 | Aug 01 04:52:57 PM PDT 24 | Aug 01 04:52:58 PM PDT 24 | 45478894 ps | ||
| T1273 | /workspace/coverage/cover_reg_top/3.uart_intr_test.4149924654 | Aug 01 04:52:57 PM PDT 24 | Aug 01 04:52:58 PM PDT 24 | 12439551 ps | ||
| T1274 | /workspace/coverage/cover_reg_top/30.uart_intr_test.1201411816 | Aug 01 04:53:49 PM PDT 24 | Aug 01 04:53:50 PM PDT 24 | 15003460 ps | ||
| T1275 | /workspace/coverage/cover_reg_top/21.uart_intr_test.2751100934 | Aug 01 04:53:50 PM PDT 24 | Aug 01 04:53:51 PM PDT 24 | 14131955 ps | ||
| T1276 | /workspace/coverage/cover_reg_top/44.uart_intr_test.1193197466 | Aug 01 04:53:49 PM PDT 24 | Aug 01 04:53:50 PM PDT 24 | 49810872 ps | ||
| T1277 | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.768788623 | Aug 01 04:53:24 PM PDT 24 | Aug 01 04:53:25 PM PDT 24 | 65823450 ps | ||
| T1278 | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3492564122 | Aug 01 04:53:07 PM PDT 24 | Aug 01 04:53:08 PM PDT 24 | 43822959 ps | ||
| T1279 | /workspace/coverage/cover_reg_top/7.uart_tl_errors.3734391745 | Aug 01 04:53:10 PM PDT 24 | Aug 01 04:53:12 PM PDT 24 | 340114436 ps | ||
| T1280 | /workspace/coverage/cover_reg_top/2.uart_csr_rw.2965018885 | Aug 01 04:52:45 PM PDT 24 | Aug 01 04:52:46 PM PDT 24 | 104667961 ps | ||
| T1281 | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2913522008 | Aug 01 04:52:57 PM PDT 24 | Aug 01 04:52:57 PM PDT 24 | 15154461 ps | ||
| T1282 | /workspace/coverage/cover_reg_top/37.uart_intr_test.2336962280 | Aug 01 04:53:51 PM PDT 24 | Aug 01 04:53:52 PM PDT 24 | 156557837 ps | ||
| T1283 | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.87402639 | Aug 01 04:53:19 PM PDT 24 | Aug 01 04:53:19 PM PDT 24 | 13501945 ps | ||
| T1284 | /workspace/coverage/cover_reg_top/38.uart_intr_test.153236663 | Aug 01 04:53:50 PM PDT 24 | Aug 01 04:53:51 PM PDT 24 | 34517678 ps | ||
| T1285 | /workspace/coverage/cover_reg_top/22.uart_intr_test.53355270 | Aug 01 04:53:50 PM PDT 24 | Aug 01 04:53:51 PM PDT 24 | 34521039 ps | ||
| T1286 | /workspace/coverage/cover_reg_top/18.uart_tl_errors.2793391429 | Aug 01 04:53:38 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 54398839 ps | ||
| T1287 | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1504559382 | Aug 01 04:53:39 PM PDT 24 | Aug 01 04:53:40 PM PDT 24 | 55066757 ps | ||
| T1288 | /workspace/coverage/cover_reg_top/31.uart_intr_test.4792834 | Aug 01 04:53:49 PM PDT 24 | Aug 01 04:53:49 PM PDT 24 | 51728639 ps | ||
| T1289 | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3184653278 | Aug 01 04:53:38 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 70196423 ps | ||
| T1290 | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.508348099 | Aug 01 04:52:31 PM PDT 24 | Aug 01 04:52:33 PM PDT 24 | 134236301 ps | ||
| T1291 | /workspace/coverage/cover_reg_top/47.uart_intr_test.1793608617 | Aug 01 04:54:06 PM PDT 24 | Aug 01 04:54:07 PM PDT 24 | 10844088 ps | ||
| T1292 | /workspace/coverage/cover_reg_top/14.uart_csr_rw.1910695848 | Aug 01 04:53:38 PM PDT 24 | Aug 01 04:53:38 PM PDT 24 | 16742662 ps | ||
| T1293 | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3787501322 | Aug 01 04:52:45 PM PDT 24 | Aug 01 04:52:46 PM PDT 24 | 75105441 ps | ||
| T1294 | /workspace/coverage/cover_reg_top/9.uart_intr_test.923681001 | Aug 01 04:53:10 PM PDT 24 | Aug 01 04:53:10 PM PDT 24 | 17426787 ps | ||
| T1295 | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1318127198 | Aug 01 04:53:38 PM PDT 24 | Aug 01 04:53:39 PM PDT 24 | 121927135 ps | ||
| T1296 | /workspace/coverage/cover_reg_top/17.uart_tl_errors.1664686921 | Aug 01 04:53:39 PM PDT 24 | Aug 01 04:53:41 PM PDT 24 | 80286306 ps | ||
| T1297 | /workspace/coverage/cover_reg_top/16.uart_csr_rw.3887724323 | Aug 01 04:53:36 PM PDT 24 | Aug 01 04:53:37 PM PDT 24 | 25874339 ps | ||
| T1298 | /workspace/coverage/cover_reg_top/42.uart_intr_test.70515572 | Aug 01 04:53:48 PM PDT 24 | Aug 01 04:53:49 PM PDT 24 | 36585342 ps | ||
| T1299 | /workspace/coverage/cover_reg_top/0.uart_tl_errors.2400546393 | Aug 01 04:52:21 PM PDT 24 | Aug 01 04:52:23 PM PDT 24 | 132021825 ps | ||
| T1300 | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2970488678 | Aug 01 04:53:36 PM PDT 24 | Aug 01 04:53:37 PM PDT 24 | 34128370 ps | ||
| T1301 | /workspace/coverage/cover_reg_top/39.uart_intr_test.3051467449 | Aug 01 04:53:50 PM PDT 24 | Aug 01 04:53:51 PM PDT 24 | 27238841 ps | ||
| T1302 | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.274039727 | Aug 01 04:52:56 PM PDT 24 | Aug 01 04:52:57 PM PDT 24 | 22946396 ps | ||
| T1303 | /workspace/coverage/cover_reg_top/5.uart_csr_rw.247830866 | Aug 01 04:53:09 PM PDT 24 | Aug 01 04:53:10 PM PDT 24 | 12256040 ps | ||
| T1304 | /workspace/coverage/cover_reg_top/1.uart_tl_errors.2805328308 | Aug 01 04:52:32 PM PDT 24 | Aug 01 04:52:33 PM PDT 24 | 38221319 ps | ||
| T1305 | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3875378866 | Aug 01 04:53:09 PM PDT 24 | Aug 01 04:53:10 PM PDT 24 | 210959771 ps | ||
| T1306 | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1951302365 | Aug 01 04:52:59 PM PDT 24 | Aug 01 04:53:00 PM PDT 24 | 20843736 ps | ||
| T1307 | /workspace/coverage/cover_reg_top/45.uart_intr_test.1952549407 | Aug 01 04:53:53 PM PDT 24 | Aug 01 04:53:53 PM PDT 24 | 44847443 ps | ||
| T1308 | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3220399341 | Aug 01 04:52:31 PM PDT 24 | Aug 01 04:52:31 PM PDT 24 | 40803258 ps | ||
| T1309 | /workspace/coverage/cover_reg_top/11.uart_intr_test.3657773488 | Aug 01 04:53:24 PM PDT 24 | Aug 01 04:53:24 PM PDT 24 | 23311923 ps | ||
| T1310 | /workspace/coverage/cover_reg_top/9.uart_tl_errors.3871096728 | Aug 01 04:53:10 PM PDT 24 | Aug 01 04:53:11 PM PDT 24 | 44233290 ps | ||
| T1311 | /workspace/coverage/cover_reg_top/13.uart_intr_test.3674829890 | Aug 01 04:53:24 PM PDT 24 | Aug 01 04:53:24 PM PDT 24 | 123245258 ps | ||
| T1312 | /workspace/coverage/cover_reg_top/5.uart_intr_test.1176381260 | Aug 01 04:52:59 PM PDT 24 | Aug 01 04:52:59 PM PDT 24 | 28693133 ps | ||
| T1313 | /workspace/coverage/cover_reg_top/6.uart_tl_errors.3541196792 | Aug 01 04:53:08 PM PDT 24 | Aug 01 04:53:10 PM PDT 24 | 22442755 ps | ||
| T1314 | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3285160313 | Aug 01 04:53:24 PM PDT 24 | Aug 01 04:53:25 PM PDT 24 | 61184391 ps | ||
| T1315 | /workspace/coverage/cover_reg_top/23.uart_intr_test.2541294237 | Aug 01 04:53:49 PM PDT 24 | Aug 01 04:53:50 PM PDT 24 | 19279033 ps |
| Test location | /workspace/coverage/default/68.uart_stress_all_with_rand_reset.1712436496 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 17235569546 ps |
| CPU time | 205.04 seconds |
| Started | Aug 01 05:01:28 PM PDT 24 |
| Finished | Aug 01 05:04:53 PM PDT 24 |
| Peak memory | 215344 kb |
| Host | smart-3d599499-c6d4-49ea-a721-3336c34018e8 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712436496 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.1712436496 |
| Directory | /workspace/68.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all.3640121418 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 226481891518 ps |
| CPU time | 555.76 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:09:38 PM PDT 24 |
| Peak memory | 216324 kb |
| Host | smart-049d641e-c84a-4fdf-a4e3-390b13ea9696 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640121418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.3640121418 |
| Directory | /workspace/43.uart_stress_all/latest |
| Test location | /workspace/coverage/default/99.uart_stress_all_with_rand_reset.1774921485 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 295183128664 ps |
| CPU time | 1206.72 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:22:10 PM PDT 24 |
| Peak memory | 230776 kb |
| Host | smart-dfbfd301-69ab-4cde-86ea-01d4500a9b31 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774921485 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.1774921485 |
| Directory | /workspace/99.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_stress_all_with_rand_reset.705065926 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 294087151408 ps |
| CPU time | 1345.63 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:24:16 PM PDT 24 |
| Peak memory | 224640 kb |
| Host | smart-f02a6bbc-0419-434d-9e16-0909e08cbb0a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705065926 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.705065926 |
| Directory | /workspace/85.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_stress_all_with_rand_reset.303401818 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 148981332652 ps |
| CPU time | 544.49 seconds |
| Started | Aug 01 05:01:53 PM PDT 24 |
| Finished | Aug 01 05:10:57 PM PDT 24 |
| Peak memory | 224592 kb |
| Host | smart-d0538937-799d-48d7-9490-2f10eb13afdd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303401818 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.303401818 |
| Directory | /workspace/92.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_stress_all_with_rand_reset.4007388491 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 85680937965 ps |
| CPU time | 1045.06 seconds |
| Started | Aug 01 05:01:39 PM PDT 24 |
| Finished | Aug 01 05:19:05 PM PDT 24 |
| Peak memory | 225676 kb |
| Host | smart-dd294744-3f5c-4894-9833-f4fab64d4c0c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007388491 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.4007388491 |
| Directory | /workspace/77.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/21.uart_long_xfer_wo_dly.2453945033 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 113463331805 ps |
| CPU time | 505.82 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 05:05:38 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-7ffdc37d-1190-4e50-ac1d-9599298a9fc2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2453945033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2453945033 |
| Directory | /workspace/21.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_overflow.2392430400 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 181031704115 ps |
| CPU time | 230.69 seconds |
| Started | Aug 01 04:55:20 PM PDT 24 |
| Finished | Aug 01 04:59:11 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-da30bc9f-3e67-489e-abe2-b9434daff7a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2392430400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2392430400 |
| Directory | /workspace/6.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_sec_cm.742026146 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 182792567 ps |
| CPU time | 0.75 seconds |
| Started | Aug 01 04:54:56 PM PDT 24 |
| Finished | Aug 01 04:54:57 PM PDT 24 |
| Peak memory | 218108 kb |
| Host | smart-d0529238-cc62-4944-bb79-1220897f2798 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742026146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.742026146 |
| Directory | /workspace/0.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all.1982661543 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 238740231937 ps |
| CPU time | 142.98 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:03:32 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-dc0772d3-3998-46b8-a72a-3f7a994019eb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982661543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.1982661543 |
| Directory | /workspace/48.uart_stress_all/latest |
| Test location | /workspace/coverage/default/293.uart_fifo_reset.649636348 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 166270420509 ps |
| CPU time | 65.27 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:05:28 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-8df79fb8-ad36-49a4-a02c-7fa7232b4427 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=649636348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.649636348 |
| Directory | /workspace/293.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_reset.3161717490 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 175718942798 ps |
| CPU time | 303.06 seconds |
| Started | Aug 01 04:55:49 PM PDT 24 |
| Finished | Aug 01 05:00:53 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-5d9315af-35ed-4265-a478-a7ecac8db396 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161717490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.3161717490 |
| Directory | /workspace/10.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/52.uart_stress_all_with_rand_reset.3086683459 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 193258360860 ps |
| CPU time | 799.3 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:14:27 PM PDT 24 |
| Peak memory | 224680 kb |
| Host | smart-830e4078-6e04-40f9-8a18-2eeb5a269242 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086683459 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.3086683459 |
| Directory | /workspace/52.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all_with_rand_reset.1619690199 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 23546178948 ps |
| CPU time | 367.67 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 05:01:52 PM PDT 24 |
| Peak memory | 212264 kb |
| Host | smart-cdb710db-cc7b-48b4-b942-ec400cdaaadd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619690199 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.1619690199 |
| Directory | /workspace/10.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_overflow.1242239459 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 217322805057 ps |
| CPU time | 54.82 seconds |
| Started | Aug 01 04:57:02 PM PDT 24 |
| Finished | Aug 01 04:57:57 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-abbea9c2-64a1-4f5f-a759-0b419da1dcf8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1242239459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.1242239459 |
| Directory | /workspace/20.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all_with_rand_reset.1945649474 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 172289774373 ps |
| CPU time | 614.93 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 05:09:23 PM PDT 24 |
| Peak memory | 224692 kb |
| Host | smart-1871e8a1-d0cb-40f1-9559-052f7737c6ae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945649474 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.1945649474 |
| Directory | /workspace/35.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/61.uart_stress_all_with_rand_reset.4221429180 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 82007965452 ps |
| CPU time | 267.29 seconds |
| Started | Aug 01 05:01:18 PM PDT 24 |
| Finished | Aug 01 05:05:45 PM PDT 24 |
| Peak memory | 216500 kb |
| Host | smart-068a845f-6fca-470f-8f78-6a997a39908a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221429180 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.4221429180 |
| Directory | /workspace/61.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_rw.3920519892 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 15178772 ps |
| CPU time | 0.66 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-60d8bcc5-286b-4e67-88e0-08184dab2552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920519892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.3920519892 |
| Directory | /workspace/9.uart_csr_rw/latest |
| Test location | /workspace/coverage/default/276.uart_fifo_reset.2486497685 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 29038116295 ps |
| CPU time | 17.12 seconds |
| Started | Aug 01 05:04:21 PM PDT 24 |
| Finished | Aug 01 05:04:38 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-ebbed2d2-24dd-4c4c-9507-648e4e93d8a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2486497685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2486497685 |
| Directory | /workspace/276.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/142.uart_fifo_reset.859395229 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 232483679166 ps |
| CPU time | 79.8 seconds |
| Started | Aug 01 05:02:40 PM PDT 24 |
| Finished | Aug 01 05:04:00 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-71543222-8505-43ee-92a7-9ffdf4152da2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=859395229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.859395229 |
| Directory | /workspace/142.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2521565357 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 94595601 ps |
| CPU time | 1.34 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-4eeefbbd-d368-44c5-b6d5-0677d984b2ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521565357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2521565357 |
| Directory | /workspace/1.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/29.uart_long_xfer_wo_dly.4239259341 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 76943635113 ps |
| CPU time | 149.39 seconds |
| Started | Aug 01 04:58:26 PM PDT 24 |
| Finished | Aug 01 05:00:56 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-674ec359-9da7-48a9-bbbf-ab85a417f0b0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4239259341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4239259341 |
| Directory | /workspace/29.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all.3552473714 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 238021586817 ps |
| CPU time | 100.98 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:57:03 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-5b2bd769-b6e4-4307-9b34-9fd1f5d18cef |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552473714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.3552473714 |
| Directory | /workspace/6.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_noise_filter.1881431070 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 347752437392 ps |
| CPU time | 105.42 seconds |
| Started | Aug 01 04:58:24 PM PDT 24 |
| Finished | Aug 01 05:00:10 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-fd31b828-96e7-454c-ad66-647458ff7840 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1881431070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1881431070 |
| Directory | /workspace/30.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_alert_test.3639403128 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 18294470 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:55:55 PM PDT 24 |
| Peak memory | 194712 kb |
| Host | smart-a8e9faa2-f4ea-45df-b0ba-252c0dde11a9 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639403128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3639403128 |
| Directory | /workspace/11.uart_alert_test/latest |
| Test location | /workspace/coverage/default/158.uart_fifo_reset.3346480644 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 245303735035 ps |
| CPU time | 50.91 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:43 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-062bbf85-83c9-411a-bed1-500ec6cfc5e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3346480644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.3346480644 |
| Directory | /workspace/158.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all.3468477181 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 388668043189 ps |
| CPU time | 534.22 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:08:48 PM PDT 24 |
| Peak memory | 216096 kb |
| Host | smart-34e2b7a6-46bb-4a08-9342-00ad5ce1ddcc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468477181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.3468477181 |
| Directory | /workspace/40.uart_stress_all/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all.3090271863 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 39098483431 ps |
| CPU time | 353.55 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:06:29 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-70e8f093-f845-4b0c-ab99-f049e76712e6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090271863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.3090271863 |
| Directory | /workspace/44.uart_stress_all/latest |
| Test location | /workspace/coverage/default/138.uart_fifo_reset.1631190479 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 55100513411 ps |
| CPU time | 117.31 seconds |
| Started | Aug 01 05:02:42 PM PDT 24 |
| Finished | Aug 01 05:04:39 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-70ac63ed-6872-4d3b-81d3-ae4c554c4cf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1631190479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.1631190479 |
| Directory | /workspace/138.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2807301235 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 271110120280 ps |
| CPU time | 615.98 seconds |
| Started | Aug 01 05:01:00 PM PDT 24 |
| Finished | Aug 01 05:11:16 PM PDT 24 |
| Peak memory | 216360 kb |
| Host | smart-899f7bb8-045c-4c4b-8b39-f128be1d2dae |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807301235 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2807301235 |
| Directory | /workspace/47.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all.2165009153 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 380109297744 ps |
| CPU time | 280.53 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:59:53 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-368ee308-d91b-476e-8ae8-c5b763863d4f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165009153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2165009153 |
| Directory | /workspace/3.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all_with_rand_reset.769209335 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 238504431633 ps |
| CPU time | 979.05 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 05:11:31 PM PDT 24 |
| Peak memory | 216420 kb |
| Host | smart-0c984899-1939-434d-9db2-ac510cb5aed4 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769209335 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.769209335 |
| Directory | /workspace/4.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1006452223 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 160926089 ps |
| CPU time | 1.41 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:40 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-847c83c6-68a3-4307-bee8-0159f17aeb15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006452223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1006452223 |
| Directory | /workspace/18.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/248.uart_fifo_reset.3329394467 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 48618402917 ps |
| CPU time | 76.3 seconds |
| Started | Aug 01 05:03:58 PM PDT 24 |
| Finished | Aug 01 05:05:15 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-4b3014a0-0d07-4f2c-a8b1-cf59899c03ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3329394467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3329394467 |
| Directory | /workspace/248.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/174.uart_fifo_reset.2952155569 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 100025653487 ps |
| CPU time | 61.14 seconds |
| Started | Aug 01 05:03:03 PM PDT 24 |
| Finished | Aug 01 05:04:04 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-bd54ab65-e51c-48ff-ac23-20991177d4bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2952155569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2952155569 |
| Directory | /workspace/174.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all.3520084369 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 75578160896 ps |
| CPU time | 481.59 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 05:07:33 PM PDT 24 |
| Peak memory | 208116 kb |
| Host | smart-842f252d-0f6b-48a3-befb-da32ff06aaeb |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520084369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3520084369 |
| Directory | /workspace/37.uart_stress_all/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_full.639030294 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 164108423366 ps |
| CPU time | 25.92 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:55:40 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-2a101e9f-8608-4b05-832f-519e350ee74e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=639030294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.639030294 |
| Directory | /workspace/5.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all.2770477199 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 258702886098 ps |
| CPU time | 113.81 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 215384 kb |
| Host | smart-cfd31532-08ad-4294-90a7-9b5a2c0a5896 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770477199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.2770477199 |
| Directory | /workspace/16.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_full.3671723431 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 138399454375 ps |
| CPU time | 755.83 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:12:43 PM PDT 24 |
| Peak memory | 200032 kb |
| Host | smart-53419d37-62aa-46f0-83e0-fdfe1b0f9bfd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3671723431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3671723431 |
| Directory | /workspace/42.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/98.uart_fifo_reset.2676840629 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 77515866089 ps |
| CPU time | 32.89 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:02:36 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-7c39459b-20b5-4ebd-b64f-2c48b9c97a59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2676840629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.2676840629 |
| Directory | /workspace/98.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/223.uart_fifo_reset.2560737994 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 34660634205 ps |
| CPU time | 13.97 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:03:51 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-1d526990-06cc-43b9-ab6c-2603bf64977d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2560737994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.2560737994 |
| Directory | /workspace/223.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all.3508683350 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 362119801245 ps |
| CPU time | 245.89 seconds |
| Started | Aug 01 04:59:40 PM PDT 24 |
| Finished | Aug 01 05:03:46 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-ee5cb7ef-78df-4cd0-8738-801d4593f464 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508683350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3508683350 |
| Directory | /workspace/39.uart_stress_all/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all.230151619 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 336917375526 ps |
| CPU time | 1519.26 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:25:27 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-bc620921-eac7-4cb3-b6e0-d1501dccfb49 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230151619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.230151619 |
| Directory | /workspace/41.uart_stress_all/latest |
| Test location | /workspace/coverage/default/16.uart_perf.948519859 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 18623985929 ps |
| CPU time | 621.8 seconds |
| Started | Aug 01 04:56:29 PM PDT 24 |
| Finished | Aug 01 05:06:51 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-8fded788-3b6d-4003-a889-ce1ac9d705a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=948519859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.948519859 |
| Directory | /workspace/16.uart_perf/latest |
| Test location | /workspace/coverage/default/288.uart_fifo_reset.1660055104 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 46336192736 ps |
| CPU time | 38.68 seconds |
| Started | Aug 01 05:04:25 PM PDT 24 |
| Finished | Aug 01 05:05:03 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-6e9f3960-a6f9-4b78-9701-36e2ba090f59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1660055104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.1660055104 |
| Directory | /workspace/288.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_reset.3962285943 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 38072473020 ps |
| CPU time | 25.08 seconds |
| Started | Aug 01 05:00:05 PM PDT 24 |
| Finished | Aug 01 05:00:32 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-bdb9338c-1afd-4527-85de-59b159acc197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962285943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3962285943 |
| Directory | /workspace/43.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_overflow.3997421095 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 70047566801 ps |
| CPU time | 48.6 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:57:19 PM PDT 24 |
| Peak memory | 199508 kb |
| Host | smart-231306df-81a3-4446-98b1-86dca0f201c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3997421095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.3997421095 |
| Directory | /workspace/17.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/193.uart_fifo_reset.952865324 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 16421677799 ps |
| CPU time | 21.7 seconds |
| Started | Aug 01 05:03:15 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-77a58191-e77e-48f6-9f8d-4ab48e1ade5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952865324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.952865324 |
| Directory | /workspace/193.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all.80935806 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 591484412120 ps |
| CPU time | 316.68 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 05:03:51 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-8fee007f-8874-4907-9d3a-4e0e59da9995 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80935806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.80935806 |
| Directory | /workspace/31.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_tx_rx.1880758687 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 24862653184 ps |
| CPU time | 22.63 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:00:57 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-5c3c2a44-233c-4768-9ba7-998b9d598a56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1880758687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1880758687 |
| Directory | /workspace/45.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/66.uart_fifo_reset.2502565253 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 51299165916 ps |
| CPU time | 49.05 seconds |
| Started | Aug 01 05:01:34 PM PDT 24 |
| Finished | Aug 01 05:02:24 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-a0215018-9d51-4807-be7d-2d48b731bfca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2502565253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.2502565253 |
| Directory | /workspace/66.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_rx.3807750851 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 37230105642 ps |
| CPU time | 23.72 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:25 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-16a38315-d37f-403a-b0a7-d619c093185f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807750851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.3807750851 |
| Directory | /workspace/1.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/111.uart_fifo_reset.2677669194 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 126515208466 ps |
| CPU time | 30.02 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:02:44 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-ce2adef5-7a80-4dcc-9852-b24e84e4ef11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677669194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.2677669194 |
| Directory | /workspace/111.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/119.uart_fifo_reset.2610423787 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 36985024358 ps |
| CPU time | 65.73 seconds |
| Started | Aug 01 05:02:25 PM PDT 24 |
| Finished | Aug 01 05:03:31 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-8d88c07c-78a4-4c1c-9c6a-8f0241069619 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2610423787 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.2610423787 |
| Directory | /workspace/119.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/179.uart_fifo_reset.2371011134 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 131762325358 ps |
| CPU time | 46.04 seconds |
| Started | Aug 01 05:03:03 PM PDT 24 |
| Finished | Aug 01 05:03:49 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-ff8204e0-bba2-4865-9fe4-a1812767dc38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2371011134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.2371011134 |
| Directory | /workspace/179.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2778175080 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 40233491454 ps |
| CPU time | 778.02 seconds |
| Started | Aug 01 04:57:13 PM PDT 24 |
| Finished | Aug 01 05:10:11 PM PDT 24 |
| Peak memory | 208296 kb |
| Host | smart-b1a37132-f9e2-4fcb-abd9-265fcc147537 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778175080 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2778175080 |
| Directory | /workspace/21.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/210.uart_fifo_reset.2770345809 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 101486920516 ps |
| CPU time | 105.32 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:05:12 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-254032e0-f833-4dc1-84ec-13291bdba237 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2770345809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.2770345809 |
| Directory | /workspace/210.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/214.uart_fifo_reset.3303154343 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 119953690826 ps |
| CPU time | 27.74 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:04:05 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-1b483e7d-ca85-43fe-a5c8-8deb74433baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3303154343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3303154343 |
| Directory | /workspace/214.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_stress_all.3030878991 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 309135959771 ps |
| CPU time | 556.23 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:10:26 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-4ecb2548-783d-4df0-acac-2d42177240fd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030878991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3030878991 |
| Directory | /workspace/47.uart_stress_all/latest |
| Test location | /workspace/coverage/default/130.uart_fifo_reset.1767336498 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 68790832985 ps |
| CPU time | 31.9 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:03:13 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-7454241e-9eb0-474b-a747-a50023210f0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1767336498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1767336498 |
| Directory | /workspace/130.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/137.uart_fifo_reset.326077804 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 132036184435 ps |
| CPU time | 26.42 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:03:08 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-a3fd0d30-5bb2-47d2-88c4-7d461649a13a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326077804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.326077804 |
| Directory | /workspace/137.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/140.uart_fifo_reset.988610791 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 37726641484 ps |
| CPU time | 15.17 seconds |
| Started | Aug 01 05:02:40 PM PDT 24 |
| Finished | Aug 01 05:02:55 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-83509818-390b-488c-b8fd-d714c6378e11 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=988610791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.988610791 |
| Directory | /workspace/140.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/145.uart_fifo_reset.1676518537 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 190678249269 ps |
| CPU time | 78.97 seconds |
| Started | Aug 01 05:02:42 PM PDT 24 |
| Finished | Aug 01 05:04:01 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-1bc2dab4-4828-4b1d-9505-efc859eab86d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676518537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.1676518537 |
| Directory | /workspace/145.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_reset.628472153 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 113104565551 ps |
| CPU time | 171.01 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:59:10 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-9cb1b93b-6111-4269-ac70-603361bf70d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=628472153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.628472153 |
| Directory | /workspace/15.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_stress_all_with_rand_reset.2889265615 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 48129832616 ps |
| CPU time | 882.77 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 05:11:14 PM PDT 24 |
| Peak memory | 224968 kb |
| Host | smart-1c330535-8a13-401f-8d3e-c2bed3165fc1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889265615 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.2889265615 |
| Directory | /workspace/16.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/171.uart_fifo_reset.3532135624 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 55118078373 ps |
| CPU time | 31.9 seconds |
| Started | Aug 01 05:03:05 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-c359ea93-1858-4e9e-84e4-0d645eda908c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3532135624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3532135624 |
| Directory | /workspace/171.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all_with_rand_reset.1225153614 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 22101169288 ps |
| CPU time | 262.88 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 05:01:12 PM PDT 24 |
| Peak memory | 216540 kb |
| Host | smart-9c40429b-8ff7-4f47-b1f1-eb955d7c9dda |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225153614 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.1225153614 |
| Directory | /workspace/18.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/180.uart_fifo_reset.643981108 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 48831285252 ps |
| CPU time | 24.05 seconds |
| Started | Aug 01 05:03:05 PM PDT 24 |
| Finished | Aug 01 05:03:29 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-b80f13f6-ec85-4884-8db5-e1bd0621bb18 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=643981108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.643981108 |
| Directory | /workspace/180.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/184.uart_fifo_reset.2931497678 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 73719592306 ps |
| CPU time | 32.79 seconds |
| Started | Aug 01 05:03:17 PM PDT 24 |
| Finished | Aug 01 05:03:50 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-856afadb-26d8-48e4-952f-1ab0013a0fa1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2931497678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2931497678 |
| Directory | /workspace/184.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_reset.2707152863 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 33671095027 ps |
| CPU time | 52.14 seconds |
| Started | Aug 01 04:56:50 PM PDT 24 |
| Finished | Aug 01 04:57:42 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-6c8d7334-1349-46e9-af13-3f54949ea4f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2707152863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.2707152863 |
| Directory | /workspace/19.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/200.uart_fifo_reset.308828503 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 22142184007 ps |
| CPU time | 34.95 seconds |
| Started | Aug 01 05:03:25 PM PDT 24 |
| Finished | Aug 01 05:04:01 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-b95347d9-b8c7-42fe-a272-14b686a1f9fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=308828503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.308828503 |
| Directory | /workspace/200.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/224.uart_fifo_reset.640894894 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 85217167762 ps |
| CPU time | 148.58 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:06:06 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-f345cafd-42f3-4260-9c57-6f33494883c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=640894894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.640894894 |
| Directory | /workspace/224.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/240.uart_fifo_reset.2266575466 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 57153955546 ps |
| CPU time | 55.11 seconds |
| Started | Aug 01 05:03:48 PM PDT 24 |
| Finished | Aug 01 05:04:43 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-56b92a7c-7034-41dc-99f3-bb6613e13757 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2266575466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.2266575466 |
| Directory | /workspace/240.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_reset.3161172133 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 83860722662 ps |
| CPU time | 139.75 seconds |
| Started | Aug 01 04:58:53 PM PDT 24 |
| Finished | Aug 01 05:01:13 PM PDT 24 |
| Peak memory | 199400 kb |
| Host | smart-1d40d555-2249-4b9e-a794-9ccab0e5dc0a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3161172133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3161172133 |
| Directory | /workspace/33.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/61.uart_fifo_reset.1403296017 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 84808396125 ps |
| CPU time | 38.46 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:01:57 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-c9d0696d-57e7-4b90-b557-bbd6324102e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1403296017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.1403296017 |
| Directory | /workspace/61.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/73.uart_stress_all_with_rand_reset.1153638597 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 518793004672 ps |
| CPU time | 953.28 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:17:32 PM PDT 24 |
| Peak memory | 216404 kb |
| Host | smart-a8cdb1ae-2ed5-493b-93e9-9a1110e29810 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153638597 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.1153638597 |
| Directory | /workspace/73.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_fifo_reset.2197294838 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 33480833700 ps |
| CPU time | 59.46 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:03:03 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-37081a13-7c01-42c2-9377-da596faa0d85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2197294838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.2197294838 |
| Directory | /workspace/97.uart_fifo_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.2142905276 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 47881036 ps |
| CPU time | 0.67 seconds |
| Started | Aug 01 04:52:32 PM PDT 24 |
| Finished | Aug 01 04:52:32 PM PDT 24 |
| Peak memory | 195304 kb |
| Host | smart-cfc24f49-6ef3-4c9c-a45a-fbf3fb0a37fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142905276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.2142905276 |
| Directory | /workspace/0.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3291993237 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 518905023 ps |
| CPU time | 2.31 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 198316 kb |
| Host | smart-fd0e49e8-c507-4e89-aad0-7ed68c67bacf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291993237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3291993237 |
| Directory | /workspace/0.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.1046510546 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 21496961 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:32 PM PDT 24 |
| Peak memory | 195700 kb |
| Host | smart-ca254331-7b89-4dd8-917d-8b6b6dffc6d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046510546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.1046510546 |
| Directory | /workspace/0.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.531042033 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 110591009 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:52:32 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-b40b8b66-3516-420d-8773-beec102e841a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531042033 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.531042033 |
| Directory | /workspace/0.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_csr_rw.2388473774 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 65292756 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:52:30 PM PDT 24 |
| Finished | Aug 01 04:52:31 PM PDT 24 |
| Peak memory | 195692 kb |
| Host | smart-92336512-bdd4-4a7b-b965-74ad54175f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388473774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.2388473774 |
| Directory | /workspace/0.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_intr_test.3894975056 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 84524932 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:32 PM PDT 24 |
| Peak memory | 194672 kb |
| Host | smart-e787c3b6-5f26-401f-a32e-bc95cc53f0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894975056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3894975056 |
| Directory | /workspace/0.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.4076817595 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 42485680 ps |
| CPU time | 0.73 seconds |
| Started | Aug 01 04:52:34 PM PDT 24 |
| Finished | Aug 01 04:52:35 PM PDT 24 |
| Peak memory | 197340 kb |
| Host | smart-167c5cae-318f-430b-a808-231826202919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076817595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr _outstanding.4076817595 |
| Directory | /workspace/0.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_errors.2400546393 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 132021825 ps |
| CPU time | 1.63 seconds |
| Started | Aug 01 04:52:21 PM PDT 24 |
| Finished | Aug 01 04:52:23 PM PDT 24 |
| Peak memory | 200340 kb |
| Host | smart-a6256252-31b3-4b47-9eed-1582c868f1cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400546393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.2400546393 |
| Directory | /workspace/0.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.2894808027 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 150398819 ps |
| CPU time | 0.97 seconds |
| Started | Aug 01 04:52:20 PM PDT 24 |
| Finished | Aug 01 04:52:21 PM PDT 24 |
| Peak memory | 199188 kb |
| Host | smart-e00a5b92-7da8-4d85-b6b5-c11d91f5c16e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894808027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.2894808027 |
| Directory | /workspace/0.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.3220399341 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 40803258 ps |
| CPU time | 0.64 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:31 PM PDT 24 |
| Peak memory | 195084 kb |
| Host | smart-09715bd6-1f86-4b73-ae56-a0540d6d8f97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220399341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.3220399341 |
| Directory | /workspace/1.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.508348099 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 134236301 ps |
| CPU time | 1.62 seconds |
| Started | Aug 01 04:52:31 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 197540 kb |
| Host | smart-3eb770e2-39e6-4463-b897-2c50a7e232fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508348099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.508348099 |
| Directory | /workspace/1.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.55419729 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 15959273 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:52:29 PM PDT 24 |
| Finished | Aug 01 04:52:30 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-25046f6b-5dee-4be2-8032-834d5c7136b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55419729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.55419729 |
| Directory | /workspace/1.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.3787501322 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 75105441 ps |
| CPU time | 1.21 seconds |
| Started | Aug 01 04:52:45 PM PDT 24 |
| Finished | Aug 01 04:52:46 PM PDT 24 |
| Peak memory | 200356 kb |
| Host | smart-218d987a-5d0a-4209-9d79-f5b067e928e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787501322 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.3787501322 |
| Directory | /workspace/1.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_csr_rw.2495182075 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 16195375 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:52:30 PM PDT 24 |
| Finished | Aug 01 04:52:31 PM PDT 24 |
| Peak memory | 195760 kb |
| Host | smart-7d6c1a89-67a0-47ea-87fa-6ab35bfe7038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495182075 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2495182075 |
| Directory | /workspace/1.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_intr_test.3884977917 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 28456735 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:52:32 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 194708 kb |
| Host | smart-8c2edf56-7b09-44a5-96f7-619cb32c31d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884977917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.3884977917 |
| Directory | /workspace/1.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.4261857342 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 115783911 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:52:33 PM PDT 24 |
| Finished | Aug 01 04:52:34 PM PDT 24 |
| Peak memory | 197472 kb |
| Host | smart-9d0ed70c-7e78-48e6-a4c6-024dd1be606e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261857342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr _outstanding.4261857342 |
| Directory | /workspace/1.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.uart_tl_errors.2805328308 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 38221319 ps |
| CPU time | 1.37 seconds |
| Started | Aug 01 04:52:32 PM PDT 24 |
| Finished | Aug 01 04:52:33 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-89a0d164-693e-40d2-b5ff-d397aa8f47e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805328308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2805328308 |
| Directory | /workspace/1.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.768788623 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 65823450 ps |
| CPU time | 0.67 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 197704 kb |
| Host | smart-f606bc01-b3ac-4a74-8163-47aaff871d4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768788623 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.768788623 |
| Directory | /workspace/10.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_csr_rw.4253697030 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 27518491 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:25 PM PDT 24 |
| Finished | Aug 01 04:53:26 PM PDT 24 |
| Peak memory | 195684 kb |
| Host | smart-dbcdd46e-7a52-456a-9a80-b73ce71f3609 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253697030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.4253697030 |
| Directory | /workspace/10.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_intr_test.3310278302 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 33800998 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 194624 kb |
| Host | smart-2e235c4c-ad89-4c2c-aa37-dd5bb04e736e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310278302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.3310278302 |
| Directory | /workspace/10.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3795120192 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 56573587 ps |
| CPU time | 0.61 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 195700 kb |
| Host | smart-e5a2b88a-71cf-498b-b53c-05a4b16391d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795120192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs r_outstanding.3795120192 |
| Directory | /workspace/10.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_errors.3010582960 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 140267830 ps |
| CPU time | 2.85 seconds |
| Started | Aug 01 04:53:22 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 200376 kb |
| Host | smart-01320e33-f246-4826-9738-01fe6e571982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010582960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3010582960 |
| Directory | /workspace/10.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.3222644087 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 96871312 ps |
| CPU time | 1.36 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-d6fbd079-025e-4244-af15-11906a90145c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222644087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.3222644087 |
| Directory | /workspace/10.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.556667235 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 48885292 ps |
| CPU time | 0.74 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 199008 kb |
| Host | smart-a85b7bc0-1ce1-4472-bc17-a65f72ba7810 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556667235 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.556667235 |
| Directory | /workspace/11.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_csr_rw.1509661943 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 15427349 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 195744 kb |
| Host | smart-c3ced8ed-bfb4-438f-a6d0-d5fe4bac4b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509661943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.1509661943 |
| Directory | /workspace/11.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_intr_test.3657773488 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 23311923 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 194776 kb |
| Host | smart-c5d33e53-2a57-46aa-a132-6d1cb07f0394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657773488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.3657773488 |
| Directory | /workspace/11.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.3285160313 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 61184391 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 196768 kb |
| Host | smart-13294e7a-5911-4698-af04-b66bd88f09a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285160313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs r_outstanding.3285160313 |
| Directory | /workspace/11.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_errors.2805737503 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 142165384 ps |
| CPU time | 1.87 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:26 PM PDT 24 |
| Peak memory | 200300 kb |
| Host | smart-6d82734e-0511-482d-a13c-135f82416b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805737503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.2805737503 |
| Directory | /workspace/11.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.4059596850 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 113748037 ps |
| CPU time | 1.27 seconds |
| Started | Aug 01 04:53:25 PM PDT 24 |
| Finished | Aug 01 04:53:26 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-3f4affc9-7070-4dc7-894a-5d4b0bb06aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059596850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.4059596850 |
| Directory | /workspace/11.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.2302081759 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 75747573 ps |
| CPU time | 0.71 seconds |
| Started | Aug 01 04:53:22 PM PDT 24 |
| Finished | Aug 01 04:53:23 PM PDT 24 |
| Peak memory | 198424 kb |
| Host | smart-0a8620ec-68c2-440a-994c-d602a959140e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302081759 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.2302081759 |
| Directory | /workspace/12.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_csr_rw.1131145963 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 13364136 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:22 PM PDT 24 |
| Finished | Aug 01 04:53:23 PM PDT 24 |
| Peak memory | 195832 kb |
| Host | smart-66b59825-9aa0-4def-a2f2-fb5079d668f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131145963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.1131145963 |
| Directory | /workspace/12.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_intr_test.2586644828 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 57733865 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-f8d27189-a1ff-4008-99d9-8d64500b12cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586644828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.2586644828 |
| Directory | /workspace/12.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2357076981 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 57364258 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:53:22 PM PDT 24 |
| Finished | Aug 01 04:53:23 PM PDT 24 |
| Peak memory | 196416 kb |
| Host | smart-9e3dc0d9-978c-46b4-bd05-42fdf5763bbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357076981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs r_outstanding.2357076981 |
| Directory | /workspace/12.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_errors.2210249154 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 32549090 ps |
| CPU time | 1.55 seconds |
| Started | Aug 01 04:53:25 PM PDT 24 |
| Finished | Aug 01 04:53:27 PM PDT 24 |
| Peak memory | 200220 kb |
| Host | smart-85abd530-a63b-41c8-a5cb-1c3d0dbc03a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210249154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2210249154 |
| Directory | /workspace/12.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.4176574130 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 100189409 ps |
| CPU time | 1 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 199348 kb |
| Host | smart-f914fb47-5d77-4ab4-ab80-71b370269f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176574130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.4176574130 |
| Directory | /workspace/12.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.2842592772 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 44567951 ps |
| CPU time | 0.81 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 199316 kb |
| Host | smart-feb33a6c-e53c-427e-91ae-118d847b4e35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842592772 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.2842592772 |
| Directory | /workspace/13.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_csr_rw.131526299 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 13103102 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:53:23 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 195696 kb |
| Host | smart-cd68cf42-73c8-4b19-a12f-aa4522dbee59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131526299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.131526299 |
| Directory | /workspace/13.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_intr_test.3674829890 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 123245258 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:24 PM PDT 24 |
| Peak memory | 194580 kb |
| Host | smart-6c4ff93a-2900-45af-8b38-0cc13b71b7b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674829890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.3674829890 |
| Directory | /workspace/13.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1218308622 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 101138398 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:53:25 PM PDT 24 |
| Finished | Aug 01 04:53:26 PM PDT 24 |
| Peak memory | 195772 kb |
| Host | smart-69f7f63b-9211-4b8f-8a28-b59e1f735c5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218308622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs r_outstanding.1218308622 |
| Directory | /workspace/13.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_errors.3150091041 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 75124588 ps |
| CPU time | 1.13 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-ffecc772-1b84-4497-9002-98daea01316b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150091041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.3150091041 |
| Directory | /workspace/13.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.3062228258 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 63668475 ps |
| CPU time | 1.03 seconds |
| Started | Aug 01 04:53:24 PM PDT 24 |
| Finished | Aug 01 04:53:25 PM PDT 24 |
| Peak memory | 199040 kb |
| Host | smart-564f3850-80f8-4c47-b423-922acbbcf6cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062228258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.3062228258 |
| Directory | /workspace/13.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2767198161 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 135279068 ps |
| CPU time | 0.86 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 200072 kb |
| Host | smart-7f52ef73-d861-4002-94c5-47b7da114617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767198161 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2767198161 |
| Directory | /workspace/14.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_csr_rw.1910695848 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 16742662 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 195684 kb |
| Host | smart-3317e777-65e6-4a08-8e99-3a514baafef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910695848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1910695848 |
| Directory | /workspace/14.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_intr_test.2450692610 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 20901994 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:37 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 194648 kb |
| Host | smart-0a9c9ac6-f1ca-4b20-9a58-a3fe4227a528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450692610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2450692610 |
| Directory | /workspace/14.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2970488678 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 34128370 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 196932 kb |
| Host | smart-7e048b98-8532-47f9-8626-ea8264daa6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970488678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs r_outstanding.2970488678 |
| Directory | /workspace/14.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_errors.3299914206 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 153401279 ps |
| CPU time | 1.53 seconds |
| Started | Aug 01 04:53:35 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 200420 kb |
| Host | smart-e9b7f220-2a1f-46f7-ab53-c8101b82c852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299914206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3299914206 |
| Directory | /workspace/14.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.164511846 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 157353790 ps |
| CPU time | 1.3 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-a3316a77-9692-49b7-a5af-87e585b4bee2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164511846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.164511846 |
| Directory | /workspace/14.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.1504559382 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 55066757 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:40 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-09e9691d-82df-481c-8ae5-7fc9c46e22f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504559382 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.1504559382 |
| Directory | /workspace/15.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_csr_rw.997160147 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 17452834 ps |
| CPU time | 0.63 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 195824 kb |
| Host | smart-eb471779-36f5-4d77-8c13-2f6be51c7682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997160147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.997160147 |
| Directory | /workspace/15.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_intr_test.3676848094 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 14273101 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 194780 kb |
| Host | smart-645dd6bf-1171-44eb-aa28-287b765a03d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676848094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3676848094 |
| Directory | /workspace/15.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.327478383 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 17168743 ps |
| CPU time | 0.67 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:40 PM PDT 24 |
| Peak memory | 196112 kb |
| Host | smart-af04d272-ae7c-413e-afb3-e126a050cb60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327478383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr _outstanding.327478383 |
| Directory | /workspace/15.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_errors.1670139277 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 62487499 ps |
| CPU time | 1.43 seconds |
| Started | Aug 01 04:53:35 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-7172751c-ab9f-4b00-bffc-b32c1545d44a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670139277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.1670139277 |
| Directory | /workspace/15.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.1154200186 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 288252624 ps |
| CPU time | 0.99 seconds |
| Started | Aug 01 04:53:37 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 199344 kb |
| Host | smart-a9066f6a-0622-4489-962f-66c7d4d9f474 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154200186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.1154200186 |
| Directory | /workspace/15.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.370240897 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 442135766 ps |
| CPU time | 0.93 seconds |
| Started | Aug 01 04:53:35 PM PDT 24 |
| Finished | Aug 01 04:53:36 PM PDT 24 |
| Peak memory | 200224 kb |
| Host | smart-798cece5-de15-40cd-8927-7e5c6aefc45a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370240897 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.370240897 |
| Directory | /workspace/16.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_csr_rw.3887724323 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 25874339 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:37 PM PDT 24 |
| Peak memory | 195952 kb |
| Host | smart-9053bdff-79c8-4d19-b64b-076c5d5fb169 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887724323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3887724323 |
| Directory | /workspace/16.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_intr_test.1538134253 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 12753633 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 194712 kb |
| Host | smart-21bb017e-b6c4-46e4-a0ec-9a569366b963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538134253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.1538134253 |
| Directory | /workspace/16.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.2774502801 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 19864661 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:53:37 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 195892 kb |
| Host | smart-a03a8863-2db7-4009-81ec-739e61998a80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774502801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs r_outstanding.2774502801 |
| Directory | /workspace/16.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_errors.2959212014 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 117493111 ps |
| CPU time | 2.45 seconds |
| Started | Aug 01 04:53:36 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-0506ed38-1f3c-4587-ad07-9f21dd12759f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959212014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2959212014 |
| Directory | /workspace/16.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.4290320660 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 285270702 ps |
| CPU time | 1.28 seconds |
| Started | Aug 01 04:53:37 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 199488 kb |
| Host | smart-b13feef9-647e-4998-9bea-201bf743e887 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290320660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.4290320660 |
| Directory | /workspace/16.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.2338970041 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 31119488 ps |
| CPU time | 0.79 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:40 PM PDT 24 |
| Peak memory | 199376 kb |
| Host | smart-c0a66e5f-3252-4264-a247-91340a18c2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338970041 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.2338970041 |
| Directory | /workspace/17.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_csr_rw.3325581821 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 17364413 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-f409e1aa-d590-421e-b06d-5762d108ad89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325581821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3325581821 |
| Directory | /workspace/17.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_intr_test.4139655310 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 39002881 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 194640 kb |
| Host | smart-335547e0-9a02-4bd3-918f-2f59032efe9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139655310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.4139655310 |
| Directory | /workspace/17.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.4188427813 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 171318374 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:53:37 PM PDT 24 |
| Finished | Aug 01 04:53:38 PM PDT 24 |
| Peak memory | 196100 kb |
| Host | smart-3c1c31fe-d550-4ad4-868b-a843c1f77dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188427813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs r_outstanding.4188427813 |
| Directory | /workspace/17.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_errors.1664686921 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 80286306 ps |
| CPU time | 1.99 seconds |
| Started | Aug 01 04:53:39 PM PDT 24 |
| Finished | Aug 01 04:53:41 PM PDT 24 |
| Peak memory | 200352 kb |
| Host | smart-88adcf50-95ab-41bc-a00a-f290e01ca2eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664686921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.1664686921 |
| Directory | /workspace/17.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1318127198 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 121927135 ps |
| CPU time | 1.36 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-fa481a9d-c45d-440a-a34d-ff6dddbf60a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318127198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1318127198 |
| Directory | /workspace/17.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.2644015493 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 77884876 ps |
| CPU time | 0.96 seconds |
| Started | Aug 01 04:53:51 PM PDT 24 |
| Finished | Aug 01 04:53:52 PM PDT 24 |
| Peak memory | 200036 kb |
| Host | smart-86e13e01-f0c2-4495-9904-2231cb47f317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644015493 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.2644015493 |
| Directory | /workspace/18.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_csr_rw.1178378286 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 11288178 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 195652 kb |
| Host | smart-dd82681c-93b8-416c-b82b-9015bea64a58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178378286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.1178378286 |
| Directory | /workspace/18.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_intr_test.2673675168 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 13957206 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 194784 kb |
| Host | smart-5e94f679-caa1-4e4e-9aad-ec267a597dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673675168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.2673675168 |
| Directory | /workspace/18.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3184653278 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 70196423 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 195904 kb |
| Host | smart-5d664e7d-c8e3-42cf-b592-8b8b137b9c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184653278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs r_outstanding.3184653278 |
| Directory | /workspace/18.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.uart_tl_errors.2793391429 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 54398839 ps |
| CPU time | 1.36 seconds |
| Started | Aug 01 04:53:38 PM PDT 24 |
| Finished | Aug 01 04:53:39 PM PDT 24 |
| Peak memory | 200364 kb |
| Host | smart-89f75498-0d78-4eb9-b75b-75657473af17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793391429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.2793391429 |
| Directory | /workspace/18.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.264562744 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 77975925 ps |
| CPU time | 0.74 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 198348 kb |
| Host | smart-7ba819d7-daca-4066-b817-a46c130dae68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264562744 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.264562744 |
| Directory | /workspace/19.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_csr_rw.788195957 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 67173435 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:53:48 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 195612 kb |
| Host | smart-61cbf7e4-02be-4d71-9104-dd9fb27f4006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788195957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.788195957 |
| Directory | /workspace/19.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_intr_test.3584263606 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 45733424 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:48 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-204c2610-1a47-456d-a667-610bec97af90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584263606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3584263606 |
| Directory | /workspace/19.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.1474274543 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 33893827 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:53:48 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 197312 kb |
| Host | smart-2e032352-a379-42a1-8eda-5994900db9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474274543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs r_outstanding.1474274543 |
| Directory | /workspace/19.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_errors.3055117134 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 31184059 ps |
| CPU time | 1.48 seconds |
| Started | Aug 01 04:53:51 PM PDT 24 |
| Finished | Aug 01 04:53:53 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-6e0f9bb6-f877-48f0-b9da-7f313f817194 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055117134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.3055117134 |
| Directory | /workspace/19.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.823995646 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 192888291 ps |
| CPU time | 1.31 seconds |
| Started | Aug 01 04:53:48 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-ea59f39e-4928-4955-a0c2-1c56b424b083 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823995646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.823995646 |
| Directory | /workspace/19.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.417219519 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 61983457 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:52:43 PM PDT 24 |
| Finished | Aug 01 04:52:44 PM PDT 24 |
| Peak memory | 195748 kb |
| Host | smart-5eb48a58-e690-497e-9834-bd21d52c2f7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417219519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.417219519 |
| Directory | /workspace/2.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.3358465250 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 220236791 ps |
| CPU time | 2.63 seconds |
| Started | Aug 01 04:52:45 PM PDT 24 |
| Finished | Aug 01 04:52:48 PM PDT 24 |
| Peak memory | 198140 kb |
| Host | smart-a95fa041-cda5-4188-848a-dd07d2655265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358465250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.3358465250 |
| Directory | /workspace/2.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3006413779 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 13813089 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:52:44 PM PDT 24 |
| Finished | Aug 01 04:52:45 PM PDT 24 |
| Peak memory | 195736 kb |
| Host | smart-66c9cc64-1643-4a34-bf88-c72deb431170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006413779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3006413779 |
| Directory | /workspace/2.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3055869765 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 82761473 ps |
| CPU time | 0.75 seconds |
| Started | Aug 01 04:52:46 PM PDT 24 |
| Finished | Aug 01 04:52:47 PM PDT 24 |
| Peak memory | 198688 kb |
| Host | smart-d9afd1ef-3e06-4139-865e-4a489c89fd36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055869765 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3055869765 |
| Directory | /workspace/2.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_csr_rw.2965018885 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 104667961 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:52:45 PM PDT 24 |
| Finished | Aug 01 04:52:46 PM PDT 24 |
| Peak memory | 195720 kb |
| Host | smart-01200873-c2df-4cbd-af95-4e143dc0ba01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965018885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.2965018885 |
| Directory | /workspace/2.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_intr_test.3223773105 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 50723563 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:52:43 PM PDT 24 |
| Finished | Aug 01 04:52:44 PM PDT 24 |
| Peak memory | 194680 kb |
| Host | smart-96f9e605-ba65-4280-89fc-f6c094a2a42b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223773105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.3223773105 |
| Directory | /workspace/2.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.4236695975 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 55772604 ps |
| CPU time | 0.79 seconds |
| Started | Aug 01 04:52:44 PM PDT 24 |
| Finished | Aug 01 04:52:45 PM PDT 24 |
| Peak memory | 197880 kb |
| Host | smart-a62b0f4c-9e5a-4a8e-83ff-8aa973dee217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236695975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr _outstanding.4236695975 |
| Directory | /workspace/2.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_errors.1639923839 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 43463327 ps |
| CPU time | 1.19 seconds |
| Started | Aug 01 04:52:44 PM PDT 24 |
| Finished | Aug 01 04:52:45 PM PDT 24 |
| Peak memory | 200288 kb |
| Host | smart-8db75dea-d7fa-45c9-9ffd-5d63f50e93fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639923839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.1639923839 |
| Directory | /workspace/2.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1057309573 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 111426251 ps |
| CPU time | 1.36 seconds |
| Started | Aug 01 04:52:44 PM PDT 24 |
| Finished | Aug 01 04:52:45 PM PDT 24 |
| Peak memory | 199632 kb |
| Host | smart-9b41295a-7e9a-4706-9353-1fdda92f5728 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057309573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1057309573 |
| Directory | /workspace/2.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/20.uart_intr_test.351621263 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 10949454 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-89c73cf3-9313-4e62-aa27-b342a80c717a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351621263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.351621263 |
| Directory | /workspace/20.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.uart_intr_test.2751100934 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 14131955 ps |
| CPU time | 0.61 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194652 kb |
| Host | smart-7009d6c2-1300-4d13-b935-232e266d86b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751100934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.2751100934 |
| Directory | /workspace/21.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.uart_intr_test.53355270 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 34521039 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194984 kb |
| Host | smart-876be714-b54c-4561-a6f1-952f7e3b55fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53355270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.53355270 |
| Directory | /workspace/22.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.uart_intr_test.2541294237 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 19279033 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-981781af-0f16-4ddf-a6c4-9afcd26508cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541294237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2541294237 |
| Directory | /workspace/23.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.uart_intr_test.3498294665 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 43351148 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:47 PM PDT 24 |
| Finished | Aug 01 04:53:48 PM PDT 24 |
| Peak memory | 194636 kb |
| Host | smart-acc3ae95-cd75-4c74-af56-469d63f6cfed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498294665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.3498294665 |
| Directory | /workspace/24.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.uart_intr_test.773811542 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 145395809 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:51 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194616 kb |
| Host | smart-a725a223-a2f7-4489-a178-39c869fee85f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773811542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.773811542 |
| Directory | /workspace/25.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.uart_intr_test.1505287581 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 36846957 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-d0710c67-5447-4a7f-b6f4-e9e4e0f1dd02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505287581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.1505287581 |
| Directory | /workspace/26.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.uart_intr_test.444536425 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 16253721 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194648 kb |
| Host | smart-27618130-dc38-427d-8f11-23e56b8708e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444536425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.444536425 |
| Directory | /workspace/27.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.uart_intr_test.2951803498 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 49591503 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-5a8f41a9-7a33-4aaa-bfc6-c6979c65f11a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951803498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.2951803498 |
| Directory | /workspace/28.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.uart_intr_test.1614378069 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 24315214 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194708 kb |
| Host | smart-e3d8b00c-be88-415a-87bf-557799d917f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614378069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1614378069 |
| Directory | /workspace/29.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.2023754192 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 27170272 ps |
| CPU time | 0.76 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 196900 kb |
| Host | smart-5e4429f0-68c2-49cf-bb2c-9d3e21cc6db9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023754192 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.2023754192 |
| Directory | /workspace/3.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1705558927 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 589087573 ps |
| CPU time | 1.56 seconds |
| Started | Aug 01 04:52:59 PM PDT 24 |
| Finished | Aug 01 04:53:01 PM PDT 24 |
| Peak memory | 198088 kb |
| Host | smart-2a31672f-46c7-4b3f-a4df-5408f1a6919f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705558927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1705558927 |
| Directory | /workspace/3.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.4131714573 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 13243593 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 195668 kb |
| Host | smart-f45a4564-d08b-4b38-833e-d14ab8438e24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131714573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.4131714573 |
| Directory | /workspace/3.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.274039727 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 22946396 ps |
| CPU time | 0.73 seconds |
| Started | Aug 01 04:52:56 PM PDT 24 |
| Finished | Aug 01 04:52:57 PM PDT 24 |
| Peak memory | 198936 kb |
| Host | smart-c4c05eb9-ab94-4013-9a25-924d72517650 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274039727 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.274039727 |
| Directory | /workspace/3.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_csr_rw.478634541 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 266950173 ps |
| CPU time | 0.63 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 196168 kb |
| Host | smart-76f5666f-b2d2-42e0-b91b-feb62fd350bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478634541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.478634541 |
| Directory | /workspace/3.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_intr_test.4149924654 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 12439551 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 194692 kb |
| Host | smart-da1e65b5-5706-4919-a74f-c801035ff56e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149924654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.4149924654 |
| Directory | /workspace/3.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.3418644169 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 107571400 ps |
| CPU time | 0.75 seconds |
| Started | Aug 01 04:52:58 PM PDT 24 |
| Finished | Aug 01 04:52:59 PM PDT 24 |
| Peak memory | 197368 kb |
| Host | smart-5fb55023-4690-4b0e-acce-21fc35534990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418644169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr _outstanding.3418644169 |
| Directory | /workspace/3.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_errors.867259324 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 75975727 ps |
| CPU time | 1.63 seconds |
| Started | Aug 01 04:52:44 PM PDT 24 |
| Finished | Aug 01 04:52:46 PM PDT 24 |
| Peak memory | 200372 kb |
| Host | smart-65a92514-97b6-49c8-85a4-de552a10475d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867259324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.867259324 |
| Directory | /workspace/3.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.2131827992 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 42239456 ps |
| CPU time | 0.95 seconds |
| Started | Aug 01 04:52:45 PM PDT 24 |
| Finished | Aug 01 04:52:46 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-30b7ba90-b6e5-41de-b047-22f208679a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131827992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.2131827992 |
| Directory | /workspace/3.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.uart_intr_test.1201411816 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 15003460 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-d46f5357-feb4-48e0-8362-5be56703bba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201411816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.1201411816 |
| Directory | /workspace/30.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.uart_intr_test.4792834 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 51728639 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 194672 kb |
| Host | smart-f17eae8f-2b05-4519-889e-90b2e13359ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4792834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.4792834 |
| Directory | /workspace/31.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.uart_intr_test.1498000611 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 22645259 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194680 kb |
| Host | smart-57c8a3b1-8bee-4a9d-acab-34210ac0183f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498000611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.1498000611 |
| Directory | /workspace/32.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.uart_intr_test.702659272 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 14476289 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194632 kb |
| Host | smart-df6f6605-d1ba-4bbe-b355-7fffada2ba7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702659272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.702659272 |
| Directory | /workspace/33.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.uart_intr_test.617072774 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 37820777 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 194680 kb |
| Host | smart-9fb654b4-5bea-4788-96e8-f538325e6356 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617072774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.617072774 |
| Directory | /workspace/34.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.uart_intr_test.3587496014 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 186616533 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194736 kb |
| Host | smart-e259c06a-160b-4c69-8dc2-1466b9f45c52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587496014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.3587496014 |
| Directory | /workspace/35.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.uart_intr_test.4057139355 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 35717109 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-01c79fa7-f09e-47b4-bcbd-d6122096ef61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057139355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.4057139355 |
| Directory | /workspace/36.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.uart_intr_test.2336962280 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 156557837 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:51 PM PDT 24 |
| Finished | Aug 01 04:53:52 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-cb47f60d-22dd-4794-a0d3-1d1f104a4a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336962280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2336962280 |
| Directory | /workspace/37.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/38.uart_intr_test.153236663 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 34517678 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-8652fe15-ba15-43fa-a63b-2d43ba46ae77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153236663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.153236663 |
| Directory | /workspace/38.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.uart_intr_test.3051467449 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 27238841 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194676 kb |
| Host | smart-24596bee-c823-4628-b15f-ec056ce5f7e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051467449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3051467449 |
| Directory | /workspace/39.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.3579439113 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 49910027 ps |
| CPU time | 0.82 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 196836 kb |
| Host | smart-50aebb94-5d6f-4c60-b807-b41aca0f4d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579439113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.3579439113 |
| Directory | /workspace/4.uart_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.613454652 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 187785502 ps |
| CPU time | 2.4 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:59 PM PDT 24 |
| Peak memory | 198724 kb |
| Host | smart-b61e0eb4-0f9f-47f6-b983-2f1d449a194d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613454652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.613454652 |
| Directory | /workspace/4.uart_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2913522008 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 15154461 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:57 PM PDT 24 |
| Peak memory | 195676 kb |
| Host | smart-c53f7a4c-ad24-4de8-917b-5e9fc4460523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913522008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2913522008 |
| Directory | /workspace/4.uart_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1951302365 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 20843736 ps |
| CPU time | 0.94 seconds |
| Started | Aug 01 04:52:59 PM PDT 24 |
| Finished | Aug 01 04:53:00 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-f28ab88f-c069-43c3-83f6-d182de0428f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951302365 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1951302365 |
| Directory | /workspace/4.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_csr_rw.2588294660 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 31119380 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:57 PM PDT 24 |
| Peak memory | 195796 kb |
| Host | smart-299850dc-0c9e-44cb-8f1b-803cfe90adc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588294660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.2588294660 |
| Directory | /workspace/4.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_intr_test.947927617 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 39066425 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:52:56 PM PDT 24 |
| Finished | Aug 01 04:52:56 PM PDT 24 |
| Peak memory | 194628 kb |
| Host | smart-224eaa42-1a12-47b2-8161-0a328776a969 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947927617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.947927617 |
| Directory | /workspace/4.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.1185033994 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 35290950 ps |
| CPU time | 0.66 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 194824 kb |
| Host | smart-2cc7841a-5ce8-4600-8733-630af0400935 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185033994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr _outstanding.1185033994 |
| Directory | /workspace/4.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_errors.1043382840 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 384504083 ps |
| CPU time | 1.96 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:53:00 PM PDT 24 |
| Peak memory | 200336 kb |
| Host | smart-ff479a6f-5611-4b5e-ac3f-6c454051d065 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043382840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.1043382840 |
| Directory | /workspace/4.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.3843931028 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 151462947 ps |
| CPU time | 1.25 seconds |
| Started | Aug 01 04:52:56 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-017043db-a81b-47ac-9a76-30510a53ebd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843931028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.3843931028 |
| Directory | /workspace/4.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.uart_intr_test.3892399948 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 31882523 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:53:53 PM PDT 24 |
| Finished | Aug 01 04:53:53 PM PDT 24 |
| Peak memory | 194732 kb |
| Host | smart-29bca5ee-49e3-4cdc-8d9e-c304467f2268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892399948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.3892399948 |
| Directory | /workspace/40.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.uart_intr_test.3407896758 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 15372145 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194540 kb |
| Host | smart-b254cda7-d540-49e9-ab41-1df043a4bd35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407896758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.3407896758 |
| Directory | /workspace/41.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.uart_intr_test.70515572 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 36585342 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:48 PM PDT 24 |
| Finished | Aug 01 04:53:49 PM PDT 24 |
| Peak memory | 194652 kb |
| Host | smart-5af04871-824a-41c0-9647-6fc5154be74f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70515572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.70515572 |
| Directory | /workspace/42.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/43.uart_intr_test.3988796263 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 12809464 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:53:50 PM PDT 24 |
| Finished | Aug 01 04:53:51 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-c5e24aea-3cdf-4bc1-9d08-b568b4ac6725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988796263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.3988796263 |
| Directory | /workspace/43.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/44.uart_intr_test.1193197466 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 49810872 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:49 PM PDT 24 |
| Finished | Aug 01 04:53:50 PM PDT 24 |
| Peak memory | 194696 kb |
| Host | smart-d5c82f3f-03c9-4caa-9241-858f744fdf51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193197466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.1193197466 |
| Directory | /workspace/44.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.uart_intr_test.1952549407 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 44847443 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:53 PM PDT 24 |
| Finished | Aug 01 04:53:53 PM PDT 24 |
| Peak memory | 194724 kb |
| Host | smart-f40546d8-be01-414f-b750-c8a23905365a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952549407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.1952549407 |
| Directory | /workspace/45.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.uart_intr_test.1586657642 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 168619087 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:54:07 PM PDT 24 |
| Finished | Aug 01 04:54:07 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-3d60feb7-33a2-4712-b55d-45633fe3e1ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586657642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1586657642 |
| Directory | /workspace/46.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.uart_intr_test.1793608617 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 10844088 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:54:06 PM PDT 24 |
| Finished | Aug 01 04:54:07 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-c48ad1e0-95f0-44a6-975c-a8fdbd58d7d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793608617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.1793608617 |
| Directory | /workspace/47.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.uart_intr_test.427676076 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 35784066 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:54:06 PM PDT 24 |
| Finished | Aug 01 04:54:07 PM PDT 24 |
| Peak memory | 194696 kb |
| Host | smart-368e9425-918a-4755-aadc-59aa1e29717d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427676076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.427676076 |
| Directory | /workspace/48.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.uart_intr_test.1374137054 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 15203993 ps |
| CPU time | 0.59 seconds |
| Started | Aug 01 04:54:06 PM PDT 24 |
| Finished | Aug 01 04:54:07 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-42d25b1a-5453-403f-97c7-9b7c9c895d9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374137054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.1374137054 |
| Directory | /workspace/49.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.1573468187 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 94706714 ps |
| CPU time | 1.2 seconds |
| Started | Aug 01 04:53:08 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 200368 kb |
| Host | smart-e830f6ea-4434-4f0e-80aa-36ccfd8fc70a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573468187 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.1573468187 |
| Directory | /workspace/5.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_csr_rw.247830866 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 12256040 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 195648 kb |
| Host | smart-305b52a5-59cf-4454-a534-47cf61ec07dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247830866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.247830866 |
| Directory | /workspace/5.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_intr_test.1176381260 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 28693133 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:52:59 PM PDT 24 |
| Finished | Aug 01 04:52:59 PM PDT 24 |
| Peak memory | 194660 kb |
| Host | smart-8a601b37-611d-46e8-84e7-842415571cc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176381260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.1176381260 |
| Directory | /workspace/5.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4009517045 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 13221036 ps |
| CPU time | 0.65 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 196144 kb |
| Host | smart-b7ae1173-ad99-402b-abc8-16dcdc79fdce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009517045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr _outstanding.4009517045 |
| Directory | /workspace/5.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_errors.4014440977 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 100712464 ps |
| CPU time | 1.35 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 200380 kb |
| Host | smart-24d0c0e2-e25c-4f5f-8f05-7c91e739c31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014440977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.4014440977 |
| Directory | /workspace/5.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.2259610748 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 45478894 ps |
| CPU time | 0.93 seconds |
| Started | Aug 01 04:52:57 PM PDT 24 |
| Finished | Aug 01 04:52:58 PM PDT 24 |
| Peak memory | 199216 kb |
| Host | smart-601b6741-5a99-498c-bfa7-05ac3ee830dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259610748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.2259610748 |
| Directory | /workspace/5.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.686754062 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 31788602 ps |
| CPU time | 0.91 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-61b322bd-28a0-49b1-add8-b930f8f904ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686754062 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.686754062 |
| Directory | /workspace/6.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_csr_rw.2325797368 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 42039892 ps |
| CPU time | 0.62 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 195712 kb |
| Host | smart-a835a5af-d8ef-43f4-82ee-ee042a2afff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325797368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2325797368 |
| Directory | /workspace/6.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_intr_test.2586549386 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 91430696 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-73591f49-2682-4d31-8257-066f74b4caf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586549386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2586549386 |
| Directory | /workspace/6.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.87402639 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 13501945 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:53:19 PM PDT 24 |
| Finished | Aug 01 04:53:19 PM PDT 24 |
| Peak memory | 195684 kb |
| Host | smart-0529e968-ba42-4dc0-b4c0-27660f5cfaad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87402639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr_o utstanding.87402639 |
| Directory | /workspace/6.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_errors.3541196792 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 22442755 ps |
| CPU time | 1.2 seconds |
| Started | Aug 01 04:53:08 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 200324 kb |
| Host | smart-69059a9a-531a-43d6-bdfc-370bff489109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541196792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.3541196792 |
| Directory | /workspace/6.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3875378866 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 210959771 ps |
| CPU time | 0.98 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 199204 kb |
| Host | smart-f68956de-0267-4505-9659-1ef82fc2e1b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875378866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3875378866 |
| Directory | /workspace/6.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.3559421266 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 207970783 ps |
| CPU time | 0.77 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-ab8f1865-8f30-452a-8b58-2597f55573e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559421266 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.3559421266 |
| Directory | /workspace/7.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_csr_rw.601836669 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 17758929 ps |
| CPU time | 0.63 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 196004 kb |
| Host | smart-5f386450-7058-405a-8678-acc2efe26779 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601836669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.601836669 |
| Directory | /workspace/7.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_intr_test.829904042 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 38372472 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:53:11 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 194672 kb |
| Host | smart-6474bd01-197b-4002-b268-ff4377e78c82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829904042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.829904042 |
| Directory | /workspace/7.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3492564122 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 43822959 ps |
| CPU time | 0.61 seconds |
| Started | Aug 01 04:53:07 PM PDT 24 |
| Finished | Aug 01 04:53:08 PM PDT 24 |
| Peak memory | 196680 kb |
| Host | smart-ae970ffd-cf61-4fbf-bba1-5fa0119832ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492564122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr _outstanding.3492564122 |
| Directory | /workspace/7.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_errors.3734391745 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 340114436 ps |
| CPU time | 1.83 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:12 PM PDT 24 |
| Peak memory | 200328 kb |
| Host | smart-e1b8290e-325d-4ac9-94c8-d6d05f1a8009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734391745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.3734391745 |
| Directory | /workspace/7.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.3498033086 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2090436979 ps |
| CPU time | 1.39 seconds |
| Started | Aug 01 04:53:11 PM PDT 24 |
| Finished | Aug 01 04:53:12 PM PDT 24 |
| Peak memory | 199600 kb |
| Host | smart-a8cdea25-2fa2-44d8-9c2d-7f4d42c1c9df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498033086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.3498033086 |
| Directory | /workspace/7.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.579804321 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 18280275 ps |
| CPU time | 0.7 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 198528 kb |
| Host | smart-64882213-5882-4cb1-a813-ee71ae8aa3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579804321 -assert nopostproc +UVM_TESTNAME= uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.579804321 |
| Directory | /workspace/8.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_csr_rw.1525764369 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 75141814 ps |
| CPU time | 0.61 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 195708 kb |
| Host | smart-98891dc7-7be6-492f-9c2e-8ebcbf05fe45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525764369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1525764369 |
| Directory | /workspace/8.uart_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_intr_test.2498650222 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 37738918 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 194688 kb |
| Host | smart-34c6e9a6-0eeb-4952-8256-1c9fac2864c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498650222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2498650222 |
| Directory | /workspace/8.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3116554937 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 79421356 ps |
| CPU time | 0.73 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 197220 kb |
| Host | smart-f1239443-e21c-4b2e-b849-f6924498db5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116554937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr _outstanding.3116554937 |
| Directory | /workspace/8.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_errors.160627845 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 170150363 ps |
| CPU time | 1.58 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 200320 kb |
| Host | smart-8fc755a7-fafb-4f58-9e68-3be6f38c126d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160627845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.160627845 |
| Directory | /workspace/8.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.908043088 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 308524434 ps |
| CPU time | 1.41 seconds |
| Started | Aug 01 04:53:09 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-aa81a108-83c3-46a9-ba99-2ac6642e4adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908043088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.908043088 |
| Directory | /workspace/8.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1391851645 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 215950415 ps |
| CPU time | 1.28 seconds |
| Started | Aug 01 04:53:25 PM PDT 24 |
| Finished | Aug 01 04:53:26 PM PDT 24 |
| Peak memory | 200308 kb |
| Host | smart-f1c46180-8909-4f2a-86e1-bf5d3dde2fcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391851645 -assert nopostproc +UVM_TESTNAME =uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1391851645 |
| Directory | /workspace/9.uart_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_intr_test.923681001 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 17426787 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:10 PM PDT 24 |
| Peak memory | 194664 kb |
| Host | smart-621fc371-eb53-4a14-a633-db988fd53fd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923681001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.923681001 |
| Directory | /workspace/9.uart_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.3820550271 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 35280427 ps |
| CPU time | 0.74 seconds |
| Started | Aug 01 04:53:22 PM PDT 24 |
| Finished | Aug 01 04:53:22 PM PDT 24 |
| Peak memory | 196064 kb |
| Host | smart-a8b2f4ec-3fac-42ba-a67c-6bc14668ab0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820550271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr _outstanding.3820550271 |
| Directory | /workspace/9.uart_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_errors.3871096728 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 44233290 ps |
| CPU time | 1.11 seconds |
| Started | Aug 01 04:53:10 PM PDT 24 |
| Finished | Aug 01 04:53:11 PM PDT 24 |
| Peak memory | 200316 kb |
| Host | smart-b58b9c55-dc51-46da-a67e-fcd3f8c90f04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871096728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.3871096728 |
| Directory | /workspace/9.uart_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.527510140 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 90405460 ps |
| CPU time | 0.94 seconds |
| Started | Aug 01 04:53:11 PM PDT 24 |
| Finished | Aug 01 04:53:12 PM PDT 24 |
| Peak memory | 198868 kb |
| Host | smart-05f040d0-1d57-40b6-83cd-fba7e06512a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527510140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.527510140 |
| Directory | /workspace/9.uart_tl_intg_err/latest |
| Test location | /workspace/coverage/default/0.uart_alert_test.2761924044 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 25087333 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:54:55 PM PDT 24 |
| Finished | Aug 01 04:54:56 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-59afa6cc-adcc-417a-89b1-e6aea3a11b4f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761924044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.2761924044 |
| Directory | /workspace/0.uart_alert_test/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_full.3957197749 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 39366401250 ps |
| CPU time | 37.88 seconds |
| Started | Aug 01 04:54:54 PM PDT 24 |
| Finished | Aug 01 04:55:32 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-5882d49f-d0c2-4cd4-a3b2-5127a3a61815 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3957197749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3957197749 |
| Directory | /workspace/0.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_overflow.3162183145 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 205065437685 ps |
| CPU time | 45.19 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:55:39 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-533ae7c2-9999-4b73-89e8-6ea5627dd2d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3162183145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3162183145 |
| Directory | /workspace/0.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/0.uart_fifo_reset.3749667438 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 27367405361 ps |
| CPU time | 50.82 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:55:44 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-6a940586-9c2e-425e-aeac-5c76b6daef04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3749667438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3749667438 |
| Directory | /workspace/0.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/0.uart_intr.1713985281 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 43348534165 ps |
| CPU time | 51.73 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:55:45 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-7a22a6d5-ff70-4a24-a0b6-574999669f30 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713985281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.1713985281 |
| Directory | /workspace/0.uart_intr/latest |
| Test location | /workspace/coverage/default/0.uart_long_xfer_wo_dly.436585351 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 31615644175 ps |
| CPU time | 208.17 seconds |
| Started | Aug 01 04:54:55 PM PDT 24 |
| Finished | Aug 01 04:58:24 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-651edcf8-e5ff-4503-acfb-a5cf405c8512 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=436585351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.436585351 |
| Directory | /workspace/0.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/0.uart_loopback.3149175270 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1105170351 ps |
| CPU time | 2.2 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:54:55 PM PDT 24 |
| Peak memory | 195516 kb |
| Host | smart-5a177ec7-0986-419f-8d6c-1b153d82b494 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3149175270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.3149175270 |
| Directory | /workspace/0.uart_loopback/latest |
| Test location | /workspace/coverage/default/0.uart_noise_filter.1744109241 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 42254035795 ps |
| CPU time | 16.03 seconds |
| Started | Aug 01 04:54:56 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 198748 kb |
| Host | smart-6649aa10-adfc-4583-aff4-4fb04fd11f30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1744109241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.1744109241 |
| Directory | /workspace/0.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/0.uart_perf.2956296596 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 21519192990 ps |
| CPU time | 172.28 seconds |
| Started | Aug 01 04:54:55 PM PDT 24 |
| Finished | Aug 01 04:57:48 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-4fa97270-6ec0-4e34-8f21-98a7d7e5c07c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2956296596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.2956296596 |
| Directory | /workspace/0.uart_perf/latest |
| Test location | /workspace/coverage/default/0.uart_rx_oversample.2470032652 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 5255849214 ps |
| CPU time | 16.27 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:55:09 PM PDT 24 |
| Peak memory | 197988 kb |
| Host | smart-dfbe5fd1-44e9-4b2b-83b7-e0fcfb819b72 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2470032652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2470032652 |
| Directory | /workspace/0.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/0.uart_rx_parity_err.951934486 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 29703724267 ps |
| CPU time | 48.49 seconds |
| Started | Aug 01 04:54:54 PM PDT 24 |
| Finished | Aug 01 04:55:43 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-7612d357-1d44-4662-a56a-8cf6009da0ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=951934486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.951934486 |
| Directory | /workspace/0.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/0.uart_rx_start_bit_filter.3609168481 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1788428841 ps |
| CPU time | 2.98 seconds |
| Started | Aug 01 04:54:52 PM PDT 24 |
| Finished | Aug 01 04:54:55 PM PDT 24 |
| Peak memory | 195284 kb |
| Host | smart-b79c2330-80a0-427b-a891-0ab8b8f8ca6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3609168481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.3609168481 |
| Directory | /workspace/0.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/0.uart_smoke.2844710368 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 296723904 ps |
| CPU time | 1.23 seconds |
| Started | Aug 01 04:54:54 PM PDT 24 |
| Finished | Aug 01 04:54:56 PM PDT 24 |
| Peak memory | 198636 kb |
| Host | smart-e91fb7c0-5318-4bfd-b1ed-f63085bbedc1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2844710368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.2844710368 |
| Directory | /workspace/0.uart_smoke/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all.1291329847 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 264621242350 ps |
| CPU time | 40.29 seconds |
| Started | Aug 01 04:54:52 PM PDT 24 |
| Finished | Aug 01 04:55:32 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-cddd8976-4c12-4090-a4cb-0370ec89f9dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291329847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1291329847 |
| Directory | /workspace/0.uart_stress_all/latest |
| Test location | /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3981481825 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 89544888865 ps |
| CPU time | 1034.73 seconds |
| Started | Aug 01 04:54:51 PM PDT 24 |
| Finished | Aug 01 05:12:06 PM PDT 24 |
| Peak memory | 224676 kb |
| Host | smart-759d0d25-d486-49e3-890d-5ac50c74e3de |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981481825 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3981481825 |
| Directory | /workspace/0.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.uart_tx_ovrd.1496268247 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 523800079 ps |
| CPU time | 2.55 seconds |
| Started | Aug 01 04:54:53 PM PDT 24 |
| Finished | Aug 01 04:54:56 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-1e826bdf-f6aa-425a-8c77-f1a4a9f2d72a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1496268247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1496268247 |
| Directory | /workspace/0.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/0.uart_tx_rx.3484840942 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 7589902765 ps |
| CPU time | 3.31 seconds |
| Started | Aug 01 04:54:55 PM PDT 24 |
| Finished | Aug 01 04:54:58 PM PDT 24 |
| Peak memory | 196812 kb |
| Host | smart-21125f95-e8ba-4990-8fa6-35f38b399af0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3484840942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.3484840942 |
| Directory | /workspace/0.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.uart_alert_test.3787634700 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 29243070 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:02 PM PDT 24 |
| Peak memory | 195148 kb |
| Host | smart-0dfe5ceb-dd88-40d7-bca9-7c9fd3d0e947 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787634700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.3787634700 |
| Directory | /workspace/1.uart_alert_test/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_full.3785802990 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 20646364730 ps |
| CPU time | 16.93 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:18 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-f93f35f9-1ad2-46ca-b5a2-249f7175c1c4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785802990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.3785802990 |
| Directory | /workspace/1.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_overflow.691651984 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 63979785307 ps |
| CPU time | 28.6 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:29 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-a14648ad-10b1-48f9-8388-8de11c9788ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691651984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.691651984 |
| Directory | /workspace/1.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/1.uart_fifo_reset.1703589735 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 129968730041 ps |
| CPU time | 200.5 seconds |
| Started | Aug 01 04:54:59 PM PDT 24 |
| Finished | Aug 01 04:58:19 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-056fc59c-bafb-4d4b-98e4-facc928fdc56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1703589735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1703589735 |
| Directory | /workspace/1.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/1.uart_intr.1720914300 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 5626207639 ps |
| CPU time | 6.67 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:08 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-926b1535-4209-4682-9b7f-ae18b296e905 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720914300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1720914300 |
| Directory | /workspace/1.uart_intr/latest |
| Test location | /workspace/coverage/default/1.uart_long_xfer_wo_dly.969441345 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 192349119088 ps |
| CPU time | 543.11 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 05:04:03 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-3e3a5bd4-b88d-4528-a621-3604e2267eea |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=969441345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.969441345 |
| Directory | /workspace/1.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/1.uart_loopback.593157749 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 3193064255 ps |
| CPU time | 6.6 seconds |
| Started | Aug 01 04:54:59 PM PDT 24 |
| Finished | Aug 01 04:55:06 PM PDT 24 |
| Peak memory | 198828 kb |
| Host | smart-28e7487e-7481-45b9-a05f-88835caf68f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=593157749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.593157749 |
| Directory | /workspace/1.uart_loopback/latest |
| Test location | /workspace/coverage/default/1.uart_noise_filter.3207667497 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 79100271562 ps |
| CPU time | 62.83 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:56:03 PM PDT 24 |
| Peak memory | 216084 kb |
| Host | smart-3eb84888-6f55-406b-934e-ba55c402ea36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3207667497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.3207667497 |
| Directory | /workspace/1.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/1.uart_perf.117756938 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 9085251904 ps |
| CPU time | 160.91 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:57:42 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-670cfe96-4de8-48cd-926b-f1cd09232ea4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=117756938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.117756938 |
| Directory | /workspace/1.uart_perf/latest |
| Test location | /workspace/coverage/default/1.uart_rx_oversample.1232951895 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 2493963572 ps |
| CPU time | 1.82 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:03 PM PDT 24 |
| Peak memory | 197824 kb |
| Host | smart-02a02c7a-eaed-499d-86f0-fc184f25f3c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1232951895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.1232951895 |
| Directory | /workspace/1.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/1.uart_rx_parity_err.2714200031 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 256042253275 ps |
| CPU time | 204.19 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-8e2ebfc8-92b5-4856-a2a4-459055ed8be3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2714200031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2714200031 |
| Directory | /workspace/1.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/1.uart_rx_start_bit_filter.1355686701 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 40893662364 ps |
| CPU time | 10.96 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 196124 kb |
| Host | smart-2c285b94-cd91-4926-81be-3daf7b19444c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1355686701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.1355686701 |
| Directory | /workspace/1.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/1.uart_sec_cm.376625999 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 66223132 ps |
| CPU time | 0.85 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:01 PM PDT 24 |
| Peak memory | 218120 kb |
| Host | smart-844d7333-aca6-426e-b7d4-8cd9f13ed64c |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376625999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.376625999 |
| Directory | /workspace/1.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/1.uart_smoke.2288642950 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 551033529 ps |
| CPU time | 2.6 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:03 PM PDT 24 |
| Peak memory | 199436 kb |
| Host | smart-69e96f3d-2b83-4910-8a6a-62211f6ab503 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2288642950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2288642950 |
| Directory | /workspace/1.uart_smoke/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all.739278026 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 124821686661 ps |
| CPU time | 107.14 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:56:48 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-52637dec-07ef-443a-a834-a76e8e089315 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739278026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.739278026 |
| Directory | /workspace/1.uart_stress_all/latest |
| Test location | /workspace/coverage/default/1.uart_stress_all_with_rand_reset.321379301 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 51515664926 ps |
| CPU time | 846.59 seconds |
| Started | Aug 01 04:55:02 PM PDT 24 |
| Finished | Aug 01 05:09:09 PM PDT 24 |
| Peak memory | 216368 kb |
| Host | smart-1224e653-fa50-415c-ac29-e422dde0294b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321379301 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.321379301 |
| Directory | /workspace/1.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.uart_tx_ovrd.1600560270 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 7254922745 ps |
| CPU time | 9.78 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:10 PM PDT 24 |
| Peak memory | 199132 kb |
| Host | smart-dee69a87-f2e6-472e-abca-8b4a293b2cbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1600560270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.1600560270 |
| Directory | /workspace/1.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_alert_test.3341273198 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 14331877 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:55:43 PM PDT 24 |
| Finished | Aug 01 04:55:44 PM PDT 24 |
| Peak memory | 195460 kb |
| Host | smart-2a8bd672-4419-4554-88d3-1d4a8a422f64 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341273198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.3341273198 |
| Directory | /workspace/10.uart_alert_test/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_full.47338526 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 119447040466 ps |
| CPU time | 59.37 seconds |
| Started | Aug 01 04:55:47 PM PDT 24 |
| Finished | Aug 01 04:56:46 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-606d0c3a-54a5-4409-a674-c4cbc24ad113 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=47338526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.47338526 |
| Directory | /workspace/10.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/10.uart_fifo_overflow.3732972604 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 16435651731 ps |
| CPU time | 28.11 seconds |
| Started | Aug 01 04:55:43 PM PDT 24 |
| Finished | Aug 01 04:56:11 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-461e5c94-cd47-498a-884e-9b5f9d03628a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3732972604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3732972604 |
| Directory | /workspace/10.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/10.uart_intr.2304023375 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 9857311244 ps |
| CPU time | 15.15 seconds |
| Started | Aug 01 04:55:47 PM PDT 24 |
| Finished | Aug 01 04:56:02 PM PDT 24 |
| Peak memory | 196564 kb |
| Host | smart-936c5120-7f1c-4145-a7f3-a4521d066ee1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304023375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.2304023375 |
| Directory | /workspace/10.uart_intr/latest |
| Test location | /workspace/coverage/default/10.uart_long_xfer_wo_dly.2458011117 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 97806623173 ps |
| CPU time | 249.14 seconds |
| Started | Aug 01 04:55:43 PM PDT 24 |
| Finished | Aug 01 04:59:52 PM PDT 24 |
| Peak memory | 199924 kb |
| Host | smart-bea46d85-78f7-4057-8928-e3250b23d1ba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2458011117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.2458011117 |
| Directory | /workspace/10.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/10.uart_loopback.3023153356 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 6001430447 ps |
| CPU time | 20.33 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:10 PM PDT 24 |
| Peak memory | 199068 kb |
| Host | smart-abdc557d-8520-4769-93a3-10c5925eeed8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3023153356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.3023153356 |
| Directory | /workspace/10.uart_loopback/latest |
| Test location | /workspace/coverage/default/10.uart_noise_filter.2303911682 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 130912577875 ps |
| CPU time | 68.59 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:59 PM PDT 24 |
| Peak memory | 208260 kb |
| Host | smart-b628942d-a7f6-42af-abf2-a448e30c8a6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2303911682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.2303911682 |
| Directory | /workspace/10.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/10.uart_perf.2998453491 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 7759157069 ps |
| CPU time | 438.54 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 05:03:09 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-fe9ffa21-360a-4dd9-acb1-8a436680f471 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2998453491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2998453491 |
| Directory | /workspace/10.uart_perf/latest |
| Test location | /workspace/coverage/default/10.uart_rx_oversample.1806548836 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 1591978841 ps |
| CPU time | 5.82 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:55:51 PM PDT 24 |
| Peak memory | 197876 kb |
| Host | smart-4c7ef921-f211-4e93-823e-342bf075cff2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1806548836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.1806548836 |
| Directory | /workspace/10.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/10.uart_rx_parity_err.2350267612 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 107844910077 ps |
| CPU time | 72.63 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:56:58 PM PDT 24 |
| Peak memory | 199548 kb |
| Host | smart-b436ceab-6b9a-40e0-a62a-34fae28c59d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2350267612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.2350267612 |
| Directory | /workspace/10.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/10.uart_rx_start_bit_filter.2681533703 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 39658192917 ps |
| CPU time | 53.72 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:44 PM PDT 24 |
| Peak memory | 196616 kb |
| Host | smart-7f08b234-49fb-4c45-b2ef-9a588532e785 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2681533703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.2681533703 |
| Directory | /workspace/10.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/10.uart_smoke.580515290 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 446236021 ps |
| CPU time | 1.88 seconds |
| Started | Aug 01 04:55:47 PM PDT 24 |
| Finished | Aug 01 04:55:49 PM PDT 24 |
| Peak memory | 198588 kb |
| Host | smart-895386b4-9873-4735-ae45-ef6131b4cd2c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=580515290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.580515290 |
| Directory | /workspace/10.uart_smoke/latest |
| Test location | /workspace/coverage/default/10.uart_stress_all.590968563 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 73270310337 ps |
| CPU time | 113.13 seconds |
| Started | Aug 01 04:55:48 PM PDT 24 |
| Finished | Aug 01 04:57:41 PM PDT 24 |
| Peak memory | 198832 kb |
| Host | smart-85a230e2-a732-4906-a79e-07565645e42b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590968563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.590968563 |
| Directory | /workspace/10.uart_stress_all/latest |
| Test location | /workspace/coverage/default/10.uart_tx_ovrd.610308244 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1159300644 ps |
| CPU time | 4.5 seconds |
| Started | Aug 01 04:55:47 PM PDT 24 |
| Finished | Aug 01 04:55:52 PM PDT 24 |
| Peak memory | 199332 kb |
| Host | smart-49e81f1d-ad06-45da-a2fd-57d8e51a18df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=610308244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.610308244 |
| Directory | /workspace/10.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/10.uart_tx_rx.1313665347 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 49165831483 ps |
| CPU time | 43.74 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:56:28 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-b6ad41ae-a177-4a5d-8200-32769d14da8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313665347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.1313665347 |
| Directory | /workspace/10.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/100.uart_fifo_reset.1577218673 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 17266042326 ps |
| CPU time | 32.33 seconds |
| Started | Aug 01 05:02:05 PM PDT 24 |
| Finished | Aug 01 05:02:37 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-1efb2660-8e2a-415b-8ecd-3a1fa98bb8a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1577218673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.1577218673 |
| Directory | /workspace/100.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/101.uart_fifo_reset.1990922907 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 46139050746 ps |
| CPU time | 13.91 seconds |
| Started | Aug 01 05:02:02 PM PDT 24 |
| Finished | Aug 01 05:02:16 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-757f2df8-e4a1-4e01-a208-e5e4c2d15a62 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1990922907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.1990922907 |
| Directory | /workspace/101.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/102.uart_fifo_reset.3632702222 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 101173292414 ps |
| CPU time | 36.34 seconds |
| Started | Aug 01 05:02:02 PM PDT 24 |
| Finished | Aug 01 05:02:38 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-0681c07a-0f16-4792-b355-048b043bc0ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632702222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.3632702222 |
| Directory | /workspace/102.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/103.uart_fifo_reset.2652233001 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 98541058112 ps |
| CPU time | 10.61 seconds |
| Started | Aug 01 05:02:05 PM PDT 24 |
| Finished | Aug 01 05:02:16 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-15887504-dd48-49f7-8a76-5d8376203c88 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2652233001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.2652233001 |
| Directory | /workspace/103.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/104.uart_fifo_reset.2411476676 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 19643054699 ps |
| CPU time | 35.71 seconds |
| Started | Aug 01 05:02:01 PM PDT 24 |
| Finished | Aug 01 05:02:37 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-a65ac1f2-5c86-4012-a18b-d6abba3828f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2411476676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.2411476676 |
| Directory | /workspace/104.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/105.uart_fifo_reset.1063439073 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 25516828054 ps |
| CPU time | 47 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:02:50 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-7cbb49e2-6450-44bf-a6b4-e595aaa9179f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1063439073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1063439073 |
| Directory | /workspace/105.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/106.uart_fifo_reset.1866833321 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 58761898285 ps |
| CPU time | 109.08 seconds |
| Started | Aug 01 05:02:06 PM PDT 24 |
| Finished | Aug 01 05:03:55 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-6b1ad02c-9e7d-4693-a743-29d7a1ec561e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866833321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.1866833321 |
| Directory | /workspace/106.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/107.uart_fifo_reset.2408777000 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 155286830290 ps |
| CPU time | 238.76 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:06:13 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-b35b92e8-73ca-4d75-8388-ad5722a07ea7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2408777000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.2408777000 |
| Directory | /workspace/107.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/108.uart_fifo_reset.1876530708 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 174051035711 ps |
| CPU time | 191.38 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:05:26 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-69fa4e72-b382-418f-865e-77e679327f16 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1876530708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.1876530708 |
| Directory | /workspace/108.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/109.uart_fifo_reset.3837083909 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 20048023999 ps |
| CPU time | 30.46 seconds |
| Started | Aug 01 05:02:15 PM PDT 24 |
| Finished | Aug 01 05:02:46 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-abf4b4e9-ef6b-4787-90dc-c96e0ffe827d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3837083909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.3837083909 |
| Directory | /workspace/109.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_full.1794698649 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 41754450495 ps |
| CPU time | 72.77 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:56:57 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-977bcdfe-e61a-41e6-a2da-7d3ea2c53afd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1794698649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.1794698649 |
| Directory | /workspace/11.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_overflow.2041369084 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 118156893019 ps |
| CPU time | 38.02 seconds |
| Started | Aug 01 04:55:43 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-e7ff802c-1153-4c47-9ad3-a90ed97cab69 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041369084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.2041369084 |
| Directory | /workspace/11.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/11.uart_fifo_reset.987232688 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 36747729780 ps |
| CPU time | 27.63 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:18 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-6e35f2fc-ba9a-4818-b6f6-5ffad505cad2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987232688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.987232688 |
| Directory | /workspace/11.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/11.uart_intr.167543008 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 44031850769 ps |
| CPU time | 38.48 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:29 PM PDT 24 |
| Peak memory | 199944 kb |
| Host | smart-3a0135f8-d287-46ed-aa83-303830811df9 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167543008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.167543008 |
| Directory | /workspace/11.uart_intr/latest |
| Test location | /workspace/coverage/default/11.uart_long_xfer_wo_dly.460469664 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 126076085377 ps |
| CPU time | 995.62 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 05:12:31 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-1d989f4f-67f8-4cad-92f2-f185f6dfe18d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=460469664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.460469664 |
| Directory | /workspace/11.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/11.uart_loopback.824761253 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 1219143672 ps |
| CPU time | 2.85 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:55:58 PM PDT 24 |
| Peak memory | 196852 kb |
| Host | smart-7cc72b4d-4493-4b7c-86dd-15745f101879 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=824761253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.824761253 |
| Directory | /workspace/11.uart_loopback/latest |
| Test location | /workspace/coverage/default/11.uart_noise_filter.147041944 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 98115932776 ps |
| CPU time | 446.55 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 05:03:17 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-a77b048d-2e1b-4f46-9d62-ed0da7a19f10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=147041944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.147041944 |
| Directory | /workspace/11.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/11.uart_perf.925250245 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 12407557768 ps |
| CPU time | 597.97 seconds |
| Started | Aug 01 04:55:54 PM PDT 24 |
| Finished | Aug 01 05:05:53 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-62757b58-c8e7-4b26-bdc9-8102775ce407 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=925250245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.925250245 |
| Directory | /workspace/11.uart_perf/latest |
| Test location | /workspace/coverage/default/11.uart_rx_oversample.3585772788 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 2018762214 ps |
| CPU time | 12.55 seconds |
| Started | Aug 01 04:55:48 PM PDT 24 |
| Finished | Aug 01 04:56:01 PM PDT 24 |
| Peak memory | 197760 kb |
| Host | smart-f87cf982-ef00-4898-80e1-907676fd05f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3585772788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3585772788 |
| Directory | /workspace/11.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/11.uart_rx_parity_err.1797698649 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 48213968253 ps |
| CPU time | 63.91 seconds |
| Started | Aug 01 04:55:57 PM PDT 24 |
| Finished | Aug 01 04:57:01 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-20304e05-62fc-4e23-bb07-d1948d152b7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1797698649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.1797698649 |
| Directory | /workspace/11.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/11.uart_rx_start_bit_filter.556012252 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 3352456710 ps |
| CPU time | 2.98 seconds |
| Started | Aug 01 04:55:59 PM PDT 24 |
| Finished | Aug 01 04:56:02 PM PDT 24 |
| Peak memory | 195880 kb |
| Host | smart-a326586c-d8a5-4195-b59b-08994b32089b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=556012252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.556012252 |
| Directory | /workspace/11.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/11.uart_smoke.1913106271 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 652551196 ps |
| CPU time | 1.35 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:55:45 PM PDT 24 |
| Peak memory | 198712 kb |
| Host | smart-8b0be1a6-002c-4a8a-8aee-11a00c46049f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1913106271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.1913106271 |
| Directory | /workspace/11.uart_smoke/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all.3736481432 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 489297813688 ps |
| CPU time | 420.2 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 05:02:56 PM PDT 24 |
| Peak memory | 208460 kb |
| Host | smart-592123d3-a7ac-4ea6-aeaa-f60be30c9323 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736481432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3736481432 |
| Directory | /workspace/11.uart_stress_all/latest |
| Test location | /workspace/coverage/default/11.uart_stress_all_with_rand_reset.1911501041 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 227486895687 ps |
| CPU time | 704.12 seconds |
| Started | Aug 01 04:55:54 PM PDT 24 |
| Finished | Aug 01 05:07:38 PM PDT 24 |
| Peak memory | 216300 kb |
| Host | smart-d9ecc31d-2029-4f27-9c6a-6d170035cd38 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911501041 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.1911501041 |
| Directory | /workspace/11.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/11.uart_tx_ovrd.1758666867 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 6529593439 ps |
| CPU time | 10.48 seconds |
| Started | Aug 01 04:55:53 PM PDT 24 |
| Finished | Aug 01 04:56:04 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-9071230c-17f4-476a-9469-a2f5eb920c6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1758666867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.1758666867 |
| Directory | /workspace/11.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/11.uart_tx_rx.2267188431 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 21483685659 ps |
| CPU time | 40.42 seconds |
| Started | Aug 01 04:55:50 PM PDT 24 |
| Finished | Aug 01 04:56:31 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-0f348ff4-3cac-4b41-8700-58cb6e7484bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2267188431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.2267188431 |
| Directory | /workspace/11.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/110.uart_fifo_reset.1322676770 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 103438537997 ps |
| CPU time | 136.34 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:04:31 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-9b517deb-6d61-46c6-bf16-c6480665fb8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1322676770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.1322676770 |
| Directory | /workspace/110.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/112.uart_fifo_reset.3906899886 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 126698991381 ps |
| CPU time | 160.46 seconds |
| Started | Aug 01 05:02:15 PM PDT 24 |
| Finished | Aug 01 05:04:56 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-cb133b8a-0399-4964-99fb-5e5ce954eac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3906899886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.3906899886 |
| Directory | /workspace/112.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/113.uart_fifo_reset.1418453594 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 29264656505 ps |
| CPU time | 46.56 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:03:00 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-c57977ce-1b88-4937-894f-7ef30bbc83bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1418453594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.1418453594 |
| Directory | /workspace/113.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/114.uart_fifo_reset.3461335679 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 58573711052 ps |
| CPU time | 84.33 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:03:39 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-f2134078-06e2-4cf8-b4f3-446d40c093a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3461335679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.3461335679 |
| Directory | /workspace/114.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/115.uart_fifo_reset.3912538106 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 49142105348 ps |
| CPU time | 37.29 seconds |
| Started | Aug 01 05:02:14 PM PDT 24 |
| Finished | Aug 01 05:02:52 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-e155b347-e95f-4b12-b680-edfd41cea501 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3912538106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3912538106 |
| Directory | /workspace/115.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/116.uart_fifo_reset.1725527157 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 20036758728 ps |
| CPU time | 33.51 seconds |
| Started | Aug 01 05:02:15 PM PDT 24 |
| Finished | Aug 01 05:02:49 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-167b5be6-35d8-43de-a97e-32924f235ecb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725527157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1725527157 |
| Directory | /workspace/116.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/117.uart_fifo_reset.80364419 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 162298604200 ps |
| CPU time | 43.92 seconds |
| Started | Aug 01 05:02:25 PM PDT 24 |
| Finished | Aug 01 05:03:09 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-35aafa66-25d1-4dba-93ad-984bb168814b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=80364419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.80364419 |
| Directory | /workspace/117.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/118.uart_fifo_reset.4100273356 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 27921531329 ps |
| CPU time | 26.57 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:02:53 PM PDT 24 |
| Peak memory | 199328 kb |
| Host | smart-19031f01-caee-4321-9eb1-42cc8eabc4b7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4100273356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.4100273356 |
| Directory | /workspace/118.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_alert_test.942389425 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 23442156 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:56:07 PM PDT 24 |
| Finished | Aug 01 04:56:07 PM PDT 24 |
| Peak memory | 195228 kb |
| Host | smart-71b35441-5bc6-40a1-bf12-ed601e776dfe |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942389425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.942389425 |
| Directory | /workspace/12.uart_alert_test/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_full.2954244935 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 105664514654 ps |
| CPU time | 59.54 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:56:55 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-6f5fafe6-72f1-4b41-9a81-f38f401c0d9b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2954244935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2954244935 |
| Directory | /workspace/12.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_overflow.4269173777 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 17683518590 ps |
| CPU time | 31.33 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:56:26 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-c53bea6e-45a3-4a70-b84f-4c9a1677daac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4269173777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.4269173777 |
| Directory | /workspace/12.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/12.uart_fifo_reset.1511583476 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 133546059537 ps |
| CPU time | 33.86 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:56:29 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-5a588507-5a50-4a11-825a-290f4c589686 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1511583476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1511583476 |
| Directory | /workspace/12.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/12.uart_intr.3076110988 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 37443495626 ps |
| CPU time | 18.58 seconds |
| Started | Aug 01 04:55:55 PM PDT 24 |
| Finished | Aug 01 04:56:14 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-6eb2d44a-4775-4a66-93ea-5d5f320aa938 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076110988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3076110988 |
| Directory | /workspace/12.uart_intr/latest |
| Test location | /workspace/coverage/default/12.uart_long_xfer_wo_dly.3513464681 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 108880635200 ps |
| CPU time | 478.94 seconds |
| Started | Aug 01 04:56:06 PM PDT 24 |
| Finished | Aug 01 05:04:05 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-df275ebd-38ea-4013-ab5d-de24a9dced66 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3513464681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.3513464681 |
| Directory | /workspace/12.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/12.uart_loopback.3350428889 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 9900925302 ps |
| CPU time | 4.94 seconds |
| Started | Aug 01 04:56:07 PM PDT 24 |
| Finished | Aug 01 04:56:12 PM PDT 24 |
| Peak memory | 198732 kb |
| Host | smart-a5bb451e-ae6a-4e8d-8128-16bd25bdf16c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3350428889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.3350428889 |
| Directory | /workspace/12.uart_loopback/latest |
| Test location | /workspace/coverage/default/12.uart_noise_filter.184298196 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 17833748347 ps |
| CPU time | 28.45 seconds |
| Started | Aug 01 04:55:53 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 196776 kb |
| Host | smart-c2f45d7b-bc80-4e7c-8ac4-d96889901d24 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=184298196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.184298196 |
| Directory | /workspace/12.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/12.uart_perf.824582134 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 20572961936 ps |
| CPU time | 312.31 seconds |
| Started | Aug 01 04:56:06 PM PDT 24 |
| Finished | Aug 01 05:01:18 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-63f3059b-a7a9-4d8a-bd73-efe133d11585 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=824582134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.824582134 |
| Directory | /workspace/12.uart_perf/latest |
| Test location | /workspace/coverage/default/12.uart_rx_oversample.2735761648 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 3158305102 ps |
| CPU time | 22.14 seconds |
| Started | Aug 01 04:55:54 PM PDT 24 |
| Finished | Aug 01 04:56:16 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-638a7b12-0611-44c0-a061-3dd62c3b1acb |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2735761648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.2735761648 |
| Directory | /workspace/12.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/12.uart_rx_parity_err.2759487147 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 99874279745 ps |
| CPU time | 34.02 seconds |
| Started | Aug 01 04:56:08 PM PDT 24 |
| Finished | Aug 01 04:56:42 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-271711ce-2ebc-4c24-b0ea-04bb5c485f65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2759487147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2759487147 |
| Directory | /workspace/12.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/12.uart_rx_start_bit_filter.324362495 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 2328351300 ps |
| CPU time | 1.51 seconds |
| Started | Aug 01 04:56:00 PM PDT 24 |
| Finished | Aug 01 04:56:01 PM PDT 24 |
| Peak memory | 195484 kb |
| Host | smart-30aab61c-4d54-4649-86f2-5cbe588ae1e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=324362495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.324362495 |
| Directory | /workspace/12.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/12.uart_smoke.4101778043 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 761597352 ps |
| CPU time | 1.5 seconds |
| Started | Aug 01 04:55:54 PM PDT 24 |
| Finished | Aug 01 04:55:56 PM PDT 24 |
| Peak memory | 198084 kb |
| Host | smart-7f7c4577-ba5b-4ec7-8c72-ffae752ed687 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4101778043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.4101778043 |
| Directory | /workspace/12.uart_smoke/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all.1972969846 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 169265709108 ps |
| CPU time | 133.18 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 04:58:18 PM PDT 24 |
| Peak memory | 216224 kb |
| Host | smart-8aef8ab5-4de3-4493-8170-14a312d1a7da |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972969846 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1972969846 |
| Directory | /workspace/12.uart_stress_all/latest |
| Test location | /workspace/coverage/default/12.uart_stress_all_with_rand_reset.129198912 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 23232925762 ps |
| CPU time | 296.55 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 05:01:01 PM PDT 24 |
| Peak memory | 216356 kb |
| Host | smart-c10f8caa-e375-41eb-8c7e-f8f7b5129812 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129198912 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.129198912 |
| Directory | /workspace/12.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/12.uart_tx_ovrd.305752638 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 7076511899 ps |
| CPU time | 23.7 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:56:28 PM PDT 24 |
| Peak memory | 199236 kb |
| Host | smart-4d02fbd0-d596-4a60-8533-3b87ec593cb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=305752638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.305752638 |
| Directory | /workspace/12.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/12.uart_tx_rx.1042266464 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 45316000307 ps |
| CPU time | 69.71 seconds |
| Started | Aug 01 04:55:54 PM PDT 24 |
| Finished | Aug 01 04:57:04 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-157e8179-5829-4066-9a8f-e4416fd6f3d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1042266464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1042266464 |
| Directory | /workspace/12.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/120.uart_fifo_reset.4004467930 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 62688194068 ps |
| CPU time | 116.34 seconds |
| Started | Aug 01 05:02:25 PM PDT 24 |
| Finished | Aug 01 05:04:22 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-3ae30ca0-f187-40da-a006-deb3131107d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4004467930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.4004467930 |
| Directory | /workspace/120.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/121.uart_fifo_reset.1901625946 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 58889446777 ps |
| CPU time | 117.56 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:04:23 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-5e6f1129-2ef5-4507-876b-60171696ab76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901625946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.1901625946 |
| Directory | /workspace/121.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/122.uart_fifo_reset.193107584 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 85282165587 ps |
| CPU time | 112.27 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:04:18 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-36cc33fb-4207-4bc5-85b0-045c353cfe73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=193107584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.193107584 |
| Directory | /workspace/122.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/123.uart_fifo_reset.711930408 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 88511457681 ps |
| CPU time | 190.76 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:05:37 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-f5ec71a6-cf65-4193-8279-b4c0263bc08f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=711930408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.711930408 |
| Directory | /workspace/123.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/124.uart_fifo_reset.466218544 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 68362255508 ps |
| CPU time | 21.41 seconds |
| Started | Aug 01 05:02:25 PM PDT 24 |
| Finished | Aug 01 05:02:47 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-24375abc-a3a1-4363-a410-4f8b76fd3c3a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=466218544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.466218544 |
| Directory | /workspace/124.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/125.uart_fifo_reset.3005452675 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 27039281642 ps |
| CPU time | 11.45 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:02:38 PM PDT 24 |
| Peak memory | 198992 kb |
| Host | smart-7aeac2fa-4165-464b-9d2e-0fc9141a2c76 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3005452675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3005452675 |
| Directory | /workspace/125.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/126.uart_fifo_reset.404278257 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 112908973719 ps |
| CPU time | 173.34 seconds |
| Started | Aug 01 05:02:25 PM PDT 24 |
| Finished | Aug 01 05:05:18 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-61ed6944-b21a-4b35-a5f8-a34a7045a320 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=404278257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.404278257 |
| Directory | /workspace/126.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/127.uart_fifo_reset.2247753679 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 54705605764 ps |
| CPU time | 32.58 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:02:58 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-ded92e45-22e7-4818-88d3-9a23d520ddaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2247753679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2247753679 |
| Directory | /workspace/127.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/128.uart_fifo_reset.1725651856 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 65061540001 ps |
| CPU time | 29.49 seconds |
| Started | Aug 01 05:02:27 PM PDT 24 |
| Finished | Aug 01 05:02:56 PM PDT 24 |
| Peak memory | 200096 kb |
| Host | smart-b2ae54af-ea98-4873-8174-877d4587cdf3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725651856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.1725651856 |
| Directory | /workspace/128.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/129.uart_fifo_reset.2206240698 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 45609010974 ps |
| CPU time | 10.8 seconds |
| Started | Aug 01 05:02:26 PM PDT 24 |
| Finished | Aug 01 05:02:37 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-ae92cd9a-b497-4aed-bed8-e5cbff476dc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2206240698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2206240698 |
| Directory | /workspace/129.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_alert_test.3101706157 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 26755795 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 04:56:05 PM PDT 24 |
| Peak memory | 195144 kb |
| Host | smart-d22a8e24-6452-4759-bec9-bddc4bc79c8d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101706157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.3101706157 |
| Directory | /workspace/13.uart_alert_test/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_full.2475524188 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 84492721518 ps |
| CPU time | 42.03 seconds |
| Started | Aug 01 04:56:03 PM PDT 24 |
| Finished | Aug 01 04:56:45 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-a9a02144-eb63-4782-9ede-cf8f10bc4565 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2475524188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2475524188 |
| Directory | /workspace/13.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_overflow.2426104537 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 98076671819 ps |
| CPU time | 33.97 seconds |
| Started | Aug 01 04:56:06 PM PDT 24 |
| Finished | Aug 01 04:56:41 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-6c638da3-6e1b-4d2d-a50e-fc5aecf7bbcf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2426104537 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.2426104537 |
| Directory | /workspace/13.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/13.uart_fifo_reset.834264838 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 171782611632 ps |
| CPU time | 138.48 seconds |
| Started | Aug 01 04:56:06 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-b8204b03-246a-47d2-8cd6-d6690b90a0b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=834264838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.834264838 |
| Directory | /workspace/13.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/13.uart_intr.3039367650 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 12070778482 ps |
| CPU time | 4.86 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 04:56:10 PM PDT 24 |
| Peak memory | 196808 kb |
| Host | smart-b1e5988b-1d91-4935-9195-025597109439 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039367650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.3039367650 |
| Directory | /workspace/13.uart_intr/latest |
| Test location | /workspace/coverage/default/13.uart_long_xfer_wo_dly.1463104452 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 193163105034 ps |
| CPU time | 340.6 seconds |
| Started | Aug 01 04:56:07 PM PDT 24 |
| Finished | Aug 01 05:01:48 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-3669a4a6-bd83-4a14-b3cd-4889b07f6a31 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1463104452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1463104452 |
| Directory | /workspace/13.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/13.uart_loopback.3646358793 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 10341189451 ps |
| CPU time | 18.37 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:56:22 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-648162b4-5582-4b5f-80a7-4e0c642a07ef |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3646358793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.3646358793 |
| Directory | /workspace/13.uart_loopback/latest |
| Test location | /workspace/coverage/default/13.uart_noise_filter.2037908495 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 72337837191 ps |
| CPU time | 107.05 seconds |
| Started | Aug 01 04:56:02 PM PDT 24 |
| Finished | Aug 01 04:57:49 PM PDT 24 |
| Peak memory | 198744 kb |
| Host | smart-67fb6157-1a85-46c5-8675-ee8645d23f2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2037908495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.2037908495 |
| Directory | /workspace/13.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/13.uart_perf.408070936 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 2286753312 ps |
| CPU time | 65.53 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:57:10 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-65bdcba3-2ab1-4420-8277-8093877f9db5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=408070936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.408070936 |
| Directory | /workspace/13.uart_perf/latest |
| Test location | /workspace/coverage/default/13.uart_rx_oversample.3677665300 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 7798552048 ps |
| CPU time | 16.27 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-627d2bf0-77d4-499e-9077-d266973c8cac |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3677665300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.3677665300 |
| Directory | /workspace/13.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/13.uart_rx_parity_err.4105323394 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 95991588187 ps |
| CPU time | 68.72 seconds |
| Started | Aug 01 04:56:08 PM PDT 24 |
| Finished | Aug 01 04:57:17 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-3ca01c6e-199e-4fdd-a331-67a383d47201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4105323394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.4105323394 |
| Directory | /workspace/13.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/13.uart_rx_start_bit_filter.1243854271 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 34749855630 ps |
| CPU time | 56.82 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:57:01 PM PDT 24 |
| Peak memory | 195692 kb |
| Host | smart-26793167-6c5c-42b6-97c7-5fff8c53b6b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1243854271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1243854271 |
| Directory | /workspace/13.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/13.uart_smoke.411561696 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 253278632 ps |
| CPU time | 1.35 seconds |
| Started | Aug 01 04:56:07 PM PDT 24 |
| Finished | Aug 01 04:56:09 PM PDT 24 |
| Peak memory | 198352 kb |
| Host | smart-41cb3723-841f-40c8-810a-308ddebd5322 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=411561696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.411561696 |
| Directory | /workspace/13.uart_smoke/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all.3801644425 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 94671744864 ps |
| CPU time | 134.7 seconds |
| Started | Aug 01 04:56:08 PM PDT 24 |
| Finished | Aug 01 04:58:23 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-248fe825-ee09-4c6c-a610-e09bdbd1f801 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801644425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3801644425 |
| Directory | /workspace/13.uart_stress_all/latest |
| Test location | /workspace/coverage/default/13.uart_stress_all_with_rand_reset.4233859913 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 268846323402 ps |
| CPU time | 629.51 seconds |
| Started | Aug 01 04:56:03 PM PDT 24 |
| Finished | Aug 01 05:06:33 PM PDT 24 |
| Peak memory | 224608 kb |
| Host | smart-3e23f20b-ab23-4cd9-8b51-58c58f508ee1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233859913 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.4233859913 |
| Directory | /workspace/13.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/13.uart_tx_ovrd.317537202 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 1053640139 ps |
| CPU time | 3.74 seconds |
| Started | Aug 01 04:56:06 PM PDT 24 |
| Finished | Aug 01 04:56:10 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-7dde0299-a672-440a-b236-d3464e0477a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=317537202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.317537202 |
| Directory | /workspace/13.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/13.uart_tx_rx.2544839894 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 92500244524 ps |
| CPU time | 58.99 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:57:03 PM PDT 24 |
| Peak memory | 200080 kb |
| Host | smart-97d00fff-ef51-42ed-a83e-c8c4341a36a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2544839894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2544839894 |
| Directory | /workspace/13.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/131.uart_fifo_reset.1961935413 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 19384629547 ps |
| CPU time | 47.93 seconds |
| Started | Aug 01 05:02:40 PM PDT 24 |
| Finished | Aug 01 05:03:28 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-f1be4144-14ed-4dd9-9b88-3c16e17a63b6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1961935413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.1961935413 |
| Directory | /workspace/131.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/132.uart_fifo_reset.567805273 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 238268623836 ps |
| CPU time | 104.82 seconds |
| Started | Aug 01 05:02:40 PM PDT 24 |
| Finished | Aug 01 05:04:25 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0fb6be70-f799-4708-ae17-bb07b9c1681a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=567805273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.567805273 |
| Directory | /workspace/132.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/133.uart_fifo_reset.116870656 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 149884224011 ps |
| CPU time | 52.99 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:03:34 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-0b915e0a-ac5e-422d-b5b6-8f0ca774d26d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=116870656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.116870656 |
| Directory | /workspace/133.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/134.uart_fifo_reset.177508311 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 8081381795 ps |
| CPU time | 7.42 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:02:48 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-d6c1ccfe-a6eb-4e9e-a4e5-0c7b25ac5a21 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177508311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.177508311 |
| Directory | /workspace/134.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/135.uart_fifo_reset.1887486791 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 41931539373 ps |
| CPU time | 58.04 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:03:40 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-8cbe11e2-1342-4672-8649-36f7ee23c056 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1887486791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.1887486791 |
| Directory | /workspace/135.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/136.uart_fifo_reset.406553203 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 122323370545 ps |
| CPU time | 163.42 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:05:25 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-fba22255-2711-41a5-bda3-7f0052f50f2d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=406553203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.406553203 |
| Directory | /workspace/136.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/139.uart_fifo_reset.875299181 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 583119480473 ps |
| CPU time | 89.22 seconds |
| Started | Aug 01 05:02:47 PM PDT 24 |
| Finished | Aug 01 05:04:17 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-cf765d7f-8b23-4217-a4fb-d8dfe1df8cd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=875299181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.875299181 |
| Directory | /workspace/139.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_alert_test.2140980675 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 21774759 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:56:22 PM PDT 24 |
| Finished | Aug 01 04:56:22 PM PDT 24 |
| Peak memory | 195268 kb |
| Host | smart-cc082e67-84cd-40d3-88e1-6dc42d431e2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140980675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2140980675 |
| Directory | /workspace/14.uart_alert_test/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_full.2174805287 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 38263193026 ps |
| CPU time | 16.92 seconds |
| Started | Aug 01 04:56:04 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-fe0c8ce3-7378-4878-8d3a-f65af7b7cf1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2174805287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.2174805287 |
| Directory | /workspace/14.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_overflow.1536786336 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 31833059850 ps |
| CPU time | 30.01 seconds |
| Started | Aug 01 04:56:03 PM PDT 24 |
| Finished | Aug 01 04:56:34 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-e69a53ba-1b81-4173-8b29-df69455bc517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1536786336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1536786336 |
| Directory | /workspace/14.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/14.uart_fifo_reset.2122342370 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 14446866985 ps |
| CPU time | 18.85 seconds |
| Started | Aug 01 04:56:21 PM PDT 24 |
| Finished | Aug 01 04:56:40 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-99fe6244-0204-41b5-913c-c397f6b46393 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2122342370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.2122342370 |
| Directory | /workspace/14.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/14.uart_intr.3527365731 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 218811523122 ps |
| CPU time | 284.49 seconds |
| Started | Aug 01 04:56:22 PM PDT 24 |
| Finished | Aug 01 05:01:07 PM PDT 24 |
| Peak memory | 198724 kb |
| Host | smart-be475a09-22eb-4651-8bfd-5385a25bb05d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527365731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3527365731 |
| Directory | /workspace/14.uart_intr/latest |
| Test location | /workspace/coverage/default/14.uart_long_xfer_wo_dly.3157196758 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 357590380661 ps |
| CPU time | 129.93 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:58:28 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-9a2dc549-2c65-4f66-b824-89b26ea5317c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3157196758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.3157196758 |
| Directory | /workspace/14.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/14.uart_loopback.3507938076 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 2783197524 ps |
| CPU time | 5.81 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:56:24 PM PDT 24 |
| Peak memory | 198984 kb |
| Host | smart-62606189-2331-433b-8aa1-441e9932d38a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3507938076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.3507938076 |
| Directory | /workspace/14.uart_loopback/latest |
| Test location | /workspace/coverage/default/14.uart_noise_filter.755041040 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 28272529709 ps |
| CPU time | 50.06 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:57:09 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-b93cce75-1b46-436c-871a-6c8791882f5d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=755041040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.755041040 |
| Directory | /workspace/14.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/14.uart_perf.3956023449 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 11264830485 ps |
| CPU time | 272.88 seconds |
| Started | Aug 01 04:56:21 PM PDT 24 |
| Finished | Aug 01 05:00:54 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-0d219319-913e-46ce-ae28-4d725356b55d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3956023449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.3956023449 |
| Directory | /workspace/14.uart_perf/latest |
| Test location | /workspace/coverage/default/14.uart_rx_oversample.839387402 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1384129016 ps |
| CPU time | 3.12 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 197952 kb |
| Host | smart-ceef4599-d93a-4365-a42b-473a77962ec1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=839387402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.839387402 |
| Directory | /workspace/14.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/14.uart_rx_parity_err.622027461 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 87137048523 ps |
| CPU time | 44.07 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:57:03 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-e21a2abc-7ffa-4a5d-ae6f-9b0278053bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=622027461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.622027461 |
| Directory | /workspace/14.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/14.uart_rx_start_bit_filter.2657197415 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 3843995685 ps |
| CPU time | 2.59 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 196336 kb |
| Host | smart-e4f007e2-8822-4483-a87b-987fd2848a38 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2657197415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.2657197415 |
| Directory | /workspace/14.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/14.uart_smoke.3924841358 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 520008302 ps |
| CPU time | 2.19 seconds |
| Started | Aug 01 04:56:05 PM PDT 24 |
| Finished | Aug 01 04:56:08 PM PDT 24 |
| Peak memory | 198844 kb |
| Host | smart-a1473e65-5c4c-4452-ab9a-97c6295d5f26 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3924841358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3924841358 |
| Directory | /workspace/14.uart_smoke/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all.1474316233 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 226187681990 ps |
| CPU time | 590.35 seconds |
| Started | Aug 01 04:56:20 PM PDT 24 |
| Finished | Aug 01 05:06:11 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-10afe045-c527-4ff8-b868-681052e22120 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474316233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.1474316233 |
| Directory | /workspace/14.uart_stress_all/latest |
| Test location | /workspace/coverage/default/14.uart_stress_all_with_rand_reset.65525410 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 48424552481 ps |
| CPU time | 610.33 seconds |
| Started | Aug 01 04:56:20 PM PDT 24 |
| Finished | Aug 01 05:06:30 PM PDT 24 |
| Peak memory | 216500 kb |
| Host | smart-84c7204f-9dc8-4093-94f7-2c967b39d362 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65525410 -assert nopostpro c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.65525410 |
| Directory | /workspace/14.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/14.uart_tx_ovrd.3107593103 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1769612881 ps |
| CPU time | 2.57 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:56:22 PM PDT 24 |
| Peak memory | 198120 kb |
| Host | smart-6662a626-b875-4970-8ad6-28f6f4889d90 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3107593103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.3107593103 |
| Directory | /workspace/14.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/14.uart_tx_rx.1133263957 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 8007526701 ps |
| CPU time | 13.44 seconds |
| Started | Aug 01 04:56:07 PM PDT 24 |
| Finished | Aug 01 04:56:20 PM PDT 24 |
| Peak memory | 197772 kb |
| Host | smart-61887f45-d418-4cc4-8778-256df48d3d00 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1133263957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1133263957 |
| Directory | /workspace/14.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/141.uart_fifo_reset.438260271 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 5151140724 ps |
| CPU time | 8.39 seconds |
| Started | Aug 01 05:02:39 PM PDT 24 |
| Finished | Aug 01 05:02:48 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-5d80d93a-f785-4aed-8027-73371dfc3b87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=438260271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.438260271 |
| Directory | /workspace/141.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/143.uart_fifo_reset.512703377 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 143700079346 ps |
| CPU time | 44.78 seconds |
| Started | Aug 01 05:02:41 PM PDT 24 |
| Finished | Aug 01 05:03:26 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-e2327885-f7c1-4574-a68f-1a16aed2e0e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=512703377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.512703377 |
| Directory | /workspace/143.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/144.uart_fifo_reset.3999420040 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 62308427552 ps |
| CPU time | 76.66 seconds |
| Started | Aug 01 05:02:40 PM PDT 24 |
| Finished | Aug 01 05:03:57 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-477989d0-2d18-4967-8ecd-f98f9e1fe8fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999420040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.3999420040 |
| Directory | /workspace/144.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/146.uart_fifo_reset.1031236483 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 132925176962 ps |
| CPU time | 74.85 seconds |
| Started | Aug 01 05:02:42 PM PDT 24 |
| Finished | Aug 01 05:03:57 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-571cd513-d8de-41cf-95ca-b4600063632b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1031236483 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1031236483 |
| Directory | /workspace/146.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/147.uart_fifo_reset.3012425229 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 20497314347 ps |
| CPU time | 25.38 seconds |
| Started | Aug 01 05:02:55 PM PDT 24 |
| Finished | Aug 01 05:03:20 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-deddfb90-830c-41d8-869c-5b9b5a4e8130 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3012425229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3012425229 |
| Directory | /workspace/147.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/148.uart_fifo_reset.340229054 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 38839133325 ps |
| CPU time | 56.86 seconds |
| Started | Aug 01 05:02:54 PM PDT 24 |
| Finished | Aug 01 05:03:51 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-be95e51f-f478-483d-a2fd-ef498e686bd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340229054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.340229054 |
| Directory | /workspace/148.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/149.uart_fifo_reset.1435845287 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 163223539772 ps |
| CPU time | 64.8 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:57 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-3641b423-167e-4bc9-a580-271a77efd418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1435845287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.1435845287 |
| Directory | /workspace/149.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/15.uart_alert_test.4133275757 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 34819225 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:56:32 PM PDT 24 |
| Finished | Aug 01 04:56:33 PM PDT 24 |
| Peak memory | 194296 kb |
| Host | smart-340c9236-bbe7-433a-8dc9-6c84b71df064 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133275757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.4133275757 |
| Directory | /workspace/15.uart_alert_test/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_full.2576971510 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 82352824480 ps |
| CPU time | 134.57 seconds |
| Started | Aug 01 04:56:20 PM PDT 24 |
| Finished | Aug 01 04:58:34 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-3656e8fd-fcd0-45b9-9fb7-ff60244cc72c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2576971510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2576971510 |
| Directory | /workspace/15.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/15.uart_fifo_overflow.50476631 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 115169299878 ps |
| CPU time | 168.66 seconds |
| Started | Aug 01 04:56:17 PM PDT 24 |
| Finished | Aug 01 04:59:06 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-d851d5e1-31af-4ebf-ba76-b56a9132b63a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=50476631 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.50476631 |
| Directory | /workspace/15.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/15.uart_intr.1644594673 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11390609311 ps |
| CPU time | 1.85 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:56:20 PM PDT 24 |
| Peak memory | 198432 kb |
| Host | smart-69660d7c-f871-4530-b4bd-a2f31f51d065 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644594673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.1644594673 |
| Directory | /workspace/15.uart_intr/latest |
| Test location | /workspace/coverage/default/15.uart_long_xfer_wo_dly.2785158241 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 63636704447 ps |
| CPU time | 403.64 seconds |
| Started | Aug 01 04:56:35 PM PDT 24 |
| Finished | Aug 01 05:03:19 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-882038d4-589d-40ca-861d-99f8828a7726 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2785158241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.2785158241 |
| Directory | /workspace/15.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/15.uart_loopback.3193567367 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 8630569531 ps |
| CPU time | 14.52 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:56:46 PM PDT 24 |
| Peak memory | 198832 kb |
| Host | smart-38cb92eb-6840-41cc-a5d2-c13fe3e54eed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3193567367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3193567367 |
| Directory | /workspace/15.uart_loopback/latest |
| Test location | /workspace/coverage/default/15.uart_noise_filter.1002247710 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 73079979973 ps |
| CPU time | 132.45 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:58:31 PM PDT 24 |
| Peak memory | 208180 kb |
| Host | smart-c53f18fd-2d80-44e6-904a-9aba0d35e2e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1002247710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1002247710 |
| Directory | /workspace/15.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/15.uart_perf.1903268320 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 24161634940 ps |
| CPU time | 159.98 seconds |
| Started | Aug 01 04:56:29 PM PDT 24 |
| Finished | Aug 01 04:59:09 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-ee868f33-228b-4154-a942-c55ec2646a8d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1903268320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1903268320 |
| Directory | /workspace/15.uart_perf/latest |
| Test location | /workspace/coverage/default/15.uart_rx_oversample.2421714016 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 6231227339 ps |
| CPU time | 10.54 seconds |
| Started | Aug 01 04:56:18 PM PDT 24 |
| Finished | Aug 01 04:56:28 PM PDT 24 |
| Peak memory | 199108 kb |
| Host | smart-153ec89f-56ce-461f-854f-3a5a3fe2b7af |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2421714016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.2421714016 |
| Directory | /workspace/15.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/15.uart_rx_parity_err.3856575722 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 48441486242 ps |
| CPU time | 19.63 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:56:50 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-ea780f7d-17df-44d3-ba5f-4894a0ba06b5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3856575722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.3856575722 |
| Directory | /workspace/15.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/15.uart_rx_start_bit_filter.3807415866 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3774336464 ps |
| CPU time | 6.66 seconds |
| Started | Aug 01 04:56:33 PM PDT 24 |
| Finished | Aug 01 04:56:40 PM PDT 24 |
| Peak memory | 196324 kb |
| Host | smart-3ffb7b94-9646-4536-b294-a37c074b64a5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3807415866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.3807415866 |
| Directory | /workspace/15.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/15.uart_smoke.3071586982 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 462142439 ps |
| CPU time | 2.23 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 198700 kb |
| Host | smart-9b60b6cc-765f-4a66-8999-11aabe49891a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3071586982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.3071586982 |
| Directory | /workspace/15.uart_smoke/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all.2701406344 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 339024858643 ps |
| CPU time | 337.67 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 05:02:07 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-89c34010-ab8a-47df-9741-1f21bd1f7d91 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701406344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.2701406344 |
| Directory | /workspace/15.uart_stress_all/latest |
| Test location | /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2361601754 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 65030463339 ps |
| CPU time | 420.67 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 05:03:31 PM PDT 24 |
| Peak memory | 216388 kb |
| Host | smart-aeb38c10-ec73-4233-8c50-4c801eee9687 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361601754 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2361601754 |
| Directory | /workspace/15.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/15.uart_tx_ovrd.1785965648 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 1369041804 ps |
| CPU time | 2.5 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:56:32 PM PDT 24 |
| Peak memory | 199504 kb |
| Host | smart-4dd3e206-107e-4488-90f0-2f610cf4b20a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1785965648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1785965648 |
| Directory | /workspace/15.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/15.uart_tx_rx.1643835113 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 73256113501 ps |
| CPU time | 30.94 seconds |
| Started | Aug 01 04:56:19 PM PDT 24 |
| Finished | Aug 01 04:56:50 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-219be3c9-5799-4bdd-8313-64a74d96d437 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1643835113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.1643835113 |
| Directory | /workspace/15.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/150.uart_fifo_reset.3525034648 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 27770817226 ps |
| CPU time | 40.11 seconds |
| Started | Aug 01 05:02:55 PM PDT 24 |
| Finished | Aug 01 05:03:35 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-71d9c623-dc8f-4b85-9a05-590d56e6d737 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3525034648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.3525034648 |
| Directory | /workspace/150.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/151.uart_fifo_reset.1841057824 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 9463435773 ps |
| CPU time | 14.95 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:07 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-35d37228-3c3c-4d1c-b076-7831b86fc3c6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1841057824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.1841057824 |
| Directory | /workspace/151.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/152.uart_fifo_reset.2660090538 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 42202493923 ps |
| CPU time | 35.83 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:28 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-fbeecffe-fc13-4351-b384-90794d80d2a2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660090538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.2660090538 |
| Directory | /workspace/152.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/153.uart_fifo_reset.2723759931 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 162159747311 ps |
| CPU time | 190.26 seconds |
| Started | Aug 01 05:02:53 PM PDT 24 |
| Finished | Aug 01 05:06:04 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-7715ca15-4f34-4df2-a7f0-51e5b7b18690 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2723759931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2723759931 |
| Directory | /workspace/153.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/154.uart_fifo_reset.3630075070 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 74674887705 ps |
| CPU time | 21.03 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:13 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-9073bb85-a313-4af2-bb85-9bc51b66ca6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3630075070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.3630075070 |
| Directory | /workspace/154.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/155.uart_fifo_reset.2542411249 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 36820121296 ps |
| CPU time | 72.65 seconds |
| Started | Aug 01 05:02:55 PM PDT 24 |
| Finished | Aug 01 05:04:08 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-3870cee2-a6a7-4cab-8aae-04465a4d561a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542411249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2542411249 |
| Directory | /workspace/155.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/156.uart_fifo_reset.1356070991 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 110097792122 ps |
| CPU time | 167.53 seconds |
| Started | Aug 01 05:02:55 PM PDT 24 |
| Finished | Aug 01 05:05:42 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-d7169609-ab95-4d8a-8102-bb18b5bedf2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1356070991 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1356070991 |
| Directory | /workspace/156.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/157.uart_fifo_reset.3064867637 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 36947241941 ps |
| CPU time | 17.35 seconds |
| Started | Aug 01 05:02:53 PM PDT 24 |
| Finished | Aug 01 05:03:10 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-003a5f6a-0613-4665-8e58-62c381288dff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3064867637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.3064867637 |
| Directory | /workspace/157.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/159.uart_fifo_reset.540573172 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 16307798875 ps |
| CPU time | 27.31 seconds |
| Started | Aug 01 05:02:53 PM PDT 24 |
| Finished | Aug 01 05:03:21 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-90bfcb93-6412-4254-b29c-62adf5331f75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=540573172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.540573172 |
| Directory | /workspace/159.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_alert_test.3748987462 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 12123864 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:56:32 PM PDT 24 |
| Peak memory | 194648 kb |
| Host | smart-81ee349b-f4d5-4d98-93a2-e517d7aaa8f8 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748987462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3748987462 |
| Directory | /workspace/16.uart_alert_test/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_full.701725179 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 35148334829 ps |
| CPU time | 15.47 seconds |
| Started | Aug 01 04:56:33 PM PDT 24 |
| Finished | Aug 01 04:56:49 PM PDT 24 |
| Peak memory | 199564 kb |
| Host | smart-0362a3c8-a112-4cf8-bc4c-16a6a2312011 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=701725179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.701725179 |
| Directory | /workspace/16.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_overflow.1963171018 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 59875032286 ps |
| CPU time | 87.92 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:57:59 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-8f0298ea-c6ba-4d19-9c37-75ac846389cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1963171018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.1963171018 |
| Directory | /workspace/16.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/16.uart_fifo_reset.2581500751 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 52684165524 ps |
| CPU time | 20.3 seconds |
| Started | Aug 01 04:56:34 PM PDT 24 |
| Finished | Aug 01 04:56:55 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-e99a7084-68e3-4b07-8f40-c4d7572e6123 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2581500751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2581500751 |
| Directory | /workspace/16.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/16.uart_intr.914154271 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 149806615892 ps |
| CPU time | 23.22 seconds |
| Started | Aug 01 04:56:33 PM PDT 24 |
| Finished | Aug 01 04:56:57 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-fd41053a-ee0e-4185-b311-04d1f98fd13e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914154271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.914154271 |
| Directory | /workspace/16.uart_intr/latest |
| Test location | /workspace/coverage/default/16.uart_long_xfer_wo_dly.2123776885 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 90026409470 ps |
| CPU time | 138.89 seconds |
| Started | Aug 01 04:56:29 PM PDT 24 |
| Finished | Aug 01 04:58:48 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-4bb66807-e320-4692-b242-17b166334fe3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2123776885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.2123776885 |
| Directory | /workspace/16.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/16.uart_loopback.4234084700 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 12433110065 ps |
| CPU time | 22.56 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:56:53 PM PDT 24 |
| Peak memory | 199708 kb |
| Host | smart-05070130-2180-44e8-85e9-efdbd349f6bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4234084700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.4234084700 |
| Directory | /workspace/16.uart_loopback/latest |
| Test location | /workspace/coverage/default/16.uart_noise_filter.2046098721 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 52691458218 ps |
| CPU time | 81.09 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:57:51 PM PDT 24 |
| Peak memory | 208268 kb |
| Host | smart-be23077e-5254-4161-a9a4-6cde0f72cff5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2046098721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.2046098721 |
| Directory | /workspace/16.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/16.uart_rx_oversample.2534717490 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 6910015311 ps |
| CPU time | 12.69 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:56:43 PM PDT 24 |
| Peak memory | 198560 kb |
| Host | smart-4827c2bc-ca8b-4bc1-b366-5f2cc9545238 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2534717490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2534717490 |
| Directory | /workspace/16.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/16.uart_rx_parity_err.2213964726 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 228151706531 ps |
| CPU time | 135.77 seconds |
| Started | Aug 01 04:56:34 PM PDT 24 |
| Finished | Aug 01 04:58:50 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-c75242fa-4f50-435e-beb1-5a6b6b5c2221 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2213964726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2213964726 |
| Directory | /workspace/16.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/16.uart_rx_start_bit_filter.858484047 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 4298228879 ps |
| CPU time | 1.34 seconds |
| Started | Aug 01 04:56:29 PM PDT 24 |
| Finished | Aug 01 04:56:30 PM PDT 24 |
| Peak memory | 196360 kb |
| Host | smart-04b32a4b-1e65-46dd-8483-f8e5ea67b435 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=858484047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.858484047 |
| Directory | /workspace/16.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/16.uart_smoke.279235931 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 659960298 ps |
| CPU time | 2.54 seconds |
| Started | Aug 01 04:56:31 PM PDT 24 |
| Finished | Aug 01 04:56:34 PM PDT 24 |
| Peak memory | 198384 kb |
| Host | smart-f97b5797-e6f6-4698-83f6-35804142a788 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=279235931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.279235931 |
| Directory | /workspace/16.uart_smoke/latest |
| Test location | /workspace/coverage/default/16.uart_tx_ovrd.3789607833 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 6511731902 ps |
| CPU time | 23.24 seconds |
| Started | Aug 01 04:56:32 PM PDT 24 |
| Finished | Aug 01 04:56:55 PM PDT 24 |
| Peak memory | 198756 kb |
| Host | smart-9bd8cf84-609e-4317-aed8-135aad628a7c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3789607833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.3789607833 |
| Directory | /workspace/16.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/16.uart_tx_rx.2833243687 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 24357268678 ps |
| CPU time | 79.42 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:57:50 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-f4f6e1f6-3770-4001-b42b-d7e0599b2e59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2833243687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.2833243687 |
| Directory | /workspace/16.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/160.uart_fifo_reset.230496442 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 121447242136 ps |
| CPU time | 53.58 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:46 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-e126bcdb-8aac-4ac8-8cd4-2b6fe2d98062 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=230496442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.230496442 |
| Directory | /workspace/160.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/161.uart_fifo_reset.3030441373 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 87069860556 ps |
| CPU time | 38.51 seconds |
| Started | Aug 01 05:02:52 PM PDT 24 |
| Finished | Aug 01 05:03:31 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-3999a5aa-2a3d-4be7-a10f-f9778f51b4cc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3030441373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3030441373 |
| Directory | /workspace/161.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/162.uart_fifo_reset.3280034306 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 15270400188 ps |
| CPU time | 10.97 seconds |
| Started | Aug 01 05:02:55 PM PDT 24 |
| Finished | Aug 01 05:03:06 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-3814b98b-9060-46f5-8d10-92cfbdc31d2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3280034306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3280034306 |
| Directory | /workspace/162.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/163.uart_fifo_reset.1244785451 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 119624775885 ps |
| CPU time | 178.69 seconds |
| Started | Aug 01 05:02:53 PM PDT 24 |
| Finished | Aug 01 05:05:52 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-19c2cb32-df66-4441-aa51-ba16d8fc2243 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244785451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1244785451 |
| Directory | /workspace/163.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/164.uart_fifo_reset.1343961468 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 39223311866 ps |
| CPU time | 67.35 seconds |
| Started | Aug 01 05:02:57 PM PDT 24 |
| Finished | Aug 01 05:04:04 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-67517b41-1faf-4857-802a-ff21e16c99ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1343961468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1343961468 |
| Directory | /workspace/164.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/165.uart_fifo_reset.4237528907 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 99192430658 ps |
| CPU time | 236.35 seconds |
| Started | Aug 01 05:02:54 PM PDT 24 |
| Finished | Aug 01 05:06:51 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-b94673bf-fa56-424b-8b9c-59fc8474e86b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4237528907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.4237528907 |
| Directory | /workspace/165.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/166.uart_fifo_reset.1017551936 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 35711898840 ps |
| CPU time | 20.16 seconds |
| Started | Aug 01 05:02:54 PM PDT 24 |
| Finished | Aug 01 05:03:14 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-27c6c959-a0b9-4c3b-a3c4-17fd0c1c7678 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1017551936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1017551936 |
| Directory | /workspace/166.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/167.uart_fifo_reset.1009501941 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 47533461165 ps |
| CPU time | 43.97 seconds |
| Started | Aug 01 05:02:54 PM PDT 24 |
| Finished | Aug 01 05:03:38 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-c7eeeaf8-53a2-4f6b-b70c-1d4088c8acc4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1009501941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.1009501941 |
| Directory | /workspace/167.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/168.uart_fifo_reset.2612879310 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 67299761937 ps |
| CPU time | 105.5 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:04:50 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-d341e07b-c77f-479c-a814-594998ddc1c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2612879310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2612879310 |
| Directory | /workspace/168.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/169.uart_fifo_reset.2718412012 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 8279380368 ps |
| CPU time | 4.16 seconds |
| Started | Aug 01 05:03:05 PM PDT 24 |
| Finished | Aug 01 05:03:09 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-2afc8c8c-7ce8-4061-b824-f83a4b6bf72c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2718412012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.2718412012 |
| Directory | /workspace/169.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_alert_test.3032695651 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 47379292 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:56:42 PM PDT 24 |
| Finished | Aug 01 04:56:43 PM PDT 24 |
| Peak memory | 195188 kb |
| Host | smart-f4f05bdd-b944-4225-80a0-e7a1c103020d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032695651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.3032695651 |
| Directory | /workspace/17.uart_alert_test/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_full.1676957046 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 15970083298 ps |
| CPU time | 24.89 seconds |
| Started | Aug 01 04:56:34 PM PDT 24 |
| Finished | Aug 01 04:56:59 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-61294a6e-8877-4873-9b0e-af805f089ee6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676957046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.1676957046 |
| Directory | /workspace/17.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/17.uart_fifo_reset.1178088738 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 17810676850 ps |
| CPU time | 30.53 seconds |
| Started | Aug 01 04:56:32 PM PDT 24 |
| Finished | Aug 01 04:57:02 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-35d80eb6-7de7-41dd-8b84-f836d19e9539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1178088738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1178088738 |
| Directory | /workspace/17.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/17.uart_intr.1630662205 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 58118526267 ps |
| CPU time | 77.63 seconds |
| Started | Aug 01 04:56:41 PM PDT 24 |
| Finished | Aug 01 04:57:59 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-81b4d58e-c615-4796-8ab1-1db3dbc3cadf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630662205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1630662205 |
| Directory | /workspace/17.uart_intr/latest |
| Test location | /workspace/coverage/default/17.uart_long_xfer_wo_dly.1810634357 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 236193018065 ps |
| CPU time | 235.4 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 05:00:35 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-401483ca-235b-40f2-b845-a0b653f5fbda |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1810634357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1810634357 |
| Directory | /workspace/17.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/17.uart_loopback.1113643823 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 1189421482 ps |
| CPU time | 2.34 seconds |
| Started | Aug 01 04:56:41 PM PDT 24 |
| Finished | Aug 01 04:56:43 PM PDT 24 |
| Peak memory | 195328 kb |
| Host | smart-e23b62f5-621b-445a-8c84-37fdcc613d6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1113643823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1113643823 |
| Directory | /workspace/17.uart_loopback/latest |
| Test location | /workspace/coverage/default/17.uart_noise_filter.1436550319 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 37693848794 ps |
| CPU time | 55.13 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:57:36 PM PDT 24 |
| Peak memory | 198884 kb |
| Host | smart-0314a5a1-f7a0-4363-ac40-cffa71e8fdeb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1436550319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1436550319 |
| Directory | /workspace/17.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/17.uart_perf.4139640801 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 16540848522 ps |
| CPU time | 915.43 seconds |
| Started | Aug 01 04:56:39 PM PDT 24 |
| Finished | Aug 01 05:11:54 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-3c02b7dd-972e-4c6d-b2ee-f997e2ddc770 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4139640801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.4139640801 |
| Directory | /workspace/17.uart_perf/latest |
| Test location | /workspace/coverage/default/17.uart_rx_oversample.3920744852 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2439220536 ps |
| CPU time | 16.07 seconds |
| Started | Aug 01 04:56:41 PM PDT 24 |
| Finished | Aug 01 04:56:57 PM PDT 24 |
| Peak memory | 197680 kb |
| Host | smart-fa569580-f5d9-4863-84cc-936e5d7346b3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3920744852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.3920744852 |
| Directory | /workspace/17.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/17.uart_rx_parity_err.4150828773 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 91359756792 ps |
| CPU time | 71.21 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:57:52 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-c2c3879a-5768-4a76-b26c-8a5d3a2ed499 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150828773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.4150828773 |
| Directory | /workspace/17.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/17.uart_rx_start_bit_filter.3898869509 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 4932646651 ps |
| CPU time | 1.73 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:56:42 PM PDT 24 |
| Peak memory | 195988 kb |
| Host | smart-76b1a0cc-12d2-42ba-b49b-7e24ad02f379 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3898869509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.3898869509 |
| Directory | /workspace/17.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/17.uart_smoke.687955595 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 650739906 ps |
| CPU time | 3.3 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:56:33 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-aee2f780-fc95-471b-8fb1-fc388917ff4f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=687955595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.687955595 |
| Directory | /workspace/17.uart_smoke/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all.2761025083 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 64780100479 ps |
| CPU time | 177.97 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:59:38 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-e8eb236c-a422-4c18-88b2-8f64c0172a83 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761025083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2761025083 |
| Directory | /workspace/17.uart_stress_all/latest |
| Test location | /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1889062918 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 75659559971 ps |
| CPU time | 176.21 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:59:36 PM PDT 24 |
| Peak memory | 216460 kb |
| Host | smart-de18ac8a-0738-46f2-a97c-7f4071f1fc70 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889062918 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1889062918 |
| Directory | /workspace/17.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/17.uart_tx_ovrd.3067403023 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 914564761 ps |
| CPU time | 4.74 seconds |
| Started | Aug 01 04:56:40 PM PDT 24 |
| Finished | Aug 01 04:56:44 PM PDT 24 |
| Peak memory | 199500 kb |
| Host | smart-f17bab89-c3ac-468d-bebe-b1dbbe03b0d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3067403023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.3067403023 |
| Directory | /workspace/17.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/17.uart_tx_rx.2585277614 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 20052437329 ps |
| CPU time | 42.05 seconds |
| Started | Aug 01 04:56:30 PM PDT 24 |
| Finished | Aug 01 04:57:12 PM PDT 24 |
| Peak memory | 198988 kb |
| Host | smart-d6e31cae-121d-49c3-8c97-5736ac6d07ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2585277614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.2585277614 |
| Directory | /workspace/17.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/170.uart_fifo_reset.359098059 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 96423973804 ps |
| CPU time | 38.93 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:03:43 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-1e3cc95e-c77d-43cc-9802-0f5c87a42d68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=359098059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.359098059 |
| Directory | /workspace/170.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/172.uart_fifo_reset.659750344 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 84396179699 ps |
| CPU time | 33.93 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:03:38 PM PDT 24 |
| Peak memory | 199024 kb |
| Host | smart-262f42d7-f124-4c0a-83ea-94a4d1587ab5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=659750344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.659750344 |
| Directory | /workspace/172.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/173.uart_fifo_reset.2704834426 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 81118151454 ps |
| CPU time | 33.74 seconds |
| Started | Aug 01 05:03:03 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-4711ca27-c369-48ea-8807-30008ef7f8a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2704834426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2704834426 |
| Directory | /workspace/173.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/175.uart_fifo_reset.3171007749 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 39075512348 ps |
| CPU time | 85.99 seconds |
| Started | Aug 01 05:03:05 PM PDT 24 |
| Finished | Aug 01 05:04:31 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-0fbdaa16-1084-4a26-b75d-7f88da5ed78d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3171007749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3171007749 |
| Directory | /workspace/175.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/176.uart_fifo_reset.384216 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 25608308413 ps |
| CPU time | 34.43 seconds |
| Started | Aug 01 05:03:05 PM PDT 24 |
| Finished | Aug 01 05:03:40 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-04e87184-ae79-40f6-8ae9-498421df9ea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=384216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.384216 |
| Directory | /workspace/176.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/177.uart_fifo_reset.35941662 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 44644746967 ps |
| CPU time | 13.5 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:03:18 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-ef32a208-53e8-4c17-aa89-e701e57e3b54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=35941662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.35941662 |
| Directory | /workspace/177.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/178.uart_fifo_reset.115504086 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 92975909395 ps |
| CPU time | 29.77 seconds |
| Started | Aug 01 05:03:03 PM PDT 24 |
| Finished | Aug 01 05:03:33 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-84955343-baf5-498f-a0db-dd51aa40a0af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=115504086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.115504086 |
| Directory | /workspace/178.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_alert_test.2011474965 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 15313450 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:56:49 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-00d8563e-0946-4381-8eb6-b46a6b752658 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011474965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2011474965 |
| Directory | /workspace/18.uart_alert_test/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_full.1108507878 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 34326386952 ps |
| CPU time | 50.15 seconds |
| Started | Aug 01 04:56:41 PM PDT 24 |
| Finished | Aug 01 04:57:31 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-050cbc0b-c05e-4500-a829-41ec9d35da6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1108507878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.1108507878 |
| Directory | /workspace/18.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_overflow.1763058320 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 25559902033 ps |
| CPU time | 44.17 seconds |
| Started | Aug 01 04:56:42 PM PDT 24 |
| Finished | Aug 01 04:57:26 PM PDT 24 |
| Peak memory | 199628 kb |
| Host | smart-b2f3f0a6-5d49-4168-8664-7b4c0053ef87 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1763058320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1763058320 |
| Directory | /workspace/18.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/18.uart_fifo_reset.1777333977 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 93627503389 ps |
| CPU time | 131.57 seconds |
| Started | Aug 01 04:56:39 PM PDT 24 |
| Finished | Aug 01 04:58:51 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-adc8d01b-7c6e-4358-ac8e-b712ad0322ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1777333977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.1777333977 |
| Directory | /workspace/18.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/18.uart_intr.2669461207 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 58708631693 ps |
| CPU time | 31.45 seconds |
| Started | Aug 01 04:56:51 PM PDT 24 |
| Finished | Aug 01 04:57:22 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-a84c1cb2-c131-41fe-ae25-ec8ee4870dd8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669461207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.2669461207 |
| Directory | /workspace/18.uart_intr/latest |
| Test location | /workspace/coverage/default/18.uart_long_xfer_wo_dly.1013622063 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 91632766284 ps |
| CPU time | 128.23 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:58:58 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-063e24d0-7971-41c5-bffc-8f4309848489 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1013622063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1013622063 |
| Directory | /workspace/18.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/18.uart_loopback.81234994 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 1192237731 ps |
| CPU time | 1.14 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:56:50 PM PDT 24 |
| Peak memory | 195636 kb |
| Host | smart-a2b32d3a-0cee-48a2-8327-729bcf677a1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=81234994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.81234994 |
| Directory | /workspace/18.uart_loopback/latest |
| Test location | /workspace/coverage/default/18.uart_noise_filter.2514039931 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 114779836019 ps |
| CPU time | 208.5 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 05:00:18 PM PDT 24 |
| Peak memory | 199508 kb |
| Host | smart-e79b241c-a7e7-4cc8-86fd-08f94a30f28d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514039931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.2514039931 |
| Directory | /workspace/18.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/18.uart_perf.1160799840 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 18044998840 ps |
| CPU time | 883.71 seconds |
| Started | Aug 01 04:56:58 PM PDT 24 |
| Finished | Aug 01 05:11:42 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-ebb6d23b-93dc-490c-8f24-4b6be4eb4c05 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1160799840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.1160799840 |
| Directory | /workspace/18.uart_perf/latest |
| Test location | /workspace/coverage/default/18.uart_rx_oversample.610172842 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4018157518 ps |
| CPU time | 8.94 seconds |
| Started | Aug 01 04:56:45 PM PDT 24 |
| Finished | Aug 01 04:56:54 PM PDT 24 |
| Peak memory | 198904 kb |
| Host | smart-4c2ead39-c56b-4e0e-9150-cea1d2edf857 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=610172842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.610172842 |
| Directory | /workspace/18.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/18.uart_rx_parity_err.796523961 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 71618943333 ps |
| CPU time | 33.59 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:57:23 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-d7f6f50b-8e5e-40b6-8cbc-58e2e09f8a7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=796523961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.796523961 |
| Directory | /workspace/18.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/18.uart_rx_start_bit_filter.669592027 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 67354104663 ps |
| CPU time | 98.61 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:58:28 PM PDT 24 |
| Peak memory | 196004 kb |
| Host | smart-25e69bb8-35a4-48ca-a627-25373261c388 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=669592027 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.669592027 |
| Directory | /workspace/18.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/18.uart_smoke.1110186513 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 854048641 ps |
| CPU time | 2.42 seconds |
| Started | Aug 01 04:56:43 PM PDT 24 |
| Finished | Aug 01 04:56:45 PM PDT 24 |
| Peak memory | 198616 kb |
| Host | smart-fe95a523-f9eb-4414-beff-2c3a68af5d08 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110186513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.1110186513 |
| Directory | /workspace/18.uart_smoke/latest |
| Test location | /workspace/coverage/default/18.uart_stress_all.3264574255 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 302740014818 ps |
| CPU time | 492.04 seconds |
| Started | Aug 01 04:56:51 PM PDT 24 |
| Finished | Aug 01 05:05:03 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-2ece4534-7c9e-48dc-98f8-0c3c092fa930 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264574255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.3264574255 |
| Directory | /workspace/18.uart_stress_all/latest |
| Test location | /workspace/coverage/default/18.uart_tx_ovrd.1783144760 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 7315529131 ps |
| CPU time | 8.58 seconds |
| Started | Aug 01 04:56:54 PM PDT 24 |
| Finished | Aug 01 04:57:03 PM PDT 24 |
| Peak memory | 199092 kb |
| Host | smart-2eb07e52-bb4d-4f19-82e5-0f49f0550202 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1783144760 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1783144760 |
| Directory | /workspace/18.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/18.uart_tx_rx.717754997 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 21561817203 ps |
| CPU time | 36.79 seconds |
| Started | Aug 01 04:56:42 PM PDT 24 |
| Finished | Aug 01 04:57:18 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-bee4f80c-835c-433f-bc7c-60d8d43c8827 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=717754997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.717754997 |
| Directory | /workspace/18.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/181.uart_fifo_reset.1672839870 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 77228883504 ps |
| CPU time | 32.71 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-6dd6a269-4268-4cd7-ab32-11732d3fbae6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1672839870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1672839870 |
| Directory | /workspace/181.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/182.uart_fifo_reset.4017061474 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 65496741925 ps |
| CPU time | 111.53 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:04:55 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-36af766a-738b-4a42-b09a-193420faff66 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4017061474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.4017061474 |
| Directory | /workspace/182.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/183.uart_fifo_reset.383990251 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 189223731621 ps |
| CPU time | 72.27 seconds |
| Started | Aug 01 05:03:04 PM PDT 24 |
| Finished | Aug 01 05:04:17 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-d4c257f5-9633-470e-8302-0faa07646468 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=383990251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.383990251 |
| Directory | /workspace/183.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/185.uart_fifo_reset.2872856381 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 37748354380 ps |
| CPU time | 17.25 seconds |
| Started | Aug 01 05:03:15 PM PDT 24 |
| Finished | Aug 01 05:03:33 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-39f7f3fb-fdd2-472f-aa2a-b6251cbb1d57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2872856381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2872856381 |
| Directory | /workspace/185.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/186.uart_fifo_reset.504090927 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 59081812248 ps |
| CPU time | 53.73 seconds |
| Started | Aug 01 05:03:16 PM PDT 24 |
| Finished | Aug 01 05:04:10 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-f73c8a69-c241-4eb1-a433-8108c16304d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=504090927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.504090927 |
| Directory | /workspace/186.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/187.uart_fifo_reset.3632637520 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 70525297269 ps |
| CPU time | 181.09 seconds |
| Started | Aug 01 05:03:16 PM PDT 24 |
| Finished | Aug 01 05:06:17 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-4c943046-5d0d-4045-bf37-9aadb7810674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3632637520 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.3632637520 |
| Directory | /workspace/187.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/188.uart_fifo_reset.385421411 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 48947715187 ps |
| CPU time | 56.67 seconds |
| Started | Aug 01 05:03:15 PM PDT 24 |
| Finished | Aug 01 05:04:12 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-b1ef1df7-55de-4062-97b7-b928fd470f3b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=385421411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.385421411 |
| Directory | /workspace/188.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/189.uart_fifo_reset.3458007196 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 34890729380 ps |
| CPU time | 20.73 seconds |
| Started | Aug 01 05:03:16 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-081db555-1892-469f-bbcc-2f1409b8c053 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3458007196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.3458007196 |
| Directory | /workspace/189.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/19.uart_alert_test.1509470560 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 41886218 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:56:59 PM PDT 24 |
| Finished | Aug 01 04:56:59 PM PDT 24 |
| Peak memory | 194528 kb |
| Host | smart-8399313e-8ac9-4310-969e-bb8ebdaa096a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509470560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1509470560 |
| Directory | /workspace/19.uart_alert_test/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_full.1796877641 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 21142343586 ps |
| CPU time | 32.41 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:57:22 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-dcb100dc-3d76-402d-ab3f-ff1ab685a0e2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1796877641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1796877641 |
| Directory | /workspace/19.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/19.uart_fifo_overflow.728974647 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 65582973566 ps |
| CPU time | 23.17 seconds |
| Started | Aug 01 04:56:53 PM PDT 24 |
| Finished | Aug 01 04:57:17 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-b52eaf5f-57d1-4d9f-aad2-9de07ee0f5bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=728974647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.728974647 |
| Directory | /workspace/19.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/19.uart_intr.3065397696 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 67888913416 ps |
| CPU time | 30.88 seconds |
| Started | Aug 01 04:56:50 PM PDT 24 |
| Finished | Aug 01 04:57:21 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-db980635-9ef3-49b8-bac8-d2238e71cf0c |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065397696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3065397696 |
| Directory | /workspace/19.uart_intr/latest |
| Test location | /workspace/coverage/default/19.uart_long_xfer_wo_dly.670756479 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 70572717622 ps |
| CPU time | 447.14 seconds |
| Started | Aug 01 04:56:52 PM PDT 24 |
| Finished | Aug 01 05:04:19 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-01d38002-a66a-4add-92db-7c5577b1ecd2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=670756479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.670756479 |
| Directory | /workspace/19.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/19.uart_loopback.2172546307 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2492218780 ps |
| CPU time | 5.97 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:56:55 PM PDT 24 |
| Peak memory | 198508 kb |
| Host | smart-6a66910b-b4ed-49ac-b13b-1afa0fe2b26f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2172546307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2172546307 |
| Directory | /workspace/19.uart_loopback/latest |
| Test location | /workspace/coverage/default/19.uart_noise_filter.500299686 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 33418507491 ps |
| CPU time | 17.06 seconds |
| Started | Aug 01 04:56:48 PM PDT 24 |
| Finished | Aug 01 04:57:06 PM PDT 24 |
| Peak memory | 199916 kb |
| Host | smart-a715e40f-007f-4045-ab3d-ccce5144bf42 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=500299686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.500299686 |
| Directory | /workspace/19.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/19.uart_perf.4038143977 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 23461137553 ps |
| CPU time | 1076.11 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 05:14:45 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-89c9c939-70f3-4353-9ec0-fe4c90352b4e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4038143977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4038143977 |
| Directory | /workspace/19.uart_perf/latest |
| Test location | /workspace/coverage/default/19.uart_rx_oversample.2363857557 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 4981418607 ps |
| CPU time | 47.09 seconds |
| Started | Aug 01 04:56:52 PM PDT 24 |
| Finished | Aug 01 04:57:39 PM PDT 24 |
| Peak memory | 198400 kb |
| Host | smart-971fa99b-ad1c-465f-a13f-033f949e03d5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2363857557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2363857557 |
| Directory | /workspace/19.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/19.uart_rx_parity_err.306559245 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 78657707009 ps |
| CPU time | 38.37 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:57:27 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-22acbca5-48f9-47a0-9204-2c9f7a662c6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=306559245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.306559245 |
| Directory | /workspace/19.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/19.uart_rx_start_bit_filter.3902043981 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 39240888103 ps |
| CPU time | 58.58 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:57:48 PM PDT 24 |
| Peak memory | 195984 kb |
| Host | smart-09b47f8f-f761-46a4-8b2c-ab2c9f5fabbc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3902043981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3902043981 |
| Directory | /workspace/19.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/19.uart_smoke.2226928654 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 649111842 ps |
| CPU time | 3.4 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:56:53 PM PDT 24 |
| Peak memory | 199604 kb |
| Host | smart-688cfa2b-2ff8-4c60-a099-553e3a46397b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2226928654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2226928654 |
| Directory | /workspace/19.uart_smoke/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all.982924541 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 290976410614 ps |
| CPU time | 389.82 seconds |
| Started | Aug 01 04:57:03 PM PDT 24 |
| Finished | Aug 01 05:03:33 PM PDT 24 |
| Peak memory | 208200 kb |
| Host | smart-04c37d34-41fe-4ef4-86da-a4e8009e0751 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982924541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.982924541 |
| Directory | /workspace/19.uart_stress_all/latest |
| Test location | /workspace/coverage/default/19.uart_stress_all_with_rand_reset.1031443560 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 63692253564 ps |
| CPU time | 1455.12 seconds |
| Started | Aug 01 04:56:59 PM PDT 24 |
| Finished | Aug 01 05:21:15 PM PDT 24 |
| Peak memory | 216396 kb |
| Host | smart-ce8aa8a8-7120-488a-897e-df239a44ce8b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031443560 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.1031443560 |
| Directory | /workspace/19.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/19.uart_tx_ovrd.632158973 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 1921237157 ps |
| CPU time | 1.98 seconds |
| Started | Aug 01 04:56:49 PM PDT 24 |
| Finished | Aug 01 04:56:51 PM PDT 24 |
| Peak memory | 198476 kb |
| Host | smart-462a494a-2e03-4ff1-8879-7a1985bcd9cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632158973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.632158973 |
| Directory | /workspace/19.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/19.uart_tx_rx.3356665096 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 12764211434 ps |
| CPU time | 12.51 seconds |
| Started | Aug 01 04:56:50 PM PDT 24 |
| Finished | Aug 01 04:57:03 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-07bb35c1-0fce-4ff6-b4f2-818a67808bf9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3356665096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.3356665096 |
| Directory | /workspace/19.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/190.uart_fifo_reset.4001296733 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 134415382565 ps |
| CPU time | 92.22 seconds |
| Started | Aug 01 05:03:14 PM PDT 24 |
| Finished | Aug 01 05:04:47 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-01930a0e-7b64-40e0-869a-ee8dbcc92ad5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4001296733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.4001296733 |
| Directory | /workspace/190.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/191.uart_fifo_reset.954224211 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 9026096439 ps |
| CPU time | 4.83 seconds |
| Started | Aug 01 05:03:15 PM PDT 24 |
| Finished | Aug 01 05:03:20 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-0c5027e3-a508-4145-8f41-0d621428d9de |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=954224211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.954224211 |
| Directory | /workspace/191.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/192.uart_fifo_reset.4131912069 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 104378993453 ps |
| CPU time | 26.66 seconds |
| Started | Aug 01 05:03:15 PM PDT 24 |
| Finished | Aug 01 05:03:41 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-e89e61ae-9dd0-4167-a6fb-433e1762f594 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4131912069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.4131912069 |
| Directory | /workspace/192.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/194.uart_fifo_reset.3027529155 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 18542365468 ps |
| CPU time | 15.73 seconds |
| Started | Aug 01 05:03:17 PM PDT 24 |
| Finished | Aug 01 05:03:33 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-08ccd101-6c63-4091-8a8b-37772ae5a3aa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3027529155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3027529155 |
| Directory | /workspace/194.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/195.uart_fifo_reset.195759913 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 200574951791 ps |
| CPU time | 349.73 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:09:16 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-43c444f4-00ca-41d9-a2ac-9ba87b20524c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=195759913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.195759913 |
| Directory | /workspace/195.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/196.uart_fifo_reset.155994664 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 21159754903 ps |
| CPU time | 15.48 seconds |
| Started | Aug 01 05:03:29 PM PDT 24 |
| Finished | Aug 01 05:03:45 PM PDT 24 |
| Peak memory | 199152 kb |
| Host | smart-14720c78-2da5-4e1d-9494-ec0438afc5fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=155994664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.155994664 |
| Directory | /workspace/196.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/197.uart_fifo_reset.3689879660 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 39325866721 ps |
| CPU time | 42.2 seconds |
| Started | Aug 01 05:03:26 PM PDT 24 |
| Finished | Aug 01 05:04:08 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-4fd8b7f4-b0cd-4455-920a-5dc77aba7ef2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3689879660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.3689879660 |
| Directory | /workspace/197.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/198.uart_fifo_reset.1582550215 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 140905587950 ps |
| CPU time | 204.32 seconds |
| Started | Aug 01 05:03:28 PM PDT 24 |
| Finished | Aug 01 05:06:52 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-ff7c1e73-ace2-4e62-bacc-8cc854576219 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1582550215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1582550215 |
| Directory | /workspace/198.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/199.uart_fifo_reset.1930878442 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 20237109714 ps |
| CPU time | 32.53 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:04:00 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-bde26444-7b80-40b2-878e-310c9ae0a098 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1930878442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1930878442 |
| Directory | /workspace/199.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_alert_test.546859270 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 11713836 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 194152 kb |
| Host | smart-d3ec3091-afe8-4ace-a5e2-1c717093445b |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546859270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.546859270 |
| Directory | /workspace/2.uart_alert_test/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_full.2713461419 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 255654881625 ps |
| CPU time | 50.81 seconds |
| Started | Aug 01 04:54:59 PM PDT 24 |
| Finished | Aug 01 04:55:50 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-7e2e9d7e-107d-4e5e-a730-f3f52875028b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2713461419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.2713461419 |
| Directory | /workspace/2.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_overflow.952959669 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 51632167733 ps |
| CPU time | 65.72 seconds |
| Started | Aug 01 04:54:59 PM PDT 24 |
| Finished | Aug 01 04:56:05 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-4619111a-a44f-424b-a0b2-57634cf5b1c8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952959669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.952959669 |
| Directory | /workspace/2.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/2.uart_fifo_reset.3962142430 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 14532559567 ps |
| CPU time | 32.15 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:32 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-caafd2da-ac5b-45d2-9575-e9484f2b07f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3962142430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.3962142430 |
| Directory | /workspace/2.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/2.uart_intr.2187474895 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 80223784753 ps |
| CPU time | 125.94 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:57:18 PM PDT 24 |
| Peak memory | 196392 kb |
| Host | smart-6ee18518-26ee-4616-b5a6-89f6cde389c3 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187474895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.2187474895 |
| Directory | /workspace/2.uart_intr/latest |
| Test location | /workspace/coverage/default/2.uart_long_xfer_wo_dly.2627022052 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 82443892627 ps |
| CPU time | 195.59 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:58:27 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-53756d8b-76da-4a63-8081-81a703ba7da2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2627022052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2627022052 |
| Directory | /workspace/2.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/2.uart_loopback.3348891065 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 5707398455 ps |
| CPU time | 10.67 seconds |
| Started | Aug 01 04:55:15 PM PDT 24 |
| Finished | Aug 01 04:55:26 PM PDT 24 |
| Peak memory | 199552 kb |
| Host | smart-f6592f65-7ab3-40a0-af39-4c5e86782a5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3348891065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.3348891065 |
| Directory | /workspace/2.uart_loopback/latest |
| Test location | /workspace/coverage/default/2.uart_noise_filter.3409903006 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 475610441747 ps |
| CPU time | 52.24 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:56:05 PM PDT 24 |
| Peak memory | 208112 kb |
| Host | smart-2875fad9-89c3-4c36-a308-2cb7212c6b0d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3409903006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3409903006 |
| Directory | /workspace/2.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/2.uart_perf.3801326768 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4661962443 ps |
| CPU time | 127.33 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:57:22 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-cc540084-0c34-4718-9ad1-ac87f0ace7d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3801326768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.3801326768 |
| Directory | /workspace/2.uart_perf/latest |
| Test location | /workspace/coverage/default/2.uart_rx_oversample.3756565373 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3714605930 ps |
| CPU time | 26.75 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:28 PM PDT 24 |
| Peak memory | 197984 kb |
| Host | smart-52af2043-f07a-4b9e-8ba0-54106fd6ac5c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3756565373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.3756565373 |
| Directory | /workspace/2.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/2.uart_rx_parity_err.3279077375 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 69506937617 ps |
| CPU time | 30.72 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:43 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-a84dc157-ac3b-473f-a37e-c1fff8330bc6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279077375 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.3279077375 |
| Directory | /workspace/2.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/2.uart_rx_start_bit_filter.1486336827 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5312503121 ps |
| CPU time | 1.78 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:13 PM PDT 24 |
| Peak memory | 196292 kb |
| Host | smart-18426ce4-de6d-44f0-ab15-27d159f814f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1486336827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.1486336827 |
| Directory | /workspace/2.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/2.uart_sec_cm.1311147809 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 591319398 ps |
| CPU time | 0.86 seconds |
| Started | Aug 01 04:55:17 PM PDT 24 |
| Finished | Aug 01 04:55:18 PM PDT 24 |
| Peak memory | 218316 kb |
| Host | smart-dd5a00c5-3bfb-45fa-a8a1-e80f6ea29712 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311147809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.1311147809 |
| Directory | /workspace/2.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/2.uart_smoke.3374584200 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 441725688 ps |
| CPU time | 1.47 seconds |
| Started | Aug 01 04:55:00 PM PDT 24 |
| Finished | Aug 01 04:55:01 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-5f4e457e-5d09-4439-a6e3-ddfce875e91c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374584200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3374584200 |
| Directory | /workspace/2.uart_smoke/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all.4291920572 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 458902942656 ps |
| CPU time | 201.19 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:58:33 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-f0e079de-7a64-4e5c-9f34-06c2ca8c9603 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291920572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.4291920572 |
| Directory | /workspace/2.uart_stress_all/latest |
| Test location | /workspace/coverage/default/2.uart_stress_all_with_rand_reset.806729393 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 19380290230 ps |
| CPU time | 476.58 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 05:03:10 PM PDT 24 |
| Peak memory | 215752 kb |
| Host | smart-76df7a7a-5106-4671-995f-a174f588c62d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806729393 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.806729393 |
| Directory | /workspace/2.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.uart_tx_ovrd.3598054506 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 896964418 ps |
| CPU time | 2.52 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 198192 kb |
| Host | smart-8e60db58-dbd1-46db-bb6b-b92d39f47b13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3598054506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3598054506 |
| Directory | /workspace/2.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/2.uart_tx_rx.3174867264 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 37896547104 ps |
| CPU time | 26.79 seconds |
| Started | Aug 01 04:55:01 PM PDT 24 |
| Finished | Aug 01 04:55:28 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-8030a0be-ec9d-4106-80be-87e56e25a333 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3174867264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3174867264 |
| Directory | /workspace/2.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/20.uart_alert_test.1442061955 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 44307124 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:02 PM PDT 24 |
| Peak memory | 195500 kb |
| Host | smart-1434b911-8d2f-4d7c-a2e4-4c197946256a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442061955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.1442061955 |
| Directory | /workspace/20.uart_alert_test/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_full.3039608596 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 103959181011 ps |
| CPU time | 192.02 seconds |
| Started | Aug 01 04:57:00 PM PDT 24 |
| Finished | Aug 01 05:00:12 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-3937198c-65ba-49f7-9b1a-409fef4a1bd7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039608596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.3039608596 |
| Directory | /workspace/20.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/20.uart_fifo_reset.3872555396 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 15094167460 ps |
| CPU time | 26.44 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:28 PM PDT 24 |
| Peak memory | 199624 kb |
| Host | smart-1ba3d8c6-614c-4853-a7ed-e5aae2d98385 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3872555396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3872555396 |
| Directory | /workspace/20.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/20.uart_intr.4284482390 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 50070331388 ps |
| CPU time | 20.5 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:22 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-92024ad9-4788-45a0-9771-4d61d6aededa |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284482390 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.4284482390 |
| Directory | /workspace/20.uart_intr/latest |
| Test location | /workspace/coverage/default/20.uart_long_xfer_wo_dly.453172448 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 145808372350 ps |
| CPU time | 436.37 seconds |
| Started | Aug 01 04:57:00 PM PDT 24 |
| Finished | Aug 01 05:04:17 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-1460d447-0095-46ad-8bfe-03e5bd6a17d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=453172448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.453172448 |
| Directory | /workspace/20.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/20.uart_loopback.48097854 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 8444293711 ps |
| CPU time | 8.3 seconds |
| Started | Aug 01 04:56:59 PM PDT 24 |
| Finished | Aug 01 04:57:08 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-646f963d-bd36-4925-b977-b5a9ffd9612d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48097854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.48097854 |
| Directory | /workspace/20.uart_loopback/latest |
| Test location | /workspace/coverage/default/20.uart_noise_filter.2838962857 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 35858816771 ps |
| CPU time | 19.68 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:21 PM PDT 24 |
| Peak memory | 198756 kb |
| Host | smart-85ce8b10-2374-4d42-b2b2-c0a40552a996 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2838962857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.2838962857 |
| Directory | /workspace/20.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/20.uart_perf.3436228450 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 7567390106 ps |
| CPU time | 446.55 seconds |
| Started | Aug 01 04:57:03 PM PDT 24 |
| Finished | Aug 01 05:04:30 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-35d404b9-fe76-4d78-b856-d0968c7f0a9b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3436228450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.3436228450 |
| Directory | /workspace/20.uart_perf/latest |
| Test location | /workspace/coverage/default/20.uart_rx_oversample.3296424421 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 4020705976 ps |
| CPU time | 10.49 seconds |
| Started | Aug 01 04:57:03 PM PDT 24 |
| Finished | Aug 01 04:57:14 PM PDT 24 |
| Peak memory | 197944 kb |
| Host | smart-c3f9326e-1d43-45dd-b65f-14b358f56d64 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3296424421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.3296424421 |
| Directory | /workspace/20.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/20.uart_rx_parity_err.713619435 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 9420565901 ps |
| CPU time | 14.18 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:16 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-571006fe-4c1f-4bb1-bca0-f8bf6c92f9c3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713619435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.713619435 |
| Directory | /workspace/20.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/20.uart_rx_start_bit_filter.1456078069 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 4455075160 ps |
| CPU time | 1.22 seconds |
| Started | Aug 01 04:57:00 PM PDT 24 |
| Finished | Aug 01 04:57:02 PM PDT 24 |
| Peak memory | 196728 kb |
| Host | smart-5b3cae8d-7982-4432-85f5-8ab52d13bebf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1456078069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.1456078069 |
| Directory | /workspace/20.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/20.uart_smoke.3160699540 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 5684498293 ps |
| CPU time | 19.85 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 04:57:21 PM PDT 24 |
| Peak memory | 199252 kb |
| Host | smart-61452d60-e672-488e-b167-23d3ce8702f9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3160699540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3160699540 |
| Directory | /workspace/20.uart_smoke/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all.2140971187 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 100471478357 ps |
| CPU time | 144.46 seconds |
| Started | Aug 01 04:57:04 PM PDT 24 |
| Finished | Aug 01 04:59:28 PM PDT 24 |
| Peak memory | 208068 kb |
| Host | smart-f712d501-effc-4a58-802d-da8d513609ad |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140971187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2140971187 |
| Directory | /workspace/20.uart_stress_all/latest |
| Test location | /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2231927917 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 363331903749 ps |
| CPU time | 959.63 seconds |
| Started | Aug 01 04:57:01 PM PDT 24 |
| Finished | Aug 01 05:13:02 PM PDT 24 |
| Peak memory | 224704 kb |
| Host | smart-ea7a493f-8d2e-458d-9931-aa6671fbb80e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231927917 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2231927917 |
| Directory | /workspace/20.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/20.uart_tx_ovrd.2851041981 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 2049660623 ps |
| CPU time | 2.1 seconds |
| Started | Aug 01 04:56:59 PM PDT 24 |
| Finished | Aug 01 04:57:01 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-eb7f85b0-4bf6-4c2d-b70f-39f01de52722 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2851041981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.2851041981 |
| Directory | /workspace/20.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/20.uart_tx_rx.2812674989 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 129060056817 ps |
| CPU time | 294.46 seconds |
| Started | Aug 01 04:56:59 PM PDT 24 |
| Finished | Aug 01 05:01:54 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-e19cd069-ce5e-4ba2-a728-ce61e4cd3b6c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2812674989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.2812674989 |
| Directory | /workspace/20.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/201.uart_fifo_reset.3797911166 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 21350402871 ps |
| CPU time | 9.68 seconds |
| Started | Aug 01 05:03:28 PM PDT 24 |
| Finished | Aug 01 05:03:38 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-779201d5-98c0-4a1f-917b-3431fa058964 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797911166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3797911166 |
| Directory | /workspace/201.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/202.uart_fifo_reset.177172693 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 80539752006 ps |
| CPU time | 33.41 seconds |
| Started | Aug 01 05:03:29 PM PDT 24 |
| Finished | Aug 01 05:04:03 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-cc77d074-65b9-4255-94a2-e8883479b45d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177172693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.177172693 |
| Directory | /workspace/202.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/203.uart_fifo_reset.2660651125 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 67637726446 ps |
| CPU time | 27.38 seconds |
| Started | Aug 01 05:03:26 PM PDT 24 |
| Finished | Aug 01 05:03:54 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-c4d290f7-c15e-43e4-b2c5-a232a26138bb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2660651125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.2660651125 |
| Directory | /workspace/203.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/204.uart_fifo_reset.1678813961 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 119371717766 ps |
| CPU time | 101.86 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:05:09 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-f6082ed9-00d8-4d95-b94a-8a72c497dddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1678813961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1678813961 |
| Directory | /workspace/204.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/205.uart_fifo_reset.2356920124 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 65444330711 ps |
| CPU time | 11.86 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:03:39 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-8d03d03e-d125-4ffc-9614-492eca27863e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2356920124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.2356920124 |
| Directory | /workspace/205.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/206.uart_fifo_reset.1815454608 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 47337348262 ps |
| CPU time | 65.34 seconds |
| Started | Aug 01 05:03:29 PM PDT 24 |
| Finished | Aug 01 05:04:35 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-ff738be8-f851-484c-b68b-6d41e00b7aa0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1815454608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.1815454608 |
| Directory | /workspace/206.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/207.uart_fifo_reset.2140279781 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 97075003927 ps |
| CPU time | 65.5 seconds |
| Started | Aug 01 05:03:26 PM PDT 24 |
| Finished | Aug 01 05:04:32 PM PDT 24 |
| Peak memory | 199536 kb |
| Host | smart-e0a032f6-7431-48d8-9a54-4e989e017db0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2140279781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2140279781 |
| Directory | /workspace/207.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/208.uart_fifo_reset.262917559 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 113300779150 ps |
| CPU time | 46.19 seconds |
| Started | Aug 01 05:03:28 PM PDT 24 |
| Finished | Aug 01 05:04:14 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-d8064be3-257f-4ad3-a918-6e4141ba23d6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=262917559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.262917559 |
| Directory | /workspace/208.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/209.uart_fifo_reset.209310748 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 55956934569 ps |
| CPU time | 38.85 seconds |
| Started | Aug 01 05:03:27 PM PDT 24 |
| Finished | Aug 01 05:04:06 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-402e32e2-0f2f-4f2e-998c-acf582e5d19e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=209310748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.209310748 |
| Directory | /workspace/209.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_alert_test.2490576042 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 17491045 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:57:10 PM PDT 24 |
| Finished | Aug 01 04:57:11 PM PDT 24 |
| Peak memory | 194684 kb |
| Host | smart-df803160-7b8d-4d36-903f-f56101148d80 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490576042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.2490576042 |
| Directory | /workspace/21.uart_alert_test/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_full.177898056 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 19782652945 ps |
| CPU time | 34.52 seconds |
| Started | Aug 01 04:57:11 PM PDT 24 |
| Finished | Aug 01 04:57:46 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-e5420d94-d823-4b5e-a5cf-e00c24eade5f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=177898056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.177898056 |
| Directory | /workspace/21.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_overflow.3637132236 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 84852938503 ps |
| CPU time | 35.05 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 04:57:47 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-ae9d8f72-1762-44c5-9ee5-eaeded8a50dd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3637132236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.3637132236 |
| Directory | /workspace/21.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/21.uart_fifo_reset.55349423 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 21654107152 ps |
| CPU time | 13.78 seconds |
| Started | Aug 01 04:57:11 PM PDT 24 |
| Finished | Aug 01 04:57:25 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-d3bb3e07-b701-420f-98e6-f1e31e16785f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=55349423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.55349423 |
| Directory | /workspace/21.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/21.uart_intr.108047774 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 46820864166 ps |
| CPU time | 30.47 seconds |
| Started | Aug 01 04:57:11 PM PDT 24 |
| Finished | Aug 01 04:57:41 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-7f78335c-57d7-43d3-9de0-3c6c0f48871f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108047774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.108047774 |
| Directory | /workspace/21.uart_intr/latest |
| Test location | /workspace/coverage/default/21.uart_loopback.1313753855 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2465093685 ps |
| CPU time | 5.82 seconds |
| Started | Aug 01 04:57:11 PM PDT 24 |
| Finished | Aug 01 04:57:17 PM PDT 24 |
| Peak memory | 198456 kb |
| Host | smart-d5d3105c-eff1-496a-8663-61c8b2334972 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1313753855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1313753855 |
| Directory | /workspace/21.uart_loopback/latest |
| Test location | /workspace/coverage/default/21.uart_noise_filter.2846707389 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 137583697126 ps |
| CPU time | 156.79 seconds |
| Started | Aug 01 04:57:11 PM PDT 24 |
| Finished | Aug 01 04:59:48 PM PDT 24 |
| Peak memory | 215408 kb |
| Host | smart-324cd1b2-0752-4612-a1f4-dd8de2058765 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2846707389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.2846707389 |
| Directory | /workspace/21.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/21.uart_perf.3589437245 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 19866144844 ps |
| CPU time | 201.81 seconds |
| Started | Aug 01 04:57:13 PM PDT 24 |
| Finished | Aug 01 05:00:35 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-a9ce8a7e-d45f-4054-9482-8dbfa8609712 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3589437245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.3589437245 |
| Directory | /workspace/21.uart_perf/latest |
| Test location | /workspace/coverage/default/21.uart_rx_oversample.1055879219 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 1711006381 ps |
| CPU time | 1.99 seconds |
| Started | Aug 01 04:57:13 PM PDT 24 |
| Finished | Aug 01 04:57:15 PM PDT 24 |
| Peak memory | 198380 kb |
| Host | smart-8f11c1f0-0139-4ecc-9491-ac7c827403b4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1055879219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1055879219 |
| Directory | /workspace/21.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/21.uart_rx_parity_err.2061130038 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 123900108465 ps |
| CPU time | 84.45 seconds |
| Started | Aug 01 04:57:10 PM PDT 24 |
| Finished | Aug 01 04:58:35 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-a06ecd49-ee64-454b-b8cd-fa2d8f8686ec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2061130038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.2061130038 |
| Directory | /workspace/21.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/21.uart_rx_start_bit_filter.2110995561 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 3111330593 ps |
| CPU time | 1.62 seconds |
| Started | Aug 01 04:57:10 PM PDT 24 |
| Finished | Aug 01 04:57:12 PM PDT 24 |
| Peak memory | 196288 kb |
| Host | smart-bf97a29d-cf12-40e7-ae3b-bf2444925e9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2110995561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2110995561 |
| Directory | /workspace/21.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/21.uart_smoke.1291152999 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 519507002 ps |
| CPU time | 1.56 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 04:57:14 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-02bf0cb8-3dc6-4b72-a085-1f62b0b2f5bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1291152999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1291152999 |
| Directory | /workspace/21.uart_smoke/latest |
| Test location | /workspace/coverage/default/21.uart_stress_all.1643875144 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 195835210147 ps |
| CPU time | 584.46 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 05:06:56 PM PDT 24 |
| Peak memory | 216036 kb |
| Host | smart-919022de-fa2f-40cb-be95-cb5e6957ac09 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643875144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1643875144 |
| Directory | /workspace/21.uart_stress_all/latest |
| Test location | /workspace/coverage/default/21.uart_tx_ovrd.1419648335 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 7201352341 ps |
| CPU time | 17.55 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 04:57:30 PM PDT 24 |
| Peak memory | 199576 kb |
| Host | smart-98aad81a-be2b-4509-bcae-40da7bfc0a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1419648335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.1419648335 |
| Directory | /workspace/21.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/21.uart_tx_rx.714356204 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 37336156313 ps |
| CPU time | 14.49 seconds |
| Started | Aug 01 04:57:12 PM PDT 24 |
| Finished | Aug 01 04:57:26 PM PDT 24 |
| Peak memory | 197036 kb |
| Host | smart-51c32a3d-4bbb-4b63-ad95-0557e5b26619 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=714356204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.714356204 |
| Directory | /workspace/21.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/211.uart_fifo_reset.4076615766 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 184261980866 ps |
| CPU time | 16.89 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:03:54 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-502ad044-9415-4755-8c5d-4fd1acb115e4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4076615766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.4076615766 |
| Directory | /workspace/211.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/212.uart_fifo_reset.326741117 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 107648558274 ps |
| CPU time | 39.19 seconds |
| Started | Aug 01 05:03:38 PM PDT 24 |
| Finished | Aug 01 05:04:18 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-27885901-8cab-432d-94e2-74cb2e6e8de8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=326741117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.326741117 |
| Directory | /workspace/212.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/213.uart_fifo_reset.736542351 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 101467200836 ps |
| CPU time | 41.65 seconds |
| Started | Aug 01 05:03:38 PM PDT 24 |
| Finished | Aug 01 05:04:20 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-a2cdaf27-309d-4806-94d5-6d531286f923 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736542351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.736542351 |
| Directory | /workspace/213.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/215.uart_fifo_reset.1210117131 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 81658319260 ps |
| CPU time | 110.64 seconds |
| Started | Aug 01 05:03:41 PM PDT 24 |
| Finished | Aug 01 05:05:32 PM PDT 24 |
| Peak memory | 198924 kb |
| Host | smart-b37d37c3-9aaa-4309-8229-4787b68c6329 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1210117131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1210117131 |
| Directory | /workspace/215.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/216.uart_fifo_reset.3101759400 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 167973901135 ps |
| CPU time | 70.65 seconds |
| Started | Aug 01 05:03:39 PM PDT 24 |
| Finished | Aug 01 05:04:49 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-a2a20ab8-0fd0-4827-84b5-36ff9db732e9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3101759400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.3101759400 |
| Directory | /workspace/216.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/217.uart_fifo_reset.3740220421 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 158835353461 ps |
| CPU time | 99.09 seconds |
| Started | Aug 01 05:03:40 PM PDT 24 |
| Finished | Aug 01 05:05:19 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-d9dff457-ec93-4d70-af0d-1cfc9165258f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3740220421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.3740220421 |
| Directory | /workspace/217.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/218.uart_fifo_reset.3011904542 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 141069452491 ps |
| CPU time | 48.56 seconds |
| Started | Aug 01 05:03:36 PM PDT 24 |
| Finished | Aug 01 05:04:25 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-1270f613-521b-4b0b-bb10-6d07dd7cd0f0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3011904542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.3011904542 |
| Directory | /workspace/218.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/219.uart_fifo_reset.1211136415 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 61619463925 ps |
| CPU time | 65.6 seconds |
| Started | Aug 01 05:03:36 PM PDT 24 |
| Finished | Aug 01 05:04:42 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-59c5a979-b225-4334-825b-618817cae5f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1211136415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1211136415 |
| Directory | /workspace/219.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_alert_test.536767552 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 89417189 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:57:25 PM PDT 24 |
| Peak memory | 194440 kb |
| Host | smart-bc57fb82-1840-4d4f-baab-ddb00d28a49c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536767552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.536767552 |
| Directory | /workspace/22.uart_alert_test/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_full.1969794599 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 75361225319 ps |
| CPU time | 105.31 seconds |
| Started | Aug 01 04:57:25 PM PDT 24 |
| Finished | Aug 01 04:59:10 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-21bc930f-b8a0-41ab-8cb8-f55cb1f495d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1969794599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.1969794599 |
| Directory | /workspace/22.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_overflow.615248717 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 24472365041 ps |
| CPU time | 15.66 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:57:40 PM PDT 24 |
| Peak memory | 198944 kb |
| Host | smart-321ce56d-9839-4b0e-bc36-096ab00fbc29 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=615248717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.615248717 |
| Directory | /workspace/22.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/22.uart_fifo_reset.1362359366 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 212082103105 ps |
| CPU time | 144.71 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:59:48 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-3a21382e-f82a-4f63-853d-e05b9ef18073 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1362359366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1362359366 |
| Directory | /workspace/22.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/22.uart_intr.2284301807 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 37583414588 ps |
| CPU time | 53.68 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:58:17 PM PDT 24 |
| Peak memory | 199636 kb |
| Host | smart-ff926cb7-b34d-4739-9dff-41375da0b917 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284301807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.2284301807 |
| Directory | /workspace/22.uart_intr/latest |
| Test location | /workspace/coverage/default/22.uart_long_xfer_wo_dly.2228826664 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 141923956431 ps |
| CPU time | 217.29 seconds |
| Started | Aug 01 04:57:25 PM PDT 24 |
| Finished | Aug 01 05:01:02 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-96d2d8d0-9b3a-42fa-b12e-16af4795cfb1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2228826664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.2228826664 |
| Directory | /workspace/22.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/22.uart_loopback.2674385286 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2334176340 ps |
| CPU time | 5.27 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:57:29 PM PDT 24 |
| Peak memory | 198504 kb |
| Host | smart-c6a444d8-892d-4679-b26a-773f643b5c5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2674385286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.2674385286 |
| Directory | /workspace/22.uart_loopback/latest |
| Test location | /workspace/coverage/default/22.uart_noise_filter.607015079 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 28548771502 ps |
| CPU time | 54.02 seconds |
| Started | Aug 01 04:57:26 PM PDT 24 |
| Finished | Aug 01 04:58:20 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-65150821-e13a-4125-9517-13fa5f8b64b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=607015079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.607015079 |
| Directory | /workspace/22.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/22.uart_perf.2338856675 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 40694253975 ps |
| CPU time | 201.19 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 05:00:45 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-3d289cd1-16b5-4a8c-81c9-96edf7adbd76 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2338856675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.2338856675 |
| Directory | /workspace/22.uart_perf/latest |
| Test location | /workspace/coverage/default/22.uart_rx_oversample.3507184421 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 6873608209 ps |
| CPU time | 56.92 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:58:21 PM PDT 24 |
| Peak memory | 198564 kb |
| Host | smart-d0a269ea-da19-452b-ae8f-63a80b26cf84 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3507184421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.3507184421 |
| Directory | /workspace/22.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/22.uart_rx_parity_err.4146920983 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 14005870823 ps |
| CPU time | 19.56 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:57:43 PM PDT 24 |
| Peak memory | 198916 kb |
| Host | smart-baeb1f3b-2563-43f3-b5c4-c4401b0258c1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4146920983 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.4146920983 |
| Directory | /workspace/22.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/22.uart_rx_start_bit_filter.637989068 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 41597310031 ps |
| CPU time | 65.55 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:58:30 PM PDT 24 |
| Peak memory | 195812 kb |
| Host | smart-8900ab04-51e6-447d-806f-01a2020a6baf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=637989068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.637989068 |
| Directory | /workspace/22.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/22.uart_smoke.1718329539 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 498141357 ps |
| CPU time | 1.9 seconds |
| Started | Aug 01 04:57:10 PM PDT 24 |
| Finished | Aug 01 04:57:12 PM PDT 24 |
| Peak memory | 198604 kb |
| Host | smart-a1929c45-e2f0-47c5-8080-efc3fa9414f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1718329539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1718329539 |
| Directory | /workspace/22.uart_smoke/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all.3944757797 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 267103210121 ps |
| CPU time | 222.25 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 05:01:05 PM PDT 24 |
| Peak memory | 215276 kb |
| Host | smart-2eedaf9a-bfc6-4bb6-8a0c-077a33231643 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944757797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.3944757797 |
| Directory | /workspace/22.uart_stress_all/latest |
| Test location | /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3353553723 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 74882424723 ps |
| CPU time | 630.72 seconds |
| Started | Aug 01 04:57:22 PM PDT 24 |
| Finished | Aug 01 05:07:53 PM PDT 24 |
| Peak memory | 216432 kb |
| Host | smart-298c1f40-7e30-41df-92d8-1b74c282cf8c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353553723 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3353553723 |
| Directory | /workspace/22.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/22.uart_tx_ovrd.2040728548 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 3635369032 ps |
| CPU time | 1.33 seconds |
| Started | Aug 01 04:57:25 PM PDT 24 |
| Finished | Aug 01 04:57:26 PM PDT 24 |
| Peak memory | 198816 kb |
| Host | smart-99b39e33-e0ca-4a32-bf7e-199a7e301dcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2040728548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2040728548 |
| Directory | /workspace/22.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/22.uart_tx_rx.2234575663 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 74250073073 ps |
| CPU time | 57.61 seconds |
| Started | Aug 01 04:57:13 PM PDT 24 |
| Finished | Aug 01 04:58:11 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-4c848a1d-0774-4d47-bf0c-e6039511e8e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2234575663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.2234575663 |
| Directory | /workspace/22.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/220.uart_fifo_reset.644236770 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 16626353015 ps |
| CPU time | 6.96 seconds |
| Started | Aug 01 05:03:38 PM PDT 24 |
| Finished | Aug 01 05:03:45 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-55ac6585-88e9-4f51-a680-b81f472a234f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=644236770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.644236770 |
| Directory | /workspace/220.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/221.uart_fifo_reset.2892096452 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 43177708537 ps |
| CPU time | 62.45 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:04:40 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-09f99d4c-1ec8-4a91-b48f-c06a38abeea4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2892096452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.2892096452 |
| Directory | /workspace/221.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/222.uart_fifo_reset.3782037277 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 45614485413 ps |
| CPU time | 23.12 seconds |
| Started | Aug 01 05:03:39 PM PDT 24 |
| Finished | Aug 01 05:04:02 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-d18d2822-30a2-41ae-b891-0503ac2b1ddd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3782037277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3782037277 |
| Directory | /workspace/222.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/225.uart_fifo_reset.3150121124 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 98027027358 ps |
| CPU time | 161.86 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:06:19 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-0bf689d4-11cf-4a4e-bbed-9191ceed9e8c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3150121124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3150121124 |
| Directory | /workspace/225.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/226.uart_fifo_reset.1639954393 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 97091766903 ps |
| CPU time | 59.12 seconds |
| Started | Aug 01 05:03:41 PM PDT 24 |
| Finished | Aug 01 05:04:40 PM PDT 24 |
| Peak memory | 199004 kb |
| Host | smart-e2cb5062-670a-4cef-bde0-9bcb33206a84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1639954393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.1639954393 |
| Directory | /workspace/226.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/227.uart_fifo_reset.3667648081 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5763199114 ps |
| CPU time | 11.4 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:03:49 PM PDT 24 |
| Peak memory | 200080 kb |
| Host | smart-e5e98ca7-776d-4ee5-b03b-0b0f5ad054fc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3667648081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3667648081 |
| Directory | /workspace/227.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/228.uart_fifo_reset.2280639135 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 42107502212 ps |
| CPU time | 36.35 seconds |
| Started | Aug 01 05:03:39 PM PDT 24 |
| Finished | Aug 01 05:04:16 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-df100bc9-8d39-4e3a-b7fd-3bfc06da8564 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2280639135 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.2280639135 |
| Directory | /workspace/228.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/229.uart_fifo_reset.2815195220 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 119358161519 ps |
| CPU time | 160.01 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:06:17 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-25f34f1d-c5b5-454a-802e-8b7f5ec0204b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2815195220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.2815195220 |
| Directory | /workspace/229.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_alert_test.1158592079 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 12049728 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:57:41 PM PDT 24 |
| Finished | Aug 01 04:57:41 PM PDT 24 |
| Peak memory | 194656 kb |
| Host | smart-906f86e8-386b-4af5-8812-2c07c4bfcacc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158592079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1158592079 |
| Directory | /workspace/23.uart_alert_test/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_full.1884098405 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 232378226460 ps |
| CPU time | 170.79 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 05:00:15 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-85db3858-7e27-4c78-8614-720d6b586bab |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1884098405 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1884098405 |
| Directory | /workspace/23.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_overflow.2424628842 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 46992127466 ps |
| CPU time | 38.15 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:58:01 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-af5ffc2a-4328-437e-a62a-8b8cc54067b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2424628842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.2424628842 |
| Directory | /workspace/23.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/23.uart_fifo_reset.2167365381 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 17091042028 ps |
| CPU time | 31.55 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:57:55 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-3358374b-0aa5-48d3-aecf-61f38243a205 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2167365381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2167365381 |
| Directory | /workspace/23.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/23.uart_intr.3236518140 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 48237544495 ps |
| CPU time | 22.83 seconds |
| Started | Aug 01 04:57:26 PM PDT 24 |
| Finished | Aug 01 04:57:49 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-2e7d1fb5-f356-45fc-b8c8-30fab2810b94 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236518140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.3236518140 |
| Directory | /workspace/23.uart_intr/latest |
| Test location | /workspace/coverage/default/23.uart_long_xfer_wo_dly.1776428894 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 38244225868 ps |
| CPU time | 233.15 seconds |
| Started | Aug 01 04:57:40 PM PDT 24 |
| Finished | Aug 01 05:01:34 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-1267d5fc-029b-41e2-8596-de0e79fe7f8c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1776428894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1776428894 |
| Directory | /workspace/23.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/23.uart_loopback.1483270671 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 5999003435 ps |
| CPU time | 2.98 seconds |
| Started | Aug 01 04:57:36 PM PDT 24 |
| Finished | Aug 01 04:57:39 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-031ac7d3-ab29-4708-8634-d021e0053921 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1483270671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.1483270671 |
| Directory | /workspace/23.uart_loopback/latest |
| Test location | /workspace/coverage/default/23.uart_noise_filter.1720443942 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 79001120115 ps |
| CPU time | 127.04 seconds |
| Started | Aug 01 04:57:24 PM PDT 24 |
| Finished | Aug 01 04:59:31 PM PDT 24 |
| Peak memory | 198828 kb |
| Host | smart-a1fc006c-a1fb-4c3f-80ce-74d8936781cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1720443942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.1720443942 |
| Directory | /workspace/23.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/23.uart_perf.3812518730 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 19347947188 ps |
| CPU time | 331.48 seconds |
| Started | Aug 01 04:57:42 PM PDT 24 |
| Finished | Aug 01 05:03:14 PM PDT 24 |
| Peak memory | 200144 kb |
| Host | smart-503677ef-d2b6-4f57-9f2b-49f77e9eb56a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3812518730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.3812518730 |
| Directory | /workspace/23.uart_perf/latest |
| Test location | /workspace/coverage/default/23.uart_rx_oversample.2464037782 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 7196581921 ps |
| CPU time | 57.18 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:58:20 PM PDT 24 |
| Peak memory | 198576 kb |
| Host | smart-c732636d-5d25-4d72-9d59-1c8a21a0183d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2464037782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.2464037782 |
| Directory | /workspace/23.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/23.uart_rx_parity_err.205632800 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 89414361136 ps |
| CPU time | 131.58 seconds |
| Started | Aug 01 04:57:35 PM PDT 24 |
| Finished | Aug 01 04:59:47 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-74bfc35f-bb0a-4213-8242-1ce9cea1eab0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=205632800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.205632800 |
| Directory | /workspace/23.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/23.uart_rx_start_bit_filter.779128950 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 2633900716 ps |
| CPU time | 4.58 seconds |
| Started | Aug 01 04:57:34 PM PDT 24 |
| Finished | Aug 01 04:57:39 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-7c858480-c7a3-4aa0-9f36-a7e8b2007514 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=779128950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.779128950 |
| Directory | /workspace/23.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/23.uart_smoke.453586309 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 5825272434 ps |
| CPU time | 4.42 seconds |
| Started | Aug 01 04:57:25 PM PDT 24 |
| Finished | Aug 01 04:57:30 PM PDT 24 |
| Peak memory | 198812 kb |
| Host | smart-974c0e41-c95a-46ae-97af-5d0bf113be94 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=453586309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.453586309 |
| Directory | /workspace/23.uart_smoke/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all.4210383792 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 14557742520 ps |
| CPU time | 13.17 seconds |
| Started | Aug 01 04:57:42 PM PDT 24 |
| Finished | Aug 01 04:57:56 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-cd7e92b5-d220-487d-b5df-4dc6219228dc |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210383792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.4210383792 |
| Directory | /workspace/23.uart_stress_all/latest |
| Test location | /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3554138373 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 190055426282 ps |
| CPU time | 767.44 seconds |
| Started | Aug 01 04:57:34 PM PDT 24 |
| Finished | Aug 01 05:10:22 PM PDT 24 |
| Peak memory | 225764 kb |
| Host | smart-51f391e2-d007-4b27-93a2-b188ca61b04f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554138373 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3554138373 |
| Directory | /workspace/23.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/23.uart_tx_ovrd.248592591 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 2262846933 ps |
| CPU time | 3.19 seconds |
| Started | Aug 01 04:57:41 PM PDT 24 |
| Finished | Aug 01 04:57:44 PM PDT 24 |
| Peak memory | 198848 kb |
| Host | smart-957ae741-a85e-4c50-8290-1c21484544fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=248592591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.248592591 |
| Directory | /workspace/23.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/23.uart_tx_rx.3331755410 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 2152907638 ps |
| CPU time | 4.05 seconds |
| Started | Aug 01 04:57:23 PM PDT 24 |
| Finished | Aug 01 04:57:27 PM PDT 24 |
| Peak memory | 197600 kb |
| Host | smart-2549b69f-165a-471c-9584-d3883ff13e50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3331755410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.3331755410 |
| Directory | /workspace/23.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/230.uart_fifo_reset.2725148669 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 60522372677 ps |
| CPU time | 21.36 seconds |
| Started | Aug 01 05:03:39 PM PDT 24 |
| Finished | Aug 01 05:04:01 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-9594de4a-51dd-4aa7-aa77-22c026052e22 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2725148669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2725148669 |
| Directory | /workspace/230.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/231.uart_fifo_reset.2382884725 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 272640455414 ps |
| CPU time | 387.09 seconds |
| Started | Aug 01 05:03:38 PM PDT 24 |
| Finished | Aug 01 05:10:06 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-4da63ff8-9616-4919-b3a0-a712314638f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2382884725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2382884725 |
| Directory | /workspace/231.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/232.uart_fifo_reset.2310253467 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 88875341678 ps |
| CPU time | 79.71 seconds |
| Started | Aug 01 05:03:37 PM PDT 24 |
| Finished | Aug 01 05:04:57 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-78a3d29a-6395-49a3-935d-40190a10e4d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2310253467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.2310253467 |
| Directory | /workspace/232.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/233.uart_fifo_reset.2391199176 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 167266348389 ps |
| CPU time | 282.94 seconds |
| Started | Aug 01 05:03:36 PM PDT 24 |
| Finished | Aug 01 05:08:20 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-49cfcafe-c507-4933-b9e3-e07ddbe2a184 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2391199176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2391199176 |
| Directory | /workspace/233.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/234.uart_fifo_reset.2580146630 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 19279206898 ps |
| CPU time | 28.84 seconds |
| Started | Aug 01 05:03:50 PM PDT 24 |
| Finished | Aug 01 05:04:19 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-f0903cb1-f221-4c9d-837d-177473a193a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2580146630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2580146630 |
| Directory | /workspace/234.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/235.uart_fifo_reset.2259273127 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 225413982517 ps |
| CPU time | 162.35 seconds |
| Started | Aug 01 05:03:49 PM PDT 24 |
| Finished | Aug 01 05:06:31 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0ab364a5-9e49-463f-a6eb-c5bc1969a0ff |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2259273127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.2259273127 |
| Directory | /workspace/235.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/236.uart_fifo_reset.1150016586 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 28418122119 ps |
| CPU time | 21.7 seconds |
| Started | Aug 01 05:03:49 PM PDT 24 |
| Finished | Aug 01 05:04:11 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-47a14dac-97bc-48fb-8500-ee5e6db425b1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1150016586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.1150016586 |
| Directory | /workspace/236.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/237.uart_fifo_reset.150691164 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 116080531815 ps |
| CPU time | 153.79 seconds |
| Started | Aug 01 05:03:50 PM PDT 24 |
| Finished | Aug 01 05:06:24 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-194cdd8e-8601-4ac0-a962-625e5365e086 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=150691164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.150691164 |
| Directory | /workspace/237.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/238.uart_fifo_reset.915021757 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 66831396594 ps |
| CPU time | 95.93 seconds |
| Started | Aug 01 05:03:50 PM PDT 24 |
| Finished | Aug 01 05:05:26 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-b47e234c-49b1-420d-bf69-afc8b5a73571 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=915021757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.915021757 |
| Directory | /workspace/238.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/239.uart_fifo_reset.3294842990 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 90304118325 ps |
| CPU time | 35.23 seconds |
| Started | Aug 01 05:03:49 PM PDT 24 |
| Finished | Aug 01 05:04:24 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-f0d2c14c-fb01-4856-91a1-25332036cb54 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3294842990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3294842990 |
| Directory | /workspace/239.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_alert_test.4255322165 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 20383696 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:57:38 PM PDT 24 |
| Finished | Aug 01 04:57:39 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-df87d9ba-df8d-421e-ab76-a8962ae0a778 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255322165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.4255322165 |
| Directory | /workspace/24.uart_alert_test/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_full.3835165756 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 299779484192 ps |
| CPU time | 32.73 seconds |
| Started | Aug 01 04:57:35 PM PDT 24 |
| Finished | Aug 01 04:58:08 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-a46de9cb-2a50-4ac0-92a0-78668bce0815 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3835165756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.3835165756 |
| Directory | /workspace/24.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_overflow.3123590245 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 41332954445 ps |
| CPU time | 18.02 seconds |
| Started | Aug 01 04:57:37 PM PDT 24 |
| Finished | Aug 01 04:57:55 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-e35c5a1f-9190-4cea-9931-0fbe7cfdaa23 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3123590245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.3123590245 |
| Directory | /workspace/24.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/24.uart_fifo_reset.3194863498 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 12912160265 ps |
| CPU time | 27.37 seconds |
| Started | Aug 01 04:57:38 PM PDT 24 |
| Finished | Aug 01 04:58:06 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-fb682ed1-9018-4bf9-a007-d7d303aa6c50 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3194863498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.3194863498 |
| Directory | /workspace/24.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/24.uart_intr.2727900785 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 231473475490 ps |
| CPU time | 293.24 seconds |
| Started | Aug 01 04:57:35 PM PDT 24 |
| Finished | Aug 01 05:02:28 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-6ea76e22-75a9-49e8-9460-f60690367f6a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727900785 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2727900785 |
| Directory | /workspace/24.uart_intr/latest |
| Test location | /workspace/coverage/default/24.uart_long_xfer_wo_dly.1439071702 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 96530433703 ps |
| CPU time | 773.93 seconds |
| Started | Aug 01 04:57:40 PM PDT 24 |
| Finished | Aug 01 05:10:34 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-97c5462b-75e1-40d5-9b2e-8285a273e756 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1439071702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.1439071702 |
| Directory | /workspace/24.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/24.uart_loopback.204032658 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 1845508861 ps |
| CPU time | 4.8 seconds |
| Started | Aug 01 04:57:40 PM PDT 24 |
| Finished | Aug 01 04:57:45 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-b20e27ad-72b9-4273-bb40-618fed002738 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=204032658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.204032658 |
| Directory | /workspace/24.uart_loopback/latest |
| Test location | /workspace/coverage/default/24.uart_noise_filter.4048266479 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 78542875781 ps |
| CPU time | 30.29 seconds |
| Started | Aug 01 04:57:35 PM PDT 24 |
| Finished | Aug 01 04:58:05 PM PDT 24 |
| Peak memory | 199676 kb |
| Host | smart-559ca8ab-66f0-4172-ad86-f9d6b72ff54f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4048266479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.4048266479 |
| Directory | /workspace/24.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/24.uart_perf.3903763703 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 19730327329 ps |
| CPU time | 1094.94 seconds |
| Started | Aug 01 04:57:38 PM PDT 24 |
| Finished | Aug 01 05:15:54 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-2da6cf37-cc13-4e75-aa70-134d2dda200a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3903763703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.3903763703 |
| Directory | /workspace/24.uart_perf/latest |
| Test location | /workspace/coverage/default/24.uart_rx_oversample.1368252356 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 6852811401 ps |
| CPU time | 62.87 seconds |
| Started | Aug 01 04:57:39 PM PDT 24 |
| Finished | Aug 01 04:58:42 PM PDT 24 |
| Peak memory | 199056 kb |
| Host | smart-4f674ef2-68c7-4747-ac66-66e7efcff8a1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1368252356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1368252356 |
| Directory | /workspace/24.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/24.uart_rx_parity_err.3785975654 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 69209532258 ps |
| CPU time | 30.34 seconds |
| Started | Aug 01 04:57:37 PM PDT 24 |
| Finished | Aug 01 04:58:08 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-e2e75cd8-983b-4734-bd9e-959a24a99e41 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3785975654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3785975654 |
| Directory | /workspace/24.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/24.uart_rx_start_bit_filter.3678352358 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5242254875 ps |
| CPU time | 8.69 seconds |
| Started | Aug 01 04:57:37 PM PDT 24 |
| Finished | Aug 01 04:57:45 PM PDT 24 |
| Peak memory | 196160 kb |
| Host | smart-db82861f-8e7a-42a1-92e4-30a1bc61242c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3678352358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.3678352358 |
| Directory | /workspace/24.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/24.uart_smoke.3337624127 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 554816279 ps |
| CPU time | 2.21 seconds |
| Started | Aug 01 04:57:41 PM PDT 24 |
| Finished | Aug 01 04:57:43 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-b5341c74-ac48-4ea9-a523-73cb761c9c9f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3337624127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3337624127 |
| Directory | /workspace/24.uart_smoke/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all.52961072 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 213762163270 ps |
| CPU time | 254.15 seconds |
| Started | Aug 01 04:57:36 PM PDT 24 |
| Finished | Aug 01 05:01:51 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-9b4721dd-f7c7-4ce2-a857-72cb7cbda6b1 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52961072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.52961072 |
| Directory | /workspace/24.uart_stress_all/latest |
| Test location | /workspace/coverage/default/24.uart_stress_all_with_rand_reset.532445030 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 116131287416 ps |
| CPU time | 244.03 seconds |
| Started | Aug 01 04:57:42 PM PDT 24 |
| Finished | Aug 01 05:01:46 PM PDT 24 |
| Peak memory | 216640 kb |
| Host | smart-125ab568-26f5-4605-9d20-f8cda2359a63 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532445030 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.532445030 |
| Directory | /workspace/24.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/24.uart_tx_ovrd.535586957 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3502082916 ps |
| CPU time | 1.31 seconds |
| Started | Aug 01 04:57:41 PM PDT 24 |
| Finished | Aug 01 04:57:42 PM PDT 24 |
| Peak memory | 198832 kb |
| Host | smart-e3ced348-c5a4-4e31-9586-906ce551a89c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=535586957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.535586957 |
| Directory | /workspace/24.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/24.uart_tx_rx.3039922105 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 130435848333 ps |
| CPU time | 37.91 seconds |
| Started | Aug 01 04:57:41 PM PDT 24 |
| Finished | Aug 01 04:58:19 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-4eb258e2-1828-4ce7-9d2d-fcaeaef1d85f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3039922105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3039922105 |
| Directory | /workspace/24.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/241.uart_fifo_reset.3428557891 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 136248701245 ps |
| CPU time | 47.72 seconds |
| Started | Aug 01 05:03:47 PM PDT 24 |
| Finished | Aug 01 05:04:35 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-4b63e491-8fc0-4713-a849-895dfebac713 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3428557891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.3428557891 |
| Directory | /workspace/241.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/242.uart_fifo_reset.2542977506 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 42783927615 ps |
| CPU time | 13.43 seconds |
| Started | Aug 01 05:03:49 PM PDT 24 |
| Finished | Aug 01 05:04:02 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-401f128b-a884-4a79-abca-d35f257a3b84 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2542977506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2542977506 |
| Directory | /workspace/242.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/243.uart_fifo_reset.2623099924 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 38763345148 ps |
| CPU time | 72.15 seconds |
| Started | Aug 01 05:03:48 PM PDT 24 |
| Finished | Aug 01 05:05:01 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-e2b11fd9-c89d-4e7b-b2f1-653645f54e82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2623099924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.2623099924 |
| Directory | /workspace/243.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/244.uart_fifo_reset.3372927856 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 170344606410 ps |
| CPU time | 39.11 seconds |
| Started | Aug 01 05:03:50 PM PDT 24 |
| Finished | Aug 01 05:04:29 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-14cb68f5-e283-4930-a7e4-10bba7b6753a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3372927856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.3372927856 |
| Directory | /workspace/244.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/245.uart_fifo_reset.1780168863 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 172126885975 ps |
| CPU time | 434.78 seconds |
| Started | Aug 01 05:03:51 PM PDT 24 |
| Finished | Aug 01 05:11:06 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-590f1161-59c6-4802-a2d9-65399fc0223b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1780168863 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1780168863 |
| Directory | /workspace/245.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/246.uart_fifo_reset.2214286003 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 296977750990 ps |
| CPU time | 24.63 seconds |
| Started | Aug 01 05:03:58 PM PDT 24 |
| Finished | Aug 01 05:04:22 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-1ec3700c-6ac0-4a2f-b457-0cdbf80f0ba0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214286003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.2214286003 |
| Directory | /workspace/246.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/247.uart_fifo_reset.3758338651 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 293895086307 ps |
| CPU time | 161.81 seconds |
| Started | Aug 01 05:03:58 PM PDT 24 |
| Finished | Aug 01 05:06:40 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-a4bae882-7354-42f1-a372-92a56445ecb8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3758338651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3758338651 |
| Directory | /workspace/247.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/249.uart_fifo_reset.3848709803 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 28747939790 ps |
| CPU time | 41.25 seconds |
| Started | Aug 01 05:03:59 PM PDT 24 |
| Finished | Aug 01 05:04:40 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-9235c9b6-f751-44fb-aeda-53c9c7b5b539 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848709803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.3848709803 |
| Directory | /workspace/249.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_alert_test.1080167513 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 32914253 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:57:52 PM PDT 24 |
| Finished | Aug 01 04:57:53 PM PDT 24 |
| Peak memory | 195180 kb |
| Host | smart-880e5796-f198-4d59-b56c-e63010049b79 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080167513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.1080167513 |
| Directory | /workspace/25.uart_alert_test/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_full.1965957396 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 109815406853 ps |
| CPU time | 129.97 seconds |
| Started | Aug 01 04:57:52 PM PDT 24 |
| Finished | Aug 01 05:00:02 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-f1ef4029-9316-436d-b286-92d3ac404087 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1965957396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.1965957396 |
| Directory | /workspace/25.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_overflow.3774663263 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 128049459866 ps |
| CPU time | 166.69 seconds |
| Started | Aug 01 04:57:56 PM PDT 24 |
| Finished | Aug 01 05:00:43 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-3af38d36-160c-4a6b-b3cd-d35293fe6571 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3774663263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.3774663263 |
| Directory | /workspace/25.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/25.uart_fifo_reset.736276409 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 197675341748 ps |
| CPU time | 44.25 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:58:33 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-9f7e8486-aaae-4b54-b550-f3e9eaf8bec0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=736276409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.736276409 |
| Directory | /workspace/25.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/25.uart_intr.2423876458 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 57987405543 ps |
| CPU time | 42.34 seconds |
| Started | Aug 01 04:57:47 PM PDT 24 |
| Finished | Aug 01 04:58:29 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-e080035c-c41a-4b9f-bff5-86657a071f92 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423876458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.2423876458 |
| Directory | /workspace/25.uart_intr/latest |
| Test location | /workspace/coverage/default/25.uart_long_xfer_wo_dly.2198792737 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 139624267949 ps |
| CPU time | 570.04 seconds |
| Started | Aug 01 04:57:51 PM PDT 24 |
| Finished | Aug 01 05:07:22 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-43f3f110-ac42-4d68-8126-d6b76e5b2a04 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2198792737 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2198792737 |
| Directory | /workspace/25.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/25.uart_loopback.92831922 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 3735490622 ps |
| CPU time | 3.22 seconds |
| Started | Aug 01 04:58:06 PM PDT 24 |
| Finished | Aug 01 04:58:09 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-4b61e64b-75f0-49a5-9517-a440214b3681 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=92831922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.92831922 |
| Directory | /workspace/25.uart_loopback/latest |
| Test location | /workspace/coverage/default/25.uart_noise_filter.862985825 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 119211836471 ps |
| CPU time | 44.01 seconds |
| Started | Aug 01 04:57:52 PM PDT 24 |
| Finished | Aug 01 04:58:36 PM PDT 24 |
| Peak memory | 199220 kb |
| Host | smart-d5a851cc-8b81-4278-8175-379731767fe4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=862985825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.862985825 |
| Directory | /workspace/25.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/25.uart_perf.3119464862 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 14912377038 ps |
| CPU time | 199.91 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 05:01:09 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-c4f40c81-fdfd-4b49-bca6-a2c70c0c3abe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3119464862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3119464862 |
| Directory | /workspace/25.uart_perf/latest |
| Test location | /workspace/coverage/default/25.uart_rx_oversample.2034127538 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 1909762992 ps |
| CPU time | 12.13 seconds |
| Started | Aug 01 04:57:49 PM PDT 24 |
| Finished | Aug 01 04:58:01 PM PDT 24 |
| Peak memory | 197880 kb |
| Host | smart-9aae3e35-5dcf-4ff2-8137-1a7833825a0d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2034127538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.2034127538 |
| Directory | /workspace/25.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/25.uart_rx_parity_err.2706158877 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 40607162010 ps |
| CPU time | 44.37 seconds |
| Started | Aug 01 04:57:49 PM PDT 24 |
| Finished | Aug 01 04:58:33 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-66aa0ff5-ed78-49b3-a692-009f68b8ea2f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2706158877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2706158877 |
| Directory | /workspace/25.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/25.uart_rx_start_bit_filter.4256890101 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 4951944377 ps |
| CPU time | 8.7 seconds |
| Started | Aug 01 04:57:47 PM PDT 24 |
| Finished | Aug 01 04:57:55 PM PDT 24 |
| Peak memory | 195904 kb |
| Host | smart-a2041337-5f72-43ae-8b0a-e3f58134c535 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4256890101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.4256890101 |
| Directory | /workspace/25.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/25.uart_smoke.2912660296 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 468278944 ps |
| CPU time | 2.04 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:57:50 PM PDT 24 |
| Peak memory | 199532 kb |
| Host | smart-d602f453-fb01-4d2d-9b98-7b1117832452 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912660296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.2912660296 |
| Directory | /workspace/25.uart_smoke/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all.3665084229 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 6291866069 ps |
| CPU time | 6.75 seconds |
| Started | Aug 01 04:57:51 PM PDT 24 |
| Finished | Aug 01 04:57:58 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-806619de-da24-43f2-9cdb-13255fb73d27 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665084229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3665084229 |
| Directory | /workspace/25.uart_stress_all/latest |
| Test location | /workspace/coverage/default/25.uart_stress_all_with_rand_reset.152961382 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 86061863046 ps |
| CPU time | 212.94 seconds |
| Started | Aug 01 04:57:50 PM PDT 24 |
| Finished | Aug 01 05:01:23 PM PDT 24 |
| Peak memory | 208232 kb |
| Host | smart-3ee90178-cc21-48b0-93d0-c9a5cf161f95 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152961382 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.152961382 |
| Directory | /workspace/25.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/25.uart_tx_ovrd.837047379 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 538052929 ps |
| CPU time | 1.91 seconds |
| Started | Aug 01 04:57:50 PM PDT 24 |
| Finished | Aug 01 04:57:52 PM PDT 24 |
| Peak memory | 198600 kb |
| Host | smart-6e89ede2-77a8-4217-8dc7-41a4ded0349e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=837047379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.837047379 |
| Directory | /workspace/25.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/25.uart_tx_rx.3873993773 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 48194517259 ps |
| CPU time | 74.41 seconds |
| Started | Aug 01 04:57:59 PM PDT 24 |
| Finished | Aug 01 04:59:13 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-7fb972ee-7f01-428e-aa73-28c958fd5b37 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3873993773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.3873993773 |
| Directory | /workspace/25.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/250.uart_fifo_reset.2345263113 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 133638746459 ps |
| CPU time | 108.57 seconds |
| Started | Aug 01 05:03:59 PM PDT 24 |
| Finished | Aug 01 05:05:47 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-a7a1fbba-61e6-402c-bd56-ef35053c1315 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2345263113 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2345263113 |
| Directory | /workspace/250.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/251.uart_fifo_reset.267157161 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 123930879033 ps |
| CPU time | 25.94 seconds |
| Started | Aug 01 05:03:59 PM PDT 24 |
| Finished | Aug 01 05:04:25 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-a7357f5f-3bea-4e66-967f-4812a438e25c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267157161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.267157161 |
| Directory | /workspace/251.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/252.uart_fifo_reset.65265571 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 20864665970 ps |
| CPU time | 35.43 seconds |
| Started | Aug 01 05:04:00 PM PDT 24 |
| Finished | Aug 01 05:04:36 PM PDT 24 |
| Peak memory | 200092 kb |
| Host | smart-0b038784-5186-411a-8784-26374286c49c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=65265571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.65265571 |
| Directory | /workspace/252.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/253.uart_fifo_reset.3035746060 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 13986161111 ps |
| CPU time | 12.43 seconds |
| Started | Aug 01 05:04:00 PM PDT 24 |
| Finished | Aug 01 05:04:13 PM PDT 24 |
| Peak memory | 199948 kb |
| Host | smart-30cf8f56-cda3-4915-b57f-60c57d422101 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3035746060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3035746060 |
| Directory | /workspace/253.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/254.uart_fifo_reset.2732701797 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 79939215300 ps |
| CPU time | 27.37 seconds |
| Started | Aug 01 05:04:04 PM PDT 24 |
| Finished | Aug 01 05:04:32 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-9601315b-4179-440d-aeed-ca91899db2df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2732701797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.2732701797 |
| Directory | /workspace/254.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/255.uart_fifo_reset.772476712 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 205032654257 ps |
| CPU time | 439.43 seconds |
| Started | Aug 01 05:04:01 PM PDT 24 |
| Finished | Aug 01 05:11:20 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-f974685b-2e78-46d9-8f56-852643ce9586 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=772476712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.772476712 |
| Directory | /workspace/255.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/256.uart_fifo_reset.756332773 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 97666151615 ps |
| CPU time | 137.01 seconds |
| Started | Aug 01 05:04:02 PM PDT 24 |
| Finished | Aug 01 05:06:19 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-7a989af9-5321-48a5-8e59-a41f5fdc464f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=756332773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.756332773 |
| Directory | /workspace/256.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/257.uart_fifo_reset.2527517332 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 123217526146 ps |
| CPU time | 98.61 seconds |
| Started | Aug 01 05:04:02 PM PDT 24 |
| Finished | Aug 01 05:05:40 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-8a3e5297-6e2c-4c7c-9a87-4a171257790c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2527517332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.2527517332 |
| Directory | /workspace/257.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/258.uart_fifo_reset.1254178911 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 78497526608 ps |
| CPU time | 98.09 seconds |
| Started | Aug 01 05:04:00 PM PDT 24 |
| Finished | Aug 01 05:05:38 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-1c40b206-a293-49ef-aef4-f81f7f23856e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1254178911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1254178911 |
| Directory | /workspace/258.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/259.uart_fifo_reset.1594698235 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 155837421367 ps |
| CPU time | 55.11 seconds |
| Started | Aug 01 05:03:59 PM PDT 24 |
| Finished | Aug 01 05:04:54 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-49981f99-0fa2-4738-81d4-b0717787f7ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1594698235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.1594698235 |
| Directory | /workspace/259.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_alert_test.1965487078 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 11914508 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:57:59 PM PDT 24 |
| Finished | Aug 01 04:58:00 PM PDT 24 |
| Peak memory | 194724 kb |
| Host | smart-1d9e5bb6-981d-452e-97d6-76bb5e500699 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965487078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.1965487078 |
| Directory | /workspace/26.uart_alert_test/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_full.968418179 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 248481981870 ps |
| CPU time | 175.36 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 05:00:44 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-0b05a37d-d88a-4436-901c-79a74c90bb1c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968418179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.968418179 |
| Directory | /workspace/26.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_overflow.1983817041 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 91374557035 ps |
| CPU time | 25.21 seconds |
| Started | Aug 01 04:57:53 PM PDT 24 |
| Finished | Aug 01 04:58:19 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-d172abca-1b18-4730-8946-46745e9d2819 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1983817041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.1983817041 |
| Directory | /workspace/26.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/26.uart_fifo_reset.601802340 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 17189074253 ps |
| CPU time | 26.8 seconds |
| Started | Aug 01 04:57:58 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-66fc8457-46cf-4e94-bc85-a4e7363c1ebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=601802340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.601802340 |
| Directory | /workspace/26.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/26.uart_intr.202379753 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 26470312026 ps |
| CPU time | 12.55 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:58:00 PM PDT 24 |
| Peak memory | 198908 kb |
| Host | smart-851655c3-9f7d-4d6f-9718-57b209850943 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202379753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.202379753 |
| Directory | /workspace/26.uart_intr/latest |
| Test location | /workspace/coverage/default/26.uart_long_xfer_wo_dly.741527594 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 50913221296 ps |
| CPU time | 454.63 seconds |
| Started | Aug 01 04:58:00 PM PDT 24 |
| Finished | Aug 01 05:05:35 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-10458808-d3c0-4922-b138-69f32bae7ed5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=741527594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.741527594 |
| Directory | /workspace/26.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/26.uart_loopback.3093659039 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 5455487354 ps |
| CPU time | 5.62 seconds |
| Started | Aug 01 04:58:02 PM PDT 24 |
| Finished | Aug 01 04:58:07 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-d71a55f7-cf22-45df-8e26-be796cbeb510 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3093659039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3093659039 |
| Directory | /workspace/26.uart_loopback/latest |
| Test location | /workspace/coverage/default/26.uart_noise_filter.2666683626 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 51443428757 ps |
| CPU time | 85.39 seconds |
| Started | Aug 01 04:57:53 PM PDT 24 |
| Finished | Aug 01 04:59:19 PM PDT 24 |
| Peak memory | 208516 kb |
| Host | smart-a56bffbc-a74c-47ab-b7bf-883762acf8f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2666683626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.2666683626 |
| Directory | /workspace/26.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/26.uart_perf.2198343332 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 24657155856 ps |
| CPU time | 715.41 seconds |
| Started | Aug 01 04:58:00 PM PDT 24 |
| Finished | Aug 01 05:09:55 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-8cd50c68-1f8e-46a7-b74c-339ea9a66e52 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2198343332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.2198343332 |
| Directory | /workspace/26.uart_perf/latest |
| Test location | /workspace/coverage/default/26.uart_rx_oversample.1575109213 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2973611513 ps |
| CPU time | 6.16 seconds |
| Started | Aug 01 04:57:52 PM PDT 24 |
| Finished | Aug 01 04:57:59 PM PDT 24 |
| Peak memory | 199052 kb |
| Host | smart-21091e5e-2c2c-42ab-a8c1-f13087893cba |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1575109213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.1575109213 |
| Directory | /workspace/26.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/26.uart_rx_parity_err.2413149996 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 23927317781 ps |
| CPU time | 22.49 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:58:11 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-38aaf013-0995-4a96-9827-0ee9fcfa61bf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2413149996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.2413149996 |
| Directory | /workspace/26.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/26.uart_rx_start_bit_filter.3833570317 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 1832941352 ps |
| CPU time | 2.21 seconds |
| Started | Aug 01 04:57:50 PM PDT 24 |
| Finished | Aug 01 04:57:52 PM PDT 24 |
| Peak memory | 195236 kb |
| Host | smart-a9e0e913-0e67-4358-ade3-86b927258674 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3833570317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.3833570317 |
| Directory | /workspace/26.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/26.uart_smoke.310950574 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 530608112 ps |
| CPU time | 1.91 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:57:50 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-fd45a07d-d827-48b7-9025-c679ff44f8ba |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=310950574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.310950574 |
| Directory | /workspace/26.uart_smoke/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all.1833962619 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 181952567961 ps |
| CPU time | 283.93 seconds |
| Started | Aug 01 04:58:02 PM PDT 24 |
| Finished | Aug 01 05:02:46 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-1a68040f-ebfe-4b94-b358-6bdc94adbc33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833962619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1833962619 |
| Directory | /workspace/26.uart_stress_all/latest |
| Test location | /workspace/coverage/default/26.uart_stress_all_with_rand_reset.3917560518 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 42206663803 ps |
| CPU time | 254.04 seconds |
| Started | Aug 01 04:58:03 PM PDT 24 |
| Finished | Aug 01 05:02:17 PM PDT 24 |
| Peak memory | 216504 kb |
| Host | smart-ce830ac4-c6e6-4104-b00c-d105b9f32dba |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917560518 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.3917560518 |
| Directory | /workspace/26.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/26.uart_tx_ovrd.2264591342 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 2481929242 ps |
| CPU time | 2.35 seconds |
| Started | Aug 01 04:57:50 PM PDT 24 |
| Finished | Aug 01 04:57:52 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-3bddac6a-1049-4dd0-9794-d0fa39237a97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2264591342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2264591342 |
| Directory | /workspace/26.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/26.uart_tx_rx.2541300314 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 21141082070 ps |
| CPU time | 15.79 seconds |
| Started | Aug 01 04:57:48 PM PDT 24 |
| Finished | Aug 01 04:58:04 PM PDT 24 |
| Peak memory | 199604 kb |
| Host | smart-54fa05b6-797f-41f1-aa16-1900858a8193 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2541300314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2541300314 |
| Directory | /workspace/26.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/261.uart_fifo_reset.2598752800 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 65041520860 ps |
| CPU time | 108.6 seconds |
| Started | Aug 01 05:04:00 PM PDT 24 |
| Finished | Aug 01 05:05:49 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-dc5c7e84-0a35-4f05-8ba6-fc05a6159314 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598752800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.2598752800 |
| Directory | /workspace/261.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/262.uart_fifo_reset.878728466 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 212343808148 ps |
| CPU time | 76.68 seconds |
| Started | Aug 01 05:03:58 PM PDT 24 |
| Finished | Aug 01 05:05:15 PM PDT 24 |
| Peak memory | 199544 kb |
| Host | smart-c4182f11-1491-4985-88d1-8b3604082d7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=878728466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.878728466 |
| Directory | /workspace/262.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/263.uart_fifo_reset.840173243 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 144606107619 ps |
| CPU time | 235.05 seconds |
| Started | Aug 01 05:04:10 PM PDT 24 |
| Finished | Aug 01 05:08:05 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-af7e009f-2e81-43ed-ad69-9fcb880bb0f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=840173243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.840173243 |
| Directory | /workspace/263.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/264.uart_fifo_reset.181828912 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 10233145855 ps |
| CPU time | 16.72 seconds |
| Started | Aug 01 05:04:12 PM PDT 24 |
| Finished | Aug 01 05:04:28 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-c422df48-9f7f-4e76-a5ff-fb759d682a6e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=181828912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.181828912 |
| Directory | /workspace/264.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/265.uart_fifo_reset.1337616374 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 304407015029 ps |
| CPU time | 123.83 seconds |
| Started | Aug 01 05:04:13 PM PDT 24 |
| Finished | Aug 01 05:06:17 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-8dfb6dd3-2c83-4c10-8644-b5517a325197 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1337616374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.1337616374 |
| Directory | /workspace/265.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/266.uart_fifo_reset.3263428829 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 100490775414 ps |
| CPU time | 197.47 seconds |
| Started | Aug 01 05:04:10 PM PDT 24 |
| Finished | Aug 01 05:07:27 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-35181849-bbc9-4947-89db-b03f5b3cbebb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3263428829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.3263428829 |
| Directory | /workspace/266.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/267.uart_fifo_reset.490608749 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 45340772109 ps |
| CPU time | 19.7 seconds |
| Started | Aug 01 05:04:14 PM PDT 24 |
| Finished | Aug 01 05:04:34 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-eb6f2942-6028-47a6-b509-65b326aab084 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=490608749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.490608749 |
| Directory | /workspace/267.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/268.uart_fifo_reset.4083571647 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 67762565660 ps |
| CPU time | 50.02 seconds |
| Started | Aug 01 05:04:11 PM PDT 24 |
| Finished | Aug 01 05:05:01 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-e91a9a58-44cd-4192-80d0-c4cdf6f2e260 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4083571647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.4083571647 |
| Directory | /workspace/268.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/269.uart_fifo_reset.3253088436 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 59564140621 ps |
| CPU time | 21.8 seconds |
| Started | Aug 01 05:04:13 PM PDT 24 |
| Finished | Aug 01 05:04:35 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-84761b95-dd4c-4dac-8c10-217d14494755 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3253088436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.3253088436 |
| Directory | /workspace/269.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_alert_test.3511019453 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 36927292 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 04:58:11 PM PDT 24 |
| Peak memory | 195140 kb |
| Host | smart-abc22a3b-8c32-4027-866f-39b84642bfb1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511019453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3511019453 |
| Directory | /workspace/27.uart_alert_test/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_full.1986658418 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 65871289350 ps |
| CPU time | 52.98 seconds |
| Started | Aug 01 04:58:01 PM PDT 24 |
| Finished | Aug 01 04:58:54 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-f0356b91-123a-4bdf-b37e-155694f87e65 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1986658418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.1986658418 |
| Directory | /workspace/27.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_overflow.913303296 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 519498669107 ps |
| CPU time | 54.29 seconds |
| Started | Aug 01 04:57:59 PM PDT 24 |
| Finished | Aug 01 04:58:54 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-8a614eab-dc2c-4100-a9f7-73925aafe0d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=913303296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.913303296 |
| Directory | /workspace/27.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/27.uart_fifo_reset.3388527778 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 34037205039 ps |
| CPU time | 12.55 seconds |
| Started | Aug 01 04:58:01 PM PDT 24 |
| Finished | Aug 01 04:58:14 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-d1c5cde1-ae2c-42d4-beb6-a697420b571c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3388527778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.3388527778 |
| Directory | /workspace/27.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/27.uart_intr.1147464591 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 10407213464 ps |
| CPU time | 16.71 seconds |
| Started | Aug 01 04:58:01 PM PDT 24 |
| Finished | Aug 01 04:58:18 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-64d07fc2-9f80-4ee3-9152-938020f02a78 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147464591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1147464591 |
| Directory | /workspace/27.uart_intr/latest |
| Test location | /workspace/coverage/default/27.uart_long_xfer_wo_dly.1264199797 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 79486130035 ps |
| CPU time | 389.15 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 05:04:40 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-beccc3f7-b0be-41e8-86e7-d6a3700ac007 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1264199797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.1264199797 |
| Directory | /workspace/27.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/27.uart_loopback.2104509180 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 9472692806 ps |
| CPU time | 5.94 seconds |
| Started | Aug 01 04:58:01 PM PDT 24 |
| Finished | Aug 01 04:58:07 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-7dc0e0ef-2bea-4d36-97a0-1c8a86724d6a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2104509180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2104509180 |
| Directory | /workspace/27.uart_loopback/latest |
| Test location | /workspace/coverage/default/27.uart_noise_filter.2336339968 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 69795929287 ps |
| CPU time | 35.33 seconds |
| Started | Aug 01 04:58:02 PM PDT 24 |
| Finished | Aug 01 04:58:37 PM PDT 24 |
| Peak memory | 199920 kb |
| Host | smart-552a1400-2c38-4ca7-a095-8118767f6f32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2336339968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.2336339968 |
| Directory | /workspace/27.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/27.uart_perf.2263002988 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 21337698287 ps |
| CPU time | 514.34 seconds |
| Started | Aug 01 04:58:02 PM PDT 24 |
| Finished | Aug 01 05:06:37 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-66406a8d-f785-41b4-98fc-cab1348911fa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2263002988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2263002988 |
| Directory | /workspace/27.uart_perf/latest |
| Test location | /workspace/coverage/default/27.uart_rx_oversample.89247516 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4437567578 ps |
| CPU time | 39.37 seconds |
| Started | Aug 01 04:57:59 PM PDT 24 |
| Finished | Aug 01 04:58:39 PM PDT 24 |
| Peak memory | 199016 kb |
| Host | smart-318fc913-565e-48ef-b744-b6376bef9401 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=89247516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.89247516 |
| Directory | /workspace/27.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/27.uart_rx_parity_err.2927037788 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 122224619458 ps |
| CPU time | 82.48 seconds |
| Started | Aug 01 04:58:00 PM PDT 24 |
| Finished | Aug 01 04:59:23 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-bada7e4a-ca09-4dcb-ab63-5aed8af9d849 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2927037788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2927037788 |
| Directory | /workspace/27.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/27.uart_rx_start_bit_filter.1395148000 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 7445500785 ps |
| CPU time | 3.66 seconds |
| Started | Aug 01 04:58:02 PM PDT 24 |
| Finished | Aug 01 04:58:06 PM PDT 24 |
| Peak memory | 196004 kb |
| Host | smart-58d40339-b144-4929-a56b-db6c0a9b42a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1395148000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1395148000 |
| Directory | /workspace/27.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/27.uart_smoke.2378775024 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 5635301288 ps |
| CPU time | 11.3 seconds |
| Started | Aug 01 04:58:00 PM PDT 24 |
| Finished | Aug 01 04:58:12 PM PDT 24 |
| Peak memory | 199500 kb |
| Host | smart-5379f267-9817-48e3-9dd7-faa7e0304ddc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2378775024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2378775024 |
| Directory | /workspace/27.uart_smoke/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all.3119387282 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 192636182593 ps |
| CPU time | 265 seconds |
| Started | Aug 01 04:58:13 PM PDT 24 |
| Finished | Aug 01 05:02:38 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-0c6a1b2e-c481-4685-9bef-3e3ec6a09f1d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119387282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.3119387282 |
| Directory | /workspace/27.uart_stress_all/latest |
| Test location | /workspace/coverage/default/27.uart_stress_all_with_rand_reset.4169442982 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 201587751408 ps |
| CPU time | 633.45 seconds |
| Started | Aug 01 04:58:22 PM PDT 24 |
| Finished | Aug 01 05:08:56 PM PDT 24 |
| Peak memory | 216304 kb |
| Host | smart-d1d3a821-fb4f-43bc-8cb2-b4b55c19846e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169442982 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.4169442982 |
| Directory | /workspace/27.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/27.uart_tx_ovrd.713569667 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 6389375937 ps |
| CPU time | 18.69 seconds |
| Started | Aug 01 04:57:59 PM PDT 24 |
| Finished | Aug 01 04:58:18 PM PDT 24 |
| Peak memory | 199532 kb |
| Host | smart-32e477e7-c515-4965-a62d-98fe5af33c09 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=713569667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.713569667 |
| Directory | /workspace/27.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/27.uart_tx_rx.472115834 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 56143721681 ps |
| CPU time | 85.62 seconds |
| Started | Aug 01 04:58:01 PM PDT 24 |
| Finished | Aug 01 04:59:27 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-ff0e520b-bdef-4b4d-8ab6-ff1471a7184d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=472115834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.472115834 |
| Directory | /workspace/27.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/270.uart_fifo_reset.3417347652 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 155476279696 ps |
| CPU time | 16.82 seconds |
| Started | Aug 01 05:04:13 PM PDT 24 |
| Finished | Aug 01 05:04:30 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-844fc0c0-1abf-4c67-889c-355123a7d744 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3417347652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.3417347652 |
| Directory | /workspace/270.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/271.uart_fifo_reset.651398200 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 9972053050 ps |
| CPU time | 15.93 seconds |
| Started | Aug 01 05:04:10 PM PDT 24 |
| Finished | Aug 01 05:04:26 PM PDT 24 |
| Peak memory | 198320 kb |
| Host | smart-19608a86-6bf0-412a-8bb0-4f57922debd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=651398200 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.651398200 |
| Directory | /workspace/271.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/272.uart_fifo_reset.4170509720 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 91718854454 ps |
| CPU time | 91.47 seconds |
| Started | Aug 01 05:04:11 PM PDT 24 |
| Finished | Aug 01 05:05:43 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-65b51cba-3e60-4948-bf23-25dfb69b7368 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4170509720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.4170509720 |
| Directory | /workspace/272.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/273.uart_fifo_reset.733373145 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 138962088546 ps |
| CPU time | 77.99 seconds |
| Started | Aug 01 05:04:11 PM PDT 24 |
| Finished | Aug 01 05:05:29 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-f2cbcfd0-17f4-4e64-8c1c-129cd330859b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=733373145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.733373145 |
| Directory | /workspace/273.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/274.uart_fifo_reset.1095379063 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 149652977417 ps |
| CPU time | 61.08 seconds |
| Started | Aug 01 05:04:11 PM PDT 24 |
| Finished | Aug 01 05:05:12 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-f84883b2-8fde-47ab-ba35-ce1209909db6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1095379063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.1095379063 |
| Directory | /workspace/274.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/275.uart_fifo_reset.599121490 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 35618851976 ps |
| CPU time | 29.58 seconds |
| Started | Aug 01 05:04:11 PM PDT 24 |
| Finished | Aug 01 05:04:41 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-0ecad5b9-6ce5-4ee3-bd39-81ac55f62bf4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=599121490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.599121490 |
| Directory | /workspace/275.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/277.uart_fifo_reset.2741462788 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 87640117150 ps |
| CPU time | 97.12 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:59 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-e4084278-c0d4-4c46-8df7-b8e0c95ca378 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2741462788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.2741462788 |
| Directory | /workspace/277.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/278.uart_fifo_reset.2555555126 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 94255265164 ps |
| CPU time | 39.2 seconds |
| Started | Aug 01 05:04:25 PM PDT 24 |
| Finished | Aug 01 05:05:04 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-3a6cbc05-763e-4035-a55b-b2e28a326b25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2555555126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2555555126 |
| Directory | /workspace/278.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/279.uart_fifo_reset.2512777422 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 37588336261 ps |
| CPU time | 50.12 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:12 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-36cd6a64-47de-4b02-ae49-38005754f1a9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2512777422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.2512777422 |
| Directory | /workspace/279.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_alert_test.3152725407 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 12438559 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:58:14 PM PDT 24 |
| Finished | Aug 01 04:58:15 PM PDT 24 |
| Peak memory | 194028 kb |
| Host | smart-2b0e67f1-8653-43c1-a840-dfcc572f4cd1 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152725407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3152725407 |
| Directory | /workspace/28.uart_alert_test/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_full.1153328393 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 46722300381 ps |
| CPU time | 33.44 seconds |
| Started | Aug 01 04:58:14 PM PDT 24 |
| Finished | Aug 01 04:58:48 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-0ba0b930-79a0-4f5c-b878-a7d614c21250 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1153328393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.1153328393 |
| Directory | /workspace/28.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_overflow.2700711286 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 143191169778 ps |
| CPU time | 273.63 seconds |
| Started | Aug 01 04:58:18 PM PDT 24 |
| Finished | Aug 01 05:02:52 PM PDT 24 |
| Peak memory | 199336 kb |
| Host | smart-2eee0289-e709-4778-be02-6f7fb1f46201 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2700711286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2700711286 |
| Directory | /workspace/28.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/28.uart_fifo_reset.775844987 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 151360325448 ps |
| CPU time | 13.73 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-9437a7ce-04ca-46ff-b192-64d2f0010332 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=775844987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.775844987 |
| Directory | /workspace/28.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/28.uart_intr.23235847 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 6426514734 ps |
| CPU time | 5 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 04:58:17 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-fbda16b8-d27d-42f8-99f7-6cd25f48fb13 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.23235847 |
| Directory | /workspace/28.uart_intr/latest |
| Test location | /workspace/coverage/default/28.uart_long_xfer_wo_dly.2091821212 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 81935583727 ps |
| CPU time | 315.49 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 05:03:28 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-1602ccff-5138-4b5f-89c5-432912dd7f19 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2091821212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2091821212 |
| Directory | /workspace/28.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/28.uart_loopback.4154802876 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 7762386502 ps |
| CPU time | 4.09 seconds |
| Started | Aug 01 04:58:18 PM PDT 24 |
| Finished | Aug 01 04:58:22 PM PDT 24 |
| Peak memory | 198324 kb |
| Host | smart-702bde6a-f310-45ae-b5e0-fa74ed22d905 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4154802876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.4154802876 |
| Directory | /workspace/28.uart_loopback/latest |
| Test location | /workspace/coverage/default/28.uart_noise_filter.917747635 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 188914634186 ps |
| CPU time | 301.05 seconds |
| Started | Aug 01 04:58:13 PM PDT 24 |
| Finished | Aug 01 05:03:14 PM PDT 24 |
| Peak memory | 200008 kb |
| Host | smart-4c7f49d4-720b-4a4b-a60e-da433c1ad313 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=917747635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.917747635 |
| Directory | /workspace/28.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/28.uart_perf.1178805264 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 18899837597 ps |
| CPU time | 267.94 seconds |
| Started | Aug 01 04:58:14 PM PDT 24 |
| Finished | Aug 01 05:02:42 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-3cd934be-6b19-445a-9565-b153218fdd1e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1178805264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1178805264 |
| Directory | /workspace/28.uart_perf/latest |
| Test location | /workspace/coverage/default/28.uart_rx_oversample.2554965649 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 5200110325 ps |
| CPU time | 12.77 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 04:58:24 PM PDT 24 |
| Peak memory | 197944 kb |
| Host | smart-3a389c6d-07cf-4ccc-a9cd-8acc5a87d87c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2554965649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.2554965649 |
| Directory | /workspace/28.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/28.uart_rx_parity_err.2562768409 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 112990222724 ps |
| CPU time | 29.91 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 04:58:42 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-d46f5163-c26d-4b6c-8a02-61c0d91024a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2562768409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.2562768409 |
| Directory | /workspace/28.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/28.uart_rx_start_bit_filter.2922548014 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 38085289290 ps |
| CPU time | 10.97 seconds |
| Started | Aug 01 04:58:15 PM PDT 24 |
| Finished | Aug 01 04:58:26 PM PDT 24 |
| Peak memory | 195920 kb |
| Host | smart-92da6c15-bb54-4356-8f06-632a496ee3af |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2922548014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2922548014 |
| Directory | /workspace/28.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/28.uart_smoke.33164526 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 119818860 ps |
| CPU time | 0.89 seconds |
| Started | Aug 01 04:58:19 PM PDT 24 |
| Finished | Aug 01 04:58:20 PM PDT 24 |
| Peak memory | 197152 kb |
| Host | smart-b1cd0bfb-53b8-4388-9637-401c8275a030 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=33164526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.33164526 |
| Directory | /workspace/28.uart_smoke/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all.3903399351 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 207887173547 ps |
| CPU time | 1605.8 seconds |
| Started | Aug 01 04:58:17 PM PDT 24 |
| Finished | Aug 01 05:25:03 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-025cd39d-5b71-4079-8c8c-b59b5fa9203b |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903399351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3903399351 |
| Directory | /workspace/28.uart_stress_all/latest |
| Test location | /workspace/coverage/default/28.uart_stress_all_with_rand_reset.1354053728 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 328241554298 ps |
| CPU time | 402.42 seconds |
| Started | Aug 01 04:58:14 PM PDT 24 |
| Finished | Aug 01 05:04:57 PM PDT 24 |
| Peak memory | 216292 kb |
| Host | smart-c57e5769-3d30-45c1-bc87-3d7dca76a71b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354053728 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.1354053728 |
| Directory | /workspace/28.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/28.uart_tx_ovrd.1517518239 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 1515792118 ps |
| CPU time | 3.3 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 04:58:15 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-6501bd6b-d689-4139-a38b-5e2a18321a9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1517518239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1517518239 |
| Directory | /workspace/28.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/28.uart_tx_rx.329955221 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 78477143948 ps |
| CPU time | 218.16 seconds |
| Started | Aug 01 04:58:13 PM PDT 24 |
| Finished | Aug 01 05:01:51 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-b9d25813-85a9-4acd-8e0b-6c3ca985844f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=329955221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.329955221 |
| Directory | /workspace/28.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/280.uart_fifo_reset.468744447 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 34310641526 ps |
| CPU time | 14.14 seconds |
| Started | Aug 01 05:04:24 PM PDT 24 |
| Finished | Aug 01 05:04:38 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-52e0695f-6bd6-47fe-9593-2d805e3f1f7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=468744447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.468744447 |
| Directory | /workspace/280.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/281.uart_fifo_reset.2479346136 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 19900861860 ps |
| CPU time | 14.96 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:38 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-e0512d2a-65ef-444d-bfaf-b2830907a4f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2479346136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2479346136 |
| Directory | /workspace/281.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/282.uart_fifo_reset.727468981 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 80249843397 ps |
| CPU time | 46.05 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:09 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-ab4448c2-0314-4887-8998-94d5e0c02b95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=727468981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.727468981 |
| Directory | /workspace/282.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/283.uart_fifo_reset.4264601448 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 7492992724 ps |
| CPU time | 10.98 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:34 PM PDT 24 |
| Peak memory | 198156 kb |
| Host | smart-7cc44127-91a9-4a65-a051-5ef3bc2c55a4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4264601448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.4264601448 |
| Directory | /workspace/283.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/284.uart_fifo_reset.2117390121 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 190302891372 ps |
| CPU time | 75.87 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:38 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-41c3b3a8-cb73-4d93-8f88-f786537655cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2117390121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2117390121 |
| Directory | /workspace/284.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/285.uart_fifo_reset.497067129 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 54415109983 ps |
| CPU time | 23.97 seconds |
| Started | Aug 01 05:04:24 PM PDT 24 |
| Finished | Aug 01 05:04:48 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-e1b92543-512f-4867-b98c-b58cc62a793c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=497067129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.497067129 |
| Directory | /workspace/285.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/286.uart_fifo_reset.161754638 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 33637108784 ps |
| CPU time | 27.29 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:50 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-93390856-8236-4a9c-8a0d-51bd72f33c25 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=161754638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.161754638 |
| Directory | /workspace/286.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/287.uart_fifo_reset.2431189877 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 14771506136 ps |
| CPU time | 26.89 seconds |
| Started | Aug 01 05:04:21 PM PDT 24 |
| Finished | Aug 01 05:04:48 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-785bf827-8f6a-419d-a9a7-58bc65ea4cc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2431189877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.2431189877 |
| Directory | /workspace/287.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/289.uart_fifo_reset.1680531290 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 51671868165 ps |
| CPU time | 20.22 seconds |
| Started | Aug 01 05:04:25 PM PDT 24 |
| Finished | Aug 01 05:04:45 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-bee15939-a583-4197-8330-fa3dcbd9a38e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1680531290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.1680531290 |
| Directory | /workspace/289.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_alert_test.1396325115 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 11199940 ps |
| CPU time | 0.53 seconds |
| Started | Aug 01 04:58:26 PM PDT 24 |
| Finished | Aug 01 04:58:26 PM PDT 24 |
| Peak memory | 195208 kb |
| Host | smart-7f3a5ce7-3878-47c1-b646-44b9083d70a6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396325115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.1396325115 |
| Directory | /workspace/29.uart_alert_test/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_full.1165104081 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 70153726578 ps |
| CPU time | 23.28 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 04:58:35 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-79dc1593-8697-43f3-b4a4-1d39f774e5a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1165104081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.1165104081 |
| Directory | /workspace/29.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_overflow.846262649 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 73133656642 ps |
| CPU time | 29.24 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 04:58:41 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-08f00caa-439f-43f4-9950-6d075227556d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=846262649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.846262649 |
| Directory | /workspace/29.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/29.uart_fifo_reset.302598797 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 15905689226 ps |
| CPU time | 10.75 seconds |
| Started | Aug 01 04:58:18 PM PDT 24 |
| Finished | Aug 01 04:58:29 PM PDT 24 |
| Peak memory | 199316 kb |
| Host | smart-75307e94-d585-475e-b0a2-47884cefa602 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=302598797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.302598797 |
| Directory | /workspace/29.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/29.uart_intr.1952533831 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 10611694442 ps |
| CPU time | 14.24 seconds |
| Started | Aug 01 04:58:18 PM PDT 24 |
| Finished | Aug 01 04:58:32 PM PDT 24 |
| Peak memory | 196488 kb |
| Host | smart-63f3b407-058e-4620-bcca-38d857d1e78d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952533831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1952533831 |
| Directory | /workspace/29.uart_intr/latest |
| Test location | /workspace/coverage/default/29.uart_loopback.543366465 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 24022653 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 04:58:26 PM PDT 24 |
| Peak memory | 195664 kb |
| Host | smart-35ba02c9-da89-4bcd-b054-96bf9058378f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543366465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.543366465 |
| Directory | /workspace/29.uart_loopback/latest |
| Test location | /workspace/coverage/default/29.uart_noise_filter.3275844839 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 10506619697 ps |
| CPU time | 12.66 seconds |
| Started | Aug 01 04:58:12 PM PDT 24 |
| Finished | Aug 01 04:58:24 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-01ead1ab-9eaf-4b0b-8845-36e65cdb57a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3275844839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3275844839 |
| Directory | /workspace/29.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/29.uart_perf.1386827318 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 18134694417 ps |
| CPU time | 520.39 seconds |
| Started | Aug 01 04:58:27 PM PDT 24 |
| Finished | Aug 01 05:07:07 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-5953f416-7a41-48a5-b7b3-3a6aebaedad3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1386827318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.1386827318 |
| Directory | /workspace/29.uart_perf/latest |
| Test location | /workspace/coverage/default/29.uart_rx_oversample.674649009 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 4556304254 ps |
| CPU time | 10.38 seconds |
| Started | Aug 01 04:58:14 PM PDT 24 |
| Finished | Aug 01 04:58:25 PM PDT 24 |
| Peak memory | 199128 kb |
| Host | smart-ffd5a25d-9b4a-4201-87e8-5a9c4dfea9c9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=674649009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.674649009 |
| Directory | /workspace/29.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/29.uart_rx_parity_err.2260924487 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 71032520032 ps |
| CPU time | 50.79 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 04:59:16 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-2f225a72-d56c-4763-b2bd-4b73ec7c98cb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2260924487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.2260924487 |
| Directory | /workspace/29.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/29.uart_rx_start_bit_filter.3374969401 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 2969395878 ps |
| CPU time | 1.15 seconds |
| Started | Aug 01 04:58:27 PM PDT 24 |
| Finished | Aug 01 04:58:28 PM PDT 24 |
| Peak memory | 196368 kb |
| Host | smart-dd16a72f-5cc0-46c4-8f06-11bc0312785b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3374969401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3374969401 |
| Directory | /workspace/29.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/29.uart_smoke.1112528023 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 112205914 ps |
| CPU time | 0.81 seconds |
| Started | Aug 01 04:58:22 PM PDT 24 |
| Finished | Aug 01 04:58:23 PM PDT 24 |
| Peak memory | 196924 kb |
| Host | smart-9d467311-aa8c-462c-9c23-5b7133914a57 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1112528023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.1112528023 |
| Directory | /workspace/29.uart_smoke/latest |
| Test location | /workspace/coverage/default/29.uart_tx_ovrd.3227579815 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 541136033 ps |
| CPU time | 1.68 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 04:58:27 PM PDT 24 |
| Peak memory | 197804 kb |
| Host | smart-cf8ade15-71ed-4b69-92d5-83cacb72bd9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3227579815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.3227579815 |
| Directory | /workspace/29.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/29.uart_tx_rx.591720052 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 15382625956 ps |
| CPU time | 23.54 seconds |
| Started | Aug 01 04:58:11 PM PDT 24 |
| Finished | Aug 01 04:58:35 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-a0496a7c-775b-4837-92c5-b075712f9253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591720052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.591720052 |
| Directory | /workspace/29.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/290.uart_fifo_reset.1227277069 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 221787126147 ps |
| CPU time | 18.19 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:41 PM PDT 24 |
| Peak memory | 199668 kb |
| Host | smart-68755348-e681-467f-b761-bc45f788a83a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1227277069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.1227277069 |
| Directory | /workspace/290.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/291.uart_fifo_reset.158069432 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 20829851587 ps |
| CPU time | 44.97 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:08 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-6df30e1d-8836-4cd7-99d8-8181f0238ccc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=158069432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.158069432 |
| Directory | /workspace/291.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/292.uart_fifo_reset.4219076031 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 18118703675 ps |
| CPU time | 28.66 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:51 PM PDT 24 |
| Peak memory | 199448 kb |
| Host | smart-61201f84-6956-4494-80dd-1560d7754b97 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4219076031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.4219076031 |
| Directory | /workspace/292.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/294.uart_fifo_reset.1152369089 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 16024819193 ps |
| CPU time | 15.14 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:39 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-556da7ed-11ae-4ba1-b2cd-ad328971e5d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1152369089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.1152369089 |
| Directory | /workspace/294.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/295.uart_fifo_reset.2230476069 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 36602876589 ps |
| CPU time | 75.54 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:05:37 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-53d90e4c-f4aa-420b-b567-7d30b6464544 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2230476069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.2230476069 |
| Directory | /workspace/295.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/296.uart_fifo_reset.3818834759 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 58949509884 ps |
| CPU time | 31.57 seconds |
| Started | Aug 01 05:04:24 PM PDT 24 |
| Finished | Aug 01 05:04:56 PM PDT 24 |
| Peak memory | 199956 kb |
| Host | smart-0fdca353-9a04-49cb-a3d8-a2a21744b5f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3818834759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.3818834759 |
| Directory | /workspace/296.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/297.uart_fifo_reset.435571904 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 20025899088 ps |
| CPU time | 30.73 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:04:53 PM PDT 24 |
| Peak memory | 199620 kb |
| Host | smart-b8066084-477f-4a36-89f5-5034210a4115 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=435571904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.435571904 |
| Directory | /workspace/297.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/298.uart_fifo_reset.656527101 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 36033547703 ps |
| CPU time | 17.49 seconds |
| Started | Aug 01 05:04:22 PM PDT 24 |
| Finished | Aug 01 05:04:39 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-64ae3d48-c762-45ab-ac7e-9ed91705c864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=656527101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.656527101 |
| Directory | /workspace/298.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/299.uart_fifo_reset.2318423328 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 117610746763 ps |
| CPU time | 84.13 seconds |
| Started | Aug 01 05:04:23 PM PDT 24 |
| Finished | Aug 01 05:05:48 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-f13b5894-b97f-4af8-b299-cfce5002599b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318423328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.2318423328 |
| Directory | /workspace/299.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_alert_test.1789075665 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 13275565 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:11 PM PDT 24 |
| Peak memory | 195136 kb |
| Host | smart-4380010a-b414-4eb5-af5f-5b7a4e54870a |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789075665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.1789075665 |
| Directory | /workspace/3.uart_alert_test/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_full.1144041248 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 57267802943 ps |
| CPU time | 14.46 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:27 PM PDT 24 |
| Peak memory | 199644 kb |
| Host | smart-061f5604-dd59-4fc7-b168-b6aa5ba9e7f8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1144041248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1144041248 |
| Directory | /workspace/3.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_overflow.315276766 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 67971438655 ps |
| CPU time | 45.26 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:56 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-1829c90c-679d-4ffe-b907-f01ff82f93f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=315276766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.315276766 |
| Directory | /workspace/3.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/3.uart_fifo_reset.1695486095 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 77159101308 ps |
| CPU time | 99.31 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:56:50 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-cd945e1c-06a1-451d-8378-7eb5d097c4b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1695486095 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.1695486095 |
| Directory | /workspace/3.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/3.uart_intr.4267473479 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 8141326180 ps |
| CPU time | 11.98 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:23 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-6d0c5d05-9d68-4b9c-8821-cafd17571635 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267473479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.4267473479 |
| Directory | /workspace/3.uart_intr/latest |
| Test location | /workspace/coverage/default/3.uart_long_xfer_wo_dly.3402387313 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 66573291705 ps |
| CPU time | 131.99 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:57:24 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-f9e64c75-1862-437c-b2c2-cb79e7053713 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3402387313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.3402387313 |
| Directory | /workspace/3.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/3.uart_loopback.1466967437 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 5500213888 ps |
| CPU time | 13 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:25 PM PDT 24 |
| Peak memory | 198804 kb |
| Host | smart-979c4554-900b-4143-861b-c83f5ee2bc59 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1466967437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.1466967437 |
| Directory | /workspace/3.uart_loopback/latest |
| Test location | /workspace/coverage/default/3.uart_noise_filter.1866509802 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 168314512957 ps |
| CPU time | 57.66 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:56:11 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-98399cf2-6691-48d9-be45-d8e6bc22ca74 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866509802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1866509802 |
| Directory | /workspace/3.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/3.uart_perf.2515180930 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4044222243 ps |
| CPU time | 235.24 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:59:07 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-8580751f-da1a-4b04-8d50-cb5063f86398 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2515180930 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2515180930 |
| Directory | /workspace/3.uart_perf/latest |
| Test location | /workspace/coverage/default/3.uart_rx_oversample.3921502139 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4557267040 ps |
| CPU time | 7.21 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:55:20 PM PDT 24 |
| Peak memory | 197972 kb |
| Host | smart-c90c54d9-9fce-4aa9-a3c7-60bc33d8fc38 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3921502139 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3921502139 |
| Directory | /workspace/3.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/3.uart_rx_parity_err.4027837776 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 280551882139 ps |
| CPU time | 55.2 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:56:08 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-d38896d3-eef4-4127-8d10-eb71140649b4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4027837776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.4027837776 |
| Directory | /workspace/3.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/3.uart_rx_start_bit_filter.3439980972 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 5493910039 ps |
| CPU time | 7.84 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:19 PM PDT 24 |
| Peak memory | 196288 kb |
| Host | smart-389aa573-843f-4698-8ab9-e68cba40a5c7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3439980972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.3439980972 |
| Directory | /workspace/3.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/3.uart_sec_cm.3383622398 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 55859294 ps |
| CPU time | 0.88 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:13 PM PDT 24 |
| Peak memory | 218120 kb |
| Host | smart-9d81ecba-8136-4b09-ac3b-e12fda999260 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383622398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.3383622398 |
| Directory | /workspace/3.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/3.uart_smoke.773544295 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 430121734 ps |
| CPU time | 2.65 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:55:16 PM PDT 24 |
| Peak memory | 198020 kb |
| Host | smart-df5d3760-6f0e-4cc0-83ba-db78106a054a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=773544295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.773544295 |
| Directory | /workspace/3.uart_smoke/latest |
| Test location | /workspace/coverage/default/3.uart_stress_all_with_rand_reset.2892608840 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 297366533391 ps |
| CPU time | 921.67 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 05:10:32 PM PDT 24 |
| Peak memory | 224576 kb |
| Host | smart-98c1188f-456b-4224-853f-842e5aa6b665 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892608840 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.2892608840 |
| Directory | /workspace/3.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/3.uart_tx_ovrd.1761633271 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 6233182579 ps |
| CPU time | 9.24 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:20 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-7dd126a8-01e1-4cba-a201-483c1a1b3c67 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1761633271 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1761633271 |
| Directory | /workspace/3.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/3.uart_tx_rx.1727419872 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 134147799774 ps |
| CPU time | 461.99 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 05:02:52 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-ff5b49e7-6173-4f9f-a993-5337e15e77a7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1727419872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.1727419872 |
| Directory | /workspace/3.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/30.uart_alert_test.3364025296 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 16410726 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:58:35 PM PDT 24 |
| Peak memory | 195204 kb |
| Host | smart-af1eb7b9-2fc1-4728-938c-ccd4ce4efe70 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364025296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3364025296 |
| Directory | /workspace/30.uart_alert_test/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_full.3691451485 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 59011555504 ps |
| CPU time | 85.97 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 04:59:51 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-0109a47c-f4ae-4528-9fef-822f6c03da01 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3691451485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3691451485 |
| Directory | /workspace/30.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_overflow.3223964334 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 17493887347 ps |
| CPU time | 16.86 seconds |
| Started | Aug 01 04:58:26 PM PDT 24 |
| Finished | Aug 01 04:58:43 PM PDT 24 |
| Peak memory | 198992 kb |
| Host | smart-d1772a78-e0fd-4683-88b9-0f514a670ecd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3223964334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.3223964334 |
| Directory | /workspace/30.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/30.uart_fifo_reset.3295182124 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 131177534658 ps |
| CPU time | 142.14 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-7d8b7f7f-3691-4896-b711-e3bbdcb71fda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3295182124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.3295182124 |
| Directory | /workspace/30.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/30.uart_intr.3884811550 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 91220659589 ps |
| CPU time | 149.38 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 05:00:55 PM PDT 24 |
| Peak memory | 199656 kb |
| Host | smart-3d0fc11c-07d6-4c41-9112-d91d0f34c671 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884811550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.3884811550 |
| Directory | /workspace/30.uart_intr/latest |
| Test location | /workspace/coverage/default/30.uart_long_xfer_wo_dly.3439356329 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 99272335730 ps |
| CPU time | 381.81 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 05:04:56 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-1b11e833-9648-4ed0-91ed-519f38b373b1 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3439356329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3439356329 |
| Directory | /workspace/30.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/30.uart_loopback.2041685614 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 9862226553 ps |
| CPU time | 13.45 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:50 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-0c927d16-2c9f-4d7d-b983-53b21a048bbd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2041685614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.2041685614 |
| Directory | /workspace/30.uart_loopback/latest |
| Test location | /workspace/coverage/default/30.uart_perf.2649464416 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 16294788799 ps |
| CPU time | 424.34 seconds |
| Started | Aug 01 04:58:41 PM PDT 24 |
| Finished | Aug 01 05:05:45 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-206194e2-b52e-43e9-8453-59607bd0407f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2649464416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.2649464416 |
| Directory | /workspace/30.uart_perf/latest |
| Test location | /workspace/coverage/default/30.uart_rx_oversample.1701372842 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4968018387 ps |
| CPU time | 40.13 seconds |
| Started | Aug 01 04:58:25 PM PDT 24 |
| Finished | Aug 01 04:59:06 PM PDT 24 |
| Peak memory | 199084 kb |
| Host | smart-2c05f184-d351-496e-9bec-8f105a4b156d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1701372842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.1701372842 |
| Directory | /workspace/30.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/30.uart_rx_parity_err.2148573961 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 143388729625 ps |
| CPU time | 220.02 seconds |
| Started | Aug 01 04:58:35 PM PDT 24 |
| Finished | Aug 01 05:02:15 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-866e296b-414d-4657-a9fe-6824b1b4471f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2148573961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2148573961 |
| Directory | /workspace/30.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/30.uart_rx_start_bit_filter.3190288337 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 44504611056 ps |
| CPU time | 19.56 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:58:54 PM PDT 24 |
| Peak memory | 195648 kb |
| Host | smart-300b9885-f932-429c-b543-222d79543621 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3190288337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3190288337 |
| Directory | /workspace/30.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/30.uart_smoke.194187977 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 532821983 ps |
| CPU time | 1.97 seconds |
| Started | Aug 01 04:58:27 PM PDT 24 |
| Finished | Aug 01 04:58:29 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-804063ff-b9d8-4271-8670-db21307ae103 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=194187977 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.194187977 |
| Directory | /workspace/30.uart_smoke/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all.3615081585 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 179699435796 ps |
| CPU time | 280.32 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 05:03:15 PM PDT 24 |
| Peak memory | 208160 kb |
| Host | smart-d01f615e-e541-4154-a60c-7fe5da8768e0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615081585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3615081585 |
| Directory | /workspace/30.uart_stress_all/latest |
| Test location | /workspace/coverage/default/30.uart_stress_all_with_rand_reset.578221452 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 12322673103 ps |
| CPU time | 156.61 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 05:01:12 PM PDT 24 |
| Peak memory | 209296 kb |
| Host | smart-078399c2-d826-4dbb-b2b6-9e42a7e29ef7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578221452 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.578221452 |
| Directory | /workspace/30.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/30.uart_tx_ovrd.1830611308 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1016637196 ps |
| CPU time | 2.24 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:58:37 PM PDT 24 |
| Peak memory | 199524 kb |
| Host | smart-e8df759d-df81-433f-9052-450b698e3e7b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1830611308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1830611308 |
| Directory | /workspace/30.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/30.uart_tx_rx.168707749 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 104596971032 ps |
| CPU time | 141.42 seconds |
| Started | Aug 01 04:58:26 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 199700 kb |
| Host | smart-2e23c622-8fea-430e-b3a6-c7e6b87e8603 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=168707749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.168707749 |
| Directory | /workspace/30.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/31.uart_alert_test.2842651490 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 77270232 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:36 PM PDT 24 |
| Peak memory | 195140 kb |
| Host | smart-94cc707c-5d2e-46fd-96de-05257833d3bb |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842651490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.2842651490 |
| Directory | /workspace/31.uart_alert_test/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_full.691768612 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 398582261354 ps |
| CPU time | 140.44 seconds |
| Started | Aug 01 04:58:38 PM PDT 24 |
| Finished | Aug 01 05:00:59 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-bac2bae4-9b12-4e0b-a39f-ebf5aa0c9d72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=691768612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.691768612 |
| Directory | /workspace/31.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_overflow.1971136282 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 14045028591 ps |
| CPU time | 12.92 seconds |
| Started | Aug 01 04:58:40 PM PDT 24 |
| Finished | Aug 01 04:58:53 PM PDT 24 |
| Peak memory | 199492 kb |
| Host | smart-4c498c0c-7cad-47c5-b9c9-a8d2d514f1d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1971136282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.1971136282 |
| Directory | /workspace/31.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/31.uart_fifo_reset.48503104 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 116810860657 ps |
| CPU time | 40.51 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:15 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-e466d0c7-66a6-40c5-8c2f-67fa2353552c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=48503104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.48503104 |
| Directory | /workspace/31.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/31.uart_intr.3921541402 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 24388763584 ps |
| CPU time | 12.37 seconds |
| Started | Aug 01 04:58:37 PM PDT 24 |
| Finished | Aug 01 04:58:50 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-34782450-9cab-46be-93a9-0542704ea3c6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921541402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.3921541402 |
| Directory | /workspace/31.uart_intr/latest |
| Test location | /workspace/coverage/default/31.uart_long_xfer_wo_dly.1968910654 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 106445377401 ps |
| CPU time | 633.67 seconds |
| Started | Aug 01 04:58:37 PM PDT 24 |
| Finished | Aug 01 05:09:11 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-33ccfcf3-fcbc-4f38-b483-2f7b55a34805 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1968910654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.1968910654 |
| Directory | /workspace/31.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/31.uart_loopback.876204193 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 9688628203 ps |
| CPU time | 6.06 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:42 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-44ee3069-b494-4c0f-99bd-02bab6fcedc9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=876204193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.876204193 |
| Directory | /workspace/31.uart_loopback/latest |
| Test location | /workspace/coverage/default/31.uart_noise_filter.1647478847 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 61634662108 ps |
| CPU time | 103.89 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 05:00:20 PM PDT 24 |
| Peak memory | 208032 kb |
| Host | smart-5ce339ab-9211-47a4-907c-2471d4ae3d61 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1647478847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.1647478847 |
| Directory | /workspace/31.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/31.uart_perf.4226812609 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 1497469820 ps |
| CPU time | 87.18 seconds |
| Started | Aug 01 04:58:35 PM PDT 24 |
| Finished | Aug 01 05:00:02 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-46ff724e-92f0-4dcb-a7c1-122f2614893e |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4226812609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4226812609 |
| Directory | /workspace/31.uart_perf/latest |
| Test location | /workspace/coverage/default/31.uart_rx_oversample.3189730867 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4123814461 ps |
| CPU time | 29.47 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:04 PM PDT 24 |
| Peak memory | 197780 kb |
| Host | smart-6cf80a03-e2c0-4cd7-aa8e-cbc768b8fec0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3189730867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.3189730867 |
| Directory | /workspace/31.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/31.uart_rx_parity_err.632778461 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 57101816007 ps |
| CPU time | 52.35 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:27 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-93746982-e8cc-4732-9d93-661e1497d51a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=632778461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.632778461 |
| Directory | /workspace/31.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/31.uart_rx_start_bit_filter.16715683 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 29814598128 ps |
| CPU time | 12.47 seconds |
| Started | Aug 01 04:58:35 PM PDT 24 |
| Finished | Aug 01 04:58:48 PM PDT 24 |
| Peak memory | 195908 kb |
| Host | smart-fdb1eb76-7f85-41ca-afd1-0a5fe6fde97d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=16715683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.16715683 |
| Directory | /workspace/31.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/31.uart_smoke.1782422580 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 627907504 ps |
| CPU time | 2.65 seconds |
| Started | Aug 01 04:58:40 PM PDT 24 |
| Finished | Aug 01 04:58:43 PM PDT 24 |
| Peak memory | 198204 kb |
| Host | smart-551c802c-2645-4791-8bf7-578197f02e3f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1782422580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1782422580 |
| Directory | /workspace/31.uart_smoke/latest |
| Test location | /workspace/coverage/default/31.uart_stress_all_with_rand_reset.567402056 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 8193255130 ps |
| CPU time | 89.22 seconds |
| Started | Aug 01 04:58:35 PM PDT 24 |
| Finished | Aug 01 05:00:04 PM PDT 24 |
| Peak memory | 208152 kb |
| Host | smart-78959859-b4f8-44cf-97bc-38560e19c333 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567402056 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.567402056 |
| Directory | /workspace/31.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/31.uart_tx_ovrd.2156962406 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 726722580 ps |
| CPU time | 2.04 seconds |
| Started | Aug 01 04:58:41 PM PDT 24 |
| Finished | Aug 01 04:58:43 PM PDT 24 |
| Peak memory | 198776 kb |
| Host | smart-9bdac47d-6eb9-4ba4-961b-84b5fcfacab8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2156962406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.2156962406 |
| Directory | /workspace/31.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/31.uart_tx_rx.1652865312 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 30200226037 ps |
| CPU time | 62.6 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:36 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-926576b0-b028-444d-9c79-e6e3965c1f51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1652865312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.1652865312 |
| Directory | /workspace/31.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/32.uart_alert_test.3742740873 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 10966138 ps |
| CPU time | 0.53 seconds |
| Started | Aug 01 04:58:49 PM PDT 24 |
| Finished | Aug 01 04:58:50 PM PDT 24 |
| Peak memory | 194832 kb |
| Host | smart-3a33c694-0844-4450-895b-85f616be616d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742740873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.3742740873 |
| Directory | /workspace/32.uart_alert_test/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_full.2829581525 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 46715206980 ps |
| CPU time | 19.13 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:58:54 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-1f035f0d-cae8-4f0d-b72f-03d37dff87d7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2829581525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.2829581525 |
| Directory | /workspace/32.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_overflow.2529645186 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 62687676986 ps |
| CPU time | 34.82 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:09 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-c632ae9a-95b9-4566-a661-f2b95c044902 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2529645186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2529645186 |
| Directory | /workspace/32.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/32.uart_fifo_reset.2977717150 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 30109620765 ps |
| CPU time | 15.08 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:51 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-f0bb2a08-2d37-4862-b111-69be7ad0bafa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2977717150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.2977717150 |
| Directory | /workspace/32.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/32.uart_intr.1944482613 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 11519769812 ps |
| CPU time | 4.54 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:41 PM PDT 24 |
| Peak memory | 196424 kb |
| Host | smart-89ce866c-6551-42ef-9d12-bc5427828c95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944482613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.1944482613 |
| Directory | /workspace/32.uart_intr/latest |
| Test location | /workspace/coverage/default/32.uart_long_xfer_wo_dly.723854975 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 132686003773 ps |
| CPU time | 1091.04 seconds |
| Started | Aug 01 04:58:46 PM PDT 24 |
| Finished | Aug 01 05:16:57 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-78b0c56b-8416-41e4-a321-732b0a4503d9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=723854975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.723854975 |
| Directory | /workspace/32.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/32.uart_loopback.2968656105 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 9804477230 ps |
| CPU time | 4.15 seconds |
| Started | Aug 01 04:58:47 PM PDT 24 |
| Finished | Aug 01 04:58:51 PM PDT 24 |
| Peak memory | 199532 kb |
| Host | smart-f1d2eb22-e04a-4bde-89fa-c1512a80111d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2968656105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.2968656105 |
| Directory | /workspace/32.uart_loopback/latest |
| Test location | /workspace/coverage/default/32.uart_noise_filter.4220149260 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 83466553707 ps |
| CPU time | 67.2 seconds |
| Started | Aug 01 04:58:53 PM PDT 24 |
| Finished | Aug 01 05:00:00 PM PDT 24 |
| Peak memory | 199112 kb |
| Host | smart-9262b1ea-660f-45c7-a0d9-abe3afecf49b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4220149260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.4220149260 |
| Directory | /workspace/32.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/32.uart_perf.2520183310 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 13726558952 ps |
| CPU time | 285.37 seconds |
| Started | Aug 01 04:58:49 PM PDT 24 |
| Finished | Aug 01 05:03:35 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-6d58515d-a3c7-42ff-8200-663a6f8c533b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2520183310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2520183310 |
| Directory | /workspace/32.uart_perf/latest |
| Test location | /workspace/coverage/default/32.uart_rx_oversample.2405777636 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4855251445 ps |
| CPU time | 46.09 seconds |
| Started | Aug 01 04:58:40 PM PDT 24 |
| Finished | Aug 01 04:59:26 PM PDT 24 |
| Peak memory | 198124 kb |
| Host | smart-1e88afb9-544b-443e-9d07-c9e2b06093c4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2405777636 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.2405777636 |
| Directory | /workspace/32.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/32.uart_rx_parity_err.451872925 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 47309003023 ps |
| CPU time | 74.15 seconds |
| Started | Aug 01 04:58:45 PM PDT 24 |
| Finished | Aug 01 04:59:59 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-67792224-00f7-4b65-9646-bbe5223ce73f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=451872925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.451872925 |
| Directory | /workspace/32.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/32.uart_rx_start_bit_filter.1634116757 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 447403197 ps |
| CPU time | 1.41 seconds |
| Started | Aug 01 04:58:53 PM PDT 24 |
| Finished | Aug 01 04:58:54 PM PDT 24 |
| Peak memory | 195452 kb |
| Host | smart-cf37a9b2-ac3e-4518-b39a-3a54a0c21e7d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1634116757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.1634116757 |
| Directory | /workspace/32.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/32.uart_smoke.2515712658 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 946139522 ps |
| CPU time | 2.64 seconds |
| Started | Aug 01 04:58:36 PM PDT 24 |
| Finished | Aug 01 04:58:39 PM PDT 24 |
| Peak memory | 199456 kb |
| Host | smart-63ecbf19-1469-436c-9aef-a08eaa7edac7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2515712658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2515712658 |
| Directory | /workspace/32.uart_smoke/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all.1312284743 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 195443835749 ps |
| CPU time | 267.04 seconds |
| Started | Aug 01 04:58:47 PM PDT 24 |
| Finished | Aug 01 05:03:14 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-8af58d5d-68b5-4c44-a418-4001063757bd |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312284743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1312284743 |
| Directory | /workspace/32.uart_stress_all/latest |
| Test location | /workspace/coverage/default/32.uart_stress_all_with_rand_reset.2813669634 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 498721566937 ps |
| CPU time | 417.85 seconds |
| Started | Aug 01 04:58:45 PM PDT 24 |
| Finished | Aug 01 05:05:43 PM PDT 24 |
| Peak memory | 216336 kb |
| Host | smart-7c120591-d472-4387-8879-3b0b7d5b0483 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813669634 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.2813669634 |
| Directory | /workspace/32.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/32.uart_tx_ovrd.2082837028 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 936548221 ps |
| CPU time | 2.43 seconds |
| Started | Aug 01 04:58:53 PM PDT 24 |
| Finished | Aug 01 04:58:56 PM PDT 24 |
| Peak memory | 197980 kb |
| Host | smart-112cf9c3-35ae-4ac7-9ade-33ace6a96b78 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2082837028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2082837028 |
| Directory | /workspace/32.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/32.uart_tx_rx.870609946 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 31557137585 ps |
| CPU time | 44.67 seconds |
| Started | Aug 01 04:58:34 PM PDT 24 |
| Finished | Aug 01 04:59:19 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-9d7e8316-2f62-41fe-937a-f8ce465324d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=870609946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.870609946 |
| Directory | /workspace/32.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/33.uart_alert_test.2174423680 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 11448219 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:59:01 PM PDT 24 |
| Finished | Aug 01 04:59:02 PM PDT 24 |
| Peak memory | 194648 kb |
| Host | smart-5c29fae7-d648-4bcb-9edd-626cd7ff9bda |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174423680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.2174423680 |
| Directory | /workspace/33.uart_alert_test/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_full.3934573804 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 31318100313 ps |
| CPU time | 53.92 seconds |
| Started | Aug 01 04:58:46 PM PDT 24 |
| Finished | Aug 01 04:59:40 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-73f6f100-b038-4de1-9059-80f015105cda |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3934573804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3934573804 |
| Directory | /workspace/33.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/33.uart_fifo_overflow.1832616916 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 25820363335 ps |
| CPU time | 40 seconds |
| Started | Aug 01 04:58:46 PM PDT 24 |
| Finished | Aug 01 04:59:26 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-6b569de3-d4e8-416a-9c97-9aca6e761310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1832616916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1832616916 |
| Directory | /workspace/33.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/33.uart_intr.2033400487 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 11726035682 ps |
| CPU time | 19.5 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:16 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-6f2e615c-d298-4d04-bd10-c35b70a0ea95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033400487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2033400487 |
| Directory | /workspace/33.uart_intr/latest |
| Test location | /workspace/coverage/default/33.uart_long_xfer_wo_dly.2555817129 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 99911197946 ps |
| CPU time | 420.17 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 05:05:57 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-39cde03f-5c00-4688-9961-39369bdf56f3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2555817129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2555817129 |
| Directory | /workspace/33.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/33.uart_loopback.49097439 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 7800234146 ps |
| CPU time | 16.04 seconds |
| Started | Aug 01 04:58:58 PM PDT 24 |
| Finished | Aug 01 04:59:15 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-dbddf373-baf5-415e-a0ce-2188f183577b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=49097439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.49097439 |
| Directory | /workspace/33.uart_loopback/latest |
| Test location | /workspace/coverage/default/33.uart_noise_filter.2333453964 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 73898281074 ps |
| CPU time | 64.75 seconds |
| Started | Aug 01 04:59:00 PM PDT 24 |
| Finished | Aug 01 05:00:05 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-1dc82678-3662-447d-8542-5aedecb18269 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2333453964 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2333453964 |
| Directory | /workspace/33.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/33.uart_perf.2426821469 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 14065569267 ps |
| CPU time | 384.39 seconds |
| Started | Aug 01 04:58:56 PM PDT 24 |
| Finished | Aug 01 05:05:21 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-e2c509fa-ba51-48ab-9d80-c8621aaa0123 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2426821469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.2426821469 |
| Directory | /workspace/33.uart_perf/latest |
| Test location | /workspace/coverage/default/33.uart_rx_oversample.2864167117 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 6631857878 ps |
| CPU time | 57.49 seconds |
| Started | Aug 01 04:59:01 PM PDT 24 |
| Finished | Aug 01 04:59:58 PM PDT 24 |
| Peak memory | 197908 kb |
| Host | smart-f1d7f8a8-db85-4555-9aff-69e10899f61c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2864167117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2864167117 |
| Directory | /workspace/33.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/33.uart_rx_parity_err.3181496552 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 30646458332 ps |
| CPU time | 51.51 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:49 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-88de3c0f-1f3b-4a2b-8e09-72d28f8201d0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3181496552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.3181496552 |
| Directory | /workspace/33.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/33.uart_rx_start_bit_filter.2070227980 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 3687980388 ps |
| CPU time | 1.88 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:58:59 PM PDT 24 |
| Peak memory | 196140 kb |
| Host | smart-51783f6c-aa3b-4975-9300-09f43e8b9dc5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2070227980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2070227980 |
| Directory | /workspace/33.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/33.uart_smoke.3282926656 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 120207989 ps |
| CPU time | 1.16 seconds |
| Started | Aug 01 04:58:46 PM PDT 24 |
| Finished | Aug 01 04:58:47 PM PDT 24 |
| Peak memory | 199432 kb |
| Host | smart-8800c947-6c4f-4beb-b936-5d140e4be7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3282926656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3282926656 |
| Directory | /workspace/33.uart_smoke/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all.503422354 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 102902841289 ps |
| CPU time | 148.1 seconds |
| Started | Aug 01 04:58:58 PM PDT 24 |
| Finished | Aug 01 05:01:26 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-8683f762-d2f0-483c-bc27-d7b73e0cffbf |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503422354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.503422354 |
| Directory | /workspace/33.uart_stress_all/latest |
| Test location | /workspace/coverage/default/33.uart_stress_all_with_rand_reset.1628884765 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 204224892975 ps |
| CPU time | 453.62 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 05:06:31 PM PDT 24 |
| Peak memory | 209364 kb |
| Host | smart-225bae89-9f06-4d36-ae74-cf0b440007c3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628884765 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.1628884765 |
| Directory | /workspace/33.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/33.uart_tx_ovrd.3063611908 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 584914933 ps |
| CPU time | 2.86 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:00 PM PDT 24 |
| Peak memory | 199192 kb |
| Host | smart-3e33d209-fb31-43e5-8a72-a0af603a5c4c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3063611908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.3063611908 |
| Directory | /workspace/33.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/33.uart_tx_rx.2010308819 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 61341917877 ps |
| CPU time | 31.97 seconds |
| Started | Aug 01 04:58:46 PM PDT 24 |
| Finished | Aug 01 04:59:19 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-29263344-ac1f-43f5-8934-6a468405e39d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010308819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2010308819 |
| Directory | /workspace/33.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/34.uart_alert_test.2295603321 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 43119388 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:08 PM PDT 24 |
| Peak memory | 194180 kb |
| Host | smart-8aae5a8a-2efe-4eb5-b0e4-1134cab9b9c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295603321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.2295603321 |
| Directory | /workspace/34.uart_alert_test/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_full.1364386351 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 63012489956 ps |
| CPU time | 47.92 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:45 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-a05ab1fd-770a-43bb-8ace-ac1d2a7cbcf7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1364386351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.1364386351 |
| Directory | /workspace/34.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_overflow.4094614266 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 89129090010 ps |
| CPU time | 88.25 seconds |
| Started | Aug 01 04:58:58 PM PDT 24 |
| Finished | Aug 01 05:00:26 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-7af9875b-8fa2-4bbd-bdb5-2b8e94ae8982 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4094614266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.4094614266 |
| Directory | /workspace/34.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/34.uart_fifo_reset.2184923954 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 97524762704 ps |
| CPU time | 47.66 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:45 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-e3cb941c-c4a7-43dc-bddc-06dd491a4974 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2184923954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.2184923954 |
| Directory | /workspace/34.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/34.uart_intr.1826153803 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 263260648761 ps |
| CPU time | 113.16 seconds |
| Started | Aug 01 04:59:06 PM PDT 24 |
| Finished | Aug 01 05:01:00 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-b7813403-a15e-4f59-b08a-dc39db14be39 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826153803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1826153803 |
| Directory | /workspace/34.uart_intr/latest |
| Test location | /workspace/coverage/default/34.uart_long_xfer_wo_dly.953332041 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 55931810715 ps |
| CPU time | 132.76 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:01:20 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-c81c5299-17d3-43ed-a1b4-5ba051064e74 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=953332041 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.953332041 |
| Directory | /workspace/34.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/34.uart_loopback.3120083429 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 9041579461 ps |
| CPU time | 5.76 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:14 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-40a90fa4-d548-4b6e-8fb2-ec14cf3c555a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3120083429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.3120083429 |
| Directory | /workspace/34.uart_loopback/latest |
| Test location | /workspace/coverage/default/34.uart_noise_filter.1879492772 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 40038789392 ps |
| CPU time | 15.55 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:24 PM PDT 24 |
| Peak memory | 199952 kb |
| Host | smart-ad5d7735-7eab-4c0a-8f44-1adbcc1c9137 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1879492772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1879492772 |
| Directory | /workspace/34.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/34.uart_perf.1329590201 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 19900749681 ps |
| CPU time | 282.18 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:03:49 PM PDT 24 |
| Peak memory | 199680 kb |
| Host | smart-77a228a0-dae8-40dc-993e-4ff894e4781b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1329590201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1329590201 |
| Directory | /workspace/34.uart_perf/latest |
| Test location | /workspace/coverage/default/34.uart_rx_oversample.1798300530 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 6814435965 ps |
| CPU time | 15.65 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:23 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-e1260ecc-bd9a-4f85-adb6-4f03080f0b91 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1798300530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.1798300530 |
| Directory | /workspace/34.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/34.uart_rx_parity_err.1383436402 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 9685972837 ps |
| CPU time | 12.08 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:21 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-167457c5-194c-4bf6-a8a5-7f2314ac8541 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1383436402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1383436402 |
| Directory | /workspace/34.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/34.uart_rx_start_bit_filter.1185137158 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3739344938 ps |
| CPU time | 1.94 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:11 PM PDT 24 |
| Peak memory | 196724 kb |
| Host | smart-9d4be795-1bb0-41f8-9162-4a2971a01424 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185137158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.1185137158 |
| Directory | /workspace/34.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/34.uart_smoke.2418027783 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 5375047290 ps |
| CPU time | 9.81 seconds |
| Started | Aug 01 04:58:58 PM PDT 24 |
| Finished | Aug 01 04:59:08 PM PDT 24 |
| Peak memory | 199560 kb |
| Host | smart-e802ae19-5e91-4fa6-b8ca-2df004ad4de2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2418027783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2418027783 |
| Directory | /workspace/34.uart_smoke/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all.929981827 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 256099885482 ps |
| CPU time | 223.91 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 05:02:52 PM PDT 24 |
| Peak memory | 199856 kb |
| Host | smart-d611fe79-3278-461f-b7e8-447fafa0117e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929981827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.929981827 |
| Directory | /workspace/34.uart_stress_all/latest |
| Test location | /workspace/coverage/default/34.uart_stress_all_with_rand_reset.2844438108 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 95774966151 ps |
| CPU time | 737.16 seconds |
| Started | Aug 01 04:59:10 PM PDT 24 |
| Finished | Aug 01 05:11:27 PM PDT 24 |
| Peak memory | 224676 kb |
| Host | smart-e4d139b5-4e6d-411d-8251-5c2e5823b8d3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844438108 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.2844438108 |
| Directory | /workspace/34.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/34.uart_tx_ovrd.1487985182 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 1023333059 ps |
| CPU time | 3.23 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:13 PM PDT 24 |
| Peak memory | 199296 kb |
| Host | smart-fa47b285-7d85-4479-8194-a3e618a6f355 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1487985182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1487985182 |
| Directory | /workspace/34.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/34.uart_tx_rx.1633278674 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 48934922759 ps |
| CPU time | 24.49 seconds |
| Started | Aug 01 04:58:57 PM PDT 24 |
| Finished | Aug 01 04:59:22 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-9a002e09-e4ce-4d95-9586-720252d08887 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1633278674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1633278674 |
| Directory | /workspace/34.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/35.uart_alert_test.3524653352 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 50263421 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:59:12 PM PDT 24 |
| Finished | Aug 01 04:59:13 PM PDT 24 |
| Peak memory | 195616 kb |
| Host | smart-7977d422-5264-4370-8f7c-90b67986bb15 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524653352 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3524653352 |
| Directory | /workspace/35.uart_alert_test/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_full.1265828954 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 41512731975 ps |
| CPU time | 13.89 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:22 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-3801c71d-d872-4923-abfb-a3dfd1317078 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1265828954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.1265828954 |
| Directory | /workspace/35.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_overflow.3259595222 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 54139603814 ps |
| CPU time | 46.97 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:56 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-2496eb79-fa2c-4ed6-b2c9-3ca420ea32f3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3259595222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3259595222 |
| Directory | /workspace/35.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/35.uart_fifo_reset.1087119532 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 22090988696 ps |
| CPU time | 11.19 seconds |
| Started | Aug 01 04:59:11 PM PDT 24 |
| Finished | Aug 01 04:59:23 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-52144227-c119-429f-a208-911d0466c881 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1087119532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.1087119532 |
| Directory | /workspace/35.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/35.uart_intr.627604824 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 237576909605 ps |
| CPU time | 354.89 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:05:02 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-88342541-268c-4485-9e70-cfe83f8245f4 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627604824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.627604824 |
| Directory | /workspace/35.uart_intr/latest |
| Test location | /workspace/coverage/default/35.uart_long_xfer_wo_dly.3172678569 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 110679240812 ps |
| CPU time | 328.8 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 05:04:37 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-6a19eda1-b602-472f-b3cb-87fe760ca4f6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3172678569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3172678569 |
| Directory | /workspace/35.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/35.uart_loopback.1185142593 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 3456258163 ps |
| CPU time | 5.56 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:13 PM PDT 24 |
| Peak memory | 197468 kb |
| Host | smart-05ed9667-5dd7-4546-bdad-ea0fb7c80e30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1185142593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.1185142593 |
| Directory | /workspace/35.uart_loopback/latest |
| Test location | /workspace/coverage/default/35.uart_noise_filter.2068810794 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 194942946586 ps |
| CPU time | 104.8 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 05:00:54 PM PDT 24 |
| Peak memory | 197440 kb |
| Host | smart-5abf8f7c-331f-4886-a098-f2bb8b7d0ccf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2068810794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.2068810794 |
| Directory | /workspace/35.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/35.uart_perf.2815540566 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 19935509032 ps |
| CPU time | 57.83 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 05:00:07 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-20b8dd95-d0bd-463c-ba4c-fb6b24f25e68 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2815540566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.2815540566 |
| Directory | /workspace/35.uart_perf/latest |
| Test location | /workspace/coverage/default/35.uart_rx_oversample.1041535798 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 2343366683 ps |
| CPU time | 15.1 seconds |
| Started | Aug 01 04:59:10 PM PDT 24 |
| Finished | Aug 01 04:59:25 PM PDT 24 |
| Peak memory | 198736 kb |
| Host | smart-7cb2180c-cc7e-4564-bf2d-653d7cd04f3a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1041535798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.1041535798 |
| Directory | /workspace/35.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/35.uart_rx_parity_err.3966117457 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 31985187172 ps |
| CPU time | 13.18 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 04:59:20 PM PDT 24 |
| Peak memory | 199524 kb |
| Host | smart-929a5e2e-aad1-4a3b-bc4c-4282d569d24c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3966117457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.3966117457 |
| Directory | /workspace/35.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/35.uart_rx_start_bit_filter.2941512784 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 3408334293 ps |
| CPU time | 1.72 seconds |
| Started | Aug 01 04:59:10 PM PDT 24 |
| Finished | Aug 01 04:59:11 PM PDT 24 |
| Peak memory | 196404 kb |
| Host | smart-83c8d9c0-d40d-43cb-887f-bd7fb027ed47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2941512784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.2941512784 |
| Directory | /workspace/35.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/35.uart_smoke.1011732640 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 686773749 ps |
| CPU time | 2.94 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:12 PM PDT 24 |
| Peak memory | 198580 kb |
| Host | smart-b9547dc7-2345-4f2d-bf3e-398426a36192 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1011732640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.1011732640 |
| Directory | /workspace/35.uart_smoke/latest |
| Test location | /workspace/coverage/default/35.uart_stress_all.2200600740 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 101545517823 ps |
| CPU time | 195.8 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:02:23 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-ee726a08-a6cd-41b6-9dcf-1aa26fd47091 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200600740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2200600740 |
| Directory | /workspace/35.uart_stress_all/latest |
| Test location | /workspace/coverage/default/35.uart_tx_ovrd.3209898266 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 908237849 ps |
| CPU time | 1.49 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 04:59:11 PM PDT 24 |
| Peak memory | 198276 kb |
| Host | smart-aacf7ee1-be4d-4c57-9729-5ce03228b99c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3209898266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3209898266 |
| Directory | /workspace/35.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/35.uart_tx_rx.3231590701 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 264388478515 ps |
| CPU time | 21.02 seconds |
| Started | Aug 01 04:59:06 PM PDT 24 |
| Finished | Aug 01 04:59:27 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-ba037904-4feb-49ad-a33f-707ad09a671c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3231590701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3231590701 |
| Directory | /workspace/35.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/36.uart_alert_test.1898190310 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 14142717 ps |
| CPU time | 0.61 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 04:59:20 PM PDT 24 |
| Peak memory | 195524 kb |
| Host | smart-a001531f-eb62-47bb-90a1-4c71b9681643 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898190310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1898190310 |
| Directory | /workspace/36.uart_alert_test/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_full.3601801803 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 258439890780 ps |
| CPU time | 34.68 seconds |
| Started | Aug 01 04:59:10 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-4e8c4e0a-2cec-415d-9e15-befd16b7ae30 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3601801803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.3601801803 |
| Directory | /workspace/36.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_overflow.1630504184 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 124675863173 ps |
| CPU time | 234.89 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:03:02 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-85265af2-a8dc-49c9-8645-0bf089b2af72 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1630504184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1630504184 |
| Directory | /workspace/36.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/36.uart_fifo_reset.2327096992 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 101063755712 ps |
| CPU time | 490.45 seconds |
| Started | Aug 01 04:59:07 PM PDT 24 |
| Finished | Aug 01 05:07:17 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-d8ec5024-c889-4565-852f-4a046e2e1e7a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2327096992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2327096992 |
| Directory | /workspace/36.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/36.uart_intr.3828369680 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 11153016791 ps |
| CPU time | 4.99 seconds |
| Started | Aug 01 04:59:08 PM PDT 24 |
| Finished | Aug 01 04:59:13 PM PDT 24 |
| Peak memory | 197372 kb |
| Host | smart-4113be94-838a-4163-8841-691052b07223 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828369680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3828369680 |
| Directory | /workspace/36.uart_intr/latest |
| Test location | /workspace/coverage/default/36.uart_long_xfer_wo_dly.1503239827 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 40276627201 ps |
| CPU time | 168.74 seconds |
| Started | Aug 01 04:59:20 PM PDT 24 |
| Finished | Aug 01 05:02:08 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-a11dc47c-ebdd-4085-ba44-aa5a1849f1a5 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1503239827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.1503239827 |
| Directory | /workspace/36.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/36.uart_loopback.4136873579 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 9470125665 ps |
| CPU time | 3.67 seconds |
| Started | Aug 01 04:59:17 PM PDT 24 |
| Finished | Aug 01 04:59:21 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-e869eeb8-2adf-4e3a-bc19-1acd3bb52c85 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136873579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.4136873579 |
| Directory | /workspace/36.uart_loopback/latest |
| Test location | /workspace/coverage/default/36.uart_noise_filter.3442994635 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 23238078431 ps |
| CPU time | 13.67 seconds |
| Started | Aug 01 04:59:20 PM PDT 24 |
| Finished | Aug 01 04:59:34 PM PDT 24 |
| Peak memory | 196652 kb |
| Host | smart-c6b9400e-8d04-4569-8b40-249b795dcc58 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442994635 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3442994635 |
| Directory | /workspace/36.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/36.uart_perf.3189312316 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 16808276199 ps |
| CPU time | 245.59 seconds |
| Started | Aug 01 04:59:17 PM PDT 24 |
| Finished | Aug 01 05:03:22 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-4753b421-319f-454f-a43e-278127d3463b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3189312316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.3189312316 |
| Directory | /workspace/36.uart_perf/latest |
| Test location | /workspace/coverage/default/36.uart_rx_oversample.4256565893 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 5803442678 ps |
| CPU time | 6.34 seconds |
| Started | Aug 01 04:59:12 PM PDT 24 |
| Finished | Aug 01 04:59:19 PM PDT 24 |
| Peak memory | 199376 kb |
| Host | smart-ecf187f8-098c-4bae-8e3c-993f87c9395d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4256565893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.4256565893 |
| Directory | /workspace/36.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/36.uart_rx_parity_err.3735198979 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 39811160950 ps |
| CPU time | 14.69 seconds |
| Started | Aug 01 04:59:20 PM PDT 24 |
| Finished | Aug 01 04:59:35 PM PDT 24 |
| Peak memory | 199560 kb |
| Host | smart-27f6dd9a-86ef-4f5e-852e-45f0c2bb9146 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3735198979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.3735198979 |
| Directory | /workspace/36.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/36.uart_rx_start_bit_filter.985752724 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 50391774302 ps |
| CPU time | 81.12 seconds |
| Started | Aug 01 04:59:18 PM PDT 24 |
| Finished | Aug 01 05:00:40 PM PDT 24 |
| Peak memory | 196040 kb |
| Host | smart-f58961d8-ad5c-4079-8aed-9957cbb161f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=985752724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.985752724 |
| Directory | /workspace/36.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/36.uart_smoke.821592038 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 271479325 ps |
| CPU time | 1.27 seconds |
| Started | Aug 01 04:59:10 PM PDT 24 |
| Finished | Aug 01 04:59:11 PM PDT 24 |
| Peak memory | 199300 kb |
| Host | smart-51df56ad-0811-472b-860b-798ae500da04 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=821592038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.821592038 |
| Directory | /workspace/36.uart_smoke/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all.3128659666 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 28136385737 ps |
| CPU time | 26.43 seconds |
| Started | Aug 01 04:59:18 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-a7b85794-ab86-4203-b801-e277e23d2f32 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128659666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.3128659666 |
| Directory | /workspace/36.uart_stress_all/latest |
| Test location | /workspace/coverage/default/36.uart_stress_all_with_rand_reset.1393628514 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 27065682558 ps |
| CPU time | 289.66 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 05:04:09 PM PDT 24 |
| Peak memory | 216500 kb |
| Host | smart-882e3cb0-e16b-47c8-b3fb-35cd2d6f91ed |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393628514 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.1393628514 |
| Directory | /workspace/36.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/36.uart_tx_ovrd.2912811889 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 514286625 ps |
| CPU time | 2.08 seconds |
| Started | Aug 01 04:59:21 PM PDT 24 |
| Finished | Aug 01 04:59:23 PM PDT 24 |
| Peak memory | 198172 kb |
| Host | smart-b29a6cc2-6a75-4010-bfdc-d243deca8a51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2912811889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.2912811889 |
| Directory | /workspace/36.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/36.uart_tx_rx.1725240040 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 135710556810 ps |
| CPU time | 282.6 seconds |
| Started | Aug 01 04:59:09 PM PDT 24 |
| Finished | Aug 01 05:03:52 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-89cd85fd-1cf7-4e30-ab9c-0fcda5bbef9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1725240040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1725240040 |
| Directory | /workspace/36.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/37.uart_alert_test.1583267805 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 13537417 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:59:32 PM PDT 24 |
| Finished | Aug 01 04:59:33 PM PDT 24 |
| Peak memory | 195332 kb |
| Host | smart-ea6306aa-db7b-4a20-8191-11a4278c7fbc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583267805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1583267805 |
| Directory | /workspace/37.uart_alert_test/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_full.2715710181 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 29672357442 ps |
| CPU time | 53.73 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 05:00:13 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-6853d0e7-8222-4a2b-a93c-bae1a452db68 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2715710181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2715710181 |
| Directory | /workspace/37.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_overflow.1755015582 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 13396846753 ps |
| CPU time | 20.22 seconds |
| Started | Aug 01 04:59:18 PM PDT 24 |
| Finished | Aug 01 04:59:38 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-cb80b875-8e70-4532-8962-5cb47a18002e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1755015582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1755015582 |
| Directory | /workspace/37.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/37.uart_fifo_reset.3102003623 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 19555691081 ps |
| CPU time | 41.22 seconds |
| Started | Aug 01 04:59:18 PM PDT 24 |
| Finished | Aug 01 05:00:00 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-25d48980-4751-4797-afd7-80a223e690ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3102003623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.3102003623 |
| Directory | /workspace/37.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/37.uart_intr.482064475 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 39042308513 ps |
| CPU time | 35.74 seconds |
| Started | Aug 01 04:59:18 PM PDT 24 |
| Finished | Aug 01 04:59:54 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-13fcb0b4-c0d3-4885-9646-f3019f112f2a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482064475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.482064475 |
| Directory | /workspace/37.uart_intr/latest |
| Test location | /workspace/coverage/default/37.uart_long_xfer_wo_dly.4193788652 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 56619415194 ps |
| CPU time | 148.24 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 05:02:00 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-04ce0c02-3955-4255-a9c1-223048a11937 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4193788652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4193788652 |
| Directory | /workspace/37.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/37.uart_loopback.3437438430 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 979919287 ps |
| CPU time | 2.07 seconds |
| Started | Aug 01 04:59:21 PM PDT 24 |
| Finished | Aug 01 04:59:23 PM PDT 24 |
| Peak memory | 195272 kb |
| Host | smart-2b8512eb-c86d-4ec5-9622-67f398221fe3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3437438430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.3437438430 |
| Directory | /workspace/37.uart_loopback/latest |
| Test location | /workspace/coverage/default/37.uart_noise_filter.3188493566 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 107845275655 ps |
| CPU time | 115.74 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 05:01:15 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-0adef2f9-db92-4dd4-a9bd-b5a554dbbbdf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3188493566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.3188493566 |
| Directory | /workspace/37.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/37.uart_perf.83535254 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 15949958521 ps |
| CPU time | 710.08 seconds |
| Started | Aug 01 04:59:34 PM PDT 24 |
| Finished | Aug 01 05:11:24 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-2507a7a5-62a0-4d81-8bd3-ac6f7e918184 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=83535254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.83535254 |
| Directory | /workspace/37.uart_perf/latest |
| Test location | /workspace/coverage/default/37.uart_rx_oversample.894836705 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 3688446366 ps |
| CPU time | 3.47 seconds |
| Started | Aug 01 04:59:17 PM PDT 24 |
| Finished | Aug 01 04:59:20 PM PDT 24 |
| Peak memory | 198000 kb |
| Host | smart-d7509c51-e1e7-490c-854d-2a9463fe8055 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=894836705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.894836705 |
| Directory | /workspace/37.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/37.uart_rx_parity_err.3397525009 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 168388237249 ps |
| CPU time | 158.07 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 05:01:57 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-58c4982f-b25d-4a1d-bdbd-e1731a917c0c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3397525009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.3397525009 |
| Directory | /workspace/37.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/37.uart_rx_start_bit_filter.4052614492 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3753000280 ps |
| CPU time | 1.76 seconds |
| Started | Aug 01 04:59:20 PM PDT 24 |
| Finished | Aug 01 04:59:22 PM PDT 24 |
| Peak memory | 195968 kb |
| Host | smart-2f325dfd-0d49-4b1d-9ebd-25c64f85e88b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4052614492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.4052614492 |
| Directory | /workspace/37.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/37.uart_smoke.2519683337 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 452824339 ps |
| CPU time | 1.69 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 04:59:20 PM PDT 24 |
| Peak memory | 198308 kb |
| Host | smart-5a5081ef-0391-46d3-845b-aceaba96edb2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2519683337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2519683337 |
| Directory | /workspace/37.uart_smoke/latest |
| Test location | /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3986974439 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 33910135989 ps |
| CPU time | 395.41 seconds |
| Started | Aug 01 04:59:30 PM PDT 24 |
| Finished | Aug 01 05:06:06 PM PDT 24 |
| Peak memory | 213920 kb |
| Host | smart-1ade7d02-3573-4fb3-9163-02cdd2114876 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986974439 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3986974439 |
| Directory | /workspace/37.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/37.uart_tx_ovrd.4093301273 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 884742017 ps |
| CPU time | 2.99 seconds |
| Started | Aug 01 04:59:17 PM PDT 24 |
| Finished | Aug 01 04:59:20 PM PDT 24 |
| Peak memory | 199488 kb |
| Host | smart-dd7956ee-019b-40ae-b92b-238d7321b017 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4093301273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4093301273 |
| Directory | /workspace/37.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/37.uart_tx_rx.987073377 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 53952419566 ps |
| CPU time | 25.04 seconds |
| Started | Aug 01 04:59:19 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-9dc97ad8-3267-4377-92d3-88857f413ed2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=987073377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.987073377 |
| Directory | /workspace/37.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/38.uart_alert_test.2768324485 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 11171608 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:59:42 PM PDT 24 |
| Finished | Aug 01 04:59:42 PM PDT 24 |
| Peak memory | 194180 kb |
| Host | smart-42e95eaa-99d0-4cb6-bf54-0591d7c0de2c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768324485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.2768324485 |
| Directory | /workspace/38.uart_alert_test/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_full.3095729042 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 23182490127 ps |
| CPU time | 17.48 seconds |
| Started | Aug 01 04:59:32 PM PDT 24 |
| Finished | Aug 01 04:59:49 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-3be9bd04-4f9c-41d0-8454-87ffc7ad1004 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3095729042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3095729042 |
| Directory | /workspace/38.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_overflow.2057604807 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 12673912699 ps |
| CPU time | 18.42 seconds |
| Started | Aug 01 04:59:32 PM PDT 24 |
| Finished | Aug 01 04:59:50 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-bb3fab84-8f6d-4a95-9ee0-81ddee8389e8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2057604807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2057604807 |
| Directory | /workspace/38.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/38.uart_fifo_reset.1338620556 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 33105743368 ps |
| CPU time | 61.05 seconds |
| Started | Aug 01 04:59:30 PM PDT 24 |
| Finished | Aug 01 05:00:32 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-bd3c9f73-4d8a-4f19-9d78-bbd5721c4b34 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1338620556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.1338620556 |
| Directory | /workspace/38.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/38.uart_intr.817141418 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 14481875161 ps |
| CPU time | 11.33 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 04:59:43 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-85b1faaf-dcc1-4bfa-9cba-6d3cbc655bd7 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817141418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.817141418 |
| Directory | /workspace/38.uart_intr/latest |
| Test location | /workspace/coverage/default/38.uart_long_xfer_wo_dly.1767421955 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 80095831895 ps |
| CPU time | 248.54 seconds |
| Started | Aug 01 04:59:32 PM PDT 24 |
| Finished | Aug 01 05:03:40 PM PDT 24 |
| Peak memory | 199880 kb |
| Host | smart-693f24b2-1c60-4864-819a-ff939b761673 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1767421955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.1767421955 |
| Directory | /workspace/38.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/38.uart_loopback.4065505619 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 12869431148 ps |
| CPU time | 13.86 seconds |
| Started | Aug 01 04:59:34 PM PDT 24 |
| Finished | Aug 01 04:59:48 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-27489c4a-b5ba-4e21-b56b-9dced1fec275 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4065505619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.4065505619 |
| Directory | /workspace/38.uart_loopback/latest |
| Test location | /workspace/coverage/default/38.uart_noise_filter.2318789246 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 77350422659 ps |
| CPU time | 35.27 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 05:00:06 PM PDT 24 |
| Peak memory | 199960 kb |
| Host | smart-0dbafbce-47ed-4d6f-a4b3-b53941bc6c5e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2318789246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.2318789246 |
| Directory | /workspace/38.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/38.uart_perf.1967958182 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 5353745228 ps |
| CPU time | 79.12 seconds |
| Started | Aug 01 04:59:34 PM PDT 24 |
| Finished | Aug 01 05:00:53 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-1256d551-d0d7-492e-bae6-0a2e002976e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1967958182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.1967958182 |
| Directory | /workspace/38.uart_perf/latest |
| Test location | /workspace/coverage/default/38.uart_rx_oversample.2778164091 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 5126875887 ps |
| CPU time | 42.46 seconds |
| Started | Aug 01 04:59:32 PM PDT 24 |
| Finished | Aug 01 05:00:14 PM PDT 24 |
| Peak memory | 197652 kb |
| Host | smart-57b06245-6040-4e52-9df9-d499238dbc13 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2778164091 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.2778164091 |
| Directory | /workspace/38.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/38.uart_rx_parity_err.1809017610 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 139398098621 ps |
| CPU time | 213.33 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 05:03:05 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-3d79f507-a958-4485-b4f8-6dec9428d97f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809017610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1809017610 |
| Directory | /workspace/38.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/38.uart_rx_start_bit_filter.1191372077 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 4096976721 ps |
| CPU time | 7.16 seconds |
| Started | Aug 01 04:59:31 PM PDT 24 |
| Finished | Aug 01 04:59:38 PM PDT 24 |
| Peak memory | 196276 kb |
| Host | smart-1fe073c5-afb8-4760-9084-4f46edba8330 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1191372077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.1191372077 |
| Directory | /workspace/38.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/38.uart_smoke.3306980243 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 650045125 ps |
| CPU time | 2.74 seconds |
| Started | Aug 01 04:59:29 PM PDT 24 |
| Finished | Aug 01 04:59:32 PM PDT 24 |
| Peak memory | 199580 kb |
| Host | smart-7219567b-7768-4db0-9d39-5b8b5f15bcc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3306980243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.3306980243 |
| Directory | /workspace/38.uart_smoke/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all.3380649909 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 123448802431 ps |
| CPU time | 229.86 seconds |
| Started | Aug 01 04:59:41 PM PDT 24 |
| Finished | Aug 01 05:03:31 PM PDT 24 |
| Peak memory | 208200 kb |
| Host | smart-2681a313-8663-4421-bff1-b4d704759e2e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380649909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3380649909 |
| Directory | /workspace/38.uart_stress_all/latest |
| Test location | /workspace/coverage/default/38.uart_stress_all_with_rand_reset.3779805185 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 356792458993 ps |
| CPU time | 356.98 seconds |
| Started | Aug 01 04:59:29 PM PDT 24 |
| Finished | Aug 01 05:05:26 PM PDT 24 |
| Peak memory | 216268 kb |
| Host | smart-e5b033fd-164f-4b76-a420-f24e367cbe1a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779805185 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.3779805185 |
| Directory | /workspace/38.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/38.uart_tx_ovrd.1047910816 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2548224579 ps |
| CPU time | 2.36 seconds |
| Started | Aug 01 04:59:29 PM PDT 24 |
| Finished | Aug 01 04:59:32 PM PDT 24 |
| Peak memory | 198420 kb |
| Host | smart-ec37e918-de42-4e57-aa90-ad53b33b164b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1047910816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.1047910816 |
| Directory | /workspace/38.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/38.uart_tx_rx.2214084363 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 146172363207 ps |
| CPU time | 24.07 seconds |
| Started | Aug 01 04:59:30 PM PDT 24 |
| Finished | Aug 01 04:59:54 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-3913ec6e-0484-42ff-a729-517525859413 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2214084363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2214084363 |
| Directory | /workspace/38.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/39.uart_alert_test.2880839801 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 17274327 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:59:43 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 195164 kb |
| Host | smart-a0a47f4d-ef15-4f92-b1e9-f9510b57d0c4 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880839801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.2880839801 |
| Directory | /workspace/39.uart_alert_test/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_full.479330792 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 99125528446 ps |
| CPU time | 37.26 seconds |
| Started | Aug 01 04:59:41 PM PDT 24 |
| Finished | Aug 01 05:00:19 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-86b37606-c330-4ad5-aa63-9256931aca10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=479330792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.479330792 |
| Directory | /workspace/39.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_overflow.2782588402 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 75966933005 ps |
| CPU time | 114.35 seconds |
| Started | Aug 01 04:59:42 PM PDT 24 |
| Finished | Aug 01 05:01:37 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-d6ba2a75-b878-46e6-b96d-06afb52f9afc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2782588402 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2782588402 |
| Directory | /workspace/39.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/39.uart_fifo_reset.3156941745 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 27722717447 ps |
| CPU time | 34.86 seconds |
| Started | Aug 01 04:59:45 PM PDT 24 |
| Finished | Aug 01 05:00:20 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-c3db93da-e65c-4455-a9a9-f22f71f8001f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3156941745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.3156941745 |
| Directory | /workspace/39.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/39.uart_intr.281616430 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 22917533200 ps |
| CPU time | 39.54 seconds |
| Started | Aug 01 04:59:44 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-160fd82f-ff13-41b6-8e97-df9e34feed9e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281616430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.281616430 |
| Directory | /workspace/39.uart_intr/latest |
| Test location | /workspace/coverage/default/39.uart_long_xfer_wo_dly.2342913540 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 48032817942 ps |
| CPU time | 184.75 seconds |
| Started | Aug 01 04:59:44 PM PDT 24 |
| Finished | Aug 01 05:02:49 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-2443f16e-f938-4bc5-9fba-e59e356ec6a4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2342913540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2342913540 |
| Directory | /workspace/39.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/39.uart_loopback.3457009424 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 6457322966 ps |
| CPU time | 14.98 seconds |
| Started | Aug 01 04:59:43 PM PDT 24 |
| Finished | Aug 01 04:59:59 PM PDT 24 |
| Peak memory | 199516 kb |
| Host | smart-475dae15-15eb-47d8-87d3-ed9956ab5abc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3457009424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.3457009424 |
| Directory | /workspace/39.uart_loopback/latest |
| Test location | /workspace/coverage/default/39.uart_noise_filter.1868221654 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 57681350574 ps |
| CPU time | 52.36 seconds |
| Started | Aug 01 04:59:43 PM PDT 24 |
| Finished | Aug 01 05:00:35 PM PDT 24 |
| Peak memory | 200012 kb |
| Host | smart-33ea1182-f5fc-47b6-b157-1d9593dda458 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1868221654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.1868221654 |
| Directory | /workspace/39.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/39.uart_perf.3027907462 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 23223561774 ps |
| CPU time | 276.13 seconds |
| Started | Aug 01 04:59:44 PM PDT 24 |
| Finished | Aug 01 05:04:21 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-938deb7c-e89e-49e1-b6c3-aae5fae35dc7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3027907462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.3027907462 |
| Directory | /workspace/39.uart_perf/latest |
| Test location | /workspace/coverage/default/39.uart_rx_oversample.2089206497 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 6236420323 ps |
| CPU time | 50.83 seconds |
| Started | Aug 01 04:59:41 PM PDT 24 |
| Finished | Aug 01 05:00:32 PM PDT 24 |
| Peak memory | 198748 kb |
| Host | smart-09da986a-62a4-44c0-bf93-44f2f22fa2fd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2089206497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.2089206497 |
| Directory | /workspace/39.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/39.uart_rx_parity_err.3367724096 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 103014386610 ps |
| CPU time | 66.85 seconds |
| Started | Aug 01 04:59:45 PM PDT 24 |
| Finished | Aug 01 05:00:52 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-0a5189d7-d6d8-45e8-ac8a-01ebb19e9306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3367724096 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3367724096 |
| Directory | /workspace/39.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/39.uart_rx_start_bit_filter.1809146818 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5462310486 ps |
| CPU time | 2.39 seconds |
| Started | Aug 01 04:59:41 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 195920 kb |
| Host | smart-f6f65608-8074-45d7-a1e5-ef4ada58de36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1809146818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.1809146818 |
| Directory | /workspace/39.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/39.uart_smoke.3134230845 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 6294250011 ps |
| CPU time | 9.1 seconds |
| Started | Aug 01 04:59:46 PM PDT 24 |
| Finished | Aug 01 04:59:55 PM PDT 24 |
| Peak memory | 199172 kb |
| Host | smart-7659f2c0-1757-41c3-8ecc-241ae304bcfa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3134230845 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.3134230845 |
| Directory | /workspace/39.uart_smoke/latest |
| Test location | /workspace/coverage/default/39.uart_stress_all_with_rand_reset.1828926732 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 38366779030 ps |
| CPU time | 566.82 seconds |
| Started | Aug 01 04:59:42 PM PDT 24 |
| Finished | Aug 01 05:09:09 PM PDT 24 |
| Peak memory | 216424 kb |
| Host | smart-47be08eb-5e76-4850-a4de-07b60d333f18 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828926732 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.1828926732 |
| Directory | /workspace/39.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/39.uart_tx_ovrd.545476557 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 222694844 ps |
| CPU time | 1.12 seconds |
| Started | Aug 01 04:59:43 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 196988 kb |
| Host | smart-1cefb580-df74-42cc-8510-f2a71907e57f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=545476557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.545476557 |
| Directory | /workspace/39.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/39.uart_tx_rx.1721735730 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 86667676539 ps |
| CPU time | 28.03 seconds |
| Started | Aug 01 04:59:43 PM PDT 24 |
| Finished | Aug 01 05:00:11 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-51dc41fe-55b1-4d2c-974f-ec9bd387a4d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1721735730 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.1721735730 |
| Directory | /workspace/39.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.uart_alert_test.3398780887 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 114100542 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-0fc8f7cb-194a-41c4-9fd3-de407047397c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398780887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.3398780887 |
| Directory | /workspace/4.uart_alert_test/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_full.4050802059 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 106345309545 ps |
| CPU time | 144.31 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:57:36 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-157b578b-8ded-451a-a638-ed4d6564fe05 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4050802059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.4050802059 |
| Directory | /workspace/4.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_overflow.1358040310 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 122587002710 ps |
| CPU time | 52.39 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:56:06 PM PDT 24 |
| Peak memory | 199724 kb |
| Host | smart-16788416-ce1e-406c-8051-2ab3e44c531c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1358040310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.1358040310 |
| Directory | /workspace/4.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/4.uart_fifo_reset.3899350857 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 20623591458 ps |
| CPU time | 31.76 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:43 PM PDT 24 |
| Peak memory | 200152 kb |
| Host | smart-22683430-10ef-400e-a0bb-eeaef780b380 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3899350857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3899350857 |
| Directory | /workspace/4.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/4.uart_intr.554139043 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 17475952168 ps |
| CPU time | 37.41 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:49 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-f944cddc-56b1-46b1-8e11-d32f8e754785 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554139043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.554139043 |
| Directory | /workspace/4.uart_intr/latest |
| Test location | /workspace/coverage/default/4.uart_long_xfer_wo_dly.3955574193 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 35300305806 ps |
| CPU time | 179.8 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:58:11 PM PDT 24 |
| Peak memory | 199844 kb |
| Host | smart-a46371ea-8ee8-4bc9-adcd-cdca834044cd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3955574193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.3955574193 |
| Directory | /workspace/4.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/4.uart_loopback.2410508681 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 3947650901 ps |
| CPU time | 4.11 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:14 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-c8fd7f53-13b9-432a-a865-1261f04672b2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2410508681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.2410508681 |
| Directory | /workspace/4.uart_loopback/latest |
| Test location | /workspace/coverage/default/4.uart_noise_filter.3460210859 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 114218816285 ps |
| CPU time | 85.05 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:56:39 PM PDT 24 |
| Peak memory | 199032 kb |
| Host | smart-92d27f1e-caff-4168-98e7-1319154345f2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3460210859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3460210859 |
| Directory | /workspace/4.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/4.uart_perf.4088074750 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 3961799900 ps |
| CPU time | 43.17 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:54 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-47f315d1-4af0-4c7c-b5d0-02eda2e7634c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4088074750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.4088074750 |
| Directory | /workspace/4.uart_perf/latest |
| Test location | /workspace/coverage/default/4.uart_rx_oversample.1147830933 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 6511384723 ps |
| CPU time | 12.8 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:22 PM PDT 24 |
| Peak memory | 199056 kb |
| Host | smart-3cc10be7-02b7-40fe-881c-db9c7bb039c6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1147830933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1147830933 |
| Directory | /workspace/4.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/4.uart_rx_parity_err.2561512235 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 138120615969 ps |
| CPU time | 187.89 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:58:22 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-48a692c4-2e15-434d-becf-b52710686075 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2561512235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.2561512235 |
| Directory | /workspace/4.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/4.uart_rx_start_bit_filter.2344619334 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 3469316335 ps |
| CPU time | 5.27 seconds |
| Started | Aug 01 04:55:15 PM PDT 24 |
| Finished | Aug 01 04:55:20 PM PDT 24 |
| Peak memory | 196444 kb |
| Host | smart-a1df14c8-e343-472a-85ae-d5300c2f2b6d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2344619334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2344619334 |
| Directory | /workspace/4.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/4.uart_sec_cm.1775826921 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 68786313 ps |
| CPU time | 0.83 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:12 PM PDT 24 |
| Peak memory | 218196 kb |
| Host | smart-857a6c9c-8e56-41d5-98cc-35c29aeef256 |
| User | root |
| Command | /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775826921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.1775826921 |
| Directory | /workspace/4.uart_sec_cm/latest |
| Test location | /workspace/coverage/default/4.uart_smoke.3410081647 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 513007296 ps |
| CPU time | 1.74 seconds |
| Started | Aug 01 04:55:16 PM PDT 24 |
| Finished | Aug 01 04:55:18 PM PDT 24 |
| Peak memory | 198256 kb |
| Host | smart-d8e20d4b-d55c-4e28-9b48-c8b5068c6e02 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3410081647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.3410081647 |
| Directory | /workspace/4.uart_smoke/latest |
| Test location | /workspace/coverage/default/4.uart_stress_all.3405915548 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 42651321013 ps |
| CPU time | 62.65 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:56:13 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-bdaae672-e08b-47cf-b74a-f4eafac2b321 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405915548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.3405915548 |
| Directory | /workspace/4.uart_stress_all/latest |
| Test location | /workspace/coverage/default/4.uart_tx_ovrd.3564631986 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 865501504 ps |
| CPU time | 1.75 seconds |
| Started | Aug 01 04:55:16 PM PDT 24 |
| Finished | Aug 01 04:55:18 PM PDT 24 |
| Peak memory | 197696 kb |
| Host | smart-55f7b494-dc51-43f6-a602-34d115fc47fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3564631986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3564631986 |
| Directory | /workspace/4.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/4.uart_tx_rx.1888586338 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 56282766594 ps |
| CPU time | 113.05 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:57:05 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-abe9f988-1aa4-4b52-aed0-5664bfc228d9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1888586338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1888586338 |
| Directory | /workspace/4.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/40.uart_alert_test.3923623782 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 175606362 ps |
| CPU time | 0.54 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 04:59:56 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-03282ca3-19c3-4b66-ae3b-9f926a2459ea |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923623782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3923623782 |
| Directory | /workspace/40.uart_alert_test/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_full.2598056550 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 40722948101 ps |
| CPU time | 18.21 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:00:12 PM PDT 24 |
| Peak memory | 199816 kb |
| Host | smart-b97cca08-fb3f-4694-94e8-843f856e6f86 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2598056550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.2598056550 |
| Directory | /workspace/40.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_overflow.2961129564 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 75415497956 ps |
| CPU time | 28.9 seconds |
| Started | Aug 01 04:59:56 PM PDT 24 |
| Finished | Aug 01 05:00:25 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-38f46f14-2c6f-4e86-95f1-381e753fa99f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2961129564 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2961129564 |
| Directory | /workspace/40.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/40.uart_fifo_reset.3516141500 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 176270390444 ps |
| CPU time | 13.87 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 05:00:07 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-b07630d0-8ac7-49e3-8966-8e4a4631631c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3516141500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.3516141500 |
| Directory | /workspace/40.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/40.uart_intr.1050871823 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 27158280372 ps |
| CPU time | 15.98 seconds |
| Started | Aug 01 04:59:51 PM PDT 24 |
| Finished | Aug 01 05:00:08 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-433a7b24-687f-4ddb-84fb-4106ce9ae623 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050871823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1050871823 |
| Directory | /workspace/40.uart_intr/latest |
| Test location | /workspace/coverage/default/40.uart_long_xfer_wo_dly.435620219 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 92666151242 ps |
| CPU time | 376.45 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 05:06:11 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-b1728ba6-78c3-4a0c-ad79-007235c9f4d7 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=435620219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.435620219 |
| Directory | /workspace/40.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/40.uart_loopback.4292827552 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 8564056013 ps |
| CPU time | 14.82 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 05:00:10 PM PDT 24 |
| Peak memory | 199112 kb |
| Host | smart-f1a152bc-1a89-4619-ba1a-0e0c1d9f2007 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4292827552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.4292827552 |
| Directory | /workspace/40.uart_loopback/latest |
| Test location | /workspace/coverage/default/40.uart_noise_filter.3979175758 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 24973589856 ps |
| CPU time | 35.64 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 05:00:31 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-2e91b2dd-4ef5-482c-ae84-94f3f340752e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3979175758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.3979175758 |
| Directory | /workspace/40.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/40.uart_perf.1531426879 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 12476371002 ps |
| CPU time | 630.48 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:10:24 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-b6e0c07e-8c97-4694-a51b-1e6a6feaefe3 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1531426879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.1531426879 |
| Directory | /workspace/40.uart_perf/latest |
| Test location | /workspace/coverage/default/40.uart_rx_oversample.2716387575 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 7764928846 ps |
| CPU time | 16.58 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:00:11 PM PDT 24 |
| Peak memory | 198808 kb |
| Host | smart-bec49c69-039e-4584-9206-492c61456856 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2716387575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.2716387575 |
| Directory | /workspace/40.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/40.uart_rx_parity_err.1873410684 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 107529021961 ps |
| CPU time | 37.7 seconds |
| Started | Aug 01 04:59:52 PM PDT 24 |
| Finished | Aug 01 05:00:30 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-36730021-641e-4df1-870e-90f4509670ca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873410684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.1873410684 |
| Directory | /workspace/40.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/40.uart_rx_start_bit_filter.2631618227 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 1992372322 ps |
| CPU time | 3.83 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 04:59:57 PM PDT 24 |
| Peak memory | 195432 kb |
| Host | smart-52cb2dd9-94d4-414c-8b91-c3159210c8f7 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2631618227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2631618227 |
| Directory | /workspace/40.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/40.uart_smoke.340654602 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 275524318 ps |
| CPU time | 1.28 seconds |
| Started | Aug 01 04:59:41 PM PDT 24 |
| Finished | Aug 01 04:59:42 PM PDT 24 |
| Peak memory | 198716 kb |
| Host | smart-6db8d8ce-c2be-480f-a22b-164258424a28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340654602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.340654602 |
| Directory | /workspace/40.uart_smoke/latest |
| Test location | /workspace/coverage/default/40.uart_stress_all_with_rand_reset.539843033 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 25852855724 ps |
| CPU time | 310.79 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:05:05 PM PDT 24 |
| Peak memory | 216352 kb |
| Host | smart-d023467f-3464-41de-9ab3-610c2dfe4a8f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539843033 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.539843033 |
| Directory | /workspace/40.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/40.uart_tx_ovrd.1931646532 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 860593005 ps |
| CPU time | 2.77 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 04:59:56 PM PDT 24 |
| Peak memory | 198912 kb |
| Host | smart-ba80cf7d-6163-4038-b0bf-e17fc6cfdab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1931646532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.1931646532 |
| Directory | /workspace/40.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/40.uart_tx_rx.857093406 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 48521307630 ps |
| CPU time | 53.65 seconds |
| Started | Aug 01 04:59:42 PM PDT 24 |
| Finished | Aug 01 05:00:36 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-ef0271e3-c5be-425f-8cef-fea6d425263c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=857093406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.857093406 |
| Directory | /workspace/40.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/41.uart_alert_test.1947770752 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 12337702 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 05:00:05 PM PDT 24 |
| Finished | Aug 01 05:00:08 PM PDT 24 |
| Peak memory | 195192 kb |
| Host | smart-e0a2470b-404c-4b72-9501-444b8b0ed64f |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947770752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.1947770752 |
| Directory | /workspace/41.uart_alert_test/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_full.3091270612 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 89163364163 ps |
| CPU time | 126.13 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:02:00 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-60d500fb-995a-4e66-8dba-9ab73a158e8d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3091270612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3091270612 |
| Directory | /workspace/41.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_overflow.3442523513 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 15364760183 ps |
| CPU time | 29.6 seconds |
| Started | Aug 01 04:59:54 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-cccde4e4-2958-4484-a4da-36af1834aaaa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3442523513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3442523513 |
| Directory | /workspace/41.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/41.uart_fifo_reset.3056326006 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 22858478616 ps |
| CPU time | 36.86 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 05:00:30 PM PDT 24 |
| Peak memory | 199604 kb |
| Host | smart-0008a3e6-1bcd-4cb2-924e-3d65b8d5a625 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3056326006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3056326006 |
| Directory | /workspace/41.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/41.uart_intr.2385637030 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 29010684357 ps |
| CPU time | 64.09 seconds |
| Started | Aug 01 04:59:56 PM PDT 24 |
| Finished | Aug 01 05:01:00 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-06ed19f5-7862-4600-9978-fae3e9b15f61 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385637030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2385637030 |
| Directory | /workspace/41.uart_intr/latest |
| Test location | /workspace/coverage/default/41.uart_long_xfer_wo_dly.4120152955 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 92625882334 ps |
| CPU time | 429.03 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:07:16 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-8c914e78-5d88-4503-a38c-be47e2f86682 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4120152955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4120152955 |
| Directory | /workspace/41.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/41.uart_loopback.3222038663 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 6290941715 ps |
| CPU time | 7.49 seconds |
| Started | Aug 01 05:00:04 PM PDT 24 |
| Finished | Aug 01 05:00:15 PM PDT 24 |
| Peak memory | 199684 kb |
| Host | smart-de77414d-0e7b-4e86-9f9c-28e6a2d33d75 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3222038663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3222038663 |
| Directory | /workspace/41.uart_loopback/latest |
| Test location | /workspace/coverage/default/41.uart_noise_filter.139486777 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 79906615205 ps |
| CPU time | 28.43 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 05:00:21 PM PDT 24 |
| Peak memory | 208156 kb |
| Host | smart-11400df6-e54c-4129-a3cc-b5c672f4030f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=139486777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.139486777 |
| Directory | /workspace/41.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/41.uart_perf.1313055225 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 8308352867 ps |
| CPU time | 209.88 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:03:37 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-bb7631fa-cdfa-48c5-be83-30e75ba42409 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1313055225 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.1313055225 |
| Directory | /workspace/41.uart_perf/latest |
| Test location | /workspace/coverage/default/41.uart_rx_oversample.2107805134 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 1500355456 ps |
| CPU time | 1.95 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 04:59:57 PM PDT 24 |
| Peak memory | 197820 kb |
| Host | smart-f68f0c72-fcef-4349-aeef-cb0eeefd10e0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2107805134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.2107805134 |
| Directory | /workspace/41.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/41.uart_rx_parity_err.1667998374 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 47136316381 ps |
| CPU time | 40.16 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 05:00:36 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-3c47820f-da59-4147-9db6-e232ecccad73 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1667998374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.1667998374 |
| Directory | /workspace/41.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/41.uart_rx_start_bit_filter.3843878070 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 743123784 ps |
| CPU time | 1.69 seconds |
| Started | Aug 01 04:59:55 PM PDT 24 |
| Finished | Aug 01 04:59:57 PM PDT 24 |
| Peak memory | 195492 kb |
| Host | smart-cd2b22cc-5f38-4bf6-9724-e39b7926efcb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3843878070 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3843878070 |
| Directory | /workspace/41.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/41.uart_smoke.968725641 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 844650256 ps |
| CPU time | 3.51 seconds |
| Started | Aug 01 04:59:53 PM PDT 24 |
| Finished | Aug 01 04:59:57 PM PDT 24 |
| Peak memory | 198088 kb |
| Host | smart-47e82a48-d5bc-44ef-9909-b221c8ea9381 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=968725641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.968725641 |
| Directory | /workspace/41.uart_smoke/latest |
| Test location | /workspace/coverage/default/41.uart_stress_all_with_rand_reset.790721683 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 136340941270 ps |
| CPU time | 751.58 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:12:39 PM PDT 24 |
| Peak memory | 224692 kb |
| Host | smart-6b86a519-f20c-45aa-8bdd-b99d26e10891 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790721683 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.790721683 |
| Directory | /workspace/41.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/41.uart_tx_ovrd.2551085950 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 743303400 ps |
| CPU time | 4.49 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:12 PM PDT 24 |
| Peak memory | 198212 kb |
| Host | smart-6217ff78-fc94-48c8-8090-bcffda563180 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2551085950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2551085950 |
| Directory | /workspace/41.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/41.uart_tx_rx.997283644 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 89770375798 ps |
| CPU time | 81.8 seconds |
| Started | Aug 01 04:59:58 PM PDT 24 |
| Finished | Aug 01 05:01:20 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-b28e15df-6bdb-4473-9585-953bbd7bd1cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=997283644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.997283644 |
| Directory | /workspace/41.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/42.uart_alert_test.3299395516 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 33347387 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 05:00:04 PM PDT 24 |
| Finished | Aug 01 05:00:08 PM PDT 24 |
| Peak memory | 194428 kb |
| Host | smart-b47ce178-a3f8-4fcb-9e86-56e07cf253cc |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299395516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3299395516 |
| Directory | /workspace/42.uart_alert_test/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_overflow.729640484 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 35080594680 ps |
| CPU time | 14.16 seconds |
| Started | Aug 01 05:00:05 PM PDT 24 |
| Finished | Aug 01 05:00:21 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-74684988-12e7-4adc-8fcc-ff6b4618dfed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=729640484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.729640484 |
| Directory | /workspace/42.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/42.uart_fifo_reset.1684457322 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 235639514993 ps |
| CPU time | 47.04 seconds |
| Started | Aug 01 05:00:07 PM PDT 24 |
| Finished | Aug 01 05:00:55 PM PDT 24 |
| Peak memory | 199884 kb |
| Host | smart-ab2687e6-1304-4493-a1e3-985e28be48e1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1684457322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.1684457322 |
| Directory | /workspace/42.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/42.uart_intr.3442946425 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 5655043659 ps |
| CPU time | 8.71 seconds |
| Started | Aug 01 05:00:08 PM PDT 24 |
| Finished | Aug 01 05:00:17 PM PDT 24 |
| Peak memory | 196584 kb |
| Host | smart-fc8ebf6c-2bf4-47a2-b1c7-fda277c0de33 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442946425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.3442946425 |
| Directory | /workspace/42.uart_intr/latest |
| Test location | /workspace/coverage/default/42.uart_long_xfer_wo_dly.2982705433 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 64557107723 ps |
| CPU time | 337.67 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:05:45 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-3cecbf8e-baaa-4428-bbbe-3c7ed39135a0 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2982705433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2982705433 |
| Directory | /workspace/42.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/42.uart_loopback.446232597 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 5920618190 ps |
| CPU time | 5.09 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:12 PM PDT 24 |
| Peak memory | 198988 kb |
| Host | smart-ddf6af4f-9d79-4a85-925e-ccb0a34b018d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=446232597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.446232597 |
| Directory | /workspace/42.uart_loopback/latest |
| Test location | /workspace/coverage/default/42.uart_noise_filter.3413125894 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 49190858012 ps |
| CPU time | 37.38 seconds |
| Started | Aug 01 05:00:05 PM PDT 24 |
| Finished | Aug 01 05:00:44 PM PDT 24 |
| Peak memory | 199048 kb |
| Host | smart-ac393e40-e2ca-40d8-8d3b-4a84d45b5c13 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3413125894 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3413125894 |
| Directory | /workspace/42.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/42.uart_perf.1929992973 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 26157426931 ps |
| CPU time | 815.54 seconds |
| Started | Aug 01 05:00:07 PM PDT 24 |
| Finished | Aug 01 05:13:43 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-4c051201-9057-4dba-8f8f-7e3720635bd9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1929992973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1929992973 |
| Directory | /workspace/42.uart_perf/latest |
| Test location | /workspace/coverage/default/42.uart_rx_oversample.90838261 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 7062249978 ps |
| CPU time | 16.39 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 197892 kb |
| Host | smart-9728fb23-080a-4bf6-8532-6bb81b4d64bf |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=90838261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.90838261 |
| Directory | /workspace/42.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/42.uart_rx_parity_err.37161081 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 171797607370 ps |
| CPU time | 81.86 seconds |
| Started | Aug 01 05:00:08 PM PDT 24 |
| Finished | Aug 01 05:01:30 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-2f85f3d5-72d8-4cc6-9ac0-c45a57d10fd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=37161081 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.37161081 |
| Directory | /workspace/42.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/42.uart_rx_start_bit_filter.3861682781 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 6585058346 ps |
| CPU time | 5.87 seconds |
| Started | Aug 01 05:00:04 PM PDT 24 |
| Finished | Aug 01 05:00:13 PM PDT 24 |
| Peak memory | 196104 kb |
| Host | smart-c7898c5a-e27b-4eeb-a2eb-ca884242713f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3861682781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.3861682781 |
| Directory | /workspace/42.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/42.uart_smoke.1361736119 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 6171355980 ps |
| CPU time | 24.56 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:32 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-1fb9e2e8-8b9a-4c53-9105-2768bc55caac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1361736119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1361736119 |
| Directory | /workspace/42.uart_smoke/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all.2807639369 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 46051472680 ps |
| CPU time | 31.83 seconds |
| Started | Aug 01 05:00:08 PM PDT 24 |
| Finished | Aug 01 05:00:40 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-a82fad00-7df5-4faa-9800-605cd697468e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807639369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.2807639369 |
| Directory | /workspace/42.uart_stress_all/latest |
| Test location | /workspace/coverage/default/42.uart_stress_all_with_rand_reset.1945822450 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 33186767645 ps |
| CPU time | 531.72 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:08:59 PM PDT 24 |
| Peak memory | 216528 kb |
| Host | smart-7aac3a11-baa4-4be3-98be-591d2d75423c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945822450 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.1945822450 |
| Directory | /workspace/42.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/42.uart_tx_ovrd.3427604266 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1656279065 ps |
| CPU time | 2.7 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:10 PM PDT 24 |
| Peak memory | 198548 kb |
| Host | smart-75141f02-2c5e-4d6e-bf67-defbdd2eaab9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3427604266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.3427604266 |
| Directory | /workspace/42.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/42.uart_tx_rx.1415717975 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 23997248116 ps |
| CPU time | 19.13 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:26 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-5bd1252b-4195-47c5-9365-970fe53632ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1415717975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.1415717975 |
| Directory | /workspace/42.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/43.uart_alert_test.3551705777 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 14036301 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 195272 kb |
| Host | smart-e3115b90-4e4d-4b62-ab10-dec02da897c6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551705777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.3551705777 |
| Directory | /workspace/43.uart_alert_test/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_full.1283685343 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 77282186007 ps |
| CPU time | 126.89 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:02:14 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-990cd8de-8499-4c61-aa73-27eee212ac2e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1283685343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1283685343 |
| Directory | /workspace/43.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/43.uart_fifo_overflow.543340380 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 87835914331 ps |
| CPU time | 163.65 seconds |
| Started | Aug 01 05:00:07 PM PDT 24 |
| Finished | Aug 01 05:02:51 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-648827c9-befb-4546-ac88-778f50510c51 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=543340380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.543340380 |
| Directory | /workspace/43.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/43.uart_intr.2396580333 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 386229211628 ps |
| CPU time | 162.14 seconds |
| Started | Aug 01 05:00:05 PM PDT 24 |
| Finished | Aug 01 05:02:49 PM PDT 24 |
| Peak memory | 198800 kb |
| Host | smart-fbac5595-b91e-4659-aab4-f910261f6678 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396580333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.2396580333 |
| Directory | /workspace/43.uart_intr/latest |
| Test location | /workspace/coverage/default/43.uart_long_xfer_wo_dly.3121594460 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 111909900676 ps |
| CPU time | 582.19 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:10:06 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-ac2f3b34-d0f9-4eec-942d-886b8e7bb0e4 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3121594460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3121594460 |
| Directory | /workspace/43.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/43.uart_loopback.2625719626 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 5161835652 ps |
| CPU time | 13.5 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:00:36 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-b9c7fe38-7625-4a25-818e-0a775b79ca48 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2625719626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2625719626 |
| Directory | /workspace/43.uart_loopback/latest |
| Test location | /workspace/coverage/default/43.uart_noise_filter.2153098617 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 200636341923 ps |
| CPU time | 80.91 seconds |
| Started | Aug 01 05:00:07 PM PDT 24 |
| Finished | Aug 01 05:01:28 PM PDT 24 |
| Peak memory | 200044 kb |
| Host | smart-f3c21448-46c2-4785-87a8-1e965bb98b9c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153098617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.2153098617 |
| Directory | /workspace/43.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/43.uart_perf.2650619439 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 7551477590 ps |
| CPU time | 302.08 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:05:24 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-677780be-cce4-400a-a90c-4fe3800c6eca |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2650619439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.2650619439 |
| Directory | /workspace/43.uart_perf/latest |
| Test location | /workspace/coverage/default/43.uart_rx_oversample.898529777 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3489509529 ps |
| CPU time | 26.8 seconds |
| Started | Aug 01 05:00:06 PM PDT 24 |
| Finished | Aug 01 05:00:34 PM PDT 24 |
| Peak memory | 198028 kb |
| Host | smart-48ba8937-0185-4f08-b82e-f0fb49b98821 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=898529777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.898529777 |
| Directory | /workspace/43.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/43.uart_rx_parity_err.2883982762 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 33582171668 ps |
| CPU time | 45.15 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:01:07 PM PDT 24 |
| Peak memory | 199508 kb |
| Host | smart-df087714-c641-4d34-9584-d337d5fabd82 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2883982762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.2883982762 |
| Directory | /workspace/43.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/43.uart_rx_start_bit_filter.2380144974 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 757034897 ps |
| CPU time | 0.92 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:00:23 PM PDT 24 |
| Peak memory | 195408 kb |
| Host | smart-0e043cf2-cc1c-477d-a324-efe8927a3bbe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2380144974 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.2380144974 |
| Directory | /workspace/43.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/43.uart_smoke.2596564663 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 667107138 ps |
| CPU time | 2.78 seconds |
| Started | Aug 01 05:00:21 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 198452 kb |
| Host | smart-f42b34e6-7c10-42cf-932f-2c4b5ab48dec |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2596564663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.2596564663 |
| Directory | /workspace/43.uart_smoke/latest |
| Test location | /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3309926754 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 339487274696 ps |
| CPU time | 845.74 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:14:29 PM PDT 24 |
| Peak memory | 224692 kb |
| Host | smart-6f102f29-b436-4b1d-9ada-35cd5e4ff4a1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309926754 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3309926754 |
| Directory | /workspace/43.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/43.uart_tx_ovrd.1245035052 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 540649031 ps |
| CPU time | 2.04 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-5861deaf-9c58-45d6-8c3c-4fa216e234c2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1245035052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.1245035052 |
| Directory | /workspace/43.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/43.uart_tx_rx.3748897751 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 71622755652 ps |
| CPU time | 53.48 seconds |
| Started | Aug 01 05:00:07 PM PDT 24 |
| Finished | Aug 01 05:01:01 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-699772f4-f99b-4b17-8e88-187c0d75e2f5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3748897751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.3748897751 |
| Directory | /workspace/43.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/44.uart_alert_test.3289402918 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 18856434 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 05:00:33 PM PDT 24 |
| Finished | Aug 01 05:00:34 PM PDT 24 |
| Peak memory | 195460 kb |
| Host | smart-2d02dcd9-7ae0-4ce4-be64-d7fe27e7f647 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289402918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.3289402918 |
| Directory | /workspace/44.uart_alert_test/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_full.1186883679 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 94000449590 ps |
| CPU time | 80.78 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:01:44 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-d4be58fe-a774-494c-8ded-53c779c848ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1186883679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1186883679 |
| Directory | /workspace/44.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_overflow.260570900 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 35114655946 ps |
| CPU time | 20 seconds |
| Started | Aug 01 05:00:21 PM PDT 24 |
| Finished | Aug 01 05:00:41 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-796ca181-971f-45f2-96f8-c6bc25f3ab9a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=260570900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.260570900 |
| Directory | /workspace/44.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/44.uart_fifo_reset.2153335714 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 103144091633 ps |
| CPU time | 85.93 seconds |
| Started | Aug 01 05:00:21 PM PDT 24 |
| Finished | Aug 01 05:01:47 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-8d5ef81d-70ce-4bca-b1fc-25c93129676d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2153335714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.2153335714 |
| Directory | /workspace/44.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/44.uart_intr.2923748045 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 535589461 ps |
| CPU time | 1.38 seconds |
| Started | Aug 01 05:00:23 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 195448 kb |
| Host | smart-fafe35dc-f6bd-4c17-9d7b-d12c118091d5 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923748045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2923748045 |
| Directory | /workspace/44.uart_intr/latest |
| Test location | /workspace/coverage/default/44.uart_long_xfer_wo_dly.1388283713 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 72330755443 ps |
| CPU time | 507.8 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:09:03 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-52d1e42f-f0a8-4a7d-9be0-f3304bc066a8 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1388283713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.1388283713 |
| Directory | /workspace/44.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/44.uart_loopback.1828996313 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 6062853259 ps |
| CPU time | 6.78 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:00:41 PM PDT 24 |
| Peak memory | 198716 kb |
| Host | smart-80dfa756-abd4-4fcc-ad04-18d29823ab63 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1828996313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1828996313 |
| Directory | /workspace/44.uart_loopback/latest |
| Test location | /workspace/coverage/default/44.uart_noise_filter.3371693024 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 57206213652 ps |
| CPU time | 88.17 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:01:50 PM PDT 24 |
| Peak memory | 208208 kb |
| Host | smart-6c8abc07-e22e-4e13-bfbf-bf7a78a029a8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3371693024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.3371693024 |
| Directory | /workspace/44.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/44.uart_perf.3138409198 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 19943466881 ps |
| CPU time | 212.57 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:04:07 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-ed191d94-7592-45b5-927a-8eba6e9b6a03 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3138409198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.3138409198 |
| Directory | /workspace/44.uart_perf/latest |
| Test location | /workspace/coverage/default/44.uart_rx_oversample.532788008 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 3389758094 ps |
| CPU time | 1.67 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:00:24 PM PDT 24 |
| Peak memory | 198020 kb |
| Host | smart-266835dd-2dba-4f6b-b181-148f46313394 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=532788008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.532788008 |
| Directory | /workspace/44.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/44.uart_rx_parity_err.1699530391 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 47937013946 ps |
| CPU time | 78.46 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:01:53 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-7e19dd60-920e-47ff-8d60-0fc3c7e2123b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1699530391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1699530391 |
| Directory | /workspace/44.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/44.uart_rx_start_bit_filter.2076660215 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 34370148787 ps |
| CPU time | 12.75 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:00:48 PM PDT 24 |
| Peak memory | 196088 kb |
| Host | smart-c6f4e12d-09a6-4a41-ba0a-97aa41cd2dc3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2076660215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2076660215 |
| Directory | /workspace/44.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/44.uart_smoke.515422851 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 5354994333 ps |
| CPU time | 18.58 seconds |
| Started | Aug 01 05:00:22 PM PDT 24 |
| Finished | Aug 01 05:00:41 PM PDT 24 |
| Peak memory | 199080 kb |
| Host | smart-fffcfb50-2a35-47d8-b590-6703ecb153fa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=515422851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.515422851 |
| Directory | /workspace/44.uart_smoke/latest |
| Test location | /workspace/coverage/default/44.uart_stress_all_with_rand_reset.1561705612 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 44844904496 ps |
| CPU time | 517.66 seconds |
| Started | Aug 01 05:00:33 PM PDT 24 |
| Finished | Aug 01 05:09:11 PM PDT 24 |
| Peak memory | 216456 kb |
| Host | smart-97fdc037-9ac2-40d0-be87-d297c16944e0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561705612 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.1561705612 |
| Directory | /workspace/44.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/44.uart_tx_ovrd.1779044219 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 6600550003 ps |
| CPU time | 13.48 seconds |
| Started | Aug 01 05:00:33 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 199064 kb |
| Host | smart-6c39643d-2209-49c3-895b-e48d64e7604e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779044219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1779044219 |
| Directory | /workspace/44.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/44.uart_tx_rx.1814424382 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 42618974109 ps |
| CPU time | 67.29 seconds |
| Started | Aug 01 05:00:21 PM PDT 24 |
| Finished | Aug 01 05:01:29 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-34658007-9783-410f-a144-c4da3f2b9799 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814424382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.1814424382 |
| Directory | /workspace/44.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/45.uart_alert_test.1120185979 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 48355058 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 05:00:33 PM PDT 24 |
| Finished | Aug 01 05:00:33 PM PDT 24 |
| Peak memory | 195260 kb |
| Host | smart-d9912613-1df0-430c-8b6c-505aa605456d |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120185979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.1120185979 |
| Directory | /workspace/45.uart_alert_test/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_full.1413544485 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 78698945979 ps |
| CPU time | 36.12 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:01:12 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-04ddea4c-e6b8-4536-9b91-db1bcb389d71 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1413544485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.1413544485 |
| Directory | /workspace/45.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_overflow.459332100 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 78910566668 ps |
| CPU time | 86.84 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:02:01 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-8b0d94b3-087f-4ab1-9812-a3506f2570d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=459332100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.459332100 |
| Directory | /workspace/45.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/45.uart_fifo_reset.1814233351 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 68058808465 ps |
| CPU time | 24.27 seconds |
| Started | Aug 01 05:00:44 PM PDT 24 |
| Finished | Aug 01 05:01:09 PM PDT 24 |
| Peak memory | 199392 kb |
| Host | smart-db0f780b-fb46-4968-b5f9-bee52ae2b234 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1814233351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1814233351 |
| Directory | /workspace/45.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/45.uart_intr.1898174766 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 167280522015 ps |
| CPU time | 124.35 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:02:38 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-2a4ac80f-756c-4901-a6bb-e2c5df3eda98 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898174766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.1898174766 |
| Directory | /workspace/45.uart_intr/latest |
| Test location | /workspace/coverage/default/45.uart_long_xfer_wo_dly.600146255 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 302928797849 ps |
| CPU time | 202.31 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:03:56 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-003398c4-9bdd-4286-a3f7-c638b1d36a6a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=600146255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.600146255 |
| Directory | /workspace/45.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/45.uart_loopback.3062070544 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 1070694013 ps |
| CPU time | 1.68 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:00:36 PM PDT 24 |
| Peak memory | 197424 kb |
| Host | smart-43382b59-d066-4b65-800c-140a87ae220a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3062070544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.3062070544 |
| Directory | /workspace/45.uart_loopback/latest |
| Test location | /workspace/coverage/default/45.uart_noise_filter.4123408598 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 111174420259 ps |
| CPU time | 67.64 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:01:41 PM PDT 24 |
| Peak memory | 207736 kb |
| Host | smart-0e7cfd52-f4bb-495f-8bd3-6b5c1716583b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4123408598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.4123408598 |
| Directory | /workspace/45.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/45.uart_perf.2559085928 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 22965693639 ps |
| CPU time | 1241.59 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:21:17 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-938a6947-c3de-46e9-986b-dcb6fe9389f9 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2559085928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.2559085928 |
| Directory | /workspace/45.uart_perf/latest |
| Test location | /workspace/coverage/default/45.uart_rx_oversample.2203079884 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 1801847777 ps |
| CPU time | 6.66 seconds |
| Started | Aug 01 05:00:33 PM PDT 24 |
| Finished | Aug 01 05:00:40 PM PDT 24 |
| Peak memory | 198512 kb |
| Host | smart-2b33fee8-b615-403c-90e4-842b678b9123 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2203079884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2203079884 |
| Directory | /workspace/45.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/45.uart_rx_parity_err.2855193637 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 31319467387 ps |
| CPU time | 53.9 seconds |
| Started | Aug 01 05:00:38 PM PDT 24 |
| Finished | Aug 01 05:01:32 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-3934c2a4-bd70-41cd-95d3-8e06e76111ea |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2855193637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.2855193637 |
| Directory | /workspace/45.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/45.uart_rx_start_bit_filter.778764591 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 41636648710 ps |
| CPU time | 56.13 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:01:31 PM PDT 24 |
| Peak memory | 195860 kb |
| Host | smart-b9864d08-d7e0-470d-b7ca-39446913b041 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=778764591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.778764591 |
| Directory | /workspace/45.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/45.uart_smoke.591330981 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 5985757406 ps |
| CPU time | 24.18 seconds |
| Started | Aug 01 05:00:36 PM PDT 24 |
| Finished | Aug 01 05:01:00 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-d47977b2-2d2c-4db0-a28e-7517267e582f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=591330981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.591330981 |
| Directory | /workspace/45.uart_smoke/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all.819368291 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 493093528763 ps |
| CPU time | 341.81 seconds |
| Started | Aug 01 05:00:35 PM PDT 24 |
| Finished | Aug 01 05:06:17 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-6886f368-3865-46d5-8772-9ac2a68335b8 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819368291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.819368291 |
| Directory | /workspace/45.uart_stress_all/latest |
| Test location | /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2601012332 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 263512071922 ps |
| CPU time | 397.81 seconds |
| Started | Aug 01 05:00:31 PM PDT 24 |
| Finished | Aug 01 05:07:09 PM PDT 24 |
| Peak memory | 224612 kb |
| Host | smart-e4173a8e-3be3-4e08-b8de-31aebcf59b7a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601012332 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2601012332 |
| Directory | /workspace/45.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/45.uart_tx_ovrd.2369460466 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 574757894 ps |
| CPU time | 1.68 seconds |
| Started | Aug 01 05:00:34 PM PDT 24 |
| Finished | Aug 01 05:00:35 PM PDT 24 |
| Peak memory | 196900 kb |
| Host | smart-abea98ca-466f-4ddc-b92f-6a55c5254263 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2369460466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2369460466 |
| Directory | /workspace/45.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_alert_test.3201554481 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 11529688 ps |
| CPU time | 0.53 seconds |
| Started | Aug 01 05:00:47 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 194656 kb |
| Host | smart-21888551-a5d0-476a-a7ae-bf9a22e93870 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201554481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.3201554481 |
| Directory | /workspace/46.uart_alert_test/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_full.1021295234 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 64034905255 ps |
| CPU time | 105.13 seconds |
| Started | Aug 01 05:00:48 PM PDT 24 |
| Finished | Aug 01 05:02:33 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-3ab4b6ba-6ec3-460f-9931-cf07d861059c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1021295234 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.1021295234 |
| Directory | /workspace/46.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_overflow.1637402015 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 105477175903 ps |
| CPU time | 34.19 seconds |
| Started | Aug 01 05:00:45 PM PDT 24 |
| Finished | Aug 01 05:01:19 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-d1f8dcb8-fcd5-42e0-95bf-4618c78c0e0e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1637402015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1637402015 |
| Directory | /workspace/46.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/46.uart_fifo_reset.2874037384 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 44049132644 ps |
| CPU time | 71.31 seconds |
| Started | Aug 01 05:00:48 PM PDT 24 |
| Finished | Aug 01 05:01:59 PM PDT 24 |
| Peak memory | 199552 kb |
| Host | smart-b394ef95-f036-458f-b7c7-e148ae8fa7a3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2874037384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2874037384 |
| Directory | /workspace/46.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/46.uart_intr.2291106955 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 13509922947 ps |
| CPU time | 14.35 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:01:00 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-33d28d68-e23c-4326-8f7f-65eebfba982e |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291106955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.2291106955 |
| Directory | /workspace/46.uart_intr/latest |
| Test location | /workspace/coverage/default/46.uart_long_xfer_wo_dly.2684647314 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 112978073814 ps |
| CPU time | 754.38 seconds |
| Started | Aug 01 05:00:51 PM PDT 24 |
| Finished | Aug 01 05:13:26 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-eeb7cc52-965b-47b2-ae8b-a8c5a65f144b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2684647314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2684647314 |
| Directory | /workspace/46.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/46.uart_loopback.3191298277 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3960927437 ps |
| CPU time | 7.84 seconds |
| Started | Aug 01 05:00:49 PM PDT 24 |
| Finished | Aug 01 05:00:57 PM PDT 24 |
| Peak memory | 198384 kb |
| Host | smart-b53d211b-7972-434e-abfa-65519b11c293 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3191298277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.3191298277 |
| Directory | /workspace/46.uart_loopback/latest |
| Test location | /workspace/coverage/default/46.uart_noise_filter.3343008824 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 47017315516 ps |
| CPU time | 79.99 seconds |
| Started | Aug 01 05:00:49 PM PDT 24 |
| Finished | Aug 01 05:02:09 PM PDT 24 |
| Peak memory | 199900 kb |
| Host | smart-108e9190-65c9-4436-8907-59d40186c428 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3343008824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3343008824 |
| Directory | /workspace/46.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/46.uart_perf.537484175 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 4123182915 ps |
| CPU time | 205.8 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:04:12 PM PDT 24 |
| Peak memory | 199864 kb |
| Host | smart-3d1e6455-d885-4578-ba91-483068cca653 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=537484175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.537484175 |
| Directory | /workspace/46.uart_perf/latest |
| Test location | /workspace/coverage/default/46.uart_rx_oversample.3139726131 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 7811444014 ps |
| CPU time | 6.91 seconds |
| Started | Aug 01 05:00:45 PM PDT 24 |
| Finished | Aug 01 05:00:52 PM PDT 24 |
| Peak memory | 198124 kb |
| Host | smart-1db04971-e734-476a-a8f8-2ecb696a1804 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3139726131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3139726131 |
| Directory | /workspace/46.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/46.uart_rx_parity_err.4286643428 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 159456454868 ps |
| CPU time | 54.85 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:01:41 PM PDT 24 |
| Peak memory | 199732 kb |
| Host | smart-987bfcc8-9cf8-41b1-a30b-ba412f243cf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4286643428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.4286643428 |
| Directory | /workspace/46.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/46.uart_rx_start_bit_filter.2452459391 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 840629045 ps |
| CPU time | 1 seconds |
| Started | Aug 01 05:00:47 PM PDT 24 |
| Finished | Aug 01 05:00:48 PM PDT 24 |
| Peak memory | 195324 kb |
| Host | smart-f7906476-7411-4dec-adff-d81eed8ad306 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2452459391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.2452459391 |
| Directory | /workspace/46.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/46.uart_smoke.1726351150 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 632518004 ps |
| CPU time | 0.87 seconds |
| Started | Aug 01 05:00:51 PM PDT 24 |
| Finished | Aug 01 05:00:51 PM PDT 24 |
| Peak memory | 198516 kb |
| Host | smart-b780222b-16be-4439-ba4f-3a5ada14a864 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1726351150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.1726351150 |
| Directory | /workspace/46.uart_smoke/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all.2685657076 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 128681648057 ps |
| CPU time | 305.49 seconds |
| Started | Aug 01 05:00:50 PM PDT 24 |
| Finished | Aug 01 05:05:56 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-a689a91a-bd83-4c37-9d91-8ebc2642be99 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685657076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2685657076 |
| Directory | /workspace/46.uart_stress_all/latest |
| Test location | /workspace/coverage/default/46.uart_stress_all_with_rand_reset.4287309450 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 86771812816 ps |
| CPU time | 748.56 seconds |
| Started | Aug 01 05:00:44 PM PDT 24 |
| Finished | Aug 01 05:13:13 PM PDT 24 |
| Peak memory | 211568 kb |
| Host | smart-8aecd6fb-d4c5-49c7-bef9-9a8c77bb244b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287309450 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.4287309450 |
| Directory | /workspace/46.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/46.uart_tx_ovrd.3002428714 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1439953189 ps |
| CPU time | 2.57 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:00:48 PM PDT 24 |
| Peak memory | 198612 kb |
| Host | smart-2b260236-abc1-419f-866b-e5a29517598d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3002428714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.3002428714 |
| Directory | /workspace/46.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/46.uart_tx_rx.2301766976 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 11071440553 ps |
| CPU time | 19.4 seconds |
| Started | Aug 01 05:00:44 PM PDT 24 |
| Finished | Aug 01 05:01:04 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-02c7a6f0-27d1-48cc-bcae-13845f6f8570 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2301766976 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.2301766976 |
| Directory | /workspace/46.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/47.uart_alert_test.2104848565 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 18208708 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:01:09 PM PDT 24 |
| Peak memory | 194664 kb |
| Host | smart-77081714-1676-4058-8f7b-a3dad4966ce6 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104848565 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.2104848565 |
| Directory | /workspace/47.uart_alert_test/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_full.2508948429 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 37703675960 ps |
| CPU time | 27.54 seconds |
| Started | Aug 01 05:00:44 PM PDT 24 |
| Finished | Aug 01 05:01:11 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-3547ab73-ec74-4bcd-9a3e-afd923977fa9 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2508948429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.2508948429 |
| Directory | /workspace/47.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_overflow.3803705607 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 74509278699 ps |
| CPU time | 55.95 seconds |
| Started | Aug 01 05:00:45 PM PDT 24 |
| Finished | Aug 01 05:01:41 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-99527072-8201-468a-8b05-199c77da80fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3803705607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3803705607 |
| Directory | /workspace/47.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/47.uart_fifo_reset.3517352276 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 232730360841 ps |
| CPU time | 336.38 seconds |
| Started | Aug 01 05:00:47 PM PDT 24 |
| Finished | Aug 01 05:06:24 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-5a48b3ba-7488-448d-960b-47defc29f16b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3517352276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3517352276 |
| Directory | /workspace/47.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/47.uart_intr.2896675257 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 75662387366 ps |
| CPU time | 42.11 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:01:28 PM PDT 24 |
| Peak memory | 199932 kb |
| Host | smart-1ebc2578-aa47-44cf-8fff-01dabc0be7c0 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896675257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.2896675257 |
| Directory | /workspace/47.uart_intr/latest |
| Test location | /workspace/coverage/default/47.uart_long_xfer_wo_dly.1801683358 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 110469440801 ps |
| CPU time | 523.95 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:09:41 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-36056deb-f1a1-4db6-8599-6c925610892c |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1801683358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.1801683358 |
| Directory | /workspace/47.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/47.uart_loopback.886425016 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 8511319504 ps |
| CPU time | 14.24 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:11 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-7bbe74f8-6c9c-4fd4-bbcd-ce428b118517 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=886425016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.886425016 |
| Directory | /workspace/47.uart_loopback/latest |
| Test location | /workspace/coverage/default/47.uart_noise_filter.491922771 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 8172305009 ps |
| CPU time | 14.63 seconds |
| Started | Aug 01 05:00:49 PM PDT 24 |
| Finished | Aug 01 05:01:04 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-c06475a4-a6bc-4a0d-8a08-c6641fc02418 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=491922771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.491922771 |
| Directory | /workspace/47.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/47.uart_perf.224816601 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3307087163 ps |
| CPU time | 83.66 seconds |
| Started | Aug 01 05:01:00 PM PDT 24 |
| Finished | Aug 01 05:02:23 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-b53cab53-1fc9-4566-855e-9dbcd54dd36d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=224816601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.224816601 |
| Directory | /workspace/47.uart_perf/latest |
| Test location | /workspace/coverage/default/47.uart_rx_oversample.1358471219 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4904421270 ps |
| CPU time | 12.84 seconds |
| Started | Aug 01 05:00:49 PM PDT 24 |
| Finished | Aug 01 05:01:02 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-58c15a5b-0b08-416d-b36c-4fe72fbff297 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1358471219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1358471219 |
| Directory | /workspace/47.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/47.uart_rx_parity_err.62136106 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 73982061599 ps |
| CPU time | 195.95 seconds |
| Started | Aug 01 05:00:50 PM PDT 24 |
| Finished | Aug 01 05:04:06 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-b138bbdb-6bfd-44a5-be3f-a38c88d1078c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=62136106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.62136106 |
| Directory | /workspace/47.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/47.uart_rx_start_bit_filter.2911080255 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 1912543546 ps |
| CPU time | 1.22 seconds |
| Started | Aug 01 05:00:49 PM PDT 24 |
| Finished | Aug 01 05:00:50 PM PDT 24 |
| Peak memory | 195256 kb |
| Host | smart-0ed5bba9-9a59-4b70-964b-0930661f6d28 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2911080255 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2911080255 |
| Directory | /workspace/47.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/47.uart_smoke.863864533 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 466220122 ps |
| CPU time | 1.33 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 198200 kb |
| Host | smart-90d29ca9-b233-4e1e-b666-300e1869b1f6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=863864533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.863864533 |
| Directory | /workspace/47.uart_smoke/latest |
| Test location | /workspace/coverage/default/47.uart_tx_ovrd.2670481523 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 466342859 ps |
| CPU time | 2.17 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:01:02 PM PDT 24 |
| Peak memory | 199584 kb |
| Host | smart-f8279bae-c1d8-4d31-8dc3-7ed6905c6010 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2670481523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2670481523 |
| Directory | /workspace/47.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/47.uart_tx_rx.996794094 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 154625954 ps |
| CPU time | 0.81 seconds |
| Started | Aug 01 05:00:46 PM PDT 24 |
| Finished | Aug 01 05:00:47 PM PDT 24 |
| Peak memory | 197588 kb |
| Host | smart-2e1e7bc4-1fe4-493d-b1a8-82b7426cbdd2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=996794094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.996794094 |
| Directory | /workspace/47.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/48.uart_alert_test.113335230 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 49268253 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:01:09 PM PDT 24 |
| Peak memory | 195452 kb |
| Host | smart-dc78161d-262a-414d-8b21-bf9238f89093 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113335230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.113335230 |
| Directory | /workspace/48.uart_alert_test/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_full.2602979710 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 39953276175 ps |
| CPU time | 55.76 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:53 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-aab9d50d-5b20-401a-873a-4fe03c14842c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2602979710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.2602979710 |
| Directory | /workspace/48.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_overflow.137346190 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 23411321324 ps |
| CPU time | 18.37 seconds |
| Started | Aug 01 05:00:58 PM PDT 24 |
| Finished | Aug 01 05:01:16 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-79596611-2817-4617-8019-6f5abeab83ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=137346190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.137346190 |
| Directory | /workspace/48.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/48.uart_fifo_reset.2624291850 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 9296075981 ps |
| CPU time | 26.49 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:24 PM PDT 24 |
| Peak memory | 199736 kb |
| Host | smart-b3cf6b14-bd67-4280-9bde-fd469319a444 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2624291850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.2624291850 |
| Directory | /workspace/48.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/48.uart_intr.2418126677 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 46955949512 ps |
| CPU time | 36.42 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:33 PM PDT 24 |
| Peak memory | 199496 kb |
| Host | smart-a404ca49-d83f-4858-98b6-e8ef5d72f565 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418126677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.2418126677 |
| Directory | /workspace/48.uart_intr/latest |
| Test location | /workspace/coverage/default/48.uart_long_xfer_wo_dly.1870547154 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 59800861384 ps |
| CPU time | 98.99 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:02:47 PM PDT 24 |
| Peak memory | 199728 kb |
| Host | smart-1683b47e-86e8-4551-bc9c-38108fb47cbe |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1870547154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.1870547154 |
| Directory | /workspace/48.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/48.uart_loopback.176436856 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 4765091844 ps |
| CPU time | 4.24 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:01:03 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-0eac583e-b357-4596-ac2c-acbaec337454 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=176436856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.176436856 |
| Directory | /workspace/48.uart_loopback/latest |
| Test location | /workspace/coverage/default/48.uart_noise_filter.1006701295 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 21341735987 ps |
| CPU time | 10.85 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:08 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-81f59b94-2df8-4d54-abd0-aab524c986d4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1006701295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1006701295 |
| Directory | /workspace/48.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/48.uart_perf.2877741617 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 27266227235 ps |
| CPU time | 697.01 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:12:36 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-ca13a8ee-bd6f-4a9e-9687-aec347fb2368 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2877741617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.2877741617 |
| Directory | /workspace/48.uart_perf/latest |
| Test location | /workspace/coverage/default/48.uart_rx_oversample.2124563681 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4540574198 ps |
| CPU time | 5.9 seconds |
| Started | Aug 01 05:01:00 PM PDT 24 |
| Finished | Aug 01 05:01:06 PM PDT 24 |
| Peak memory | 198080 kb |
| Host | smart-0c15254a-99d9-4a45-9cfb-c6edadc058b6 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2124563681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.2124563681 |
| Directory | /workspace/48.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/48.uart_rx_parity_err.2026013921 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 84534943222 ps |
| CPU time | 41.32 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:01:40 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-cbfd77c8-fea9-4344-9ff5-6c3eac59d7ee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2026013921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.2026013921 |
| Directory | /workspace/48.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/48.uart_rx_start_bit_filter.1954525213 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 4812643321 ps |
| CPU time | 2.5 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:00:59 PM PDT 24 |
| Peak memory | 196364 kb |
| Host | smart-6c87c2df-611d-41e2-ba2e-5f1a549e1390 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1954525213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1954525213 |
| Directory | /workspace/48.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/48.uart_smoke.1459842395 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 5915872203 ps |
| CPU time | 7.13 seconds |
| Started | Aug 01 05:00:57 PM PDT 24 |
| Finished | Aug 01 05:01:04 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-3ea4f6f8-aefd-4690-bbcf-d29fb35e6db5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1459842395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.1459842395 |
| Directory | /workspace/48.uart_smoke/latest |
| Test location | /workspace/coverage/default/48.uart_stress_all_with_rand_reset.3957530168 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 146723140647 ps |
| CPU time | 504.99 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:09:25 PM PDT 24 |
| Peak memory | 226388 kb |
| Host | smart-3d487950-d90f-4a97-a4bc-5c93043dde8b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957530168 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.3957530168 |
| Directory | /workspace/48.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/48.uart_tx_ovrd.690468350 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 6591917985 ps |
| CPU time | 15.89 seconds |
| Started | Aug 01 05:00:59 PM PDT 24 |
| Finished | Aug 01 05:01:15 PM PDT 24 |
| Peak memory | 199716 kb |
| Host | smart-f7a06067-2d3a-47b1-976a-8a3b87da7a55 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=690468350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.690468350 |
| Directory | /workspace/48.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/48.uart_tx_rx.2572280419 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 4417261772 ps |
| CPU time | 7.97 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:01:17 PM PDT 24 |
| Peak memory | 199524 kb |
| Host | smart-75f8e0bc-36a1-47fe-84b8-1eb1183e4350 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2572280419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.2572280419 |
| Directory | /workspace/48.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/49.uart_alert_test.1987808448 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 36164776 ps |
| CPU time | 0.53 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:01:10 PM PDT 24 |
| Peak memory | 194184 kb |
| Host | smart-1fe2e0ad-1f33-46de-a246-3e476abd6068 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987808448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.1987808448 |
| Directory | /workspace/49.uart_alert_test/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_full.2432018188 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 193946195164 ps |
| CPU time | 114.44 seconds |
| Started | Aug 01 05:01:13 PM PDT 24 |
| Finished | Aug 01 05:03:07 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-b58ae00c-e2b4-45e9-8653-4d63f5bf7822 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2432018188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.2432018188 |
| Directory | /workspace/49.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_overflow.4241304678 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 79239505852 ps |
| CPU time | 62.97 seconds |
| Started | Aug 01 05:01:13 PM PDT 24 |
| Finished | Aug 01 05:02:16 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-1cdc6210-8247-4b27-bd19-cb48db64b188 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4241304678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.4241304678 |
| Directory | /workspace/49.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/49.uart_fifo_reset.517138536 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 98913689297 ps |
| CPU time | 39.05 seconds |
| Started | Aug 01 05:01:07 PM PDT 24 |
| Finished | Aug 01 05:01:47 PM PDT 24 |
| Peak memory | 199752 kb |
| Host | smart-5cfd80d1-290f-4821-9d27-d0c6708470ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=517138536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.517138536 |
| Directory | /workspace/49.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/49.uart_intr.3966875969 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 25140087373 ps |
| CPU time | 22.08 seconds |
| Started | Aug 01 05:01:11 PM PDT 24 |
| Finished | Aug 01 05:01:33 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-1eb38227-3b7b-4956-a40e-2e0d6daa5c28 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966875969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3966875969 |
| Directory | /workspace/49.uart_intr/latest |
| Test location | /workspace/coverage/default/49.uart_long_xfer_wo_dly.767665710 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 64948434609 ps |
| CPU time | 207.48 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:04:37 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-d89a40b8-8950-43ce-af40-43f3e6c83d99 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=767665710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.767665710 |
| Directory | /workspace/49.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/49.uart_loopback.905706173 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 2275062986 ps |
| CPU time | 5.67 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:01:14 PM PDT 24 |
| Peak memory | 198524 kb |
| Host | smart-4b5cf992-1b84-40d2-b2a9-dd223870a3f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=905706173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.905706173 |
| Directory | /workspace/49.uart_loopback/latest |
| Test location | /workspace/coverage/default/49.uart_noise_filter.3717304361 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 202583708639 ps |
| CPU time | 64.08 seconds |
| Started | Aug 01 05:01:13 PM PDT 24 |
| Finished | Aug 01 05:02:17 PM PDT 24 |
| Peak memory | 199896 kb |
| Host | smart-cceb4de1-b34e-4e68-b34a-22c58ba66082 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3717304361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.3717304361 |
| Directory | /workspace/49.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/49.uart_perf.2202257751 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 23698014256 ps |
| CPU time | 388.72 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:07:37 PM PDT 24 |
| Peak memory | 199892 kb |
| Host | smart-f00209e3-b885-4a0b-97ce-b9f51bbbe241 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2202257751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.2202257751 |
| Directory | /workspace/49.uart_perf/latest |
| Test location | /workspace/coverage/default/49.uart_rx_oversample.2928651543 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 4322793081 ps |
| CPU time | 7.54 seconds |
| Started | Aug 01 05:01:07 PM PDT 24 |
| Finished | Aug 01 05:01:15 PM PDT 24 |
| Peak memory | 198812 kb |
| Host | smart-93cac3af-ca54-4e05-92de-310c485b6bff |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2928651543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.2928651543 |
| Directory | /workspace/49.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/49.uart_rx_parity_err.1593732285 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 169138626181 ps |
| CPU time | 206.66 seconds |
| Started | Aug 01 05:01:11 PM PDT 24 |
| Finished | Aug 01 05:04:38 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-0a0becf8-4351-47f9-a425-5ee7498c10ce |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1593732285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.1593732285 |
| Directory | /workspace/49.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/49.uart_rx_start_bit_filter.2218599057 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 1501447902 ps |
| CPU time | 2.65 seconds |
| Started | Aug 01 05:01:09 PM PDT 24 |
| Finished | Aug 01 05:01:12 PM PDT 24 |
| Peak memory | 195428 kb |
| Host | smart-c76f161a-4afe-43ff-8d01-833ec774d253 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2218599057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2218599057 |
| Directory | /workspace/49.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/49.uart_smoke.4034014155 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5791232659 ps |
| CPU time | 19.08 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:01:28 PM PDT 24 |
| Peak memory | 199704 kb |
| Host | smart-d2b252c0-4efd-42ff-8fb0-67b2a4bdeda2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4034014155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.4034014155 |
| Directory | /workspace/49.uart_smoke/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all.1835867506 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 226924287581 ps |
| CPU time | 336.93 seconds |
| Started | Aug 01 05:01:10 PM PDT 24 |
| Finished | Aug 01 05:06:47 PM PDT 24 |
| Peak memory | 199808 kb |
| Host | smart-2797aa27-f297-4318-9cf1-4a558a1ea988 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835867506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1835867506 |
| Directory | /workspace/49.uart_stress_all/latest |
| Test location | /workspace/coverage/default/49.uart_stress_all_with_rand_reset.2193995712 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 334358758728 ps |
| CPU time | 1355.8 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:23:44 PM PDT 24 |
| Peak memory | 215240 kb |
| Host | smart-8e65c5a0-398f-498f-a32e-8a1c0c810d6e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193995712 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.2193995712 |
| Directory | /workspace/49.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/49.uart_tx_ovrd.2956443129 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 6735614442 ps |
| CPU time | 27.78 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:01:36 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-766256c6-57c3-4b2d-a8e9-0c2fdbb080d1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2956443129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2956443129 |
| Directory | /workspace/49.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/49.uart_tx_rx.998688014 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 148936685119 ps |
| CPU time | 64.23 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:02:12 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-727109bf-07da-44ed-a6b1-ec0680c25097 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=998688014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.998688014 |
| Directory | /workspace/49.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/5.uart_alert_test.2132156752 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 13740055 ps |
| CPU time | 0.58 seconds |
| Started | Aug 01 04:55:20 PM PDT 24 |
| Finished | Aug 01 04:55:21 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-fb821495-e13b-4991-bb79-89735a271845 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132156752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2132156752 |
| Directory | /workspace/5.uart_alert_test/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_overflow.1402371026 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 104992238053 ps |
| CPU time | 158.6 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:57:51 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-37ca62e3-fd49-45f5-b584-3fb33462fe6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1402371026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1402371026 |
| Directory | /workspace/5.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/5.uart_fifo_reset.860205130 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 185408731298 ps |
| CPU time | 75.75 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:56:28 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-3a486222-6d04-4c9d-9417-69a65d3660d5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=860205130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.860205130 |
| Directory | /workspace/5.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/5.uart_intr.3502925992 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 36437151358 ps |
| CPU time | 19.37 seconds |
| Started | Aug 01 04:55:17 PM PDT 24 |
| Finished | Aug 01 04:55:36 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-bc8752b9-1a54-4124-97be-2fc71be1c21f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502925992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.3502925992 |
| Directory | /workspace/5.uart_intr/latest |
| Test location | /workspace/coverage/default/5.uart_long_xfer_wo_dly.2789042224 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 45242661649 ps |
| CPU time | 436.12 seconds |
| Started | Aug 01 04:55:20 PM PDT 24 |
| Finished | Aug 01 05:02:36 PM PDT 24 |
| Peak memory | 199000 kb |
| Host | smart-5b90b31c-5e94-41b3-90d4-8693a265a368 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2789042224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.2789042224 |
| Directory | /workspace/5.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/5.uart_loopback.2511073503 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 4366659817 ps |
| CPU time | 2.78 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:55:24 PM PDT 24 |
| Peak memory | 197932 kb |
| Host | smart-2d8defbb-6b83-4f32-bc8c-a0e64b695c03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2511073503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2511073503 |
| Directory | /workspace/5.uart_loopback/latest |
| Test location | /workspace/coverage/default/5.uart_noise_filter.3830182117 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 88924805489 ps |
| CPU time | 104.11 seconds |
| Started | Aug 01 04:55:14 PM PDT 24 |
| Finished | Aug 01 04:56:58 PM PDT 24 |
| Peak memory | 199912 kb |
| Host | smart-c91abdd5-a4e6-4e3a-aa08-cde7d0bd8387 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3830182117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.3830182117 |
| Directory | /workspace/5.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/5.uart_perf.2557770670 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 10234751887 ps |
| CPU time | 566.05 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 05:04:47 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-97617ad6-5fc4-4877-9f80-7beb40e24f20 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2557770670 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2557770670 |
| Directory | /workspace/5.uart_perf/latest |
| Test location | /workspace/coverage/default/5.uart_rx_oversample.2296735434 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 1592747329 ps |
| CPU time | 5.84 seconds |
| Started | Aug 01 04:55:10 PM PDT 24 |
| Finished | Aug 01 04:55:16 PM PDT 24 |
| Peak memory | 198248 kb |
| Host | smart-df35ee48-69e6-4118-9015-ba46b6fe5899 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2296735434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2296735434 |
| Directory | /workspace/5.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/5.uart_rx_parity_err.2689594770 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 27956249487 ps |
| CPU time | 21.19 seconds |
| Started | Aug 01 04:55:13 PM PDT 24 |
| Finished | Aug 01 04:55:34 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-6e2cabbe-3b9f-4600-832e-dfed861f5daa |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2689594770 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2689594770 |
| Directory | /workspace/5.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/5.uart_rx_start_bit_filter.1933775966 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3806482970 ps |
| CPU time | 5.66 seconds |
| Started | Aug 01 04:55:11 PM PDT 24 |
| Finished | Aug 01 04:55:17 PM PDT 24 |
| Peak memory | 196272 kb |
| Host | smart-f1beb9fb-fafa-4877-9d1c-4d4b2cf3e362 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1933775966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1933775966 |
| Directory | /workspace/5.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/5.uart_smoke.740052363 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 888832243 ps |
| CPU time | 5.38 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:18 PM PDT 24 |
| Peak memory | 199512 kb |
| Host | smart-fc6b9e0e-a842-451c-9fb9-f7e22576a30a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=740052363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.740052363 |
| Directory | /workspace/5.uart_smoke/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all.3277091410 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 439517180224 ps |
| CPU time | 206.61 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:58:51 PM PDT 24 |
| Peak memory | 208144 kb |
| Host | smart-8510b2b7-8031-45ea-a14d-f6041493745d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277091410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.3277091410 |
| Directory | /workspace/5.uart_stress_all/latest |
| Test location | /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1407325558 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 19797256617 ps |
| CPU time | 299.19 seconds |
| Started | Aug 01 04:55:20 PM PDT 24 |
| Finished | Aug 01 05:00:20 PM PDT 24 |
| Peak memory | 215700 kb |
| Host | smart-194e6d9a-40d4-4ad5-bff1-18a5436db2b7 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407325558 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1407325558 |
| Directory | /workspace/5.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/5.uart_tx_ovrd.1701341072 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 602264993 ps |
| CPU time | 1.68 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:14 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-8fb31182-42d3-4345-b730-e6a848185029 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1701341072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.1701341072 |
| Directory | /workspace/5.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/5.uart_tx_rx.1289220092 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 53207601002 ps |
| CPU time | 24.41 seconds |
| Started | Aug 01 04:55:12 PM PDT 24 |
| Finished | Aug 01 04:55:36 PM PDT 24 |
| Peak memory | 200140 kb |
| Host | smart-27fe7ea2-a94b-42ec-8eb7-0425a1d62e03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1289220092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.1289220092 |
| Directory | /workspace/5.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/50.uart_fifo_reset.1702251040 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 20507661732 ps |
| CPU time | 36.18 seconds |
| Started | Aug 01 05:01:12 PM PDT 24 |
| Finished | Aug 01 05:01:49 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-2fbdb1be-850f-4211-9620-4cb08dcbcfd1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1702251040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.1702251040 |
| Directory | /workspace/50.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/50.uart_stress_all_with_rand_reset.2257086821 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 162777310483 ps |
| CPU time | 509.9 seconds |
| Started | Aug 01 05:01:07 PM PDT 24 |
| Finished | Aug 01 05:09:37 PM PDT 24 |
| Peak memory | 216456 kb |
| Host | smart-642617fa-526d-4985-9047-47dff098902a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257086821 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.2257086821 |
| Directory | /workspace/50.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/51.uart_fifo_reset.1196389078 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 70305423195 ps |
| CPU time | 109.05 seconds |
| Started | Aug 01 05:01:11 PM PDT 24 |
| Finished | Aug 01 05:03:00 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-4db55ed8-58a5-4dd7-b8f5-538d2b8703bd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1196389078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.1196389078 |
| Directory | /workspace/51.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1852088922 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 34755374316 ps |
| CPU time | 343.43 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:06:52 PM PDT 24 |
| Peak memory | 216388 kb |
| Host | smart-038390a2-7ff5-40bc-9dc8-62cdd502d92f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852088922 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1852088922 |
| Directory | /workspace/51.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/52.uart_fifo_reset.3710302513 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 148872774611 ps |
| CPU time | 61.25 seconds |
| Started | Aug 01 05:01:07 PM PDT 24 |
| Finished | Aug 01 05:02:08 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-b42eb90f-4239-4023-afd3-6e34e296b40a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3710302513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.3710302513 |
| Directory | /workspace/52.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_fifo_reset.2053805708 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 191351949240 ps |
| CPU time | 70.62 seconds |
| Started | Aug 01 05:01:08 PM PDT 24 |
| Finished | Aug 01 05:02:19 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-7bb0cf8c-943d-4426-a579-1152ae57686b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2053805708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.2053805708 |
| Directory | /workspace/53.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/53.uart_stress_all_with_rand_reset.4042245800 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 76894459893 ps |
| CPU time | 540.21 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:10:19 PM PDT 24 |
| Peak memory | 216436 kb |
| Host | smart-01307d48-fd3e-400e-bb78-758545448fac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042245800 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.4042245800 |
| Directory | /workspace/53.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/54.uart_fifo_reset.2514489023 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 35441282720 ps |
| CPU time | 36.62 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:01:56 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-de8453ec-13f3-472e-9900-6eb787d99923 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2514489023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2514489023 |
| Directory | /workspace/54.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/54.uart_stress_all_with_rand_reset.1487595242 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 33943049770 ps |
| CPU time | 513.05 seconds |
| Started | Aug 01 05:01:20 PM PDT 24 |
| Finished | Aug 01 05:09:53 PM PDT 24 |
| Peak memory | 216428 kb |
| Host | smart-072195ee-7c52-4b27-b1aa-aa42a7235f52 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487595242 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.1487595242 |
| Directory | /workspace/54.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/55.uart_fifo_reset.511240855 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 59645066449 ps |
| CPU time | 131.45 seconds |
| Started | Aug 01 05:01:24 PM PDT 24 |
| Finished | Aug 01 05:03:36 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-84084673-f2ba-472b-b5a2-64c302c46ac1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=511240855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.511240855 |
| Directory | /workspace/55.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/55.uart_stress_all_with_rand_reset.3040834854 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 95476704659 ps |
| CPU time | 316.16 seconds |
| Started | Aug 01 05:01:18 PM PDT 24 |
| Finished | Aug 01 05:06:34 PM PDT 24 |
| Peak memory | 214800 kb |
| Host | smart-69a56e51-1e9b-4e62-9ad7-5a829c041438 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040834854 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.3040834854 |
| Directory | /workspace/55.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/56.uart_fifo_reset.3775763014 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 12725916266 ps |
| CPU time | 22.66 seconds |
| Started | Aug 01 05:01:21 PM PDT 24 |
| Finished | Aug 01 05:01:43 PM PDT 24 |
| Peak memory | 199640 kb |
| Host | smart-cf607689-ae85-4fa0-9be8-3a11f661beca |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3775763014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3775763014 |
| Directory | /workspace/56.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2295421567 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 136162802893 ps |
| CPU time | 1066.38 seconds |
| Started | Aug 01 05:01:18 PM PDT 24 |
| Finished | Aug 01 05:19:04 PM PDT 24 |
| Peak memory | 230508 kb |
| Host | smart-d985ddd4-a4b0-4267-8446-ea0b14f82dd6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295421567 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2295421567 |
| Directory | /workspace/56.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/57.uart_fifo_reset.2099538783 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 98606248619 ps |
| CPU time | 42.22 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:02:02 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-74750c4e-6270-4b41-a04b-1c2ce9f9b7bc |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2099538783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2099538783 |
| Directory | /workspace/57.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/57.uart_stress_all_with_rand_reset.955877987 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 215681959887 ps |
| CPU time | 307.46 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:06:27 PM PDT 24 |
| Peak memory | 216288 kb |
| Host | smart-b764c6b9-83b7-4825-a2bb-4e07a69437b1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955877987 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.955877987 |
| Directory | /workspace/57.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/58.uart_fifo_reset.3438623831 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 32698283295 ps |
| CPU time | 13.9 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:01:33 PM PDT 24 |
| Peak memory | 198592 kb |
| Host | smart-cb95907e-7cb6-43c6-8a74-32c2357fb563 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3438623831 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3438623831 |
| Directory | /workspace/58.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/58.uart_stress_all_with_rand_reset.1221306392 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 14758920670 ps |
| CPU time | 201.9 seconds |
| Started | Aug 01 05:01:21 PM PDT 24 |
| Finished | Aug 01 05:04:44 PM PDT 24 |
| Peak memory | 216264 kb |
| Host | smart-4dcd197a-36f4-4b48-96d0-03c7b990c9b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221306392 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.1221306392 |
| Directory | /workspace/58.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/59.uart_fifo_reset.495949339 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 51957513714 ps |
| CPU time | 16.97 seconds |
| Started | Aug 01 05:01:17 PM PDT 24 |
| Finished | Aug 01 05:01:34 PM PDT 24 |
| Peak memory | 199852 kb |
| Host | smart-9d58a0c6-b5f7-47fa-b739-a78a3ab21e10 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=495949339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.495949339 |
| Directory | /workspace/59.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/59.uart_stress_all_with_rand_reset.354838383 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 70065176205 ps |
| CPU time | 1561.5 seconds |
| Started | Aug 01 05:01:21 PM PDT 24 |
| Finished | Aug 01 05:27:23 PM PDT 24 |
| Peak memory | 225572 kb |
| Host | smart-c0670c47-41cf-4451-8c36-2b67982c8042 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354838383 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.354838383 |
| Directory | /workspace/59.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_alert_test.97842621 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 19456082 ps |
| CPU time | 0.6 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:55:22 PM PDT 24 |
| Peak memory | 195528 kb |
| Host | smart-f589755c-fb8b-4d0c-9029-c6bc6921de3c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97842621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.97842621 |
| Directory | /workspace/6.uart_alert_test/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_full.1081903191 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 23910739057 ps |
| CPU time | 32.69 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:55:54 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-9165a173-4b3b-4ee8-b27a-f33e54b95648 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1081903191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.1081903191 |
| Directory | /workspace/6.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/6.uart_fifo_reset.3663825280 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 54966220294 ps |
| CPU time | 47.03 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:56:11 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-a799cb55-d407-4b4f-94bd-ba7d48ee0f47 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3663825280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.3663825280 |
| Directory | /workspace/6.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/6.uart_intr.548088519 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 31143825183 ps |
| CPU time | 61.14 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:56:23 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-62fcebad-d123-4ddf-82d7-f5dbaebd9126 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548088519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.548088519 |
| Directory | /workspace/6.uart_intr/latest |
| Test location | /workspace/coverage/default/6.uart_long_xfer_wo_dly.2558503943 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 42916040025 ps |
| CPU time | 76.14 seconds |
| Started | Aug 01 04:55:23 PM PDT 24 |
| Finished | Aug 01 04:56:40 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-48dba1e9-be47-42c3-a320-af53d5f197e2 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2558503943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2558503943 |
| Directory | /workspace/6.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/6.uart_loopback.578372272 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1297296950 ps |
| CPU time | 2.1 seconds |
| Started | Aug 01 04:55:20 PM PDT 24 |
| Finished | Aug 01 04:55:22 PM PDT 24 |
| Peak memory | 197660 kb |
| Host | smart-2dca6220-b236-49c7-8788-252d9e2d2817 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=578372272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.578372272 |
| Directory | /workspace/6.uart_loopback/latest |
| Test location | /workspace/coverage/default/6.uart_noise_filter.1866571806 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 14775212384 ps |
| CPU time | 24.35 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:55:47 PM PDT 24 |
| Peak memory | 197448 kb |
| Host | smart-811881ce-f253-4be5-a02f-b07b309099a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1866571806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1866571806 |
| Directory | /workspace/6.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/6.uart_perf.3173976240 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 14742711302 ps |
| CPU time | 862.66 seconds |
| Started | Aug 01 04:55:23 PM PDT 24 |
| Finished | Aug 01 05:09:45 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-c4a1b91a-773b-41ee-b3d2-fb12ec2a51dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3173976240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.3173976240 |
| Directory | /workspace/6.uart_perf/latest |
| Test location | /workspace/coverage/default/6.uart_rx_oversample.1712214086 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2724591714 ps |
| CPU time | 4.13 seconds |
| Started | Aug 01 04:55:25 PM PDT 24 |
| Finished | Aug 01 04:55:29 PM PDT 24 |
| Peak memory | 197840 kb |
| Host | smart-b93a0bb3-7c9a-4725-b801-89e30ea52e77 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1712214086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.1712214086 |
| Directory | /workspace/6.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/6.uart_rx_parity_err.2822715773 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 22514074185 ps |
| CPU time | 15.76 seconds |
| Started | Aug 01 04:55:23 PM PDT 24 |
| Finished | Aug 01 04:55:39 PM PDT 24 |
| Peak memory | 198048 kb |
| Host | smart-a2e7947d-4dcd-477f-9aed-1e490c32c1f4 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2822715773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.2822715773 |
| Directory | /workspace/6.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/6.uart_rx_start_bit_filter.1779601314 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 34574111502 ps |
| CPU time | 3.17 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:55:27 PM PDT 24 |
| Peak memory | 196220 kb |
| Host | smart-dc54c020-b830-4070-b5ab-2381e979222a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1779601314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1779601314 |
| Directory | /workspace/6.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/6.uart_smoke.266751209 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 296457503 ps |
| CPU time | 0.98 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:55:22 PM PDT 24 |
| Peak memory | 198252 kb |
| Host | smart-50577802-2e15-4cbb-8723-5a591b198cd0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=266751209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.266751209 |
| Directory | /workspace/6.uart_smoke/latest |
| Test location | /workspace/coverage/default/6.uart_stress_all_with_rand_reset.1127411060 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 26044643516 ps |
| CPU time | 330.8 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 05:00:55 PM PDT 24 |
| Peak memory | 216564 kb |
| Host | smart-1b943da9-502a-4994-87e1-91fedcc8b34f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127411060 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.1127411060 |
| Directory | /workspace/6.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/6.uart_tx_ovrd.2962989825 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1065047980 ps |
| CPU time | 3.71 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:55:26 PM PDT 24 |
| Peak memory | 199588 kb |
| Host | smart-360f2da9-e569-4158-a568-17e5bfdf3146 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962989825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2962989825 |
| Directory | /workspace/6.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/6.uart_tx_rx.4002349868 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 105110407576 ps |
| CPU time | 131.22 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:57:32 PM PDT 24 |
| Peak memory | 199836 kb |
| Host | smart-467d04f6-d397-4e8d-b749-96803cca873e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4002349868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.4002349868 |
| Directory | /workspace/6.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/60.uart_fifo_reset.250446316 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 28803909004 ps |
| CPU time | 30.07 seconds |
| Started | Aug 01 05:01:17 PM PDT 24 |
| Finished | Aug 01 05:01:47 PM PDT 24 |
| Peak memory | 199688 kb |
| Host | smart-26194c35-3086-429b-b895-df9f85398bdd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=250446316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.250446316 |
| Directory | /workspace/60.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/60.uart_stress_all_with_rand_reset.1744561940 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 248089001814 ps |
| CPU time | 868.83 seconds |
| Started | Aug 01 05:01:20 PM PDT 24 |
| Finished | Aug 01 05:15:49 PM PDT 24 |
| Peak memory | 224644 kb |
| Host | smart-3d926525-1a3c-479a-9123-e1172c77e61f |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744561940 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.1744561940 |
| Directory | /workspace/60.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/62.uart_fifo_reset.281296967 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 36454254735 ps |
| CPU time | 56.46 seconds |
| Started | Aug 01 05:01:18 PM PDT 24 |
| Finished | Aug 01 05:02:15 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-5339b757-c57c-475b-b873-0f580dc296be |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=281296967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.281296967 |
| Directory | /workspace/62.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/62.uart_stress_all_with_rand_reset.3807595588 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 357515076802 ps |
| CPU time | 584.31 seconds |
| Started | Aug 01 05:01:20 PM PDT 24 |
| Finished | Aug 01 05:11:04 PM PDT 24 |
| Peak memory | 216356 kb |
| Host | smart-27f4b1f0-a711-40b9-a0ff-304509d69022 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807595588 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.3807595588 |
| Directory | /workspace/62.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/63.uart_fifo_reset.3157901164 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 34816772523 ps |
| CPU time | 61.96 seconds |
| Started | Aug 01 05:01:20 PM PDT 24 |
| Finished | Aug 01 05:02:22 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-55c18574-d2c8-4aaf-88e2-ef6dda33d077 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3157901164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3157901164 |
| Directory | /workspace/63.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1565726729 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 75534514603 ps |
| CPU time | 522.56 seconds |
| Started | Aug 01 05:01:19 PM PDT 24 |
| Finished | Aug 01 05:10:01 PM PDT 24 |
| Peak memory | 210500 kb |
| Host | smart-fe2d4133-0907-4c41-8e2e-7fb41f95e7b0 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565726729 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1565726729 |
| Directory | /workspace/63.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/64.uart_fifo_reset.952512332 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 73665162028 ps |
| CPU time | 58.96 seconds |
| Started | Aug 01 05:01:37 PM PDT 24 |
| Finished | Aug 01 05:02:37 PM PDT 24 |
| Peak memory | 199792 kb |
| Host | smart-3042f6c8-d5f1-4cc5-82fd-1fbe9b286907 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=952512332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.952512332 |
| Directory | /workspace/64.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/64.uart_stress_all_with_rand_reset.2580308291 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 117230909724 ps |
| CPU time | 1372.02 seconds |
| Started | Aug 01 05:01:27 PM PDT 24 |
| Finished | Aug 01 05:24:19 PM PDT 24 |
| Peak memory | 226908 kb |
| Host | smart-0ab58cfc-7176-436a-ba1e-0d9624b7ce8e |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580308291 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.2580308291 |
| Directory | /workspace/64.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/65.uart_fifo_reset.2774822897 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 35517752408 ps |
| CPU time | 59.09 seconds |
| Started | Aug 01 05:01:29 PM PDT 24 |
| Finished | Aug 01 05:02:28 PM PDT 24 |
| Peak memory | 199964 kb |
| Host | smart-d07adb35-940f-4e03-8b91-f0dfb439a289 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2774822897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2774822897 |
| Directory | /workspace/65.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/65.uart_stress_all_with_rand_reset.1199449223 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 372487764155 ps |
| CPU time | 784.22 seconds |
| Started | Aug 01 05:01:28 PM PDT 24 |
| Finished | Aug 01 05:14:33 PM PDT 24 |
| Peak memory | 216336 kb |
| Host | smart-b800f8f6-dc4d-4d37-83cb-e9bf2c63f1b6 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199449223 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.1199449223 |
| Directory | /workspace/65.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/66.uart_stress_all_with_rand_reset.3573335907 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 39413078059 ps |
| CPU time | 1054.7 seconds |
| Started | Aug 01 05:01:31 PM PDT 24 |
| Finished | Aug 01 05:19:05 PM PDT 24 |
| Peak memory | 212752 kb |
| Host | smart-77db0011-bd76-4799-a20b-76293ee3039c |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573335907 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.3573335907 |
| Directory | /workspace/66.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/67.uart_fifo_reset.2963831749 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 20392472931 ps |
| CPU time | 31.95 seconds |
| Started | Aug 01 05:01:29 PM PDT 24 |
| Finished | Aug 01 05:02:01 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-e7531e51-7d16-4918-b503-d77e849785fd |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2963831749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.2963831749 |
| Directory | /workspace/67.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/67.uart_stress_all_with_rand_reset.139549156 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 38679651758 ps |
| CPU time | 90.68 seconds |
| Started | Aug 01 05:01:29 PM PDT 24 |
| Finished | Aug 01 05:03:00 PM PDT 24 |
| Peak memory | 216152 kb |
| Host | smart-f896b912-25e0-42a1-a694-0030ffaab31b |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139549156 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.139549156 |
| Directory | /workspace/67.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/68.uart_fifo_reset.3848312786 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 52709105163 ps |
| CPU time | 104.09 seconds |
| Started | Aug 01 05:01:30 PM PDT 24 |
| Finished | Aug 01 05:03:15 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-37710800-7dfc-4354-b1c4-11f46dae471d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3848312786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.3848312786 |
| Directory | /workspace/68.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/69.uart_fifo_reset.2962946479 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 99093065550 ps |
| CPU time | 232.89 seconds |
| Started | Aug 01 05:01:34 PM PDT 24 |
| Finished | Aug 01 05:05:27 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-32ac737e-99db-457d-9487-541f2c865268 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2962946479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.2962946479 |
| Directory | /workspace/69.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_alert_test.2335045522 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 18847645 ps |
| CPU time | 0.57 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:55:33 PM PDT 24 |
| Peak memory | 195200 kb |
| Host | smart-45943884-7801-4523-b1bc-1c0a47c2d312 |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335045522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2335045522 |
| Directory | /workspace/7.uart_alert_test/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_full.206049028 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 67820496165 ps |
| CPU time | 45.04 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:56:07 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-54701ee7-825d-4145-81ff-1d93bdebd828 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=206049028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.206049028 |
| Directory | /workspace/7.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_overflow.2425081134 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 102097138226 ps |
| CPU time | 39.46 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:56:00 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-3b1ca823-c718-4039-9986-ef48ff3d3142 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2425081134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2425081134 |
| Directory | /workspace/7.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/7.uart_fifo_reset.1873862268 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 37399888952 ps |
| CPU time | 33.64 seconds |
| Started | Aug 01 04:55:21 PM PDT 24 |
| Finished | Aug 01 04:55:54 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-159a9c49-7f0a-4e29-a5ce-67ac7cc3171d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1873862268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1873862268 |
| Directory | /workspace/7.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/7.uart_intr.2393333696 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 45147749614 ps |
| CPU time | 85.13 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:56:47 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-5db8e29b-95e2-4766-934c-b423d6ff7f89 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393333696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.2393333696 |
| Directory | /workspace/7.uart_intr/latest |
| Test location | /workspace/coverage/default/7.uart_long_xfer_wo_dly.1531060182 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 76646893001 ps |
| CPU time | 225.32 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:59:18 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-5d51709a-598e-4f59-bcf8-f4dc61573aaa |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1531060182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1531060182 |
| Directory | /workspace/7.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/7.uart_loopback.3480206655 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 6938596460 ps |
| CPU time | 7.3 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:55:39 PM PDT 24 |
| Peak memory | 198408 kb |
| Host | smart-57a25c33-88ad-4865-8e3b-d31a8619a358 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3480206655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.3480206655 |
| Directory | /workspace/7.uart_loopback/latest |
| Test location | /workspace/coverage/default/7.uart_noise_filter.1867551301 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 52893307497 ps |
| CPU time | 23.52 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:55:48 PM PDT 24 |
| Peak memory | 199040 kb |
| Host | smart-236ce475-ed84-4f79-ab06-0fe449ec9a17 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1867551301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.1867551301 |
| Directory | /workspace/7.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/7.uart_perf.2887510021 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 21282509481 ps |
| CPU time | 251.92 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:59:44 PM PDT 24 |
| Peak memory | 199772 kb |
| Host | smart-700ebbc2-2953-473d-aee5-532ffbf1ba5d |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2887510021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.2887510021 |
| Directory | /workspace/7.uart_perf/latest |
| Test location | /workspace/coverage/default/7.uart_rx_oversample.3108570321 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 5533663197 ps |
| CPU time | 50.25 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:56:15 PM PDT 24 |
| Peak memory | 199720 kb |
| Host | smart-cb1d3b7b-ac15-4049-8399-dec62866d19b |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3108570321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.3108570321 |
| Directory | /workspace/7.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/7.uart_rx_parity_err.1627154264 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 158546061245 ps |
| CPU time | 72.56 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:56:34 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-fbee288c-e1d6-414c-adba-39aed61bcedf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1627154264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1627154264 |
| Directory | /workspace/7.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/7.uart_rx_start_bit_filter.101526952 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 421161394 ps |
| CPU time | 1.32 seconds |
| Started | Aug 01 04:55:24 PM PDT 24 |
| Finished | Aug 01 04:55:25 PM PDT 24 |
| Peak memory | 195276 kb |
| Host | smart-3c685501-b863-464f-b4ec-54eed37592cf |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=101526952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.101526952 |
| Directory | /workspace/7.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/7.uart_smoke.2010441715 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 577628276 ps |
| CPU time | 1.4 seconds |
| Started | Aug 01 04:55:22 PM PDT 24 |
| Finished | Aug 01 04:55:24 PM PDT 24 |
| Peak memory | 198568 kb |
| Host | smart-8993abe2-11b7-4588-8826-5c77d1b457ac |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2010441715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2010441715 |
| Directory | /workspace/7.uart_smoke/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all.170133927 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 109151486843 ps |
| CPU time | 171.88 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:58:26 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-a1acdb16-f6c0-479c-9a8e-e60f0f28d991 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170133927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.170133927 |
| Directory | /workspace/7.uart_stress_all/latest |
| Test location | /workspace/coverage/default/7.uart_stress_all_with_rand_reset.1538595654 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 98308120303 ps |
| CPU time | 761.64 seconds |
| Started | Aug 01 04:55:31 PM PDT 24 |
| Finished | Aug 01 05:08:13 PM PDT 24 |
| Peak memory | 213428 kb |
| Host | smart-17f7987c-f6b3-4f53-a74c-7d75a15cebe3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538595654 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.1538595654 |
| Directory | /workspace/7.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/7.uart_tx_ovrd.524483824 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 592942461 ps |
| CPU time | 1.53 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:55:34 PM PDT 24 |
| Peak memory | 198100 kb |
| Host | smart-e82e1843-e0c7-4d3f-9bb8-cbc23e1e1a95 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=524483824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.524483824 |
| Directory | /workspace/7.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/7.uart_tx_rx.4081926815 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 33270636237 ps |
| CPU time | 11.56 seconds |
| Started | Aug 01 04:55:23 PM PDT 24 |
| Finished | Aug 01 04:55:34 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-932dc851-cc31-4eed-b891-3672cc674dfb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4081926815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.4081926815 |
| Directory | /workspace/7.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/70.uart_fifo_reset.2900824370 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 73496168131 ps |
| CPU time | 112.33 seconds |
| Started | Aug 01 05:01:32 PM PDT 24 |
| Finished | Aug 01 05:03:25 PM PDT 24 |
| Peak memory | 199860 kb |
| Host | smart-27bc28f5-4a48-4f88-88a3-e5ac4112b873 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2900824370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2900824370 |
| Directory | /workspace/70.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/70.uart_stress_all_with_rand_reset.2438467856 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 46312457382 ps |
| CPU time | 201.55 seconds |
| Started | Aug 01 05:01:28 PM PDT 24 |
| Finished | Aug 01 05:04:49 PM PDT 24 |
| Peak memory | 209232 kb |
| Host | smart-7e6f1938-7a8e-4894-a4d9-d8427fa55910 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438467856 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.2438467856 |
| Directory | /workspace/70.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/71.uart_fifo_reset.4106304745 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 15672217555 ps |
| CPU time | 29.52 seconds |
| Started | Aug 01 05:01:30 PM PDT 24 |
| Finished | Aug 01 05:01:59 PM PDT 24 |
| Peak memory | 199652 kb |
| Host | smart-c9a6d8e0-3c96-49a4-a0c9-6c5a70530560 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4106304745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4106304745 |
| Directory | /workspace/71.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/71.uart_stress_all_with_rand_reset.2971898272 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 151235782754 ps |
| CPU time | 925.29 seconds |
| Started | Aug 01 05:01:28 PM PDT 24 |
| Finished | Aug 01 05:16:53 PM PDT 24 |
| Peak memory | 227484 kb |
| Host | smart-f89c0e83-8ed9-41e5-8521-5b1cd17361bc |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971898272 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.2971898272 |
| Directory | /workspace/71.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/72.uart_fifo_reset.4130597573 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 104267513744 ps |
| CPU time | 47.03 seconds |
| Started | Aug 01 05:01:28 PM PDT 24 |
| Finished | Aug 01 05:02:15 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-5d66804f-624c-4f95-abe7-7cc70c4ace32 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4130597573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.4130597573 |
| Directory | /workspace/72.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/72.uart_stress_all_with_rand_reset.1567506068 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 151307197557 ps |
| CPU time | 413.83 seconds |
| Started | Aug 01 05:01:29 PM PDT 24 |
| Finished | Aug 01 05:08:23 PM PDT 24 |
| Peak memory | 224656 kb |
| Host | smart-d696eadd-4284-4e38-a325-b96df67bbff3 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567506068 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.1567506068 |
| Directory | /workspace/72.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/73.uart_fifo_reset.1857413879 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 9225127974 ps |
| CPU time | 26.92 seconds |
| Started | Aug 01 05:01:37 PM PDT 24 |
| Finished | Aug 01 05:02:04 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-aeda43fd-0bcc-45dd-abb4-cc5b2632826e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1857413879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.1857413879 |
| Directory | /workspace/73.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/74.uart_fifo_reset.3999656540 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 19058751500 ps |
| CPU time | 30.22 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:02:08 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-6222c547-63d2-4e3a-b742-806892d8bcb1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3999656540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3999656540 |
| Directory | /workspace/74.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_fifo_reset.1077251322 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 73280477914 ps |
| CPU time | 394.7 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:08:13 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-8a6d07d1-9c93-49de-afc5-2eb72b25b41a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1077251322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.1077251322 |
| Directory | /workspace/75.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/75.uart_stress_all_with_rand_reset.1570775085 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 55530963109 ps |
| CPU time | 699.8 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:13:18 PM PDT 24 |
| Peak memory | 216504 kb |
| Host | smart-8bef48cd-eacb-4484-b138-9e9d3c55f835 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570775085 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.1570775085 |
| Directory | /workspace/75.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/76.uart_fifo_reset.1774827418 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 26695973765 ps |
| CPU time | 11.67 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:01:50 PM PDT 24 |
| Peak memory | 199616 kb |
| Host | smart-ea9d5e06-0f52-4da1-9854-e0a3b545df2b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774827418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.1774827418 |
| Directory | /workspace/76.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/76.uart_stress_all_with_rand_reset.4038344901 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 74413873470 ps |
| CPU time | 360.9 seconds |
| Started | Aug 01 05:01:37 PM PDT 24 |
| Finished | Aug 01 05:07:39 PM PDT 24 |
| Peak memory | 216464 kb |
| Host | smart-62fcc448-0937-42db-b551-271f699cad43 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038344901 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.4038344901 |
| Directory | /workspace/76.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/77.uart_fifo_reset.1713895361 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 43685873860 ps |
| CPU time | 9.84 seconds |
| Started | Aug 01 05:01:40 PM PDT 24 |
| Finished | Aug 01 05:01:50 PM PDT 24 |
| Peak memory | 199888 kb |
| Host | smart-1c59b3d5-e18e-41d3-838f-bee3ce11280e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1713895361 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1713895361 |
| Directory | /workspace/77.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_fifo_reset.1769693457 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 198457979778 ps |
| CPU time | 67.48 seconds |
| Started | Aug 01 05:01:39 PM PDT 24 |
| Finished | Aug 01 05:02:47 PM PDT 24 |
| Peak memory | 199800 kb |
| Host | smart-d453682a-3638-4812-8569-c88761f1c566 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769693457 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1769693457 |
| Directory | /workspace/78.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/78.uart_stress_all_with_rand_reset.3557281478 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 96878307190 ps |
| CPU time | 1093.05 seconds |
| Started | Aug 01 05:01:37 PM PDT 24 |
| Finished | Aug 01 05:19:51 PM PDT 24 |
| Peak memory | 227244 kb |
| Host | smart-e93d2188-b8dd-4e62-a9e5-13680ffc06ee |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557281478 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.3557281478 |
| Directory | /workspace/78.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/79.uart_fifo_reset.2703929040 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 22101465925 ps |
| CPU time | 33.2 seconds |
| Started | Aug 01 05:01:40 PM PDT 24 |
| Finished | Aug 01 05:02:13 PM PDT 24 |
| Peak memory | 199832 kb |
| Host | smart-c4f8d24e-fe10-4d0f-b572-1fc06268e6b8 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2703929040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.2703929040 |
| Directory | /workspace/79.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/79.uart_stress_all_with_rand_reset.774486550 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 178237848025 ps |
| CPU time | 374.38 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:07:53 PM PDT 24 |
| Peak memory | 215456 kb |
| Host | smart-06ccbf35-58dc-4bea-a800-1522f9db2483 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774486550 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.774486550 |
| Directory | /workspace/79.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_alert_test.3854251290 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 11221963 ps |
| CPU time | 0.56 seconds |
| Started | Aug 01 04:55:38 PM PDT 24 |
| Finished | Aug 01 04:55:39 PM PDT 24 |
| Peak memory | 194612 kb |
| Host | smart-222a0d7c-950e-4c0d-9d26-5dce74f33f6c |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854251290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3854251290 |
| Directory | /workspace/8.uart_alert_test/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_full.1249852084 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 91007538439 ps |
| CPU time | 246.67 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:59:39 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-2d1bba00-831d-46d8-aad0-4a77ad0c205a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1249852084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.1249852084 |
| Directory | /workspace/8.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_overflow.4228531435 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 91842675652 ps |
| CPU time | 199.07 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:58:51 PM PDT 24 |
| Peak memory | 199744 kb |
| Host | smart-c8eb6aa5-4e93-486d-b74f-a097c04f1b0f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4228531435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4228531435 |
| Directory | /workspace/8.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/8.uart_fifo_reset.1845355965 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 43347216369 ps |
| CPU time | 18.35 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:55:53 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-89bb4ab4-8674-45a9-866e-ac5bbd05e521 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1845355965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.1845355965 |
| Directory | /workspace/8.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/8.uart_intr.1785560351 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 220023962734 ps |
| CPU time | 370.76 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 05:01:45 PM PDT 24 |
| Peak memory | 199672 kb |
| Host | smart-c7f1f52c-10f0-4f90-801d-aecacef1c11f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785560351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.1785560351 |
| Directory | /workspace/8.uart_intr/latest |
| Test location | /workspace/coverage/default/8.uart_long_xfer_wo_dly.3618032731 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 61674451699 ps |
| CPU time | 623.87 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 05:05:58 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-46165df6-1e45-450a-85b3-ce67aede705a |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3618032731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.3618032731 |
| Directory | /workspace/8.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/8.uart_loopback.843998742 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 11519779792 ps |
| CPU time | 10.53 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:55:43 PM PDT 24 |
| Peak memory | 199776 kb |
| Host | smart-72289e75-3d55-4e8c-8919-32e9739112ed |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=843998742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.843998742 |
| Directory | /workspace/8.uart_loopback/latest |
| Test location | /workspace/coverage/default/8.uart_noise_filter.3475350903 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 48702513265 ps |
| CPU time | 25.97 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:55:59 PM PDT 24 |
| Peak memory | 198380 kb |
| Host | smart-a6567f97-3a9f-4f87-abd3-ab1c34d2c805 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3475350903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.3475350903 |
| Directory | /workspace/8.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/8.uart_perf.3295100123 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 22974774393 ps |
| CPU time | 246.02 seconds |
| Started | Aug 01 04:55:31 PM PDT 24 |
| Finished | Aug 01 04:59:38 PM PDT 24 |
| Peak memory | 199692 kb |
| Host | smart-9f889843-fb0b-44be-b767-eb17993ee24f |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3295100123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.3295100123 |
| Directory | /workspace/8.uart_perf/latest |
| Test location | /workspace/coverage/default/8.uart_rx_oversample.9142324 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5412305261 ps |
| CPU time | 47.03 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:56:21 PM PDT 24 |
| Peak memory | 197944 kb |
| Host | smart-7c035a69-5d57-41b9-9ade-19c50f7bf919 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=9142324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.9142324 |
| Directory | /workspace/8.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/8.uart_rx_parity_err.1054183321 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 25336685989 ps |
| CPU time | 50.26 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:56:22 PM PDT 24 |
| Peak memory | 199712 kb |
| Host | smart-0653229b-f0ef-4f5a-8fc1-d9b5250e2cee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1054183321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.1054183321 |
| Directory | /workspace/8.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/8.uart_rx_start_bit_filter.2650031007 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 42045107360 ps |
| CPU time | 33.61 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:56:06 PM PDT 24 |
| Peak memory | 196056 kb |
| Host | smart-d790f29c-dd6c-4014-9e50-bc0e474bdfee |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2650031007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.2650031007 |
| Directory | /workspace/8.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/8.uart_smoke.1377613591 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 6244371015 ps |
| CPU time | 9.91 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:55:45 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-4f770bd9-4624-48e6-a9de-1f2ddf03f5fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1377613591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.1377613591 |
| Directory | /workspace/8.uart_smoke/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all.1349943731 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 113266087958 ps |
| CPU time | 194.84 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:58:49 PM PDT 24 |
| Peak memory | 208168 kb |
| Host | smart-c5d3e551-bb36-420e-8377-2694c1a13f47 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349943731 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.1349943731 |
| Directory | /workspace/8.uart_stress_all/latest |
| Test location | /workspace/coverage/default/8.uart_stress_all_with_rand_reset.411083015 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 14220556552 ps |
| CPU time | 136.96 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:57:49 PM PDT 24 |
| Peak memory | 209508 kb |
| Host | smart-ebd8a63a-67d8-47cf-ad44-a58c677f7027 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411083015 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.411083015 |
| Directory | /workspace/8.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/8.uart_tx_ovrd.1895914773 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 745627982 ps |
| CPU time | 3.01 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:55:36 PM PDT 24 |
| Peak memory | 199404 kb |
| Host | smart-e45fc51f-61c8-4718-92b2-4930ca2c6310 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1895914773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.1895914773 |
| Directory | /workspace/8.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/8.uart_tx_rx.4136395898 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 39922323567 ps |
| CPU time | 102.03 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:57:15 PM PDT 24 |
| Peak memory | 199872 kb |
| Host | smart-67a54ba9-4be8-4d9a-ba4a-1ce9d494ed03 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4136395898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.4136395898 |
| Directory | /workspace/8.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/80.uart_fifo_reset.3332949258 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 98004793958 ps |
| CPU time | 42.74 seconds |
| Started | Aug 01 05:01:38 PM PDT 24 |
| Finished | Aug 01 05:02:21 PM PDT 24 |
| Peak memory | 199784 kb |
| Host | smart-c1553b59-9692-4ebc-a136-53874a097ace |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3332949258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.3332949258 |
| Directory | /workspace/80.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/80.uart_stress_all_with_rand_reset.339547475 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 115866076172 ps |
| CPU time | 820.15 seconds |
| Started | Aug 01 05:01:39 PM PDT 24 |
| Finished | Aug 01 05:15:20 PM PDT 24 |
| Peak memory | 224736 kb |
| Host | smart-a3e4a7d2-e7d7-4afa-b6ce-24c55b7c269a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339547475 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.339547475 |
| Directory | /workspace/80.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/81.uart_fifo_reset.3669259201 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 89663603464 ps |
| CPU time | 41.95 seconds |
| Started | Aug 01 05:01:43 PM PDT 24 |
| Finished | Aug 01 05:02:25 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-ee06363e-1129-47aa-8c87-eb39d377768a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3669259201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.3669259201 |
| Directory | /workspace/81.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2622199044 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 77874370536 ps |
| CPU time | 1128.57 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:20:40 PM PDT 24 |
| Peak memory | 216464 kb |
| Host | smart-170abea7-a2de-4055-9703-3783e735b9b1 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622199044 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2622199044 |
| Directory | /workspace/81.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/82.uart_fifo_reset.4285255633 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 18888806774 ps |
| CPU time | 61.78 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:02:53 PM PDT 24 |
| Peak memory | 199820 kb |
| Host | smart-21d5ba1b-b1d0-401f-a64b-2451244855df |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4285255633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.4285255633 |
| Directory | /workspace/82.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/82.uart_stress_all_with_rand_reset.3983171555 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 18587674109 ps |
| CPU time | 205.68 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:05:16 PM PDT 24 |
| Peak memory | 210496 kb |
| Host | smart-a7350b0a-088f-4bf6-a8ee-34fb4450e5ac |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983171555 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.3983171555 |
| Directory | /workspace/82.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/83.uart_fifo_reset.1988782515 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 55440349091 ps |
| CPU time | 65.79 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:02:56 PM PDT 24 |
| Peak memory | 199824 kb |
| Host | smart-24428c38-ab1f-42c0-852a-9daf7b255b93 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1988782515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1988782515 |
| Directory | /workspace/83.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2433193406 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 195695136696 ps |
| CPU time | 1019.44 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:18:50 PM PDT 24 |
| Peak memory | 216292 kb |
| Host | smart-55266076-ecd9-43ff-9bfa-7fb66d0b0b8d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433193406 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2433193406 |
| Directory | /workspace/83.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/84.uart_fifo_reset.1676358647 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 73462688794 ps |
| CPU time | 137.58 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:04:09 PM PDT 24 |
| Peak memory | 199908 kb |
| Host | smart-1456f85c-2d7f-4888-a759-5ec8c2843c56 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1676358647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.1676358647 |
| Directory | /workspace/84.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/84.uart_stress_all_with_rand_reset.3265268893 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 68725545517 ps |
| CPU time | 971.28 seconds |
| Started | Aug 01 05:01:53 PM PDT 24 |
| Finished | Aug 01 05:18:04 PM PDT 24 |
| Peak memory | 216356 kb |
| Host | smart-02667afd-6b1c-4548-8d78-9e56bfbcd29d |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265268893 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.3265268893 |
| Directory | /workspace/84.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/85.uart_fifo_reset.986270277 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 5949435272 ps |
| CPU time | 12.5 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:02:03 PM PDT 24 |
| Peak memory | 199904 kb |
| Host | smart-285cb4fc-1b8d-47af-b788-b191114f3cb3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=986270277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.986270277 |
| Directory | /workspace/85.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_fifo_reset.1012357774 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 49298432642 ps |
| CPU time | 39.81 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:02:31 PM PDT 24 |
| Peak memory | 199868 kb |
| Host | smart-aefb917e-6f14-450d-866e-9c2f6c0bc417 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1012357774 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.1012357774 |
| Directory | /workspace/86.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/86.uart_stress_all_with_rand_reset.3385408746 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 60504691057 ps |
| CPU time | 632.55 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:12:23 PM PDT 24 |
| Peak memory | 216416 kb |
| Host | smart-c079fb9d-6384-49e9-af22-ad8ab9958712 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385408746 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.3385408746 |
| Directory | /workspace/86.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/87.uart_fifo_reset.1450411512 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 66080131158 ps |
| CPU time | 19.82 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:02:11 PM PDT 24 |
| Peak memory | 199740 kb |
| Host | smart-93f5511a-0956-4a0d-bdf9-8ba24edb360e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1450411512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.1450411512 |
| Directory | /workspace/87.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/87.uart_stress_all_with_rand_reset.3190475331 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 192604777135 ps |
| CPU time | 818.48 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:15:30 PM PDT 24 |
| Peak memory | 224684 kb |
| Host | smart-a8118e27-3724-4224-a4ee-a13c67f4d853 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190475331 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.3190475331 |
| Directory | /workspace/87.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/88.uart_fifo_reset.3855097439 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 79519861496 ps |
| CPU time | 22.77 seconds |
| Started | Aug 01 05:01:51 PM PDT 24 |
| Finished | Aug 01 05:02:14 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-ea7515ee-4e85-4408-9000-5b48ba01067a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3855097439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3855097439 |
| Directory | /workspace/88.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/88.uart_stress_all_with_rand_reset.2613963304 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 592446719980 ps |
| CPU time | 347.64 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:07:38 PM PDT 24 |
| Peak memory | 210928 kb |
| Host | smart-6c3b6491-1ea8-4966-bbb0-8a7e756fa9c2 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613963304 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.2613963304 |
| Directory | /workspace/88.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/89.uart_fifo_reset.464827409 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 48358821043 ps |
| CPU time | 80.27 seconds |
| Started | Aug 01 05:01:49 PM PDT 24 |
| Finished | Aug 01 05:03:10 PM PDT 24 |
| Peak memory | 199780 kb |
| Host | smart-e48957ef-e3ef-4a89-9e29-475a985734fe |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=464827409 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.464827409 |
| Directory | /workspace/89.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/89.uart_stress_all_with_rand_reset.2095105018 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 250239975325 ps |
| CPU time | 774.47 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:14:45 PM PDT 24 |
| Peak memory | 216352 kb |
| Host | smart-1ec0297e-5d65-4eb9-bf9a-7f6c21101446 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095105018 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.2095105018 |
| Directory | /workspace/89.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_alert_test.2915695049 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 42570880 ps |
| CPU time | 0.55 seconds |
| Started | Aug 01 04:55:48 PM PDT 24 |
| Finished | Aug 01 04:55:49 PM PDT 24 |
| Peak memory | 195124 kb |
| Host | smart-4b9d1d58-c206-457a-8dc5-0a2acd9e4bff |
| User | root |
| Command | /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915695049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2915695049 |
| Directory | /workspace/9.uart_alert_test/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_full.3903870488 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 64764341478 ps |
| CPU time | 26.32 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:56:00 PM PDT 24 |
| Peak memory | 199788 kb |
| Host | smart-a6249eda-dc37-4eae-aa96-198e94f8c58d |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3903870488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3903870488 |
| Directory | /workspace/9.uart_fifo_full/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_overflow.371413780 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 20366684698 ps |
| CPU time | 44 seconds |
| Started | Aug 01 04:55:34 PM PDT 24 |
| Finished | Aug 01 04:56:18 PM PDT 24 |
| Peak memory | 199848 kb |
| Host | smart-5e67d3c6-904f-4278-9c82-48360afcb791 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=371413780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.371413780 |
| Directory | /workspace/9.uart_fifo_overflow/latest |
| Test location | /workspace/coverage/default/9.uart_fifo_reset.3338173394 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 144665620547 ps |
| CPU time | 111.68 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:57:25 PM PDT 24 |
| Peak memory | 199812 kb |
| Host | smart-d65145b0-e2ba-4c53-8a43-fcfc2b2cbb1e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3338173394 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.3338173394 |
| Directory | /workspace/9.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/9.uart_intr.2432716377 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 3641763253 ps |
| CPU time | 5.48 seconds |
| Started | Aug 01 04:55:32 PM PDT 24 |
| Finished | Aug 01 04:55:38 PM PDT 24 |
| Peak memory | 196556 kb |
| Host | smart-c0fd997c-a32e-4668-b925-b21dcc3f4d7a |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432716377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2432716377 |
| Directory | /workspace/9.uart_intr/latest |
| Test location | /workspace/coverage/default/9.uart_long_xfer_wo_dly.2098269064 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 73244376341 ps |
| CPU time | 181.98 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:58:46 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-941546c4-8c42-4283-9681-1671b059c379 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2098269064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2098269064 |
| Directory | /workspace/9.uart_long_xfer_wo_dly/latest |
| Test location | /workspace/coverage/default/9.uart_loopback.1901133550 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 5186174342 ps |
| CPU time | 11.01 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:55:56 PM PDT 24 |
| Peak memory | 198492 kb |
| Host | smart-45fefbea-7253-4c9d-b8f6-d1f710f7dbbb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901133550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.1901133550 |
| Directory | /workspace/9.uart_loopback/latest |
| Test location | /workspace/coverage/default/9.uart_noise_filter.1769653151 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 49949057062 ps |
| CPU time | 96.35 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:57:21 PM PDT 24 |
| Peak memory | 200112 kb |
| Host | smart-6c7f607f-fcf1-4556-9430-23b0b6d9b7d3 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1769653151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1769653151 |
| Directory | /workspace/9.uart_noise_filter/latest |
| Test location | /workspace/coverage/default/9.uart_perf.4014560603 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 11414899099 ps |
| CPU time | 723.33 seconds |
| Started | Aug 01 04:55:42 PM PDT 24 |
| Finished | Aug 01 05:07:45 PM PDT 24 |
| Peak memory | 199828 kb |
| Host | smart-1cbe3147-120d-43ed-b837-af5a70ffde52 |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4014560603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.4014560603 |
| Directory | /workspace/9.uart_perf/latest |
| Test location | /workspace/coverage/default/9.uart_rx_oversample.3489644611 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 1588102915 ps |
| CPU time | 3.09 seconds |
| Started | Aug 01 04:55:31 PM PDT 24 |
| Finished | Aug 01 04:55:35 PM PDT 24 |
| Peak memory | 197856 kb |
| Host | smart-4d34eaac-77e6-4c0c-b3f3-18e46fd601dd |
| User | root |
| Command | /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3489644611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.3489644611 |
| Directory | /workspace/9.uart_rx_oversample/latest |
| Test location | /workspace/coverage/default/9.uart_rx_parity_err.2748566979 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 147127904631 ps |
| CPU time | 65.94 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:56:51 PM PDT 24 |
| Peak memory | 199760 kb |
| Host | smart-4fe411c3-1e25-461d-bcb8-4be7e8082b5a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2748566979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.2748566979 |
| Directory | /workspace/9.uart_rx_parity_err/latest |
| Test location | /workspace/coverage/default/9.uart_rx_start_bit_filter.4150424923 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 33245253726 ps |
| CPU time | 24.75 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:56:09 PM PDT 24 |
| Peak memory | 196180 kb |
| Host | smart-bb0ebbda-ee3f-487e-97e6-6427fe1f1bde |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4150424923 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.4150424923 |
| Directory | /workspace/9.uart_rx_start_bit_filter/latest |
| Test location | /workspace/coverage/default/9.uart_smoke.3494861800 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 6048081988 ps |
| CPU time | 11.82 seconds |
| Started | Aug 01 04:55:43 PM PDT 24 |
| Finished | Aug 01 04:55:55 PM PDT 24 |
| Peak memory | 199876 kb |
| Host | smart-59fae4e0-9565-4dab-ad8b-0ba5bc3d366a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3494861800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3494861800 |
| Directory | /workspace/9.uart_smoke/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all.1173304431 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 23426836630 ps |
| CPU time | 24.87 seconds |
| Started | Aug 01 04:55:44 PM PDT 24 |
| Finished | Aug 01 04:56:09 PM PDT 24 |
| Peak memory | 199928 kb |
| Host | smart-9f84cda0-0be5-4bd0-b2f8-c5159f16f18d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173304431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.1173304431 |
| Directory | /workspace/9.uart_stress_all/latest |
| Test location | /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2677867172 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 433867965886 ps |
| CPU time | 431.47 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 05:02:56 PM PDT 24 |
| Peak memory | 216288 kb |
| Host | smart-4c196331-9040-46f8-9e2c-efd2a93c2073 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677867172 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2677867172 |
| Directory | /workspace/9.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/9.uart_tx_ovrd.1071749148 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 687086952 ps |
| CPU time | 2 seconds |
| Started | Aug 01 04:55:45 PM PDT 24 |
| Finished | Aug 01 04:55:47 PM PDT 24 |
| Peak memory | 199564 kb |
| Host | smart-e359f092-dc8b-4d9b-ae88-88f1dd696f36 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1071749148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.1071749148 |
| Directory | /workspace/9.uart_tx_ovrd/latest |
| Test location | /workspace/coverage/default/9.uart_tx_rx.340465045 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 17320476739 ps |
| CPU time | 7.93 seconds |
| Started | Aug 01 04:55:33 PM PDT 24 |
| Finished | Aug 01 04:55:41 PM PDT 24 |
| Peak memory | 197020 kb |
| Host | smart-63e2a301-fba4-44dc-a7cb-a5188bce505e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=340465045 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.340465045 |
| Directory | /workspace/9.uart_tx_rx/latest |
| Test location | /workspace/coverage/default/90.uart_fifo_reset.4022874644 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 109324157094 ps |
| CPU time | 147.94 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:04:19 PM PDT 24 |
| Peak memory | 199756 kb |
| Host | smart-a0538cce-26cb-4da6-a78c-d5dbbb5bf092 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4022874644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4022874644 |
| Directory | /workspace/90.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/90.uart_stress_all_with_rand_reset.821446505 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 54866050846 ps |
| CPU time | 767.86 seconds |
| Started | Aug 01 05:01:52 PM PDT 24 |
| Finished | Aug 01 05:14:40 PM PDT 24 |
| Peak memory | 216460 kb |
| Host | smart-0ed3b25c-fe5b-478f-a89e-294eb39b19fd |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821446505 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.821446505 |
| Directory | /workspace/90.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/91.uart_fifo_reset.1213548634 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 6981043365 ps |
| CPU time | 18.92 seconds |
| Started | Aug 01 05:01:52 PM PDT 24 |
| Finished | Aug 01 05:02:11 PM PDT 24 |
| Peak memory | 199768 kb |
| Host | smart-1cec57e9-199a-4ccd-bd09-ca4e4be57c8f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1213548634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1213548634 |
| Directory | /workspace/91.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/91.uart_stress_all_with_rand_reset.2040088654 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 118804070739 ps |
| CPU time | 409.61 seconds |
| Started | Aug 01 05:01:52 PM PDT 24 |
| Finished | Aug 01 05:08:42 PM PDT 24 |
| Peak memory | 216408 kb |
| Host | smart-7af7fddc-e4fd-4cbd-a601-f08fe83a48cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040088654 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.2040088654 |
| Directory | /workspace/91.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/92.uart_fifo_reset.1500001464 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 47706130383 ps |
| CPU time | 12.55 seconds |
| Started | Aug 01 05:01:53 PM PDT 24 |
| Finished | Aug 01 05:02:06 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-047cefa9-3eb1-4930-adec-aa975b79c7db |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1500001464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1500001464 |
| Directory | /workspace/92.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_fifo_reset.4273300601 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 61745064205 ps |
| CPU time | 46.48 seconds |
| Started | Aug 01 05:01:50 PM PDT 24 |
| Finished | Aug 01 05:02:37 PM PDT 24 |
| Peak memory | 199804 kb |
| Host | smart-c1504ecb-c049-4459-9392-bf4d2124c036 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4273300601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.4273300601 |
| Directory | /workspace/93.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/93.uart_stress_all_with_rand_reset.3169769444 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 180110572384 ps |
| CPU time | 390.64 seconds |
| Started | Aug 01 05:02:06 PM PDT 24 |
| Finished | Aug 01 05:08:37 PM PDT 24 |
| Peak memory | 216400 kb |
| Host | smart-6df076f5-335a-4878-9690-f46d4b691799 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169769444 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.3169769444 |
| Directory | /workspace/93.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/94.uart_fifo_reset.1187005657 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 54937076029 ps |
| CPU time | 24.97 seconds |
| Started | Aug 01 05:02:02 PM PDT 24 |
| Finished | Aug 01 05:02:27 PM PDT 24 |
| Peak memory | 199840 kb |
| Host | smart-5561e425-92ab-4d74-9986-5ee00f7bfb43 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1187005657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1187005657 |
| Directory | /workspace/94.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/94.uart_stress_all_with_rand_reset.886051276 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 106322517899 ps |
| CPU time | 264.64 seconds |
| Started | Aug 01 05:02:04 PM PDT 24 |
| Finished | Aug 01 05:06:28 PM PDT 24 |
| Peak memory | 213156 kb |
| Host | smart-7527ce0a-9577-401a-8ae7-ea1b153666cb |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886051276 -assert nopostpr oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.886051276 |
| Directory | /workspace/94.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/95.uart_fifo_reset.892606620 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 30962591367 ps |
| CPU time | 48.13 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:02:52 PM PDT 24 |
| Peak memory | 199796 kb |
| Host | smart-fa4de7f5-db07-4181-82a6-152ed143079c |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=892606620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.892606620 |
| Directory | /workspace/95.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3579625470 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 51720083397 ps |
| CPU time | 267.41 seconds |
| Started | Aug 01 05:02:02 PM PDT 24 |
| Finished | Aug 01 05:06:29 PM PDT 24 |
| Peak memory | 216392 kb |
| Host | smart-f2ba3486-0503-45f5-8479-9f74b3f1ac98 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579625470 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3579625470 |
| Directory | /workspace/95.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/96.uart_fifo_reset.1441351586 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 43302602026 ps |
| CPU time | 16.51 seconds |
| Started | Aug 01 05:02:05 PM PDT 24 |
| Finished | Aug 01 05:02:22 PM PDT 24 |
| Peak memory | 199764 kb |
| Host | smart-99637cf4-ba7c-4a6a-8c60-116da8f0b1a1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1441351586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.1441351586 |
| Directory | /workspace/96.uart_fifo_reset/latest |
| Test location | /workspace/coverage/default/96.uart_stress_all_with_rand_reset.2170988861 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 17014120197 ps |
| CPU time | 78.74 seconds |
| Started | Aug 01 05:02:04 PM PDT 24 |
| Finished | Aug 01 05:03:22 PM PDT 24 |
| Peak memory | 216100 kb |
| Host | smart-9a182e92-7cd1-4fdf-84c2-6dd09e181c8a |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170988861 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.2170988861 |
| Directory | /workspace/96.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/97.uart_stress_all_with_rand_reset.1970622486 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 53590427632 ps |
| CPU time | 668.62 seconds |
| Started | Aug 01 05:02:04 PM PDT 24 |
| Finished | Aug 01 05:13:13 PM PDT 24 |
| Peak memory | 216348 kb |
| Host | smart-4ba17e9d-f456-4e94-b579-3e509ade4c89 |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970622486 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.1970622486 |
| Directory | /workspace/97.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/98.uart_stress_all_with_rand_reset.2764801656 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 73343539857 ps |
| CPU time | 216.95 seconds |
| Started | Aug 01 05:02:03 PM PDT 24 |
| Finished | Aug 01 05:05:40 PM PDT 24 |
| Peak memory | 216328 kb |
| Host | smart-141e6326-9b26-4782-9b5a-a474cf7fb2db |
| User | root |
| Command | /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764801656 -assert nopostp roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.2764801656 |
| Directory | /workspace/98.uart_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/99.uart_fifo_reset.4032029364 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 93448148030 ps |
| CPU time | 21.2 seconds |
| Started | Aug 01 05:02:06 PM PDT 24 |
| Finished | Aug 01 05:02:27 PM PDT 24 |
| Peak memory | 199748 kb |
| Host | smart-4d0b3212-c8f4-46dd-b8fd-0032044bcd6b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4032029364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.4032029364 |
| Directory | /workspace/99.uart_fifo_reset/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |