Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	111664	1			T1	578		T2	7		T3	22
all_values[1]	111664	1			T1	578		T2	7		T3	22
all_values[2]	111664	1			T1	578		T2	7		T3	22
all_values[3]	111664	1			T1	578		T2	7		T3	22
all_values[4]	111664	1			T1	578		T2	7		T3	22
all_values[5]	111664	1			T1	578		T2	7		T3	22
all_values[6]	111664	1			T1	578		T2	7		T3	22
all_values[7]	111664	1			T1	578		T2	7		T3	22
all_values[8]	111664	1			T1	578		T2	7		T3	22

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506562

1

T1

2284

T2

38

T3

124

auto[1]

498414

1

T1

2918

T2

25

T3

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

910698

1

T1

4789

T2

48

T3

169

auto[1]

94278

1

T1

413

T2

15

T3

29

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	32350	1			T1	158		T2	1		T4	18
all_values[0]	auto[0]	auto[1]	23821	1			T1	4		T2	4		T4	7
all_values[0]	auto[1]	auto[0]	33064	1			T1	137		T4	2		T5	19
all_values[0]	auto[1]	auto[1]	22429	1			T1	279		T2	2		T3	22
all_values[1]	auto[0]	auto[0]	55680	1			T1	309		T2	3		T3	19
all_values[1]	auto[0]	auto[1]	1594	1			T1	5		T2	1		T3	1
all_values[1]	auto[1]	auto[0]	52723	1			T1	262		T2	3		T3	2
all_values[1]	auto[1]	auto[1]	1667	1			T1	2		T5	2		T6	1
all_values[2]	auto[0]	auto[0]	56546	1			T1	358		T2	3		T3	20
all_values[2]	auto[0]	auto[1]	2954	1			T1	4		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	49702	1			T1	207		T2	3		T4	18
all_values[2]	auto[1]	auto[1]	2462	1			T1	9		T4	7		T5	5
all_values[3]	auto[0]	auto[0]	53613	1			T1	160		T2	2		T4	11
all_values[3]	auto[0]	auto[1]	334	1			T5	4		T6	1		T7	4
all_values[3]	auto[1]	auto[0]	57448	1			T1	418		T2	4		T3	22
all_values[3]	auto[1]	auto[1]	269	1			T2	1		T7	3		T111	1
all_values[4]	auto[0]	auto[0]	58445	1			T1	161		T2	6		T3	20
all_values[4]	auto[0]	auto[1]	508	1			T5	3		T7	3		T12	6
all_values[4]	auto[1]	auto[0]	52238	1			T1	417		T2	1		T3	2
all_values[4]	auto[1]	auto[1]	473	1			T5	1		T7	4		T15	1
all_values[5]	auto[0]	auto[0]	57802	1			T1	233		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	170	1			T5	1		T7	8		T14	2
all_values[5]	auto[1]	auto[0]	53513	1			T1	345		T2	4		T3	20
all_values[5]	auto[1]	auto[1]	179	1			T7	2		T14	2		T37	2
all_values[6]	auto[0]	auto[0]	54197	1			T1	301		T2	5		T3	18
all_values[6]	auto[0]	auto[1]	177	1			T5	3		T7	2		T32	1
all_values[6]	auto[1]	auto[0]	57107	1			T1	277		T2	2		T3	4
all_values[6]	auto[1]	auto[1]	183	1			T5	3		T7	1		T14	2
all_values[7]	auto[0]	auto[0]	50682	1			T1	261		T2	4		T3	22
all_values[7]	auto[0]	auto[1]	351	1			T5	3		T7	2		T12	4
all_values[7]	auto[1]	auto[0]	60334	1			T1	317		T2	3		T4	32
all_values[7]	auto[1]	auto[1]	297	1			T5	3		T7	4		T110	2
all_values[8]	auto[0]	auto[0]	37139	1			T1	313		T2	1		T3	18
all_values[8]	auto[0]	auto[1]	20199	1			T1	17		T2	4		T3	2
all_values[8]	auto[1]	auto[0]	38115	1			T1	155		T4	21		T5	24
all_values[8]	auto[1]	auto[1]	16211	1			T1	93		T2	2		T3	2