Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2472	1			T1	2		T2	2		T3	1
auto[BaudRate115200]	2080	1			T1	3		T2	2		T4	2
auto[BaudRate230400]	2285	1			T1	3		T2	1		T4	1
auto[BaudRate128Kbps]	2052	1			T1	2		T4	1		T5	5
auto[BaudRate256Kbps]	2491	1			T1	3		T2	1		T3	1
auto[BaudRate1Mbps]	1889	1			T1	2		T2	3		T3	1
auto[BaudRate1p5Mbps]	1306	1			T3	4		T4	2		T5	4

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1225	1			T7	66		T33	8		T21	8
freqs[25]	1411	1			T10	10		T292	2		T166	10
freqs[48]	779	1			T20	8		T284	7		T268	8
freqs[50]	811	1			T4	9		T167	5		T106	14
freqs[100]	1013	1			T257	2		T240	7		T124	10

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	202	1			T7	6		T33	2		T103	2
auto[BaudRate9600]	freqs[25]	232	1			T166	2		T57	1		T129	2
auto[BaudRate9600]	freqs[48]	100	1			T20	4		T268	1		T314	6
auto[BaudRate9600]	freqs[50]	113	1			T4	1		T167	1		T106	3
auto[BaudRate9600]	freqs[100]	155	1			T240	3		T124	3		T315	1
auto[BaudRate115200]	freqs[24]	180	1			T7	19		T21	1		T132	1
auto[BaudRate115200]	freqs[25]	195	1			T10	1		T292	1		T166	1
auto[BaudRate115200]	freqs[48]	124	1			T284	1		T268	1		T314	6
auto[BaudRate115200]	freqs[50]	100	1			T4	2		T167	1		T106	3
auto[BaudRate115200]	freqs[100]	150	1			T257	1		T240	1		T124	4
auto[BaudRate230400]	freqs[24]	165	1			T7	8		T21	2		T132	1
auto[BaudRate230400]	freqs[25]	210	1			T10	2		T292	1		T166	1
auto[BaudRate230400]	freqs[48]	117	1			T20	2		T284	2		T268	1
auto[BaudRate230400]	freqs[50]	152	1			T4	1		T167	2		T106	4
auto[BaudRate230400]	freqs[100]	138	1			T315	2		T271	1		T31	1
auto[BaudRate128Kbps]	freqs[24]	180	1			T7	8		T33	3		T21	2
auto[BaudRate128Kbps]	freqs[25]	178	1			T10	2		T166	2		T57	1
auto[BaudRate128Kbps]	freqs[48]	101	1			T20	1		T268	1		T314	6
auto[BaudRate128Kbps]	freqs[50]	120	1			T4	1		T167	1		T106	1
auto[BaudRate128Kbps]	freqs[100]	132	1			T240	1		T124	2		T271	1
auto[BaudRate256Kbps]	freqs[24]	181	1			T7	5		T33	1		T21	3
auto[BaudRate256Kbps]	freqs[25]	239	1			T10	1		T57	2		T129	5
auto[BaudRate256Kbps]	freqs[48]	124	1			T284	2		T268	2		T314	6
auto[BaudRate256Kbps]	freqs[50]	118	1			T4	1		T149	2		T247	14
auto[BaudRate256Kbps]	freqs[100]	162	1			T257	1		T240	1		T124	1
auto[BaudRate1Mbps]	freqs[24]	215	1			T7	13		T33	2		T132	3
auto[BaudRate1Mbps]	freqs[25]	216	1			T10	3		T166	2		T57	1
auto[BaudRate1Mbps]	freqs[48]	109	1			T20	1		T284	2		T268	1
auto[BaudRate1Mbps]	freqs[50]	99	1			T4	1		T106	2		T149	1
auto[BaudRate1Mbps]	freqs[100]	160	1			T240	1		T315	2		T271	1
auto[BaudRate1p5Mbps]	freqs[25]	141	1			T10	1		T166	2		T57	1
auto[BaudRate1p5Mbps]	freqs[48]	104	1			T268	1		T314	9		T316	1
auto[BaudRate1p5Mbps]	freqs[50]	109	1			T4	2		T106	1		T149	1
auto[BaudRate1p5Mbps]	freqs[100]	116	1			T271	1		T279	1		T31	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded