Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.46	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	5	125	96.15

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	5	125	96.15	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	31571646	1			T1	215985		T2	12		T3	94
all_levels[1]	200201	1			T1	286		T2	4		T5	14
all_levels[2]	2187	1			T1	5		T2	3		T4	1
all_levels[3]	949	1			T1	2		T2	1		T4	2
all_levels[4]	704	1			T2	2		T4	1		T5	1
all_levels[5]	514	1			T1	1		T5	2		T9	1
all_levels[6]	374	1			T2	4		T6	1		T7	3
all_levels[7]	347	1			T2	2		T4	1		T7	2
all_levels[8]	279	1			T7	2		T33	1		T109	1
all_levels[9]	283	1			T5	1		T6	1		T7	1
all_levels[10]	177	1			T4	1		T72	1		T16	1
all_levels[11]	171	1			T118	1		T119	1		T13	4
all_levels[12]	147	1			T4	1		T9	1		T33	3
all_levels[13]	139	1			T120	1		T53	1		T121	1
all_levels[14]	123	1			T4	1		T9	1		T111	1
all_levels[15]	137	1			T9	1		T111	2		T120	1
all_levels[16]	100	1			T9	2		T72	1		T111	1
all_levels[17]	84	1			T7	1		T121	1		T122	1
all_levels[18]	106	1			T1	2		T72	1		T19	1
all_levels[19]	92	1			T123	1		T13	1		T53	2
all_levels[20]	83	1			T20	1		T111	1		T120	1
all_levels[21]	70	1			T121	1		T124	1		T125	1
all_levels[22]	72	1			T10	1		T20	1		T33	1
all_levels[23]	71	1			T7	1		T109	1		T19	1
all_levels[24]	67	1			T5	1		T13	1		T126	1
all_levels[25]	56	1			T5	4		T111	1		T127	1
all_levels[26]	53	1			T127	1		T128	1		T113	2
all_levels[27]	39	1			T129	1		T130	2		T131	1
all_levels[28]	58	1			T5	1		T72	1		T21	1
all_levels[29]	47	1			T20	1		T132	1		T102	1
all_levels[30]	42	1			T19	1		T133	1		T134	1
all_levels[31]	39	1			T21	1		T13	1		T19	1
all_levels[32]	22	1			T129	1		T130	2		T135	4
all_levels[33]	52	1			T109	1		T102	1		T129	1
all_levels[34]	37	1			T19	2		T124	1		T136	1
all_levels[35]	38	1			T7	1		T111	1		T102	2
all_levels[36]	33	1			T5	1		T132	1		T13	1
all_levels[37]	30	1			T4	1		T19	1		T133	1
all_levels[38]	22	1			T33	2		T111	3		T38	1
all_levels[39]	22	1			T19	1		T137	1		T138	1
all_levels[40]	20	1			T129	1		T139	1		T140	3
all_levels[41]	23	1			T7	1		T121	1		T141	1
all_levels[42]	22	1			T20	1		T13	2		T139	1
all_levels[43]	16	1			T133	1		T129	1		T138	2
all_levels[44]	22	1			T55	2		T129	1		T137	1
all_levels[45]	14	1			T128	1		T142	1		T39	1
all_levels[46]	18	1			T109	1		T13	1		T121	1
all_levels[47]	16	1			T9	1		T103	2		T129	1
all_levels[48]	15	1			T9	1		T132	1		T140	1
all_levels[49]	20	1			T34	1		T57	2		T143	1
all_levels[50]	29	1			T13	1		T143	2		T144	1
all_levels[51]	15	1			T126	1		T145	2		T146	2
all_levels[52]	3	1			T147	1		T148	2		-	-
all_levels[53]	15	1			T129	1		T149	1		T150	1
all_levels[54]	13	1			T6	4		T129	1		T130	1
all_levels[55]	9	1			T151	1		T142	1		T152	2
all_levels[56]	8	1			T153	1		T154	1		T40	1
all_levels[57]	9	1			T7	1		T155	1		T156	1
all_levels[58]	8	1			T21	3		T155	1		T157	1
all_levels[59]	6	1			T158	2		T159	1		T160	1
all_levels[60]	9	1			T161	1		T162	1		T156	1
all_levels[61]	6	1			T54	1		T28	1		T163	1
all_levels[62]	10	1			T150	2		T131	1		T40	1
all_levels[63]	13	1			T128	1		T139	1		T164	1
all_levels[64]	107	1			T6	1		T119	1		T109	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31775150

1

T1

216277

T2

20

T3

88

auto[1]

5009

1

T1

4

T2

8

T3

6

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	5	125	96.15	5

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[58] , all_levels[59] , all_levels[60] , all_levels[61]]	[auto[1]]	--	--	4

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	31567127	1			T1	215982		T2	8		T3	88
all_levels[0]	auto[1]	4519	1			T1	3		T2	4		T3	6
all_levels[1]	auto[0]	200119	1			T1	286		T2	3		T5	14
all_levels[1]	auto[1]	82	1			T2	1		T53	1		T102	1
all_levels[2]	auto[0]	2159	1			T1	5		T2	3		T4	1
all_levels[2]	auto[1]	28	1			T6	1		T9	1		T165	1
all_levels[3]	auto[0]	921	1			T1	2		T2	1		T4	2
all_levels[3]	auto[1]	28	1			T166	2		T112	1		T125	1
all_levels[4]	auto[0]	682	1			T2	2		T4	1		T5	1
all_levels[4]	auto[1]	22	1			T119	1		T109	1		T102	1
all_levels[5]	auto[0]	492	1			T1	1		T5	2		T9	1
all_levels[5]	auto[1]	22	1			T167	1		T168	1		T169	1
all_levels[6]	auto[0]	349	1			T2	1		T6	1		T7	3
all_levels[6]	auto[1]	25	1			T2	3		T112	1		T125	1
all_levels[7]	auto[0]	322	1			T2	2		T4	1		T7	2
all_levels[7]	auto[1]	25	1			T111	1		T170	2		T138	2
all_levels[8]	auto[0]	266	1			T7	2		T33	1		T109	1
all_levels[8]	auto[1]	13	1			T53	1		T171	1		T172	1
all_levels[9]	auto[0]	265	1			T5	1		T6	1		T7	1
all_levels[9]	auto[1]	18	1			T173	1		T152	2		T174	1
all_levels[10]	auto[0]	168	1			T4	1		T72	1		T16	1
all_levels[10]	auto[1]	9	1			T175	2		T176	3		T177	1
all_levels[11]	auto[0]	162	1			T118	1		T119	1		T13	4
all_levels[11]	auto[1]	9	1			T178	1		T179	1		T180	1
all_levels[12]	auto[0]	141	1			T4	1		T9	1		T33	1
all_levels[12]	auto[1]	6	1			T33	2		T181	1		T182	2
all_levels[13]	auto[0]	127	1			T120	1		T53	1		T121	1
all_levels[13]	auto[1]	12	1			T122	1		T172	1		T183	1
all_levels[14]	auto[0]	110	1			T4	1		T9	1		T111	1
all_levels[14]	auto[1]	13	1			T184	3		T185	1		T186	1
all_levels[15]	auto[0]	122	1			T9	1		T111	1		T120	1
all_levels[15]	auto[1]	15	1			T111	1		T172	1		T187	1
all_levels[16]	auto[0]	95	1			T9	2		T72	1		T111	1
all_levels[16]	auto[1]	5	1			T188	1		T189	2		T190	1
all_levels[17]	auto[0]	79	1			T7	1		T121	1		T122	1
all_levels[17]	auto[1]	5	1			T131	1		T173	2		T186	1
all_levels[18]	auto[0]	103	1			T1	1		T72	1		T19	1
all_levels[18]	auto[1]	3	1			T1	1		T169	1		T191	1
all_levels[19]	auto[0]	89	1			T123	1		T13	1		T53	2
all_levels[19]	auto[1]	3	1			T192	1		T193	1		T194	1
all_levels[20]	auto[0]	78	1			T20	1		T111	1		T120	1
all_levels[20]	auto[1]	5	1			T170	2		T195	1		T196	1
all_levels[21]	auto[0]	63	1			T121	1		T124	1		T125	1
all_levels[21]	auto[1]	7	1			T150	2		T37	1		T197	3
all_levels[22]	auto[0]	67	1			T10	1		T20	1		T33	1
all_levels[22]	auto[1]	5	1			T198	1		T188	1		T199	1
all_levels[23]	auto[0]	65	1			T7	1		T109	1		T19	1
all_levels[23]	auto[1]	6	1			T195	1		T200	1		T154	3
all_levels[24]	auto[0]	61	1			T5	1		T13	1		T126	1
all_levels[24]	auto[1]	6	1			T140	1		T201	1		T38	1
all_levels[25]	auto[0]	46	1			T5	1		T111	1		T127	1
all_levels[25]	auto[1]	10	1			T5	3		T184	1		T202	2
all_levels[26]	auto[0]	51	1			T127	1		T128	1		T113	2
all_levels[26]	auto[1]	2	1			T203	1		T204	1		-	-
all_levels[27]	auto[0]	37	1			T129	1		T130	2		T131	1
all_levels[27]	auto[1]	2	1			T205	2		-	-		-	-
all_levels[28]	auto[0]	51	1			T5	1		T72	1		T21	1
all_levels[28]	auto[1]	7	1			T126	1		T206	2		T207	1
all_levels[29]	auto[0]	42	1			T20	1		T132	1		T102	1
all_levels[29]	auto[1]	5	1			T208	2		T44	1		T209	2
all_levels[30]	auto[0]	38	1			T19	1		T133	1		T134	1
all_levels[30]	auto[1]	4	1			T210	1		T211	1		T212	1
all_levels[31]	auto[0]	35	1			T21	1		T13	1		T19	1
all_levels[31]	auto[1]	4	1			T38	2		T190	1		T213	1
all_levels[32]	auto[0]	19	1			T129	1		T130	2		T135	1
all_levels[32]	auto[1]	3	1			T135	3		-	-		-	-
all_levels[33]	auto[0]	49	1			T109	1		T102	1		T129	1
all_levels[33]	auto[1]	3	1			T214	1		T215	2		-	-
all_levels[34]	auto[0]	35	1			T19	2		T124	1		T136	1
all_levels[34]	auto[1]	2	1			T137	2		-	-		-	-
all_levels[35]	auto[0]	32	1			T7	1		T111	1		T102	1
all_levels[35]	auto[1]	6	1			T102	1		T216	1		T217	1
all_levels[36]	auto[0]	30	1			T5	1		T132	1		T13	1
all_levels[36]	auto[1]	3	1			T200	1		T218	1		T219	1
all_levels[37]	auto[0]	29	1			T4	1		T19	1		T133	1
all_levels[37]	auto[1]	1	1			T220	1		-	-		-	-
all_levels[38]	auto[0]	16	1			T33	1		T111	1		T38	1
all_levels[38]	auto[1]	6	1			T33	1		T111	2		T221	2
all_levels[39]	auto[0]	21	1			T19	1		T137	1		T138	1
all_levels[39]	auto[1]	1	1			T222	1		-	-		-	-
all_levels[40]	auto[0]	18	1			T129	1		T139	1		T140	1
all_levels[40]	auto[1]	2	1			T140	2		-	-		-	-
all_levels[41]	auto[0]	22	1			T7	1		T121	1		T141	1
all_levels[41]	auto[1]	1	1			T221	1		-	-		-	-
all_levels[42]	auto[0]	20	1			T20	1		T13	2		T139	1
all_levels[42]	auto[1]	2	1			T223	1		T224	1		-	-
all_levels[43]	auto[0]	14	1			T133	1		T129	1		T138	1
all_levels[43]	auto[1]	2	1			T138	1		T225	1		-	-
all_levels[44]	auto[0]	19	1			T55	1		T129	1		T137	1
all_levels[44]	auto[1]	3	1			T55	1		T226	1		T227	1
all_levels[45]	auto[0]	14	1			T128	1		T142	1		T39	1
all_levels[46]	auto[0]	17	1			T109	1		T13	1		T121	1
all_levels[46]	auto[1]	1	1			T228	1		-	-		-	-
all_levels[47]	auto[0]	15	1			T9	1		T103	1		T129	1
all_levels[47]	auto[1]	1	1			T103	1		-	-		-	-
all_levels[48]	auto[0]	13	1			T9	1		T132	1		T140	1
all_levels[48]	auto[1]	2	1			T229	1		T230	1		-	-
all_levels[49]	auto[0]	18	1			T34	1		T57	1		T143	1
all_levels[49]	auto[1]	2	1			T57	1		T187	1		-	-
all_levels[50]	auto[0]	22	1			T13	1		T143	2		T144	1
all_levels[50]	auto[1]	7	1			T231	1		T232	1		T182	1
all_levels[51]	auto[0]	13	1			T126	1		T145	1		T146	1
all_levels[51]	auto[1]	2	1			T145	1		T146	1		-	-
all_levels[52]	auto[0]	2	1			T147	1		T148	1		-	-
all_levels[52]	auto[1]	1	1			T148	1		-	-		-	-
all_levels[53]	auto[0]	11	1			T129	1		T149	1		T150	1
all_levels[53]	auto[1]	4	1			T233	4		-	-		-	-
all_levels[54]	auto[0]	11	1			T6	3		T129	1		T130	1
all_levels[54]	auto[1]	2	1			T6	1		T234	1		-	-
all_levels[55]	auto[0]	8	1			T151	1		T142	1		T152	1
all_levels[55]	auto[1]	1	1			T152	1		-	-		-	-
all_levels[56]	auto[0]	7	1			T153	1		T154	1		T40	1
all_levels[56]	auto[1]	1	1			T235	1		-	-		-	-
all_levels[57]	auto[0]	6	1			T7	1		T155	1		T156	1
all_levels[57]	auto[1]	3	1			T236	1		T237	2		-	-
all_levels[58]	auto[0]	8	1			T21	3		T155	1		T157	1
all_levels[59]	auto[0]	6	1			T158	2		T159	1		T160	1
all_levels[60]	auto[0]	9	1			T161	1		T162	1		T156	1
all_levels[61]	auto[0]	6	1			T54	1		T28	1		T163	1
all_levels[62]	auto[0]	9	1			T150	1		T131	1		T40	1
all_levels[62]	auto[1]	1	1			T150	1		-	-		-	-
all_levels[63]	auto[0]	12	1			T128	1		T139	1		T164	1
all_levels[63]	auto[1]	1	1			T190	1		-	-		-	-
all_levels[64]	auto[0]	87	1			T6	1		T119	1		T109	1
all_levels[64]	auto[1]	20	1			T123	1		T128	1		T137	1