Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	111664	1			T1	578		T2	7		T3	22
all_pins[1]	111664	1			T1	578		T2	7		T3	22
all_pins[2]	111664	1			T1	578		T2	7		T3	22
all_pins[3]	111664	1			T1	578		T2	7		T3	22
all_pins[4]	111664	1			T1	578		T2	7		T3	22
all_pins[5]	111664	1			T1	578		T2	7		T3	22
all_pins[6]	111664	1			T1	578		T2	7		T3	22
all_pins[7]	111664	1			T1	578		T2	7		T3	22
all_pins[8]	111664	1			T1	578		T2	7		T3	22

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	959923	1			T1	4818		T2	57		T3	173
values[0x1]	45053	1			T1	384		T2	6		T3	25
transitions[0x0=>0x1]	36076	1			T1	287		T2	5		T3	23
transitions[0x1=>0x0]	35886	1			T1	287		T2	5		T3	23

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89163	1			T1	299		T2	5		T4	27
all_pins[0]	values[0x1]	22501	1			T1	279		T2	2		T3	22
all_pins[0]	transitions[0x0=>0x1]	21854	1			T1	277		T2	2		T3	22
all_pins[0]	transitions[0x1=>0x0]	1013	1			T111	3		T109	15		T14	1
all_pins[1]	values[0x0]	110004	1			T1	576		T2	7		T3	22
all_pins[1]	values[0x1]	1660	1			T1	2		T5	2		T6	1
all_pins[1]	transitions[0x0=>0x1]	1547	1			T5	2		T6	1		T7	2
all_pins[1]	transitions[0x1=>0x0]	2415	1			T1	7		T4	7		T5	5
all_pins[2]	values[0x0]	109136	1			T1	569		T2	7		T3	22
all_pins[2]	values[0x1]	2528	1			T1	9		T4	7		T5	5
all_pins[2]	transitions[0x0=>0x1]	2475	1			T1	9		T4	7		T5	5
all_pins[2]	transitions[0x1=>0x0]	216	1			T2	1		T7	2		T111	1
all_pins[3]	values[0x0]	111395	1			T1	578		T2	6		T3	22
all_pins[3]	values[0x1]	269	1			T2	1		T7	3		T111	1
all_pins[3]	transitions[0x0=>0x1]	225	1			T2	1		T111	1		T109	3
all_pins[3]	transitions[0x1=>0x0]	429	1			T5	1		T7	1		T15	1
all_pins[4]	values[0x0]	111191	1			T1	578		T2	7		T3	22
all_pins[4]	values[0x1]	473	1			T5	1		T7	4		T15	1
all_pins[4]	transitions[0x0=>0x1]	390	1			T5	1		T7	3		T15	1
all_pins[4]	transitions[0x1=>0x0]	163	1			T7	1		T15	2		T110	2
all_pins[5]	values[0x0]	111418	1			T1	578		T2	7		T3	22
all_pins[5]	values[0x1]	246	1			T7	2		T15	2		T16	2
all_pins[5]	transitions[0x0=>0x1]	199	1			T7	2		T15	2		T16	2
all_pins[5]	transitions[0x1=>0x0]	742	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x0]	110875	1			T1	577		T2	6		T3	21
all_pins[6]	values[0x1]	789	1			T1	1		T2	1		T3	1
all_pins[6]	transitions[0x0=>0x1]	750	1			T1	1		T2	1		T3	1
all_pins[6]	transitions[0x1=>0x0]	258	1			T5	3		T7	3		T110	2
all_pins[7]	values[0x0]	111367	1			T1	578		T2	7		T3	22
all_pins[7]	values[0x1]	297	1			T5	3		T7	4		T110	2
all_pins[7]	transitions[0x0=>0x1]	198	1			T5	2		T7	4		T110	2
all_pins[7]	transitions[0x1=>0x0]	16191	1			T1	93		T2	2		T3	2
all_pins[8]	values[0x0]	95374	1			T1	485		T2	5		T3	20
all_pins[8]	values[0x1]	16290	1			T1	93		T2	2		T3	2
all_pins[8]	transitions[0x0=>0x1]	8438	1			T2	1		T4	8		T5	2
all_pins[8]	transitions[0x1=>0x0]	14459	1			T1	186		T2	1		T3	20