Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	8988491	1			T1	36612		T2	26		T3	6
all_levels[1]	1591095	1			T1	40777		T3	86		T4	7
all_levels[2]	263269	1			T1	1282		T4	13		T5	10
all_levels[3]	223278	1			T1	1287		T5	4		T7	14
all_levels[4]	474424	1			T1	1284		T7	23		T9	9
all_levels[5]	262874	1			T1	1253		T4	2		T7	9
all_levels[6]	261832	1			T1	1290		T2	1		T4	2
all_levels[7]	376416	1			T1	1283		T4	8		T5	30
all_levels[8]	399117	1			T1	1281		T5	20		T7	7
all_levels[9]	215652	1			T1	1265		T5	17		T6	1
all_levels[10]	250377	1			T1	1274		T4	3		T5	9
all_levels[11]	234496	1			T1	1251		T4	14		T5	25
all_levels[12]	199656	1			T1	1283		T4	19		T5	12
all_levels[13]	359497	1			T1	1287		T4	1		T5	14
all_levels[14]	215837	1			T1	1284		T4	9		T5	24
all_levels[15]	424890	1			T1	1271		T4	1		T5	38
all_levels[16]	258929	1			T1	1279		T5	26		T7	4
all_levels[17]	231598	1			T1	1278		T7	4		T9	4
all_levels[18]	198121	1			T1	1282		T7	6		T9	4
all_levels[19]	225564	1			T1	1283		T4	4		T6	5
all_levels[20]	223440	1			T1	1281		T7	5		T9	7
all_levels[21]	249600	1			T1	1291		T7	4		T9	6
all_levels[22]	262531	1			T1	1281		T5	1		T7	5
all_levels[23]	205572	1			T1	1224		T5	1		T7	7
all_levels[24]	239734	1			T1	1228		T7	6		T22	2131
all_levels[25]	284471	1			T1	1230		T7	2		T22	2135
all_levels[26]	300833	1			T1	1230		T7	5		T22	2144
all_levels[27]	211798	1			T1	1114		T5	1		T7	11
all_levels[28]	158989	1			T1	479		T7	3		T22	2143
all_levels[29]	471355	1			T1	480		T7	5		T22	2134
all_levels[30]	173158	1			T1	481		T7	3		T22	2133
all_levels[31]	561631	1			T1	3367		T7	94		T20	2
all_levels[32]	12781163	1			T1	101212		T4	22		T5	14

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31775150

1

T1

216277

T2

20

T3

88

auto[1]

4538

1

T1

7

T2

7

T3

4

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	8985875	1			T1	36607		T2	19		T3	4
all_levels[0]	auto[1]	2616	1			T1	5		T2	7		T3	2
all_levels[1]	auto[0]	1590811	1			T1	40777		T3	84		T4	7
all_levels[1]	auto[1]	284	1			T3	2		T6	1		T33	1
all_levels[2]	auto[0]	263243	1			T1	1282		T4	13		T5	10
all_levels[2]	auto[1]	26	1			T9	2		T112	1		T195	1
all_levels[3]	auto[0]	223090	1			T1	1287		T5	3		T7	14
all_levels[3]	auto[1]	188	1			T5	1		T292	18		T167	1
all_levels[4]	auto[0]	474390	1			T1	1284		T7	23		T9	9
all_levels[4]	auto[1]	34	1			T109	2		T126	2		T315	1
all_levels[5]	auto[0]	262849	1			T1	1253		T4	2		T7	9
all_levels[5]	auto[1]	25	1			T53	1		T35	1		T263	1
all_levels[6]	auto[0]	261801	1			T1	1290		T2	1		T4	2
all_levels[6]	auto[1]	31	1			T125	1		T140	2		T308	1
all_levels[7]	auto[0]	376264	1			T1	1283		T4	8		T5	30
all_levels[7]	auto[1]	152	1			T34	1		T57	1		T279	2
all_levels[8]	auto[0]	399080	1			T1	1281		T5	20		T7	7
all_levels[8]	auto[1]	37	1			T124	1		T319	1		T320	1
all_levels[9]	auto[0]	215625	1			T1	1264		T5	17		T6	1
all_levels[9]	auto[1]	27	1			T1	1		T54	2		T216	1
all_levels[10]	auto[0]	250357	1			T1	1274		T4	3		T5	9
all_levels[10]	auto[1]	20	1			T270	1		T96	1		T321	1
all_levels[11]	auto[0]	234473	1			T1	1251		T4	14		T5	25
all_levels[11]	auto[1]	23	1			T111	1		T137	1		T171	1
all_levels[12]	auto[0]	199642	1			T1	1283		T4	19		T5	12
all_levels[12]	auto[1]	14	1			T283	1		T266	1		T168	1
all_levels[13]	auto[0]	359471	1			T1	1287		T4	1		T5	14
all_levels[13]	auto[1]	26	1			T7	2		T103	1		T248	2
all_levels[14]	auto[0]	215817	1			T1	1284		T4	9		T5	23
all_levels[14]	auto[1]	20	1			T5	1		T22	1		T126	1
all_levels[15]	auto[0]	424792	1			T1	1271		T4	1		T5	38
all_levels[15]	auto[1]	98	1			T15	4		T136	1		T268	1
all_levels[16]	auto[0]	258898	1			T1	1279		T5	26		T7	4
all_levels[16]	auto[1]	31	1			T284	1		T135	1		T142	1
all_levels[17]	auto[0]	231578	1			T1	1278		T7	4		T9	4
all_levels[17]	auto[1]	20	1			T130	1		T248	1		T322	2
all_levels[18]	auto[0]	198096	1			T1	1282		T7	6		T9	4
all_levels[18]	auto[1]	25	1			T119	1		T103	1		T128	1
all_levels[19]	auto[0]	225531	1			T1	1283		T4	4		T6	2
all_levels[19]	auto[1]	33	1			T6	3		T166	3		T16	1
all_levels[20]	auto[0]	223426	1			T1	1281		T7	5		T9	7
all_levels[20]	auto[1]	14	1			T216	2		T204	1		T323	1
all_levels[21]	auto[0]	249580	1			T1	1291		T7	4		T9	6
all_levels[21]	auto[1]	20	1			T111	1		T261	1		T296	1
all_levels[22]	auto[0]	262513	1			T1	1281		T5	1		T7	5
all_levels[22]	auto[1]	18	1			T16	2		T259	4		T279	2
all_levels[23]	auto[0]	205552	1			T1	1224		T5	1		T7	7
all_levels[23]	auto[1]	20	1			T125	1		T38	1		T324	1
all_levels[24]	auto[0]	239718	1			T1	1228		T7	6		T22	2131
all_levels[24]	auto[1]	16	1			T170	1		T124	1		T279	1
all_levels[25]	auto[0]	284449	1			T1	1230		T7	2		T22	2135
all_levels[25]	auto[1]	22	1			T35	2		T136	2		T315	4
all_levels[26]	auto[0]	300825	1			T1	1230		T7	5		T22	2144
all_levels[26]	auto[1]	8	1			T123	1		T178	1		T325	1
all_levels[27]	auto[0]	211775	1			T1	1114		T5	1		T7	11
all_levels[27]	auto[1]	23	1			T35	1		T217	1		T140	1
all_levels[28]	auto[0]	158972	1			T1	479		T7	3		T22	2143
all_levels[28]	auto[1]	17	1			T145	1		T305	2		T326	4
all_levels[29]	auto[0]	471339	1			T1	480		T7	5		T22	2134
all_levels[29]	auto[1]	16	1			T140	1		T327	1		T328	2
all_levels[30]	auto[0]	173142	1			T1	481		T7	3		T22	2133
all_levels[30]	auto[1]	16	1			T122	1		T329	1		T330	1
all_levels[31]	auto[0]	561623	1			T1	3367		T7	94		T20	2
all_levels[31]	auto[1]	8	1			T162	1		T326	4		T331	1
all_levels[32]	auto[0]	12780553	1			T1	101211		T4	22		T5	10
all_levels[32]	auto[1]	610	1			T1	1		T5	4		T7	1