Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	763	1			T5	8		T7	15		T14	4
all_values[1]	763	1			T5	8		T7	15		T14	4
all_values[2]	763	1			T5	8		T7	15		T14	4
all_values[3]	763	1			T5	8		T7	15		T14	4
all_values[4]	763	1			T5	8		T7	15		T14	4
all_values[5]	763	1			T5	8		T7	15		T14	4
all_values[6]	763	1			T5	8		T7	15		T14	4
all_values[7]	763	1			T5	8		T7	15		T14	4
all_values[8]	763	1			T5	8		T7	15		T14	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3731

1

T5

41

T7

79

T14

26

auto[1]

3136

1

T5

31

T7

56

T14

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2248

1

T5

29

T7

52

T14

6

auto[1]

4619

1

T5

43

T7

83

T14

30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4112

1

T5

47

T7

90

T14

19

auto[1]

2755

1

T5

25

T7

45

T14

17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	239	1			T5	3		T7	8		T14	4
all_values[0]	auto[0]	auto[1]	auto[1]	217	1			T5	2		T7	1		T32	1
all_values[0]	auto[1]	auto[0]	auto[1]	166	1			T7	3		T32	4		T37	4
all_values[0]	auto[1]	auto[1]	auto[1]	141	1			T5	3		T7	3		T32	1
all_values[1]	auto[0]	auto[0]	auto[0]	240	1			T5	1		T7	3		T14	1
all_values[1]	auto[0]	auto[1]	auto[0]	202	1			T5	3		T7	5		T14	2
all_values[1]	auto[1]	auto[0]	auto[1]	189	1			T5	4		T7	6		T14	1
all_values[1]	auto[1]	auto[1]	auto[1]	132	1			T7	1		T37	2		T95	1
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T5	5		T7	4		T14	1
all_values[2]	auto[0]	auto[0]	auto[1]	77	1			T14	1		T32	1		T95	1
all_values[2]	auto[0]	auto[1]	auto[0]	134	1			T5	3		T7	5		T32	1
all_values[2]	auto[0]	auto[1]	auto[1]	88	1			T7	3		T96	2		T97	3
all_values[2]	auto[1]	auto[0]	auto[1]	156	1			T7	1		T14	1		T32	4
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T7	2		T14	1		T32	1
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T7	2		T32	2		T37	2
all_values[3]	auto[0]	auto[0]	auto[1]	83	1			T5	2		T7	2		T14	1
all_values[3]	auto[0]	auto[1]	auto[0]	134	1			T5	3		T7	4		T37	3
all_values[3]	auto[0]	auto[1]	auto[1]	68	1			T7	2		T32	1		T37	1
all_values[3]	auto[1]	auto[0]	auto[1]	179	1			T5	3		T7	2		T14	3
all_values[3]	auto[1]	auto[1]	auto[1]	129	1			T7	3		T32	2		T37	1
all_values[4]	auto[0]	auto[0]	auto[0]	159	1			T5	1		T7	6		T14	1
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T5	1		T7	1		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T5	3		T32	3		T96	1
all_values[4]	auto[0]	auto[1]	auto[1]	89	1			T7	1		T32	2		T95	1
all_values[4]	auto[1]	auto[0]	auto[1]	172	1			T5	2		T7	2		T14	2
all_values[4]	auto[1]	auto[1]	auto[1]	135	1			T5	1		T7	5		T37	1
all_values[5]	auto[0]	auto[0]	auto[0]	163	1			T5	1		T7	4		T32	3
all_values[5]	auto[0]	auto[0]	auto[1]	77	1			T7	6		T14	1		T32	1
all_values[5]	auto[0]	auto[1]	auto[0]	140	1			T5	5		T32	3		T37	2
all_values[5]	auto[0]	auto[1]	auto[1]	77	1			T7	1		T96	1		T97	1
all_values[5]	auto[1]	auto[0]	auto[1]	164	1			T5	2		T7	4		T14	2
all_values[5]	auto[1]	auto[1]	auto[1]	142	1			T14	1		T32	2		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	164	1			T5	2		T7	6		T14	1
all_values[6]	auto[0]	auto[0]	auto[1]	84	1			T5	1		T7	1		T32	1
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T7	6		T32	1		T95	1
all_values[6]	auto[0]	auto[1]	auto[1]	84	1			T5	2		T14	1		T32	1
all_values[6]	auto[1]	auto[0]	auto[1]	148	1			T5	2		T7	1		T14	1
all_values[6]	auto[1]	auto[1]	auto[1]	147	1			T5	1		T7	1		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T7	3		T32	2		T37	3
all_values[7]	auto[0]	auto[0]	auto[1]	85	1			T5	1		T7	2		T14	1
all_values[7]	auto[0]	auto[1]	auto[0]	144	1			T5	2		T7	4		T32	1
all_values[7]	auto[0]	auto[1]	auto[1]	62	1			T5	1		T7	3		T32	4
all_values[7]	auto[1]	auto[0]	auto[1]	177	1			T5	3		T7	1		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	119	1			T5	1		T7	2		T14	1
all_values[8]	auto[0]	auto[0]	auto[1]	268	1			T5	4		T7	4		T14	1
all_values[8]	auto[0]	auto[1]	auto[1]	193	1			T5	1		T7	3		T14	2
all_values[8]	auto[1]	auto[0]	auto[1]	171	1			T5	3		T7	7		T32	3
all_values[8]	auto[1]	auto[1]	auto[1]	131	1			T7	1		T14	1		T32	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal