Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.13 99.10 97.65 100.00 98.38 100.00 99.66


Total test records in report: 1317
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T1255 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4052898941 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:00 PM PDT 24 82746823 ps
T79 /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3431429532 Aug 02 05:22:15 PM PDT 24 Aug 02 05:22:17 PM PDT 24 429981630 ps
T1256 /workspace/coverage/cover_reg_top/15.uart_intr_test.3902699995 Aug 02 05:22:12 PM PDT 24 Aug 02 05:22:13 PM PDT 24 17339977 ps
T1257 /workspace/coverage/cover_reg_top/46.uart_intr_test.3289278038 Aug 02 05:22:20 PM PDT 24 Aug 02 05:22:20 PM PDT 24 14847481 ps
T1258 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3958460530 Aug 02 05:22:12 PM PDT 24 Aug 02 05:22:13 PM PDT 24 32563836 ps
T1259 /workspace/coverage/cover_reg_top/14.uart_tl_errors.3500864703 Aug 02 05:22:13 PM PDT 24 Aug 02 05:22:15 PM PDT 24 383102146 ps
T1260 /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1262444342 Aug 02 05:21:57 PM PDT 24 Aug 02 05:21:59 PM PDT 24 34539936 ps
T1261 /workspace/coverage/cover_reg_top/26.uart_intr_test.3853244190 Aug 02 05:22:21 PM PDT 24 Aug 02 05:22:21 PM PDT 24 12913040 ps
T1262 /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1130134988 Aug 02 05:22:04 PM PDT 24 Aug 02 05:22:06 PM PDT 24 1044269609 ps
T1263 /workspace/coverage/cover_reg_top/10.uart_intr_test.4267163614 Aug 02 05:22:17 PM PDT 24 Aug 02 05:22:18 PM PDT 24 41062334 ps
T1264 /workspace/coverage/cover_reg_top/10.uart_tl_errors.3962165007 Aug 02 05:22:13 PM PDT 24 Aug 02 05:22:14 PM PDT 24 35775300 ps
T1265 /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2717944568 Aug 02 05:22:09 PM PDT 24 Aug 02 05:22:10 PM PDT 24 57269350 ps
T1266 /workspace/coverage/cover_reg_top/5.uart_intr_test.4293424400 Aug 02 05:22:08 PM PDT 24 Aug 02 05:22:09 PM PDT 24 15737655 ps
T1267 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2961434807 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:01 PM PDT 24 48895301 ps
T1268 /workspace/coverage/cover_reg_top/10.uart_csr_rw.1632122517 Aug 02 05:22:12 PM PDT 24 Aug 02 05:22:13 PM PDT 24 43105021 ps
T1269 /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1903317069 Aug 02 05:22:04 PM PDT 24 Aug 02 05:22:05 PM PDT 24 29763356 ps
T1270 /workspace/coverage/cover_reg_top/16.uart_intr_test.4012814972 Aug 02 05:22:14 PM PDT 24 Aug 02 05:22:15 PM PDT 24 16354169 ps
T1271 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.711353215 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:00 PM PDT 24 24544585 ps
T1272 /workspace/coverage/cover_reg_top/28.uart_intr_test.3768138830 Aug 02 05:22:19 PM PDT 24 Aug 02 05:22:20 PM PDT 24 36416454 ps
T1273 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3067140690 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:01 PM PDT 24 15596596 ps
T1274 /workspace/coverage/cover_reg_top/4.uart_intr_test.1916607721 Aug 02 05:22:09 PM PDT 24 Aug 02 05:22:09 PM PDT 24 20390907 ps
T1275 /workspace/coverage/cover_reg_top/24.uart_intr_test.1586649659 Aug 02 05:22:21 PM PDT 24 Aug 02 05:22:22 PM PDT 24 30427818 ps
T1276 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1305767803 Aug 02 05:22:14 PM PDT 24 Aug 02 05:22:15 PM PDT 24 16973097 ps
T1277 /workspace/coverage/cover_reg_top/34.uart_intr_test.2832716734 Aug 02 05:22:24 PM PDT 24 Aug 02 05:22:25 PM PDT 24 27457484 ps
T1278 /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1218088909 Aug 02 05:22:15 PM PDT 24 Aug 02 05:22:16 PM PDT 24 87545696 ps
T1279 /workspace/coverage/cover_reg_top/38.uart_intr_test.1169689945 Aug 02 05:22:21 PM PDT 24 Aug 02 05:22:22 PM PDT 24 41474175 ps
T1280 /workspace/coverage/cover_reg_top/14.uart_csr_rw.2896628157 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 37644368 ps
T1281 /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.76303938 Aug 02 05:22:06 PM PDT 24 Aug 02 05:22:07 PM PDT 24 81728697 ps
T1282 /workspace/coverage/cover_reg_top/41.uart_intr_test.2193528371 Aug 02 05:22:26 PM PDT 24 Aug 02 05:22:27 PM PDT 24 14481083 ps
T1283 /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.642455545 Aug 02 05:22:08 PM PDT 24 Aug 02 05:22:09 PM PDT 24 16434393 ps
T1284 /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1542486097 Aug 02 05:22:08 PM PDT 24 Aug 02 05:22:10 PM PDT 24 88220792 ps
T1285 /workspace/coverage/cover_reg_top/13.uart_tl_errors.2694316674 Aug 02 05:22:11 PM PDT 24 Aug 02 05:22:13 PM PDT 24 71940522 ps
T1286 /workspace/coverage/cover_reg_top/45.uart_intr_test.2295288714 Aug 02 05:22:21 PM PDT 24 Aug 02 05:22:22 PM PDT 24 14843637 ps
T1287 /workspace/coverage/cover_reg_top/14.uart_intr_test.2494582301 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 23777211 ps
T1288 /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1282288885 Aug 02 05:22:19 PM PDT 24 Aug 02 05:22:20 PM PDT 24 336552156 ps
T50 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1812667594 Aug 02 05:22:00 PM PDT 24 Aug 02 05:22:01 PM PDT 24 31944885 ps
T1289 /workspace/coverage/cover_reg_top/40.uart_intr_test.2715502984 Aug 02 05:22:22 PM PDT 24 Aug 02 05:22:23 PM PDT 24 17695570 ps
T51 /workspace/coverage/cover_reg_top/7.uart_csr_rw.190832182 Aug 02 05:22:14 PM PDT 24 Aug 02 05:22:14 PM PDT 24 57928982 ps
T1290 /workspace/coverage/cover_reg_top/8.uart_csr_rw.469414762 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 30701496 ps
T1291 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1862789033 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 239393877 ps
T1292 /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2262154237 Aug 02 05:22:12 PM PDT 24 Aug 02 05:22:13 PM PDT 24 131930780 ps
T1293 /workspace/coverage/cover_reg_top/20.uart_intr_test.4230653347 Aug 02 05:22:26 PM PDT 24 Aug 02 05:22:26 PM PDT 24 39840834 ps
T1294 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.359123582 Aug 02 05:22:05 PM PDT 24 Aug 02 05:22:05 PM PDT 24 34901957 ps
T1295 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2378748676 Aug 02 05:22:15 PM PDT 24 Aug 02 05:22:16 PM PDT 24 47303763 ps
T1296 /workspace/coverage/cover_reg_top/3.uart_tl_errors.2051246956 Aug 02 05:22:06 PM PDT 24 Aug 02 05:22:08 PM PDT 24 70621076 ps
T1297 /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1841474179 Aug 02 05:22:20 PM PDT 24 Aug 02 05:22:22 PM PDT 24 260685764 ps
T1298 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1850394276 Aug 02 05:21:59 PM PDT 24 Aug 02 05:22:01 PM PDT 24 237841224 ps
T1299 /workspace/coverage/cover_reg_top/11.uart_csr_rw.3191877701 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 47872372 ps
T1300 /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1740134969 Aug 02 05:22:12 PM PDT 24 Aug 02 05:22:13 PM PDT 24 19707091 ps
T1301 /workspace/coverage/cover_reg_top/48.uart_intr_test.2188104959 Aug 02 05:22:20 PM PDT 24 Aug 02 05:22:21 PM PDT 24 13497556 ps
T1302 /workspace/coverage/cover_reg_top/17.uart_intr_test.1118303972 Aug 02 05:22:17 PM PDT 24 Aug 02 05:22:18 PM PDT 24 77543617 ps
T1303 /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1202703644 Aug 02 05:22:20 PM PDT 24 Aug 02 05:22:21 PM PDT 24 47702722 ps
T1304 /workspace/coverage/cover_reg_top/13.uart_intr_test.2571325702 Aug 02 05:22:17 PM PDT 24 Aug 02 05:22:17 PM PDT 24 36900266 ps
T1305 /workspace/coverage/cover_reg_top/25.uart_intr_test.3770379913 Aug 02 05:22:21 PM PDT 24 Aug 02 05:22:22 PM PDT 24 13118331 ps
T1306 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2920571330 Aug 02 05:22:13 PM PDT 24 Aug 02 05:22:14 PM PDT 24 94824643 ps
T1307 /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3790496728 Aug 02 05:22:22 PM PDT 24 Aug 02 05:22:22 PM PDT 24 12307074 ps
T1308 /workspace/coverage/cover_reg_top/16.uart_csr_rw.3462712710 Aug 02 05:22:11 PM PDT 24 Aug 02 05:22:12 PM PDT 24 24311833 ps
T1309 /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1747121133 Aug 02 05:22:16 PM PDT 24 Aug 02 05:22:17 PM PDT 24 49841450 ps
T1310 /workspace/coverage/cover_reg_top/18.uart_csr_rw.3095294362 Aug 02 05:22:27 PM PDT 24 Aug 02 05:22:28 PM PDT 24 13832154 ps
T1311 /workspace/coverage/cover_reg_top/36.uart_intr_test.2016154783 Aug 02 05:22:24 PM PDT 24 Aug 02 05:22:24 PM PDT 24 33713101 ps
T1312 /workspace/coverage/cover_reg_top/33.uart_intr_test.1937752399 Aug 02 05:22:28 PM PDT 24 Aug 02 05:22:28 PM PDT 24 52098989 ps
T1313 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2900902380 Aug 02 05:22:11 PM PDT 24 Aug 02 05:22:12 PM PDT 24 43036168 ps
T1314 /workspace/coverage/cover_reg_top/18.uart_tl_errors.548678058 Aug 02 05:22:14 PM PDT 24 Aug 02 05:22:16 PM PDT 24 400609997 ps
T52 /workspace/coverage/cover_reg_top/0.uart_csr_rw.636861669 Aug 02 05:21:58 PM PDT 24 Aug 02 05:21:58 PM PDT 24 11701464 ps
T1315 /workspace/coverage/cover_reg_top/9.uart_intr_test.3257847158 Aug 02 05:22:14 PM PDT 24 Aug 02 05:22:15 PM PDT 24 29079155 ps
T1316 /workspace/coverage/cover_reg_top/8.uart_intr_test.2029949608 Aug 02 05:22:13 PM PDT 24 Aug 02 05:22:14 PM PDT 24 11387016 ps
T1317 /workspace/coverage/cover_reg_top/19.uart_csr_rw.3827639353 Aug 02 05:22:23 PM PDT 24 Aug 02 05:22:24 PM PDT 24 35429052 ps

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2327963141
Short name T7
Test name
Test status
Simulation time 370096065653 ps
CPU time 1123.45 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:54:27 PM PDT 24
Peak memory 224820 kb
Host smart-0dcba2a4-a58e-45d1-81b5-c6e006bfc701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327963141 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2327963141
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.831796967
Short name T13
Test name
Test status
Simulation time 1164952507459 ps
CPU time 551.64 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:44:17 PM PDT 24
Peak memory 216608 kb
Host smart-9d492e41-2d9a-4dcb-b1c6-943796f89145
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831796967 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.831796967
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_stress_all.3742867273
Short name T22
Test name
Test status
Simulation time 152182251512 ps
CPU time 707.34 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:48:03 PM PDT 24
Peak memory 199888 kb
Host smart-574052cc-8a3c-4150-892b-92c02c9522a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742867273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3742867273
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all.507086016
Short name T16
Test name
Test status
Simulation time 193787772385 ps
CPU time 668.04 seconds
Started Aug 02 05:35:28 PM PDT 24
Finished Aug 02 05:46:36 PM PDT 24
Peak memory 208244 kb
Host smart-f9acf08d-ef13-407b-917e-be46dd537fc4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507086016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.507086016
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.2230361984
Short name T19
Test name
Test status
Simulation time 269549954382 ps
CPU time 577.01 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:45:13 PM PDT 24
Peak memory 224760 kb
Host smart-30f86eba-7d44-4c67-b1e1-1ee68c0efcc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230361984 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.2230361984
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.2513147147
Short name T28
Test name
Test status
Simulation time 84088292680 ps
CPU time 1232.28 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:56:35 PM PDT 24
Peak memory 224856 kb
Host smart-cd03ee6b-bf79-4a8f-8df4-0faac976da1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513147147 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.2513147147
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.2994310606
Short name T124
Test name
Test status
Simulation time 327246276654 ps
CPU time 539.1 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:44:20 PM PDT 24
Peak memory 199868 kb
Host smart-a96bcbf8-6491-4ea4-bea1-fec0548fab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994310606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.2994310606
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.993145533
Short name T129
Test name
Test status
Simulation time 291149697475 ps
CPU time 353.16 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 216468 kb
Host smart-3119ebb6-dbb3-49ed-9ac3-5068d7e912aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993145533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.993145533
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_alert_test.2205441335
Short name T8
Test name
Test status
Simulation time 43071326 ps
CPU time 0.54 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 195624 kb
Host smart-eac05e81-a790-47b9-b828-14dd2fe57d16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205441335 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2205441335
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.159832613
Short name T77
Test name
Test status
Simulation time 333924349 ps
CPU time 1.39 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 199880 kb
Host smart-a95356f5-4244-4722-bddd-cc04d30b38a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159832613 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.159832613
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3354872580
Short name T113
Test name
Test status
Simulation time 312098445194 ps
CPU time 324.8 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:41:27 PM PDT 24
Peak memory 200008 kb
Host smart-2febfd97-6ddd-4961-b682-79c73814cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354872580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3354872580
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_intr.2279240123
Short name T15
Test name
Test status
Simulation time 52353819532 ps
CPU time 51.55 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:37:18 PM PDT 24
Peak memory 199972 kb
Host smart-19bc1518-425a-4e9a-b37d-be8616f9dbd5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279240123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.2279240123
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2782879963
Short name T29
Test name
Test status
Simulation time 129609631658 ps
CPU time 1056.89 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:54:04 PM PDT 24
Peak memory 224284 kb
Host smart-889d23ad-ba18-4da3-8060-da7331bea46f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782879963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2782879963
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3730619371
Short name T103
Test name
Test status
Simulation time 251940308319 ps
CPU time 257.99 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:42:31 PM PDT 24
Peak memory 199940 kb
Host smart-363e1d08-3042-4e52-a0ff-9b7a4ec531d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730619371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3730619371
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3683754321
Short name T141
Test name
Test status
Simulation time 317820563456 ps
CPU time 59.55 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:38:04 PM PDT 24
Peak memory 199860 kb
Host smart-b3162b7b-7e3a-4dfa-b320-ab1d406b83e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683754321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3683754321
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_stress_all.638671864
Short name T164
Test name
Test status
Simulation time 212138802503 ps
CPU time 139.6 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 200012 kb
Host smart-ece159b1-03eb-418f-94a0-96f8254ab008
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638671864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.638671864
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_sec_cm.1523195934
Short name T25
Test name
Test status
Simulation time 504929669 ps
CPU time 0.84 seconds
Started Aug 02 05:35:15 PM PDT 24
Finished Aug 02 05:35:16 PM PDT 24
Peak memory 218508 kb
Host smart-03852bf7-5d46-4946-8d52-87aeccee4173
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523195934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.1523195934
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.4216509902
Short name T143
Test name
Test status
Simulation time 248412492442 ps
CPU time 866.1 seconds
Started Aug 02 05:35:19 PM PDT 24
Finished Aug 02 05:49:45 PM PDT 24
Peak memory 216448 kb
Host smart-be9ff032-2c77-4eef-a24e-59923668fbae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216509902 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.4216509902
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.1604316771
Short name T32
Test name
Test status
Simulation time 237517272950 ps
CPU time 615.87 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:45:38 PM PDT 24
Peak memory 216028 kb
Host smart-623f9d51-ddeb-4e4f-8cd1-b56a2ab5c096
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604316771 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.1604316771
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.3182777577
Short name T20
Test name
Test status
Simulation time 181222557421 ps
CPU time 116.91 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:37:32 PM PDT 24
Peak memory 199896 kb
Host smart-dcbd28b7-a630-4779-bfbe-93d601fb51bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182777577 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.3182777577
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_stress_all.307967546
Short name T247
Test name
Test status
Simulation time 121231431577 ps
CPU time 767.61 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:49:46 PM PDT 24
Peak memory 208260 kb
Host smart-8f0bf7f6-ea9b-4328-b224-97a53896790b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307967546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.307967546
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.3769586945
Short name T111
Test name
Test status
Simulation time 29984203523 ps
CPU time 13.01 seconds
Started Aug 02 05:37:18 PM PDT 24
Finished Aug 02 05:37:31 PM PDT 24
Peak memory 199992 kb
Host smart-88e8e763-cf94-4503-aee4-f0f946973ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769586945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.3769586945
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.636861669
Short name T52
Test name
Test status
Simulation time 11701464 ps
CPU time 0.61 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 195996 kb
Host smart-41027ee9-dde4-4cf1-95b3-6038b86a5a44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636861669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.636861669
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.87051632
Short name T66
Test name
Test status
Simulation time 63193710 ps
CPU time 0.77 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 197248 kb
Host smart-8e80ef70-7182-4bd9-a4b9-a7ec21b452d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87051632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_o
utstanding.87051632
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.uart_fifo_full.2356965902
Short name T163
Test name
Test status
Simulation time 255109110351 ps
CPU time 217.04 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:38:42 PM PDT 24
Peak memory 199924 kb
Host smart-ef1849aa-cb23-4653-bfbb-478c3b18d950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356965902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.2356965902
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.2075577658
Short name T40
Test name
Test status
Simulation time 380838195531 ps
CPU time 1142.59 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:56:06 PM PDT 24
Peak memory 232952 kb
Host smart-c0f187b2-5011-490d-912e-af9c7d63ce24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075577658 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.2075577658
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_rx.1428375140
Short name T264
Test name
Test status
Simulation time 121720895753 ps
CPU time 229.87 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:39:41 PM PDT 24
Peak memory 199968 kb
Host smart-32d59c64-f673-4267-8692-74d8b9dc5111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428375140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.1428375140
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.3648446270
Short name T128
Test name
Test status
Simulation time 127496444571 ps
CPU time 256.44 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:40:16 PM PDT 24
Peak memory 199852 kb
Host smart-9322efbb-5272-4080-bd2d-9f70446650c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648446270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.3648446270
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.1172837127
Short name T200
Test name
Test status
Simulation time 119712948271 ps
CPU time 205.59 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:40:12 PM PDT 24
Peak memory 199904 kb
Host smart-fc9b88ec-f342-4a72-b71f-69682f25ecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172837127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.1172837127
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.2706245210
Short name T38
Test name
Test status
Simulation time 221512154776 ps
CPU time 858.97 seconds
Started Aug 02 05:37:19 PM PDT 24
Finished Aug 02 05:51:38 PM PDT 24
Peak memory 216480 kb
Host smart-d295b766-cfa2-4f27-85c6-9ba4132abd70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706245210 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.2706245210
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1503335065
Short name T268
Test name
Test status
Simulation time 41122685585 ps
CPU time 27.71 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:36:38 PM PDT 24
Peak memory 199948 kb
Host smart-9b1ae0f3-ff88-459b-b074-6a67fe84dd3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503335065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1503335065
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.3131712123
Short name T80
Test name
Test status
Simulation time 342616045 ps
CPU time 1.39 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:26 PM PDT 24
Peak memory 199784 kb
Host smart-2f544b6f-281c-4bc2-bde2-0e2a2d122a56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131712123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.3131712123
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.2103069744
Short name T112
Test name
Test status
Simulation time 273947377975 ps
CPU time 84.3 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:37:48 PM PDT 24
Peak memory 199884 kb
Host smart-4df33b1e-94e5-412d-957d-7e0230502d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103069744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.2103069744
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.2516646994
Short name T21
Test name
Test status
Simulation time 64974295861 ps
CPU time 31.12 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:37:12 PM PDT 24
Peak memory 199992 kb
Host smart-5a85247e-4dc0-4005-a892-66816f7a5c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516646994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.2516646994
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_stress_all.1079744073
Short name T204
Test name
Test status
Simulation time 946081061456 ps
CPU time 1051.09 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:54:29 PM PDT 24
Peak memory 216376 kb
Host smart-f666adba-82a1-46ad-94db-d054aea3bc3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079744073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.1079744073
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all.1070457698
Short name T1
Test name
Test status
Simulation time 122405533102 ps
CPU time 338.23 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:40:44 PM PDT 24
Peak memory 199916 kb
Host smart-9ac1ca9f-5c2f-44ed-8b7b-3f24c9394f41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070457698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.1070457698
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.4050305164
Short name T636
Test name
Test status
Simulation time 98447069485 ps
CPU time 149.01 seconds
Started Aug 02 05:35:17 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 200004 kb
Host smart-44c3f29e-c953-48bc-b066-6ec1ce76529e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050305164 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.4050305164
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.2776751985
Short name T122
Test name
Test status
Simulation time 92172199660 ps
CPU time 99.57 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:37:31 PM PDT 24
Peak memory 199952 kb
Host smart-929a0065-a2ba-4876-909c-41a44d294520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776751985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.2776751985
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.1857372521
Short name T184
Test name
Test status
Simulation time 51914238285 ps
CPU time 38.24 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:38 PM PDT 24
Peak memory 199936 kb
Host smart-2aa3f441-0dc1-4e98-bf6f-fa17a736804f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857372521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.1857372521
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2483161872
Short name T188
Test name
Test status
Simulation time 62871901816 ps
CPU time 22.65 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:18 PM PDT 24
Peak memory 199968 kb
Host smart-111c37ec-c50b-4db7-92d3-6e673d47c3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483161872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2483161872
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.2343878410
Short name T148
Test name
Test status
Simulation time 51456462011 ps
CPU time 83.9 seconds
Started Aug 02 05:37:53 PM PDT 24
Finished Aug 02 05:39:17 PM PDT 24
Peak memory 199920 kb
Host smart-cca0676a-92fe-4159-b148-726b11d6efdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343878410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.2343878410
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.68234296
Short name T140
Test name
Test status
Simulation time 74796688273 ps
CPU time 56.59 seconds
Started Aug 02 05:38:34 PM PDT 24
Finished Aug 02 05:39:30 PM PDT 24
Peak memory 199932 kb
Host smart-1f28d69e-a265-4f36-b4f0-50ae29f0b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68234296 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.68234296
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.1623427170
Short name T158
Test name
Test status
Simulation time 90160624536 ps
CPU time 172.93 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:39:53 PM PDT 24
Peak memory 199804 kb
Host smart-32eabd33-a90a-4d4b-8c18-9c39b60efe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623427170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.1623427170
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.3059931533
Short name T44
Test name
Test status
Simulation time 276838154290 ps
CPU time 426.86 seconds
Started Aug 02 05:37:34 PM PDT 24
Finished Aug 02 05:44:41 PM PDT 24
Peak memory 224948 kb
Host smart-772c2cd9-2237-4344-99ad-236f4345a9b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059931533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.3059931533
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.3437254438
Short name T367
Test name
Test status
Simulation time 16350052533 ps
CPU time 28.89 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:13 PM PDT 24
Peak memory 199804 kb
Host smart-29312f1d-ab75-4070-8940-4169ba74f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437254438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.3437254438
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1546245541
Short name T102
Test name
Test status
Simulation time 262201754143 ps
CPU time 103.89 seconds
Started Aug 02 05:37:45 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 199932 kb
Host smart-f96c54e3-f932-4632-a922-018be1d6b57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546245541 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1546245541
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.2752930338
Short name T713
Test name
Test status
Simulation time 32928262789 ps
CPU time 39.04 seconds
Started Aug 02 05:37:46 PM PDT 24
Finished Aug 02 05:38:25 PM PDT 24
Peak memory 199868 kb
Host smart-c88ba07f-f249-4b5a-8504-dacb9342c932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752930338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.2752930338
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.1221189389
Short name T126
Test name
Test status
Simulation time 29501299580 ps
CPU time 51.26 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:35 PM PDT 24
Peak memory 200012 kb
Host smart-20075344-5555-4da4-b92b-cd7cee7afced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221189389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.1221189389
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.3335865825
Short name T178
Test name
Test status
Simulation time 23022993728 ps
CPU time 38.33 seconds
Started Aug 02 05:37:47 PM PDT 24
Finished Aug 02 05:38:25 PM PDT 24
Peak memory 199988 kb
Host smart-e6194170-5059-4ba9-81f5-7fa5452c7ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335865825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.3335865825
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.4068405811
Short name T145
Test name
Test status
Simulation time 150266879247 ps
CPU time 51.77 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 199724 kb
Host smart-35c9efb1-03fd-4493-a2f8-930519d1d23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068405811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.4068405811
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.1426570250
Short name T150
Test name
Test status
Simulation time 18968045753 ps
CPU time 11.8 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:38:36 PM PDT 24
Peak memory 199960 kb
Host smart-b4d5988e-010f-47a7-a7ba-d7f53eac295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426570250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.1426570250
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.2333205825
Short name T185
Test name
Test status
Simulation time 179283982747 ps
CPU time 291.72 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:43:16 PM PDT 24
Peak memory 199948 kb
Host smart-5abdbf23-9a8f-47bb-8a61-652fe311e9cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333205825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.2333205825
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.2046309228
Short name T135
Test name
Test status
Simulation time 21718208314 ps
CPU time 19.56 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 199988 kb
Host smart-b6dc5f81-0d82-4b7f-8a58-9f965fa3cc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046309228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.2046309228
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.746368618
Short name T181
Test name
Test status
Simulation time 194948332469 ps
CPU time 122.89 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:38:51 PM PDT 24
Peak memory 199800 kb
Host smart-03731236-a11e-491f-b28d-bc8fbd9586ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746368618 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.746368618
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.556502297
Short name T227
Test name
Test status
Simulation time 158887869106 ps
CPU time 794.9 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:50:31 PM PDT 24
Peak memory 224204 kb
Host smart-6e304db8-05ef-4640-ac14-b9059effc976
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556502297 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.556502297
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.644566939
Short name T116
Test name
Test status
Simulation time 42274311 ps
CPU time 0.94 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 199552 kb
Host smart-871c8277-3224-4e15-80cd-fdc91f761a3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644566939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.644566939
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.2662787229
Short name T193
Test name
Test status
Simulation time 9501355305 ps
CPU time 12.77 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:16 PM PDT 24
Peak memory 199944 kb
Host smart-0a0107cd-f955-4c71-a391-b0c6829dc0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662787229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.2662787229
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.3510553132
Short name T6
Test name
Test status
Simulation time 43516350315 ps
CPU time 60.18 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 199952 kb
Host smart-a8fe3afb-f3ee-405a-9b36-225794c383b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510553132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.3510553132
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2845701422
Short name T221
Test name
Test status
Simulation time 457448764127 ps
CPU time 1723.33 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 06:04:36 PM PDT 24
Peak memory 232952 kb
Host smart-afa7fc03-b988-47bf-8388-2ea15e956642
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845701422 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2845701422
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3417725424
Short name T223
Test name
Test status
Simulation time 50172864533 ps
CPU time 81.79 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 200000 kb
Host smart-87a0e3b1-e7b1-405a-a117-36264ed645be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417725424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3417725424
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.2761466089
Short name T235
Test name
Test status
Simulation time 24487183962 ps
CPU time 47.57 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 199992 kb
Host smart-158bd867-a1a2-4e60-ade3-69b1757d1194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761466089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.2761466089
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2654515325
Short name T810
Test name
Test status
Simulation time 139789801931 ps
CPU time 123.18 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:39:58 PM PDT 24
Peak memory 199996 kb
Host smart-2dad1068-6ba2-42dc-aaca-05a4c97825f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654515325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2654515325
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.4022459981
Short name T444
Test name
Test status
Simulation time 133798627888 ps
CPU time 245.4 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:42:01 PM PDT 24
Peak memory 199872 kb
Host smart-e5d2c539-dadc-4efe-ad72-a129a603d7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022459981 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.4022459981
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.3757014427
Short name T231
Test name
Test status
Simulation time 34379862655 ps
CPU time 16.28 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 199984 kb
Host smart-57063432-d226-4a4d-8db2-6ebf7f8d8a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757014427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.3757014427
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.1170127944
Short name T229
Test name
Test status
Simulation time 29024612697 ps
CPU time 10.19 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:06 PM PDT 24
Peak memory 199872 kb
Host smart-cdeb40fb-bfe2-4b47-a230-2e5493a90fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170127944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.1170127944
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.730373082
Short name T138
Test name
Test status
Simulation time 53065463023 ps
CPU time 32.97 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 199904 kb
Host smart-5633fe0f-3c26-41ee-8459-b5040f915a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730373082 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.730373082
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_stress_all.112390495
Short name T215
Test name
Test status
Simulation time 72303336922 ps
CPU time 147.77 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199924 kb
Host smart-ba15d8ba-3f33-44ee-b528-b6ccf1edd0b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112390495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.112390495
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.3987134969
Short name T236
Test name
Test status
Simulation time 38611833400 ps
CPU time 23.53 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:38 PM PDT 24
Peak memory 199996 kb
Host smart-d0a48f42-4ddc-4119-b2d8-5f220a1042c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987134969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.3987134969
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.4293019692
Short name T152
Test name
Test status
Simulation time 17735072829 ps
CPU time 29.81 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 199904 kb
Host smart-845934a7-6396-44d3-a63e-f0e7957a48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293019692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.4293019692
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4155184735
Short name T222
Test name
Test status
Simulation time 95998012458 ps
CPU time 52.74 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:39:01 PM PDT 24
Peak memory 199808 kb
Host smart-60fde97c-fc6c-4039-96e2-b536acea842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155184735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4155184735
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.1839878516
Short name T205
Test name
Test status
Simulation time 28886371602 ps
CPU time 10.47 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:18 PM PDT 24
Peak memory 199900 kb
Host smart-39a455ba-d7a5-4138-9e52-31036f8133b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839878516 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.1839878516
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.163528619
Short name T326
Test name
Test status
Simulation time 50130503409 ps
CPU time 18.71 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 200012 kb
Host smart-4cc7e4c2-8daf-44f0-8ce2-01d1d9f48834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163528619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.163528619
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.431177905
Short name T212
Test name
Test status
Simulation time 43997314655 ps
CPU time 29.08 seconds
Started Aug 02 05:38:04 PM PDT 24
Finished Aug 02 05:38:33 PM PDT 24
Peak memory 199980 kb
Host smart-a6f3b284-41cf-4cda-93e4-c11f0868bcf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431177905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.431177905
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.549734874
Short name T233
Test name
Test status
Simulation time 14695907859 ps
CPU time 29.54 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 199936 kb
Host smart-fa9e7182-56e5-4051-873f-f77d2c7ad287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549734874 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.549734874
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3690059472
Short name T220
Test name
Test status
Simulation time 380228346337 ps
CPU time 574.7 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:45:32 PM PDT 24
Peak memory 226880 kb
Host smart-b286ad9b-f51f-421d-9c71-8bdc3148dbf5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690059472 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3690059472
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.655513451
Short name T190
Test name
Test status
Simulation time 129246055253 ps
CPU time 194.38 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:41:27 PM PDT 24
Peak memory 199904 kb
Host smart-1a6e36ee-46af-44b5-9b2b-b120c8945434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655513451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.655513451
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2515437201
Short name T228
Test name
Test status
Simulation time 19017219767 ps
CPU time 12.68 seconds
Started Aug 02 05:38:37 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 200000 kb
Host smart-8661bc7f-49b3-429a-86d7-0b3ee7309a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515437201 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2515437201
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2080892103
Short name T57
Test name
Test status
Simulation time 33186746908 ps
CPU time 14.8 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:38:49 PM PDT 24
Peak memory 199948 kb
Host smart-5f24ccb1-59e7-42cf-a1f6-3a1b833d552c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080892103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2080892103
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.1309806316
Short name T137
Test name
Test status
Simulation time 21666937954 ps
CPU time 19.66 seconds
Started Aug 02 05:37:18 PM PDT 24
Finished Aug 02 05:37:38 PM PDT 24
Peak memory 199904 kb
Host smart-564b379f-c335-4265-a5e1-b56fa50c5c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309806316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.1309806316
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3600768881
Short name T1200
Test name
Test status
Simulation time 18199551 ps
CPU time 0.67 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 195784 kb
Host smart-daf9760d-ee46-46b7-a871-85c35309f2a2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600768881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3600768881
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.1262444342
Short name T1260
Test name
Test status
Simulation time 34539936 ps
CPU time 1.51 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:59 PM PDT 24
Peak memory 198180 kb
Host smart-dbafa1d4-b5a4-4afd-812d-335ab9633644
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262444342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.1262444342
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.711353215
Short name T1271
Test name
Test status
Simulation time 24544585 ps
CPU time 0.58 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 195792 kb
Host smart-98595117-0af6-43e5-897c-b928b90aad3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711353215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.711353215
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.2355449524
Short name T1243
Test name
Test status
Simulation time 36294270 ps
CPU time 1.06 seconds
Started Aug 02 05:21:57 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 200216 kb
Host smart-4aaaf85e-8182-4ed4-8772-509223d4cc75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355449524 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.2355449524
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.3360903752
Short name T1198
Test name
Test status
Simulation time 16623679 ps
CPU time 0.62 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 194848 kb
Host smart-f8e23abb-6b16-42c1-b226-7eba1abddfbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360903752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.3360903752
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.3910667533
Short name T1193
Test name
Test status
Simulation time 126139966 ps
CPU time 2.2 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:03 PM PDT 24
Peak memory 200468 kb
Host smart-6dcd118b-5260-4ad0-ab36-8b1537a972e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910667533 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.3910667533
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.4052898941
Short name T1255
Test name
Test status
Simulation time 82746823 ps
CPU time 0.96 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 199156 kb
Host smart-54ec91cc-6cfc-49a7-9cbc-2e07a09a5f80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052898941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.4052898941
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1812667594
Short name T50
Test name
Test status
Simulation time 31944885 ps
CPU time 0.82 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 197056 kb
Host smart-f009c608-5e64-45da-8cb0-2a3f440ed595
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812667594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1812667594
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.151174422
Short name T1235
Test name
Test status
Simulation time 139429705 ps
CPU time 1.59 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 198156 kb
Host smart-6ef00951-133a-41c2-8e1a-6f20c1e83c09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151174422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.151174422
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1917353461
Short name T1204
Test name
Test status
Simulation time 14491579 ps
CPU time 0.61 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 195840 kb
Host smart-ab5af37c-d745-4143-81ae-91602b2f7553
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917353461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1917353461
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2360054624
Short name T1196
Test name
Test status
Simulation time 96224465 ps
CPU time 1.47 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 200496 kb
Host smart-b678a7f3-2724-429e-a8dc-0266baae71ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360054624 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.2360054624
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2961434807
Short name T1267
Test name
Test status
Simulation time 48895301 ps
CPU time 0.62 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 195660 kb
Host smart-55a38a0f-d0b9-4b7f-b0fa-849ef845cf3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961434807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2961434807
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.1859556881
Short name T1208
Test name
Test status
Simulation time 51173284 ps
CPU time 0.55 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:00 PM PDT 24
Peak memory 194736 kb
Host smart-9eba71b2-3355-4d85-971c-5f62503810ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859556881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.1859556881
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.3067140690
Short name T1273
Test name
Test status
Simulation time 15596596 ps
CPU time 0.69 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 196888 kb
Host smart-cd89becc-6543-48a7-b1b7-124ae07cd87d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067140690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.3067140690
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2431679283
Short name T1192
Test name
Test status
Simulation time 217618433 ps
CPU time 1.15 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 200448 kb
Host smart-92288c4d-c0a0-437f-8169-2bb499e328b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431679283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2431679283
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.4252058532
Short name T1202
Test name
Test status
Simulation time 22931032 ps
CPU time 0.8 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 198776 kb
Host smart-8b7c552d-910b-4a88-a3b0-fa742dd754a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252058532 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.4252058532
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.1632122517
Short name T1268
Test name
Test status
Simulation time 43105021 ps
CPU time 0.61 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 195904 kb
Host smart-9650ec95-fba2-4bb8-8071-71dc0ec15103
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632122517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.1632122517
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.4267163614
Short name T1263
Test name
Test status
Simulation time 41062334 ps
CPU time 0.55 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 194812 kb
Host smart-eb35f991-f38c-46b4-88ff-50c0c256fc0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267163614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.4267163614
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.2378748676
Short name T1295
Test name
Test status
Simulation time 47303763 ps
CPU time 0.76 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:16 PM PDT 24
Peak memory 196448 kb
Host smart-ba998c42-e9fc-4427-a8ec-7e817e5c502c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378748676 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.2378748676
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3962165007
Short name T1264
Test name
Test status
Simulation time 35775300 ps
CPU time 0.89 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 200180 kb
Host smart-ad99d10d-6725-4148-93fb-97cf42bab4bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962165007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3962165007
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.1218088909
Short name T1278
Test name
Test status
Simulation time 87545696 ps
CPU time 0.95 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:16 PM PDT 24
Peak memory 199424 kb
Host smart-59595811-cb70-4212-8f4c-a3164cf1ac62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218088909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.1218088909
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.1305767803
Short name T1276
Test name
Test status
Simulation time 16973097 ps
CPU time 0.69 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 197664 kb
Host smart-254832d0-8299-4963-9ef2-b7600944a8c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305767803 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.1305767803
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3191877701
Short name T1299
Test name
Test status
Simulation time 47872372 ps
CPU time 0.6 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 195896 kb
Host smart-8ba7d8a3-e7a9-4e84-847e-da431df626da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191877701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3191877701
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.1724706717
Short name T1240
Test name
Test status
Simulation time 44531925 ps
CPU time 0.55 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 194724 kb
Host smart-114ef215-0018-4847-9020-0be08abbe48f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724706717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.1724706717
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.1097496792
Short name T65
Test name
Test status
Simulation time 24343009 ps
CPU time 0.64 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 196244 kb
Host smart-5a1137a3-f6b2-4db2-956a-45796426d9b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097496792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.1097496792
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3682519616
Short name T1184
Test name
Test status
Simulation time 29949560 ps
CPU time 1.45 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 200384 kb
Host smart-9c843fce-e96e-4c87-b479-204fba49043d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682519616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3682519616
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1282288885
Short name T1288
Test name
Test status
Simulation time 336552156 ps
CPU time 0.99 seconds
Started Aug 02 05:22:19 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 199276 kb
Host smart-b1d08b63-7f7f-4e62-9a18-f77d89ba37bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282288885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1282288885
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.1358342789
Short name T1183
Test name
Test status
Simulation time 296092258 ps
CPU time 0.81 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 200244 kb
Host smart-14567e75-97fc-4e9a-9e47-5e918e764ca8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358342789 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.1358342789
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.3253529485
Short name T1221
Test name
Test status
Simulation time 44634671 ps
CPU time 0.58 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 195872 kb
Host smart-de288822-fafa-4d5e-800d-c48707d96088
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253529485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.3253529485
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.958212744
Short name T1212
Test name
Test status
Simulation time 38689775 ps
CPU time 0.57 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:25 PM PDT 24
Peak memory 194736 kb
Host smart-3af89b54-b965-4f28-b0cb-5aa2e33fddde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958212744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.958212744
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.2900902380
Short name T1313
Test name
Test status
Simulation time 43036168 ps
CPU time 0.65 seconds
Started Aug 02 05:22:11 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 196132 kb
Host smart-cc285e69-749f-4d3c-9ad9-1ed684b98009
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900902380 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.2900902380
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.2368815222
Short name T1217
Test name
Test status
Simulation time 1743126404 ps
CPU time 2.3 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 200440 kb
Host smart-4d187254-8776-4d6d-8d24-ece41601d92c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368815222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.2368815222
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.914351388
Short name T78
Test name
Test status
Simulation time 41255620 ps
CPU time 0.92 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 199372 kb
Host smart-9ac1081b-f002-4623-aa3d-f26107e688e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914351388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.914351388
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.226054159
Short name T1220
Test name
Test status
Simulation time 23663217 ps
CPU time 1.08 seconds
Started Aug 02 05:22:54 PM PDT 24
Finished Aug 02 05:22:55 PM PDT 24
Peak memory 200500 kb
Host smart-ca59db88-6c47-4e64-bcc0-fa5684b10113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226054159 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.226054159
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.2050360684
Short name T1226
Test name
Test status
Simulation time 43579465 ps
CPU time 0.58 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:28 PM PDT 24
Peak memory 195848 kb
Host smart-9a76afed-668a-4851-92b6-98aefcc9845b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050360684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.2050360684
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.2571325702
Short name T1304
Test name
Test status
Simulation time 36900266 ps
CPU time 0.58 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 194820 kb
Host smart-91951c8a-1a36-4488-adc2-fb475c9fab8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571325702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.2571325702
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.1740134969
Short name T1300
Test name
Test status
Simulation time 19707091 ps
CPU time 0.72 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 195768 kb
Host smart-011b8ba4-ca09-4acb-976d-0557d3147816
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740134969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_cs
r_outstanding.1740134969
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.2694316674
Short name T1285
Test name
Test status
Simulation time 71940522 ps
CPU time 1.94 seconds
Started Aug 02 05:22:11 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 200496 kb
Host smart-5ffe82a3-fe1e-4d56-943b-c9ad2371025e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694316674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.2694316674
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.2502608420
Short name T1186
Test name
Test status
Simulation time 30815125 ps
CPU time 0.83 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 200216 kb
Host smart-4a1dd0b9-15ba-4df0-bede-c365a46acb9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502608420 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.2502608420
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.2896628157
Short name T1280
Test name
Test status
Simulation time 37644368 ps
CPU time 0.62 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 195724 kb
Host smart-9334d258-2b89-46a3-9ffa-a835bcbcf82c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896628157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.2896628157
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.2494582301
Short name T1287
Test name
Test status
Simulation time 23777211 ps
CPU time 0.57 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 194844 kb
Host smart-ccb9df03-9a22-42ef-b588-71a47fa3824f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494582301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.2494582301
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.890138729
Short name T62
Test name
Test status
Simulation time 40255926 ps
CPU time 0.7 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 195268 kb
Host smart-f56281b1-d516-49be-bd2e-748c38359edc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890138729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_csr
_outstanding.890138729
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.3500864703
Short name T1259
Test name
Test status
Simulation time 383102146 ps
CPU time 1.37 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 200472 kb
Host smart-eb113fff-ca33-469a-bbc8-1a5c1849d622
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500864703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.3500864703
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.1862789033
Short name T1291
Test name
Test status
Simulation time 239393877 ps
CPU time 1.26 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 199720 kb
Host smart-0f1312d1-4b16-442b-b734-1ae941dbb329
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862789033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.1862789033
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.2526902675
Short name T1219
Test name
Test status
Simulation time 105102238 ps
CPU time 1.36 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 200452 kb
Host smart-86775a46-cbc8-431d-a57f-f13178c908b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526902675 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.2526902675
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.1841103892
Short name T63
Test name
Test status
Simulation time 24840388 ps
CPU time 0.65 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 195700 kb
Host smart-48e8faed-1604-4cc9-a930-be447c1446db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841103892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.1841103892
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.3902699995
Short name T1256
Test name
Test status
Simulation time 17339977 ps
CPU time 0.59 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 194756 kb
Host smart-161dadb9-21a8-4e9b-b7df-e56a07409983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902699995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.3902699995
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.13821434
Short name T1248
Test name
Test status
Simulation time 11937305 ps
CPU time 0.63 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:16 PM PDT 24
Peak memory 195864 kb
Host smart-370821d9-4d81-4744-9235-42f201acdd01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13821434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_csr_
outstanding.13821434
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.547518678
Short name T1189
Test name
Test status
Simulation time 155110903 ps
CPU time 2.05 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 200424 kb
Host smart-e7517d47-5197-48d6-ade9-2e09ed74f9c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547518678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.547518678
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.2920571330
Short name T1306
Test name
Test status
Simulation time 94824643 ps
CPU time 0.96 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 198964 kb
Host smart-dae65d44-74ab-4539-8d7c-96ae14607985
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920571330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.2920571330
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.2207085848
Short name T1242
Test name
Test status
Simulation time 105692093 ps
CPU time 0.84 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 200256 kb
Host smart-d75c75ce-e7c6-4154-b1f4-2dd3997fcf3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207085848 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.2207085848
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.3462712710
Short name T1308
Test name
Test status
Simulation time 24311833 ps
CPU time 0.61 seconds
Started Aug 02 05:22:11 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 195676 kb
Host smart-71ad0452-fb93-4356-8212-4cd48126e005
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462712710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.3462712710
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.4012814972
Short name T1270
Test name
Test status
Simulation time 16354169 ps
CPU time 0.61 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 194732 kb
Host smart-07f785b8-e4ec-4657-bd24-29753e66ef1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012814972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.4012814972
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.1747121133
Short name T1309
Test name
Test status
Simulation time 49841450 ps
CPU time 0.8 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 197580 kb
Host smart-d76e5bd4-3a59-4ae6-aa23-d83b65520dd7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747121133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_cs
r_outstanding.1747121133
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.2843351601
Short name T1237
Test name
Test status
Simulation time 232258047 ps
CPU time 1.24 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:19 PM PDT 24
Peak memory 200460 kb
Host smart-1ecff989-b404-401f-a559-f865f145dbd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843351601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.2843351601
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.1426140252
Short name T1222
Test name
Test status
Simulation time 72292679 ps
CPU time 0.98 seconds
Started Aug 02 05:22:18 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 199148 kb
Host smart-0677418e-7269-4f35-ba3e-f3337e18d33c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426140252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.1426140252
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.1143608553
Short name T1199
Test name
Test status
Simulation time 18923516 ps
CPU time 0.7 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 197900 kb
Host smart-2dd08c63-2727-4262-8a57-e623d92ad93a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143608553 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.1143608553
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.3774824869
Short name T71
Test name
Test status
Simulation time 11729103 ps
CPU time 0.63 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 195904 kb
Host smart-faad0d0d-1899-4c32-b7e8-c9b16b82f5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774824869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.3774824869
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.1118303972
Short name T1302
Test name
Test status
Simulation time 77543617 ps
CPU time 0.6 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 194848 kb
Host smart-5efa23b8-acac-4d98-ba94-20b5da38d369
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118303972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.1118303972
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.121852373
Short name T1216
Test name
Test status
Simulation time 59469739 ps
CPU time 0.75 seconds
Started Aug 02 05:22:18 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 197036 kb
Host smart-16d2fef0-ca2b-470e-83e5-a48eb60ffef9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121852373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_csr
_outstanding.121852373
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.4078645947
Short name T1191
Test name
Test status
Simulation time 253705704 ps
CPU time 1.4 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 200456 kb
Host smart-0b6e20de-3ead-493e-ab54-506595d179ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078645947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.4078645947
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.1841474179
Short name T1297
Test name
Test status
Simulation time 260685764 ps
CPU time 1.18 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 199704 kb
Host smart-99e1f45f-dd95-4e64-97f9-41a6b86c4414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841474179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.1841474179
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.4241328703
Short name T1188
Test name
Test status
Simulation time 32885770 ps
CPU time 0.74 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 199460 kb
Host smart-2bc176c5-1538-4bf3-ab23-bbcdc75b3076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241328703 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.4241328703
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.3095294362
Short name T1310
Test name
Test status
Simulation time 13832154 ps
CPU time 0.59 seconds
Started Aug 02 05:22:27 PM PDT 24
Finished Aug 02 05:22:28 PM PDT 24
Peak memory 195908 kb
Host smart-d47b9deb-04c6-40cf-923b-b9adccbc5261
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095294362 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.3095294362
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.1537019623
Short name T1223
Test name
Test status
Simulation time 10854238 ps
CPU time 0.55 seconds
Started Aug 02 05:22:23 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194760 kb
Host smart-b84011a1-c388-4c7c-9674-220e0c3895c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537019623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.1537019623
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.3790496728
Short name T1307
Test name
Test status
Simulation time 12307074 ps
CPU time 0.6 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 195860 kb
Host smart-cc2e4d22-3839-4de9-8a38-5fc963f1a7d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790496728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_cs
r_outstanding.3790496728
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.548678058
Short name T1314
Test name
Test status
Simulation time 400609997 ps
CPU time 1.58 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:16 PM PDT 24
Peak memory 200496 kb
Host smart-120c2197-2b40-49e4-8822-e98476bab7b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548678058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.548678058
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.1202703644
Short name T1303
Test name
Test status
Simulation time 47702722 ps
CPU time 0.93 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 199432 kb
Host smart-127b8465-9c6e-4dfb-bd1a-863008880d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202703644 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.1202703644
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.728828188
Short name T1232
Test name
Test status
Simulation time 21201289 ps
CPU time 1.02 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:25 PM PDT 24
Peak memory 200260 kb
Host smart-241ad755-5f88-4e05-b01f-3653754351bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728828188 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.728828188
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.3827639353
Short name T1317
Test name
Test status
Simulation time 35429052 ps
CPU time 0.62 seconds
Started Aug 02 05:22:23 PM PDT 24
Finished Aug 02 05:22:24 PM PDT 24
Peak memory 195792 kb
Host smart-e987ee1a-31ce-4ff3-afc0-0fbcefcc4f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827639353 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.3827639353
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3292743881
Short name T1254
Test name
Test status
Simulation time 44521098 ps
CPU time 0.58 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194840 kb
Host smart-18995532-faa2-4484-8f58-fd808414727d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292743881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3292743881
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2909735793
Short name T70
Test name
Test status
Simulation time 26084625 ps
CPU time 0.77 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 197472 kb
Host smart-db5b452c-2e0e-4392-b853-6b42886cb718
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909735793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2909735793
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.988215456
Short name T1230
Test name
Test status
Simulation time 64207903 ps
CPU time 1.31 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 200476 kb
Host smart-517902f4-b1b1-460e-9ade-d7c85160a080
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988215456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.988215456
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.2717944568
Short name T1265
Test name
Test status
Simulation time 57269350 ps
CPU time 0.67 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 196064 kb
Host smart-eb6a3557-c8fb-4265-a1c4-64909ba66aed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717944568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.2717944568
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.825613703
Short name T49
Test name
Test status
Simulation time 133661983 ps
CPU time 1.59 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 198084 kb
Host smart-4703078f-62a2-41c9-b2a4-9fa764cffa69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825613703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.825613703
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.1130134988
Short name T1262
Test name
Test status
Simulation time 1044269609 ps
CPU time 1.28 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:06 PM PDT 24
Peak memory 195840 kb
Host smart-0c3b5f12-c8ee-453b-a273-7418707dc597
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130134988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.1130134988
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.3156784268
Short name T1195
Test name
Test status
Simulation time 66942473 ps
CPU time 0.79 seconds
Started Aug 02 05:22:07 PM PDT 24
Finished Aug 02 05:22:08 PM PDT 24
Peak memory 200036 kb
Host smart-2727e422-b3b1-4a52-9dc8-4152467dbf9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156784268 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.3156784268
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4100288346
Short name T46
Test name
Test status
Simulation time 17468186 ps
CPU time 0.61 seconds
Started Aug 02 05:22:06 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 195608 kb
Host smart-922596fc-f585-425a-9c78-f1d728e12d0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100288346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4100288346
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1895980742
Short name T1181
Test name
Test status
Simulation time 38359155 ps
CPU time 0.62 seconds
Started Aug 02 05:21:58 PM PDT 24
Finished Aug 02 05:21:58 PM PDT 24
Peak memory 194776 kb
Host smart-d5a80d0f-2d62-4e45-9182-5074ddf07186
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895980742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1895980742
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.2683037269
Short name T1253
Test name
Test status
Simulation time 16355150 ps
CPU time 0.65 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 196152 kb
Host smart-e92895a7-70f3-401f-87bf-baee78789d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683037269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.2683037269
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.3407931562
Short name T1229
Test name
Test status
Simulation time 1486084175 ps
CPU time 2.33 seconds
Started Aug 02 05:22:00 PM PDT 24
Finished Aug 02 05:22:02 PM PDT 24
Peak memory 200456 kb
Host smart-11b7f524-00f4-4b28-bc16-1cc0228dd0eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407931562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.3407931562
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.1850394276
Short name T1298
Test name
Test status
Simulation time 237841224 ps
CPU time 0.96 seconds
Started Aug 02 05:21:59 PM PDT 24
Finished Aug 02 05:22:01 PM PDT 24
Peak memory 199168 kb
Host smart-77319c5d-0fda-4850-9109-d39ed5a22c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850394276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.1850394276
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.4230653347
Short name T1293
Test name
Test status
Simulation time 39840834 ps
CPU time 0.57 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:22:26 PM PDT 24
Peak memory 194776 kb
Host smart-fc6ebe7a-84dc-4b77-a716-478309b23363
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230653347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.4230653347
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.281962547
Short name T1227
Test name
Test status
Simulation time 32587161 ps
CPU time 0.56 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:22:27 PM PDT 24
Peak memory 194776 kb
Host smart-940f3715-5b28-4630-aa1a-6882412f792e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281962547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.281962547
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.2810400630
Short name T1245
Test name
Test status
Simulation time 27710847 ps
CPU time 0.54 seconds
Started Aug 02 05:22:19 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 194824 kb
Host smart-b3b77835-5c2c-429c-91a6-888f53dd27e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810400630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.2810400630
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.3766401463
Short name T1213
Test name
Test status
Simulation time 16313954 ps
CPU time 0.63 seconds
Started Aug 02 05:22:19 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 194800 kb
Host smart-259e3800-0a45-4063-96a7-698e775f4e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766401463 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.3766401463
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.1586649659
Short name T1275
Test name
Test status
Simulation time 30427818 ps
CPU time 0.69 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 194836 kb
Host smart-41f3b266-c5ce-41ad-ad7b-6768491c6a6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586649659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.1586649659
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.3770379913
Short name T1305
Test name
Test status
Simulation time 13118331 ps
CPU time 0.62 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 194772 kb
Host smart-678e5430-babb-4582-ba9f-fb9798fc55b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770379913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.3770379913
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.3853244190
Short name T1261
Test name
Test status
Simulation time 12913040 ps
CPU time 0.58 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194776 kb
Host smart-cf11a9b9-eb37-41be-b963-cfb3536eaf71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853244190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.3853244190
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.2385535476
Short name T1228
Test name
Test status
Simulation time 37076183 ps
CPU time 0.59 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194896 kb
Host smart-327ff6fd-de19-4c07-bb70-b579900d88f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385535476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.2385535476
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.3768138830
Short name T1272
Test name
Test status
Simulation time 36416454 ps
CPU time 0.56 seconds
Started Aug 02 05:22:19 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 194812 kb
Host smart-f1f3b8ef-aff0-40d8-914a-2e5eef986b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768138830 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.3768138830
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1637755419
Short name T1214
Test name
Test status
Simulation time 13996441 ps
CPU time 0.61 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194792 kb
Host smart-c36dc853-c3bc-44fe-99f2-522f8ce4da80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637755419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1637755419
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.359123582
Short name T1294
Test name
Test status
Simulation time 34901957 ps
CPU time 0.69 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 195816 kb
Host smart-586078e2-ecc5-4a95-9966-2408331d18bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359123582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.359123582
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.1392430284
Short name T1218
Test name
Test status
Simulation time 259618642 ps
CPU time 2.61 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 198080 kb
Host smart-b14985a0-db48-46b3-88d6-5d527afdc7a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392430284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.1392430284
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2206339796
Short name T1211
Test name
Test status
Simulation time 34341013 ps
CPU time 0.59 seconds
Started Aug 02 05:22:10 PM PDT 24
Finished Aug 02 05:22:11 PM PDT 24
Peak memory 195840 kb
Host smart-2a13e32d-e670-4b32-ab63-2f74b35b474f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206339796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2206339796
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3214904594
Short name T1197
Test name
Test status
Simulation time 22432240 ps
CPU time 1.08 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:06 PM PDT 24
Peak memory 200260 kb
Host smart-8a083f23-59c4-44dd-8eee-d77ac4639350
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214904594 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3214904594
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.3264197211
Short name T48
Test name
Test status
Simulation time 40066539 ps
CPU time 0.6 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 195924 kb
Host smart-eb422084-53d7-4d46-8382-e5f1f6b951e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264197211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.3264197211
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1627398428
Short name T1252
Test name
Test status
Simulation time 105292326 ps
CPU time 0.58 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 194736 kb
Host smart-1ee108f7-53ef-404e-b4f4-669bedd21392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627398428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1627398428
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.522181875
Short name T64
Test name
Test status
Simulation time 120795376 ps
CPU time 0.83 seconds
Started Aug 02 05:22:07 PM PDT 24
Finished Aug 02 05:22:08 PM PDT 24
Peak memory 196420 kb
Host smart-3d88cf0c-606d-4407-8c12-312dac6cb7f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522181875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr_
outstanding.522181875
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.2051246956
Short name T1296
Test name
Test status
Simulation time 70621076 ps
CPU time 1.45 seconds
Started Aug 02 05:22:06 PM PDT 24
Finished Aug 02 05:22:08 PM PDT 24
Peak memory 200488 kb
Host smart-6a13d92a-ecae-4503-8ff0-b9ad54cca9d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051246956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.2051246956
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.468387500
Short name T76
Test name
Test status
Simulation time 219831080 ps
CPU time 0.95 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:09 PM PDT 24
Peak memory 198876 kb
Host smart-dfc7afda-b069-4aec-845c-e37785d5da69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468387500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.468387500
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.2432010586
Short name T1205
Test name
Test status
Simulation time 16570271 ps
CPU time 0.57 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194832 kb
Host smart-3e4c9a61-3e06-4205-87ed-085b533a6d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432010586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.2432010586
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3609390715
Short name T1206
Test name
Test status
Simulation time 17411450 ps
CPU time 0.57 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:24 PM PDT 24
Peak memory 194856 kb
Host smart-4f5a8096-b539-46ad-b1f6-5e1ee8251b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609390715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3609390715
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.802245206
Short name T1194
Test name
Test status
Simulation time 36894523 ps
CPU time 0.57 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:25 PM PDT 24
Peak memory 194696 kb
Host smart-b70f0d05-6d9e-4afd-91f7-7e0666c677b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802245206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.802245206
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.1937752399
Short name T1312
Test name
Test status
Simulation time 52098989 ps
CPU time 0.58 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:22:28 PM PDT 24
Peak memory 194840 kb
Host smart-2eb52ab1-5c0e-499a-99f8-35558d505bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937752399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.1937752399
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.2832716734
Short name T1277
Test name
Test status
Simulation time 27457484 ps
CPU time 0.61 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:25 PM PDT 24
Peak memory 194872 kb
Host smart-188b57f1-e61b-46af-84b8-3e261777c9ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832716734 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.2832716734
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1122989071
Short name T1203
Test name
Test status
Simulation time 13690833 ps
CPU time 0.57 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 194808 kb
Host smart-e2f6ff61-f4bf-4026-a426-7fdc1805ce01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122989071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1122989071
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.2016154783
Short name T1311
Test name
Test status
Simulation time 33713101 ps
CPU time 0.58 seconds
Started Aug 02 05:22:24 PM PDT 24
Finished Aug 02 05:22:24 PM PDT 24
Peak memory 194804 kb
Host smart-f7ffe538-4c8d-436e-88e8-8b8bab65fde3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016154783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.2016154783
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.2628790822
Short name T1247
Test name
Test status
Simulation time 29138590 ps
CPU time 0.59 seconds
Started Aug 02 05:22:28 PM PDT 24
Finished Aug 02 05:22:28 PM PDT 24
Peak memory 194828 kb
Host smart-b7619b16-0dd3-4f67-83a2-5bf897056c43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628790822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.2628790822
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.1169689945
Short name T1279
Test name
Test status
Simulation time 41474175 ps
CPU time 0.54 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 194836 kb
Host smart-41e941e8-b8cf-41d6-a670-417397d21454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169689945 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.1169689945
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.253933904
Short name T1246
Test name
Test status
Simulation time 121979165 ps
CPU time 0.58 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194800 kb
Host smart-fd5d5618-22de-49e2-91f0-3fc7703cb698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253933904 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.253933904
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2810001698
Short name T1236
Test name
Test status
Simulation time 20820721 ps
CPU time 0.65 seconds
Started Aug 02 05:22:07 PM PDT 24
Finished Aug 02 05:22:08 PM PDT 24
Peak memory 195300 kb
Host smart-d9ee3d54-0f16-4f6d-bdf8-2154f4d63d24
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810001698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2810001698
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.381732579
Short name T1201
Test name
Test status
Simulation time 140426167 ps
CPU time 1.61 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 198484 kb
Host smart-40c4548b-de79-48fb-ab65-762ed1e975f3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381732579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.381732579
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.3596278881
Short name T45
Test name
Test status
Simulation time 51822146 ps
CPU time 0.62 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 195824 kb
Host smart-addc9a0e-56f8-4786-9044-528dfeaf6f6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596278881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.3596278881
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.2950429850
Short name T1190
Test name
Test status
Simulation time 49589436 ps
CPU time 1.18 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 200488 kb
Host smart-76f7e7e2-048d-46d4-a2f3-40dd75fffa4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950429850 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.2950429850
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.1339247529
Short name T1249
Test name
Test status
Simulation time 44149146 ps
CPU time 0.6 seconds
Started Aug 02 05:22:11 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 195868 kb
Host smart-1cdc4ed0-808b-4909-ab72-b6f51b4e535d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339247529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.1339247529
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.1916607721
Short name T1274
Test name
Test status
Simulation time 20390907 ps
CPU time 0.58 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:09 PM PDT 24
Peak memory 194780 kb
Host smart-b884cd45-4800-4de0-8662-f2f2b5857647
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916607721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.1916607721
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.76303938
Short name T1281
Test name
Test status
Simulation time 81728697 ps
CPU time 0.72 seconds
Started Aug 02 05:22:06 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 196208 kb
Host smart-a6834f87-56fc-4889-b8f0-f8893d44024e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76303938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr_o
utstanding.76303938
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.3910751465
Short name T1207
Test name
Test status
Simulation time 36795354 ps
CPU time 1.81 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:06 PM PDT 24
Peak memory 200440 kb
Host smart-cf703e39-9315-4205-a9d9-6915abd15f38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910751465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.3910751465
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.544834160
Short name T117
Test name
Test status
Simulation time 366022970 ps
CPU time 1.62 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:11 PM PDT 24
Peak memory 199628 kb
Host smart-fc8b25fd-d1b3-4c7e-9003-e00c4febc638
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544834160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.544834160
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2715502984
Short name T1289
Test name
Test status
Simulation time 17695570 ps
CPU time 0.62 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194788 kb
Host smart-8b672108-0b41-4f12-ab7e-9ade32bfa082
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715502984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2715502984
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.2193528371
Short name T1282
Test name
Test status
Simulation time 14481083 ps
CPU time 0.57 seconds
Started Aug 02 05:22:26 PM PDT 24
Finished Aug 02 05:22:27 PM PDT 24
Peak memory 194768 kb
Host smart-b8cd57e7-a014-4f4b-be64-165e2aa964bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193528371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.2193528371
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.1904165436
Short name T1241
Test name
Test status
Simulation time 15420261 ps
CPU time 0.59 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194796 kb
Host smart-835ddc36-dcb3-4f23-9627-e2d58a638b37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904165436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.1904165436
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.71045706
Short name T1231
Test name
Test status
Simulation time 33528585 ps
CPU time 0.58 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194820 kb
Host smart-e49b59b8-ae05-4770-ae9e-b2c979792b69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71045706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.71045706
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.912939088
Short name T1238
Test name
Test status
Simulation time 66960646 ps
CPU time 0.61 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194800 kb
Host smart-46b00ea3-8042-4453-8c72-ee9163850fbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912939088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.912939088
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2295288714
Short name T1286
Test name
Test status
Simulation time 14843637 ps
CPU time 0.58 seconds
Started Aug 02 05:22:21 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 194788 kb
Host smart-43177e1f-5d97-43d1-ba36-6cd99f42eae8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295288714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2295288714
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.3289278038
Short name T1257
Test name
Test status
Simulation time 14847481 ps
CPU time 0.57 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:20 PM PDT 24
Peak memory 194812 kb
Host smart-ce7d2f66-150b-4d05-bde8-0ea8c525edc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289278038 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.3289278038
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.132072705
Short name T1225
Test name
Test status
Simulation time 84449503 ps
CPU time 0.6 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:23 PM PDT 24
Peak memory 194816 kb
Host smart-984e297f-6255-4497-839c-60a8b6e4d0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132072705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.132072705
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.2188104959
Short name T1301
Test name
Test status
Simulation time 13497556 ps
CPU time 0.56 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:21 PM PDT 24
Peak memory 194888 kb
Host smart-9c66ba89-853c-44dd-a831-c4cf4fa1ecf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188104959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.2188104959
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.2338141578
Short name T1210
Test name
Test status
Simulation time 22794951 ps
CPU time 0.57 seconds
Started Aug 02 05:22:22 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 194828 kb
Host smart-27b0abeb-4207-46d4-993c-91a961b6118f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338141578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.2338141578
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.642455545
Short name T1283
Test name
Test status
Simulation time 16434393 ps
CPU time 0.67 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:09 PM PDT 24
Peak memory 198224 kb
Host smart-be21f8d2-ec49-458c-961b-5d1f116e5b4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642455545 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.642455545
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.1446065827
Short name T1234
Test name
Test status
Simulation time 14578999 ps
CPU time 0.64 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:04 PM PDT 24
Peak memory 195928 kb
Host smart-47912376-deab-4056-ae9b-50a9816e3ae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446065827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.1446065827
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4293424400
Short name T1266
Test name
Test status
Simulation time 15737655 ps
CPU time 0.6 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:09 PM PDT 24
Peak memory 194256 kb
Host smart-8ac0bef3-ef0e-4b82-b92a-9f28a1324e14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293424400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4293424400
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.3091206181
Short name T68
Test name
Test status
Simulation time 17649449 ps
CPU time 0.78 seconds
Started Aug 02 05:22:09 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 197276 kb
Host smart-a146c79e-cad4-4209-a439-acf65f05baa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091206181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.3091206181
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1007479019
Short name T1182
Test name
Test status
Simulation time 1081058990 ps
CPU time 2.18 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 200444 kb
Host smart-953b7122-7a68-4343-846a-9d660783cdd9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007479019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1007479019
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.1542486097
Short name T1284
Test name
Test status
Simulation time 88220792 ps
CPU time 1.28 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 199736 kb
Host smart-de97a21f-a37e-4b1f-858c-a69422075b43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542486097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.1542486097
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.1903317069
Short name T1269
Test name
Test status
Simulation time 29763356 ps
CPU time 0.77 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:05 PM PDT 24
Peak memory 200248 kb
Host smart-cc8b8377-a98f-47d0-ba36-25e699be7d9a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903317069 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.1903317069
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.604251802
Short name T47
Test name
Test status
Simulation time 55037533 ps
CPU time 0.62 seconds
Started Aug 02 05:22:06 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 195524 kb
Host smart-859e2f94-07eb-42c7-8ea6-157fba0c89f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604251802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.604251802
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.3253715349
Short name T1239
Test name
Test status
Simulation time 41217849 ps
CPU time 0.57 seconds
Started Aug 02 05:22:10 PM PDT 24
Finished Aug 02 05:22:10 PM PDT 24
Peak memory 194812 kb
Host smart-c288fb1c-1479-4b41-a975-6d17b923b172
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253715349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.3253715349
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.3773898074
Short name T1251
Test name
Test status
Simulation time 58492290 ps
CPU time 0.67 seconds
Started Aug 02 05:22:11 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 197056 kb
Host smart-dfc79efe-d8e6-43d9-bc02-6bc6cad4dd6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773898074 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.3773898074
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.1056212097
Short name T1187
Test name
Test status
Simulation time 279647607 ps
CPU time 1.88 seconds
Started Aug 02 05:22:06 PM PDT 24
Finished Aug 02 05:22:08 PM PDT 24
Peak memory 200464 kb
Host smart-390a6cc6-ca84-448c-b36a-97fac42d6863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056212097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.1056212097
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.929301879
Short name T74
Test name
Test status
Simulation time 310646325 ps
CPU time 1.29 seconds
Started Aug 02 05:22:04 PM PDT 24
Finished Aug 02 05:22:06 PM PDT 24
Peak memory 199648 kb
Host smart-d46b332f-5426-4f6e-adef-89d6f229b331
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929301879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.929301879
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.4217865705
Short name T1250
Test name
Test status
Simulation time 84324357 ps
CPU time 1.26 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 200496 kb
Host smart-84ea41f7-83e1-43e7-9260-455ca6c9ead2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217865705 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.4217865705
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.190832182
Short name T51
Test name
Test status
Simulation time 57928982 ps
CPU time 0.59 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 195860 kb
Host smart-053f073c-ca37-470f-a2f5-f543d6d021e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190832182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.190832182
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1050019291
Short name T1224
Test name
Test status
Simulation time 82017486 ps
CPU time 0.54 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:12 PM PDT 24
Peak memory 194808 kb
Host smart-ecdfe365-e4b1-4350-94aa-88f247df68a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050019291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1050019291
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.3889291857
Short name T1233
Test name
Test status
Simulation time 19208581 ps
CPU time 0.77 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 197432 kb
Host smart-b2ad511d-4ed3-43ff-a8ca-e13f8295caf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889291857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.3889291857
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2332131381
Short name T1209
Test name
Test status
Simulation time 291189461 ps
CPU time 1.84 seconds
Started Aug 02 05:22:05 PM PDT 24
Finished Aug 02 05:22:07 PM PDT 24
Peak memory 200500 kb
Host smart-72a4f8a6-9f49-4d32-8224-b64ddc5c5bf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332131381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2332131381
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.4043017388
Short name T75
Test name
Test status
Simulation time 165461467 ps
CPU time 0.89 seconds
Started Aug 02 05:22:08 PM PDT 24
Finished Aug 02 05:22:09 PM PDT 24
Peak memory 199180 kb
Host smart-9e8d8024-d5df-4379-97f9-c573ebc60826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043017388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.4043017388
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.2262154237
Short name T1292
Test name
Test status
Simulation time 131930780 ps
CPU time 0.98 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 200216 kb
Host smart-03cf03e3-d1c6-4c58-81cc-755bed870fc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262154237 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.2262154237
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.469414762
Short name T1290
Test name
Test status
Simulation time 30701496 ps
CPU time 0.64 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 196000 kb
Host smart-b9255da7-98a1-4eb0-8bf2-a67f281cf801
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469414762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.469414762
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.2029949608
Short name T1316
Test name
Test status
Simulation time 11387016 ps
CPU time 0.58 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 194840 kb
Host smart-dc88c43d-9b67-4ac2-b671-fa014e7fc535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029949608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.2029949608
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.3958460530
Short name T1258
Test name
Test status
Simulation time 32563836 ps
CPU time 0.83 seconds
Started Aug 02 05:22:12 PM PDT 24
Finished Aug 02 05:22:13 PM PDT 24
Peak memory 196852 kb
Host smart-13c56635-dce3-48de-b086-2ca59ada8f1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958460530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.3958460530
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2250314171
Short name T1244
Test name
Test status
Simulation time 383624406 ps
CPU time 1.81 seconds
Started Aug 02 05:22:20 PM PDT 24
Finished Aug 02 05:22:22 PM PDT 24
Peak memory 200456 kb
Host smart-1d0bc281-243f-47d0-80cc-5fcfa113e37d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250314171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2250314171
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.3431429532
Short name T79
Test name
Test status
Simulation time 429981630 ps
CPU time 1.44 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 199856 kb
Host smart-38edf202-bfa1-49d1-8e91-64b0dc1becc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431429532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.3431429532
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.916933872
Short name T1185
Test name
Test status
Simulation time 21641444 ps
CPU time 0.77 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 199496 kb
Host smart-1ff9fc7a-5936-46b8-af70-b8c46894550c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916933872 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.916933872
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.4190320147
Short name T69
Test name
Test status
Simulation time 13170723 ps
CPU time 0.6 seconds
Started Aug 02 05:22:17 PM PDT 24
Finished Aug 02 05:22:18 PM PDT 24
Peak memory 195844 kb
Host smart-10a6bd0d-57aa-45c5-b6bd-603d8c2753fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190320147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.4190320147
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.3257847158
Short name T1315
Test name
Test status
Simulation time 29079155 ps
CPU time 0.59 seconds
Started Aug 02 05:22:14 PM PDT 24
Finished Aug 02 05:22:15 PM PDT 24
Peak memory 194824 kb
Host smart-8d12aaf8-3656-44ad-8dbe-07af8bfafccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257847158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.3257847158
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.2073402609
Short name T67
Test name
Test status
Simulation time 32354147 ps
CPU time 0.73 seconds
Started Aug 02 05:22:16 PM PDT 24
Finished Aug 02 05:22:17 PM PDT 24
Peak memory 197512 kb
Host smart-52b393b0-5dca-4a02-8aa4-2a6fae9276c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073402609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.2073402609
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2309363254
Short name T1215
Test name
Test status
Simulation time 30512913 ps
CPU time 1.49 seconds
Started Aug 02 05:22:13 PM PDT 24
Finished Aug 02 05:22:14 PM PDT 24
Peak memory 200468 kb
Host smart-0897d729-75a0-4da5-b3a4-327af4a272fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309363254 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2309363254
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.4204973262
Short name T81
Test name
Test status
Simulation time 126989615 ps
CPU time 1.3 seconds
Started Aug 02 05:22:15 PM PDT 24
Finished Aug 02 05:22:16 PM PDT 24
Peak memory 199824 kb
Host smart-36c28a68-f1b8-45a1-848a-f26d460fec0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204973262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.4204973262
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.305441825
Short name T1107
Test name
Test status
Simulation time 38341771 ps
CPU time 0.55 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 195420 kb
Host smart-ab8e2470-27aa-4a7e-97af-3420df800460
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305441825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.305441825
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.3708178761
Short name T461
Test name
Test status
Simulation time 87580103596 ps
CPU time 56.96 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 199880 kb
Host smart-bd274db6-a0a3-48fa-9b58-0ebc8c0d5574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708178761 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.3708178761
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.2176525416
Short name T86
Test name
Test status
Simulation time 75349456550 ps
CPU time 53.96 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 199760 kb
Host smart-48be7d21-2233-4759-8df7-9d51f14722cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176525416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.2176525416
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3978549662
Short name T495
Test name
Test status
Simulation time 30110296189 ps
CPU time 12.93 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 198356 kb
Host smart-26459bfb-c1a6-47bb-9b2f-abe887ead594
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978549662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3978549662
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.1641696279
Short name T73
Test name
Test status
Simulation time 123059685692 ps
CPU time 792.89 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:48:29 PM PDT 24
Peak memory 199888 kb
Host smart-118de07b-8c78-4104-87f2-7cbda41ad051
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1641696279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.1641696279
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.243711862
Short name T375
Test name
Test status
Simulation time 3635528877 ps
CPU time 2.91 seconds
Started Aug 02 05:35:09 PM PDT 24
Finished Aug 02 05:35:13 PM PDT 24
Peak memory 199552 kb
Host smart-34752172-5b6c-48af-8e18-b89379fa4852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243711862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.243711862
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_noise_filter.212382748
Short name T1126
Test name
Test status
Simulation time 8860148383 ps
CPU time 14.04 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:20 PM PDT 24
Peak memory 199864 kb
Host smart-5b2ec21f-ccb3-4ebf-befa-f5e47b995b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212382748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.212382748
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/0.uart_perf.236796287
Short name T346
Test name
Test status
Simulation time 14407516587 ps
CPU time 184.75 seconds
Started Aug 02 05:35:17 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 199992 kb
Host smart-a817dc07-3955-4908-9fea-cde6bf608d15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236796287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.236796287
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.2162883908
Short name T881
Test name
Test status
Simulation time 3062412865 ps
CPU time 12.47 seconds
Started Aug 02 05:35:15 PM PDT 24
Finished Aug 02 05:35:28 PM PDT 24
Peak memory 198908 kb
Host smart-af83a56e-61dd-4a8d-89ea-eb2fcc6cdcf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2162883908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.2162883908
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.163356519
Short name T936
Test name
Test status
Simulation time 189640830381 ps
CPU time 288.35 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:39:53 PM PDT 24
Peak memory 199908 kb
Host smart-78350753-624a-4839-8133-2a1dd30c9bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163356519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.163356519
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.430220652
Short name T356
Test name
Test status
Simulation time 3687930112 ps
CPU time 6.12 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:11 PM PDT 24
Peak memory 196136 kb
Host smart-336661e1-47ad-4009-9400-f4a907273267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430220652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.430220652
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_smoke.3149523624
Short name T361
Test name
Test status
Simulation time 739098800 ps
CPU time 3.55 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:19 PM PDT 24
Peak memory 199600 kb
Host smart-cbeac995-0edd-4a94-b957-b7c26dac064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149523624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.3149523624
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.3146741073
Short name T1071
Test name
Test status
Simulation time 42268266551 ps
CPU time 690.94 seconds
Started Aug 02 05:35:01 PM PDT 24
Finished Aug 02 05:46:32 PM PDT 24
Peak memory 216624 kb
Host smart-69d587f2-5979-4e28-9829-80189f4dab8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146741073 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.3146741073
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1228692175
Short name T466
Test name
Test status
Simulation time 927428792 ps
CPU time 2.65 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:23 PM PDT 24
Peak memory 198512 kb
Host smart-26efefc9-5d9e-4f67-bf3e-da6cdcb77954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228692175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1228692175
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.152556329
Short name T297
Test name
Test status
Simulation time 78480145884 ps
CPU time 24.36 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:35:50 PM PDT 24
Peak memory 199916 kb
Host smart-05473db4-d945-4940-8fae-07b1d1bebb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152556329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.152556329
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4284720932
Short name T487
Test name
Test status
Simulation time 35135173 ps
CPU time 0.6 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:03 PM PDT 24
Peak memory 195692 kb
Host smart-20741712-09ee-4960-9e84-1d9af7461389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284720932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4284720932
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.1196111895
Short name T120
Test name
Test status
Simulation time 21400007457 ps
CPU time 35.95 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:40 PM PDT 24
Peak memory 199896 kb
Host smart-a5d8720e-0f3a-43c0-a2dd-a19d233466bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196111895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.1196111895
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/1.uart_intr.2869042612
Short name T933
Test name
Test status
Simulation time 46504839904 ps
CPU time 24.43 seconds
Started Aug 02 05:35:19 PM PDT 24
Finished Aug 02 05:35:44 PM PDT 24
Peak memory 199748 kb
Host smart-f178151d-e751-4387-adca-4048044e6b07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869042612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.2869042612
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.1618711233
Short name T643
Test name
Test status
Simulation time 41327520150 ps
CPU time 263.13 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 199960 kb
Host smart-31386887-79db-4c1e-addf-f1db220288b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1618711233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.1618711233
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.2886948612
Short name T623
Test name
Test status
Simulation time 8332144389 ps
CPU time 8.25 seconds
Started Aug 02 05:35:08 PM PDT 24
Finished Aug 02 05:35:21 PM PDT 24
Peak memory 199344 kb
Host smart-8b7a54e6-1365-4d16-a754-e88765ca4146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886948612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.2886948612
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.2770538028
Short name T626
Test name
Test status
Simulation time 73480416732 ps
CPU time 61.04 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 208260 kb
Host smart-13a602b9-be07-4486-9c52-f96ae73e2818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770538028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.2770538028
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.2011045252
Short name T531
Test name
Test status
Simulation time 15065666026 ps
CPU time 416.99 seconds
Started Aug 02 05:35:18 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 200020 kb
Host smart-8a6a1dca-933b-4cb2-9034-a1c6c513ca40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2011045252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.2011045252
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.3523736441
Short name T712
Test name
Test status
Simulation time 1983721223 ps
CPU time 1.62 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 197932 kb
Host smart-d8cb7163-9cc4-4632-bc8a-a99a62b0b4b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523736441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.3523736441
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2589620194
Short name T831
Test name
Test status
Simulation time 10689532660 ps
CPU time 17.49 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 199928 kb
Host smart-0aa03dc9-922b-4559-860f-2e87f97696e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589620194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2589620194
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.4040130111
Short name T939
Test name
Test status
Simulation time 44237791676 ps
CPU time 34.97 seconds
Started Aug 02 05:35:05 PM PDT 24
Finished Aug 02 05:35:41 PM PDT 24
Peak memory 195924 kb
Host smart-5d45dff0-200d-4b6a-9c05-9f028b4f77bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040130111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.4040130111
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2719147371
Short name T26
Test name
Test status
Simulation time 136400804 ps
CPU time 0.83 seconds
Started Aug 02 05:35:14 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 218392 kb
Host smart-831c8da1-a49d-44e4-96d7-7ed011256ad4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719147371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2719147371
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.2460451355
Short name T357
Test name
Test status
Simulation time 645031288 ps
CPU time 1.58 seconds
Started Aug 02 05:35:24 PM PDT 24
Finished Aug 02 05:35:26 PM PDT 24
Peak memory 198796 kb
Host smart-cc1755f8-261a-455a-9d68-653a45a43a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460451355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.2460451355
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.419013648
Short name T945
Test name
Test status
Simulation time 1280949908 ps
CPU time 1.6 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:05 PM PDT 24
Peak memory 199580 kb
Host smart-f29e2095-1c4e-43cb-9d28-d87de37d89fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419013648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.419013648
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.1708047704
Short name T627
Test name
Test status
Simulation time 32383055316 ps
CPU time 47.81 seconds
Started Aug 02 05:35:00 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 199972 kb
Host smart-53d47ff8-d3b6-46ef-a7aa-b9a378344b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708047704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.1708047704
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_alert_test.4227208590
Short name T861
Test name
Test status
Simulation time 28913023 ps
CPU time 0.54 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 194720 kb
Host smart-5323216b-4a8a-4a2a-82bb-498395ee3c58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227208590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.4227208590
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/10.uart_fifo_full.866741118
Short name T267
Test name
Test status
Simulation time 110807594482 ps
CPU time 163.75 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:38:24 PM PDT 24
Peak memory 199988 kb
Host smart-150b9b5a-4eef-4d77-a09c-75d4ef2d21fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866741118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.866741118
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.3223028365
Short name T985
Test name
Test status
Simulation time 40472649563 ps
CPU time 16.99 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 199920 kb
Host smart-3331f012-0e9c-4cec-819d-586f31e67078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223028365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.3223028365
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.17130844
Short name T325
Test name
Test status
Simulation time 16811826614 ps
CPU time 55.02 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:36:26 PM PDT 24
Peak memory 199996 kb
Host smart-bc19433d-423a-4d87-804e-981c0288a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17130844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.17130844
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.1725789816
Short name T252
Test name
Test status
Simulation time 280062135598 ps
CPU time 540.23 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:44:43 PM PDT 24
Peak memory 199900 kb
Host smart-d605cb1e-1b87-4592-a82c-027bc3ab5a52
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725789816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.1725789816
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1559061887
Short name T1146
Test name
Test status
Simulation time 123837165514 ps
CPU time 220.21 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:39:32 PM PDT 24
Peak memory 199920 kb
Host smart-a911fb7a-05a3-44a2-891d-9f587914a9ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1559061887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1559061887
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.2310628847
Short name T397
Test name
Test status
Simulation time 6273566065 ps
CPU time 9.38 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:35:57 PM PDT 24
Peak memory 199784 kb
Host smart-c37534af-9d3f-4423-9a7f-5585c1fd8f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310628847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.2310628847
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.1895614120
Short name T723
Test name
Test status
Simulation time 150853069071 ps
CPU time 123.34 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:37:49 PM PDT 24
Peak memory 208120 kb
Host smart-2cde246f-6e38-42fe-950c-9923a7d9aa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895614120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.1895614120
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2955699307
Short name T543
Test name
Test status
Simulation time 24221719018 ps
CPU time 700.14 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:47:21 PM PDT 24
Peak memory 199960 kb
Host smart-66b495aa-f498-481d-ae8f-25175ec25182
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2955699307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2955699307
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.2843304482
Short name T732
Test name
Test status
Simulation time 7643134170 ps
CPU time 6.51 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 197796 kb
Host smart-fc5f675c-55f8-4c37-8776-da20ba810f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2843304482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.2843304482
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.339771426
Short name T246
Test name
Test status
Simulation time 301377774329 ps
CPU time 299.3 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:40:41 PM PDT 24
Peak memory 200040 kb
Host smart-b94521fc-84ee-493d-acc8-32c3e1e4378b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339771426 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.339771426
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3669514050
Short name T396
Test name
Test status
Simulation time 4557149403 ps
CPU time 6.66 seconds
Started Aug 02 05:35:30 PM PDT 24
Finished Aug 02 05:35:36 PM PDT 24
Peak memory 196304 kb
Host smart-5430a677-1729-4dce-81e9-4d0f6748e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669514050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3669514050
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.1772667319
Short name T1157
Test name
Test status
Simulation time 693306927 ps
CPU time 3.42 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 198912 kb
Host smart-6156ebf7-cdc9-4d90-9e74-8941cd7efd35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772667319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.1772667319
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.2085360624
Short name T1131
Test name
Test status
Simulation time 54054215437 ps
CPU time 102.1 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:37:32 PM PDT 24
Peak memory 199968 kb
Host smart-3cebaa51-59ff-423e-b2ae-589b62b9edb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085360624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.2085360624
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.3321806099
Short name T982
Test name
Test status
Simulation time 49138950264 ps
CPU time 208.95 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:39:14 PM PDT 24
Peak memory 208300 kb
Host smart-db9463e1-7ffa-4d22-b74d-b1c008ca6ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321806099 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.3321806099
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.477113398
Short name T272
Test name
Test status
Simulation time 842186239 ps
CPU time 3.04 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 199516 kb
Host smart-9187969c-e6f5-4c48-b6e2-af8593a86276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477113398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.477113398
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.3350261571
Short name T254
Test name
Test status
Simulation time 45534920987 ps
CPU time 176.65 seconds
Started Aug 02 05:35:30 PM PDT 24
Finished Aug 02 05:38:27 PM PDT 24
Peak memory 200012 kb
Host smart-fe93b108-1b09-4024-b573-58502dc38bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350261571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.3350261571
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.3747849505
Short name T192
Test name
Test status
Simulation time 130586774772 ps
CPU time 98.71 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 199812 kb
Host smart-fa0b4045-62e1-4cf1-9f7b-b2efd483baaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747849505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.3747849505
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.2746653092
Short name T144
Test name
Test status
Simulation time 123443623336 ps
CPU time 58.71 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199956 kb
Host smart-297d62dc-4d3c-4f57-aaa0-fd707d93a379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746653092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.2746653092
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.1262837591
Short name T1085
Test name
Test status
Simulation time 169729438792 ps
CPU time 43.77 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199976 kb
Host smart-ae53c5f9-eb22-4f7e-9a76-e9520e531bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262837591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.1262837591
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.827644699
Short name T378
Test name
Test status
Simulation time 12332553253 ps
CPU time 5.01 seconds
Started Aug 02 05:37:41 PM PDT 24
Finished Aug 02 05:37:47 PM PDT 24
Peak memory 199560 kb
Host smart-a46141fa-6b93-401d-9ba7-64057e41dbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827644699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.827644699
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.4101790679
Short name T516
Test name
Test status
Simulation time 25282848518 ps
CPU time 15.09 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:37:58 PM PDT 24
Peak memory 200020 kb
Host smart-f5d42545-5701-4fa5-9ec1-6fa989146474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101790679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.4101790679
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.1418863428
Short name T539
Test name
Test status
Simulation time 109206129676 ps
CPU time 54.85 seconds
Started Aug 02 05:37:46 PM PDT 24
Finished Aug 02 05:38:41 PM PDT 24
Peak memory 199584 kb
Host smart-c61257d3-c3de-4ada-b124-0e939f6e9a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418863428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.1418863428
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.2879367545
Short name T865
Test name
Test status
Simulation time 64752301498 ps
CPU time 51.73 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:38:35 PM PDT 24
Peak memory 199988 kb
Host smart-eecc376d-98b0-48bb-ab20-66f4974bbb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879367545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.2879367545
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.110975323
Short name T217
Test name
Test status
Simulation time 10886547189 ps
CPU time 17.23 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:01 PM PDT 24
Peak memory 199948 kb
Host smart-de7388a3-4234-49c5-9a85-16b5e2e58a9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110975323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.110975323
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.1570856664
Short name T725
Test name
Test status
Simulation time 25251126887 ps
CPU time 17.87 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:02 PM PDT 24
Peak memory 199972 kb
Host smart-1502fb86-a780-486c-9601-b434dc7d5fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570856664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.1570856664
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.3175633044
Short name T1040
Test name
Test status
Simulation time 11938474 ps
CPU time 0.52 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:35:44 PM PDT 24
Peak memory 194612 kb
Host smart-9c9670c7-ca9f-4716-838a-75a2e3957f6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175633044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.3175633044
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.2435041202
Short name T127
Test name
Test status
Simulation time 70976432316 ps
CPU time 102.51 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:37:35 PM PDT 24
Peak memory 199716 kb
Host smart-bd092015-014e-4de5-b8ba-2f1ad94f7f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435041202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.2435041202
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.3794197522
Short name T412
Test name
Test status
Simulation time 52842436346 ps
CPU time 53.15 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 199952 kb
Host smart-3625624e-ad43-48da-b324-ef164d62412d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794197522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.3794197522
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.4099998738
Short name T256
Test name
Test status
Simulation time 85948682696 ps
CPU time 173.42 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 199944 kb
Host smart-c0c797d8-72cb-462e-a616-8ea05c6aa1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099998738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.4099998738
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1284972510
Short name T317
Test name
Test status
Simulation time 5761557534 ps
CPU time 9.54 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 196908 kb
Host smart-8906b490-a1dd-48fd-9913-6da1a9a94595
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284972510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1284972510
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.2624286435
Short name T340
Test name
Test status
Simulation time 77450150957 ps
CPU time 166.54 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199908 kb
Host smart-1666ffcc-995e-481b-9768-00fa27757ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624286435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.2624286435
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2425874975
Short name T332
Test name
Test status
Simulation time 2589988075 ps
CPU time 2.54 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 198312 kb
Host smart-1c919fbf-d189-444f-b0fe-2693fc3ae9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425874975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2425874975
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.1862099518
Short name T302
Test name
Test status
Simulation time 89830415770 ps
CPU time 39.7 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 200140 kb
Host smart-5a1661cb-b898-4eb2-a445-f0d1c5b15840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862099518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.1862099518
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3403960323
Short name T1021
Test name
Test status
Simulation time 16092239847 ps
CPU time 728.38 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:48:00 PM PDT 24
Peak memory 199988 kb
Host smart-5e229b3f-baa1-44e5-8fad-c4fe43ddcec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3403960323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3403960323
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.2341650972
Short name T834
Test name
Test status
Simulation time 3821556086 ps
CPU time 8.59 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 197832 kb
Host smart-fe5285d0-2901-48bc-bed1-0001161d62c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341650972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.2341650972
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.373244550
Short name T762
Test name
Test status
Simulation time 228623379034 ps
CPU time 661.19 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:46:51 PM PDT 24
Peak memory 199940 kb
Host smart-486c6e03-5794-40ac-bee9-f6bccfb1e9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373244550 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.373244550
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.1641968627
Short name T698
Test name
Test status
Simulation time 5914494377 ps
CPU time 10.28 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:35:57 PM PDT 24
Peak memory 196140 kb
Host smart-6771e980-1322-4449-88d7-4b71acc47171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641968627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.1641968627
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.783578825
Short name T1013
Test name
Test status
Simulation time 5499990691 ps
CPU time 27.02 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:36:19 PM PDT 24
Peak memory 199540 kb
Host smart-fc2c4220-7be1-4be8-b323-cac3d22006a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783578825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.783578825
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all.3915497376
Short name T855
Test name
Test status
Simulation time 166275456211 ps
CPU time 67.79 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 200068 kb
Host smart-30b5246c-56c2-45fc-8968-243e63db2900
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915497376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.3915497376
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.4065378603
Short name T748
Test name
Test status
Simulation time 2284593654 ps
CPU time 1.83 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 198556 kb
Host smart-888de39b-1758-4288-b3e7-e5f8f521ac56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065378603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.4065378603
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.662139196
Short name T677
Test name
Test status
Simulation time 63181742481 ps
CPU time 63.63 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 199988 kb
Host smart-ab32dc23-3700-4789-bdc8-6a0403f4186e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662139196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.662139196
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.2798691048
Short name T91
Test name
Test status
Simulation time 16166745264 ps
CPU time 14.87 seconds
Started Aug 02 05:37:45 PM PDT 24
Finished Aug 02 05:38:00 PM PDT 24
Peak memory 199900 kb
Host smart-9cb7acb1-0554-4ef1-a310-f1d060eef1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798691048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.2798691048
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1607133890
Short name T320
Test name
Test status
Simulation time 18110027029 ps
CPU time 24.64 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:38:08 PM PDT 24
Peak memory 199776 kb
Host smart-500448aa-bd66-42ba-9790-81c557b5f923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607133890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1607133890
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.1132940090
Short name T904
Test name
Test status
Simulation time 122359148460 ps
CPU time 182.02 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:40:46 PM PDT 24
Peak memory 199936 kb
Host smart-3a060eaa-da07-43e8-8e36-ab799fd065ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132940090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.1132940090
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2029284355
Short name T183
Test name
Test status
Simulation time 24760072399 ps
CPU time 43.69 seconds
Started Aug 02 05:37:46 PM PDT 24
Finished Aug 02 05:38:30 PM PDT 24
Peak memory 199900 kb
Host smart-db1158cb-2db3-4f39-a069-bb7cc4fe910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029284355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2029284355
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.3046991806
Short name T718
Test name
Test status
Simulation time 15362852202 ps
CPU time 51.13 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199940 kb
Host smart-3f6b1376-79ac-46ee-8c3e-efa3152b45fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046991806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.3046991806
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.327190307
Short name T673
Test name
Test status
Simulation time 69766626858 ps
CPU time 91.56 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 200044 kb
Host smart-47efe4e1-8005-4535-8452-728b1a6e3dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327190307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.327190307
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.3487983410
Short name T2
Test name
Test status
Simulation time 51861179114 ps
CPU time 16.85 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:01 PM PDT 24
Peak memory 200052 kb
Host smart-9b641d83-2331-4db4-a079-d8ad77253d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487983410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.3487983410
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.1542219667
Short name T1104
Test name
Test status
Simulation time 26511586906 ps
CPU time 22.04 seconds
Started Aug 02 05:37:45 PM PDT 24
Finished Aug 02 05:38:07 PM PDT 24
Peak memory 199972 kb
Host smart-db91f1d5-0585-47b3-9150-da44c9a66f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542219667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.1542219667
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.1992950913
Short name T687
Test name
Test status
Simulation time 30427194427 ps
CPU time 50.25 seconds
Started Aug 02 05:37:42 PM PDT 24
Finished Aug 02 05:38:33 PM PDT 24
Peak memory 200012 kb
Host smart-e17746ab-e0a9-4cc2-95ac-904024dbec20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992950913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.1992950913
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.4283864858
Short name T1038
Test name
Test status
Simulation time 107333262 ps
CPU time 0.54 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 195652 kb
Host smart-10dc2114-d128-45bf-a33c-c70e27664df4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283864858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.4283864858
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2407653032
Short name T533
Test name
Test status
Simulation time 20865657391 ps
CPU time 6.65 seconds
Started Aug 02 05:35:32 PM PDT 24
Finished Aug 02 05:35:39 PM PDT 24
Peak memory 198460 kb
Host smart-966a56db-090e-46b3-9e17-0f8fbdd894a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407653032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2407653032
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.2903443454
Short name T160
Test name
Test status
Simulation time 220868830289 ps
CPU time 70.32 seconds
Started Aug 02 05:35:38 PM PDT 24
Finished Aug 02 05:36:49 PM PDT 24
Peak memory 199944 kb
Host smart-3c26c731-a61c-4cb8-aea3-13c95e0fd0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903443454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.2903443454
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.1843906124
Short name T1050
Test name
Test status
Simulation time 27258596581 ps
CPU time 11 seconds
Started Aug 02 05:35:45 PM PDT 24
Finished Aug 02 05:35:57 PM PDT 24
Peak memory 200012 kb
Host smart-77409e11-f8ac-45dc-ba00-b92b9d14fdfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843906124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.1843906124
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_intr.3187737825
Short name T1154
Test name
Test status
Simulation time 139110606439 ps
CPU time 205.67 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:39:13 PM PDT 24
Peak memory 199984 kb
Host smart-b8e47f49-5164-4401-a20b-46b222b435d6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187737825 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.3187737825
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.77333651
Short name T485
Test name
Test status
Simulation time 53023942905 ps
CPU time 320.18 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:40:57 PM PDT 24
Peak memory 199936 kb
Host smart-93b528d2-7f48-48d1-8c88-a67d604968c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=77333651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.77333651
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.2760301356
Short name T383
Test name
Test status
Simulation time 2470789361 ps
CPU time 4.51 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 198660 kb
Host smart-5dd40a1b-8ee5-4a65-b07d-54a38b06cd86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760301356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.2760301356
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.3755711442
Short name T101
Test name
Test status
Simulation time 116490036548 ps
CPU time 177.97 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:39:06 PM PDT 24
Peak memory 199732 kb
Host smart-e8f8bd5a-c9fd-4b4d-827c-7f1510af9e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755711442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.3755711442
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.4057493640
Short name T255
Test name
Test status
Simulation time 8402623067 ps
CPU time 113.9 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:37:42 PM PDT 24
Peak memory 199928 kb
Host smart-fa98d21a-643d-4e55-92f8-31d2f5accbbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057493640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.4057493640
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.910859170
Short name T943
Test name
Test status
Simulation time 4041280008 ps
CPU time 32.01 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 199168 kb
Host smart-a1399d77-3dc8-4bfe-af00-fba10c502488
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910859170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.910859170
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.4030267526
Short name T594
Test name
Test status
Simulation time 82422182985 ps
CPU time 17.89 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 199984 kb
Host smart-b5e74399-11e2-4151-a034-5b5af6ce5e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030267526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.4030267526
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.1287962127
Short name T417
Test name
Test status
Simulation time 2219610990 ps
CPU time 4.31 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 195532 kb
Host smart-6c5f0558-fcbc-47d4-af74-93de36357193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287962127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.1287962127
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.696928062
Short name T711
Test name
Test status
Simulation time 881439203 ps
CPU time 1.21 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 198512 kb
Host smart-1c9db9a6-5f56-46d3-8097-9a32d5f3c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696928062 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.696928062
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.1445344818
Short name T1046
Test name
Test status
Simulation time 19842803898 ps
CPU time 10.09 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 200004 kb
Host smart-ea03f489-93ad-46a2-8080-952097ab76ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445344818 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.1445344818
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.849500372
Short name T843
Test name
Test status
Simulation time 851692752434 ps
CPU time 1595.5 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 06:02:17 PM PDT 24
Peak memory 233028 kb
Host smart-27a77867-882a-4020-86fa-72c76057e561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849500372 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.849500372
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.3509278337
Short name T635
Test name
Test status
Simulation time 6949581601 ps
CPU time 11.92 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:53 PM PDT 24
Peak memory 199984 kb
Host smart-7ee40a11-fd34-4800-9395-5ae5e4f76a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509278337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.3509278337
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.1448857975
Short name T431
Test name
Test status
Simulation time 8308868115 ps
CPU time 14.15 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 196908 kb
Host smart-db7c0af3-0c98-4c4f-a41a-bb33c545c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448857975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.1448857975
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.2035017032
Short name T766
Test name
Test status
Simulation time 146614936858 ps
CPU time 17.35 seconds
Started Aug 02 05:37:42 PM PDT 24
Finished Aug 02 05:37:59 PM PDT 24
Peak memory 198992 kb
Host smart-cc6ed69f-3252-48ea-94ec-b2c734895df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035017032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.2035017032
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.2223205011
Short name T1084
Test name
Test status
Simulation time 191048718250 ps
CPU time 49.38 seconds
Started Aug 02 05:37:41 PM PDT 24
Finished Aug 02 05:38:31 PM PDT 24
Peak memory 200016 kb
Host smart-55498826-47a0-40cd-b43d-fe9a9493b6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223205011 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.2223205011
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.2297788301
Short name T637
Test name
Test status
Simulation time 20349597245 ps
CPU time 35.75 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:20 PM PDT 24
Peak memory 199908 kb
Host smart-a156a435-62f4-47ed-ac2d-76fe2c80f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297788301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.2297788301
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1064064913
Short name T808
Test name
Test status
Simulation time 88112920309 ps
CPU time 119.02 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:39:43 PM PDT 24
Peak memory 199984 kb
Host smart-e41277a2-d8e2-4cb8-9f40-2b406a764625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064064913 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1064064913
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.4048044056
Short name T926
Test name
Test status
Simulation time 302584491274 ps
CPU time 100.73 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 199940 kb
Host smart-866f422b-3c6f-47ec-89e7-adbe7fa3e4ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048044056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.4048044056
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.3018592448
Short name T248
Test name
Test status
Simulation time 169721458964 ps
CPU time 125.58 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:39:48 PM PDT 24
Peak memory 199952 kb
Host smart-268a0430-5a43-40da-9e73-640e7e912611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018592448 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.3018592448
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.13897873
Short name T151
Test name
Test status
Simulation time 54641722913 ps
CPU time 17.7 seconds
Started Aug 02 05:37:43 PM PDT 24
Finished Aug 02 05:38:01 PM PDT 24
Peak memory 199976 kb
Host smart-2349d99e-a2e9-4b7c-9d4f-9a3ad1e6beea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13897873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.13897873
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.1166138169
Short name T870
Test name
Test status
Simulation time 22833500 ps
CPU time 0.52 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 195632 kb
Host smart-9f8f26bf-e963-42d3-aef7-e65ff58c756b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166138169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.1166138169
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.2952485058
Short name T887
Test name
Test status
Simulation time 153233494766 ps
CPU time 205.69 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:39:22 PM PDT 24
Peak memory 199940 kb
Host smart-3fc1a548-2776-472c-bd47-92265e822710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952485058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.2952485058
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.1402801043
Short name T1051
Test name
Test status
Simulation time 20775068367 ps
CPU time 32.18 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 199728 kb
Host smart-e194aeed-a90d-4ec2-92e5-7bfd6e1d9126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402801043 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.1402801043
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1234994749
Short name T980
Test name
Test status
Simulation time 79584526506 ps
CPU time 121.99 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:37:52 PM PDT 24
Peak memory 199884 kb
Host smart-7a8f4a14-94e9-4271-8efc-920d5fcec146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234994749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1234994749
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.307483269
Short name T990
Test name
Test status
Simulation time 25799853630 ps
CPU time 17.61 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 199900 kb
Host smart-d6c4fd72-c870-4dc7-a09b-ffc6a5b2c286
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307483269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.307483269
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1763763187
Short name T351
Test name
Test status
Simulation time 129781861137 ps
CPU time 289.62 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:40:38 PM PDT 24
Peak memory 199900 kb
Host smart-8d12a768-81ee-4f8e-a7c3-7ad740732628
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1763763187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1763763187
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1351351420
Short name T889
Test name
Test status
Simulation time 13597705871 ps
CPU time 11.07 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 199904 kb
Host smart-8047e85e-4d39-4024-b99f-3c0e29a22fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351351420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1351351420
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.588861284
Short name T1139
Test name
Test status
Simulation time 77030161328 ps
CPU time 29.79 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 200068 kb
Host smart-838f289f-4dfd-4651-8334-ced3f2e39c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588861284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.588861284
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.829860086
Short name T526
Test name
Test status
Simulation time 24380610267 ps
CPU time 328.04 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:41:27 PM PDT 24
Peak memory 200012 kb
Host smart-30d6f1fc-dc09-419a-94c5-a07b56c289dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=829860086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.829860086
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.460435728
Short name T642
Test name
Test status
Simulation time 5066855023 ps
CPU time 5.79 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 198184 kb
Host smart-eb37fbff-fc51-468d-8d17-ad9e13e9cbc7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=460435728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.460435728
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.3605929805
Short name T780
Test name
Test status
Simulation time 106693843317 ps
CPU time 45.3 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:36:38 PM PDT 24
Peak memory 199996 kb
Host smart-41fc3fee-c4e5-439f-9256-17574ac8ee55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605929805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.3605929805
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1726496176
Short name T265
Test name
Test status
Simulation time 4820322151 ps
CPU time 2.42 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 196540 kb
Host smart-55277d73-8eee-4491-8057-2707528cfc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726496176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1726496176
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.4289554877
Short name T1053
Test name
Test status
Simulation time 949040119 ps
CPU time 1.5 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:35:55 PM PDT 24
Peak memory 199568 kb
Host smart-3c78ad78-4a0e-45c3-953d-fbac0c1cf221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289554877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.4289554877
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.3619305441
Short name T1008
Test name
Test status
Simulation time 498926677032 ps
CPU time 246.69 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:40:05 PM PDT 24
Peak memory 199992 kb
Host smart-4a6c669e-ec63-4c17-a4bf-06c0c6135143
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619305441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.3619305441
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.2013868275
Short name T98
Test name
Test status
Simulation time 42804956689 ps
CPU time 382.03 seconds
Started Aug 02 05:35:45 PM PDT 24
Finished Aug 02 05:42:08 PM PDT 24
Peak memory 216452 kb
Host smart-473c5084-ae9a-4e2c-9896-f82816d9d5d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013868275 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.2013868275
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.264952184
Short name T624
Test name
Test status
Simulation time 7591598040 ps
CPU time 9.01 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 199124 kb
Host smart-cbddb091-9ff4-419f-9394-612f2d7d661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264952184 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.264952184
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/13.uart_tx_rx.876403697
Short name T291
Test name
Test status
Simulation time 63962390385 ps
CPU time 95.97 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:37:16 PM PDT 24
Peak memory 200012 kb
Host smart-bfffa142-5ac6-4af3-8b44-540ab016ec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876403697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.876403697
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.3196082902
Short name T1004
Test name
Test status
Simulation time 39017983579 ps
CPU time 66.82 seconds
Started Aug 02 05:37:41 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 199964 kb
Host smart-92377be5-3173-44d3-865d-61294a207854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196082902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.3196082902
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.1502852721
Short name T1005
Test name
Test status
Simulation time 57912886752 ps
CPU time 21.35 seconds
Started Aug 02 05:37:44 PM PDT 24
Finished Aug 02 05:38:05 PM PDT 24
Peak memory 199968 kb
Host smart-42ee2724-3db5-41b1-87e9-cfb965fd3896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502852721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.1502852721
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.457529337
Short name T530
Test name
Test status
Simulation time 12745718726 ps
CPU time 21.36 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:16 PM PDT 24
Peak memory 200044 kb
Host smart-e81bb69f-e326-4cf8-900b-8607d2afa594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457529337 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.457529337
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.3909925033
Short name T1137
Test name
Test status
Simulation time 139370451767 ps
CPU time 106.33 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 200028 kb
Host smart-b8b4eb80-f8ee-41bb-b4b0-c09660081aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909925033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.3909925033
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.1461100996
Short name T125
Test name
Test status
Simulation time 116559160483 ps
CPU time 164.35 seconds
Started Aug 02 05:37:53 PM PDT 24
Finished Aug 02 05:40:38 PM PDT 24
Peak memory 200048 kb
Host smart-94ef190b-3756-4de0-88fa-b2170e6fa92e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461100996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.1461100996
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.2609316740
Short name T209
Test name
Test status
Simulation time 29294238385 ps
CPU time 18.02 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:12 PM PDT 24
Peak memory 199984 kb
Host smart-43846e9b-c5b8-47a3-b04a-3971e079b295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609316740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.2609316740
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.426733757
Short name T1128
Test name
Test status
Simulation time 283326555690 ps
CPU time 123.69 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:39:58 PM PDT 24
Peak memory 199968 kb
Host smart-27c86bcb-483a-48ce-a4bb-384dad7232cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426733757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.426733757
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.1498936158
Short name T1164
Test name
Test status
Simulation time 55686848 ps
CPU time 0.55 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 195360 kb
Host smart-49f28297-dd28-4ff1-92f3-1c7beb24e09c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498936158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.1498936158
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1807960999
Short name T513
Test name
Test status
Simulation time 40113497860 ps
CPU time 34.83 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:36:19 PM PDT 24
Peak memory 199904 kb
Host smart-0cb310a4-ead5-4f48-80d9-f4167c23d52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807960999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1807960999
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.1694292686
Short name T282
Test name
Test status
Simulation time 86017102617 ps
CPU time 46.22 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 199960 kb
Host smart-7f100c44-9587-40af-86a8-01e4da98ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694292686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.1694292686
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.3672279742
Short name T591
Test name
Test status
Simulation time 72231916211 ps
CPU time 52.52 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:54 PM PDT 24
Peak memory 199980 kb
Host smart-b5f70177-ef3b-42d7-9e99-408d7a83f2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672279742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.3672279742
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.3988615853
Short name T1063
Test name
Test status
Simulation time 143252669165 ps
CPU time 106.17 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 195888 kb
Host smart-9ccf2cc5-5fd7-4169-8393-bba97687c3b2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988615853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.3988615853
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.120741400
Short name T348
Test name
Test status
Simulation time 140057702858 ps
CPU time 202.84 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:39:22 PM PDT 24
Peak memory 199984 kb
Host smart-5c6d4da9-501c-46e7-8d3d-1691083a5d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=120741400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.120741400
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2358279482
Short name T822
Test name
Test status
Simulation time 3644000683 ps
CPU time 13.32 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 199788 kb
Host smart-cb39cb00-0ca4-4d96-97ff-ec4cf6ab8903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358279482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2358279482
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_noise_filter.909579346
Short name T1083
Test name
Test status
Simulation time 33333143004 ps
CPU time 32.6 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 200068 kb
Host smart-634174ac-aae3-41a8-97b5-3b3f8b5de522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909579346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_noise_filter.909579346
Directory /workspace/14.uart_noise_filter/latest

Test location /workspace/coverage/default/14.uart_perf.19502625
Short name T734
Test name
Test status
Simulation time 5386924007 ps
CPU time 315.3 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:41:06 PM PDT 24
Peak memory 199992 kb
Host smart-16a3be16-77a2-4688-acb7-7bf341761328
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19502625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.19502625
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.2527537551
Short name T408
Test name
Test status
Simulation time 6781738153 ps
CPU time 15.86 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 198128 kb
Host smart-93c97ea8-66ce-4c4a-a01d-9a1bcaa4c205
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2527537551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.2527537551
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.760439622
Short name T448
Test name
Test status
Simulation time 193790089914 ps
CPU time 515.18 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:44:26 PM PDT 24
Peak memory 199912 kb
Host smart-1cd26004-f46b-4319-89fb-ec619e1bbe8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760439622 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.760439622
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.3238158637
Short name T446
Test name
Test status
Simulation time 5978579901 ps
CPU time 9.7 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 196124 kb
Host smart-6c70c6ac-2ecb-4aaf-a774-5ba9b490c327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238158637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.3238158637
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.283233456
Short name T1091
Test name
Test status
Simulation time 335850396 ps
CPU time 1.21 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 198824 kb
Host smart-26ade60f-8d2c-405b-9817-5c4d037093d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283233456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.283233456
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.2441379182
Short name T1065
Test name
Test status
Simulation time 216663015007 ps
CPU time 123.42 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 200000 kb
Host smart-4f27f83b-7404-4d7b-bfe8-730d7423bec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441379182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.2441379182
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1198873781
Short name T312
Test name
Test status
Simulation time 80594245305 ps
CPU time 698.41 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:47:23 PM PDT 24
Peak memory 216504 kb
Host smart-19cdf7eb-b00d-4603-85ba-612b82c434ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198873781 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1198873781
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1415093196
Short name T1155
Test name
Test status
Simulation time 639103572 ps
CPU time 2.88 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:35:47 PM PDT 24
Peak memory 198972 kb
Host smart-cca41ab7-869e-4c2a-865e-47acb0cd6ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415093196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1415093196
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.3350135093
Short name T737
Test name
Test status
Simulation time 59671154773 ps
CPU time 27.19 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:24 PM PDT 24
Peak memory 199824 kb
Host smart-ead83c62-0b97-4fc8-99e6-da7c76bef561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350135093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.3350135093
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1923888152
Short name T709
Test name
Test status
Simulation time 18650958016 ps
CPU time 28.72 seconds
Started Aug 02 05:37:57 PM PDT 24
Finished Aug 02 05:38:25 PM PDT 24
Peak memory 199920 kb
Host smart-67998822-6a75-48eb-b050-0c2c24d1fdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923888152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1923888152
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.1912287808
Short name T224
Test name
Test status
Simulation time 227807563270 ps
CPU time 90.8 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 200008 kb
Host smart-64110766-0c7f-45e0-a192-856cce8453c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912287808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.1912287808
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.1115352580
Short name T440
Test name
Test status
Simulation time 103496600413 ps
CPU time 45.3 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:39 PM PDT 24
Peak memory 199948 kb
Host smart-ffdcb2d0-86d6-4d4a-9039-d41927040278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115352580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.1115352580
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2988847900
Short name T925
Test name
Test status
Simulation time 80439495656 ps
CPU time 125.1 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:40:00 PM PDT 24
Peak memory 199952 kb
Host smart-250057d4-aa3b-43ed-8df7-8f3592b37bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988847900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2988847900
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.325003679
Short name T989
Test name
Test status
Simulation time 156124658563 ps
CPU time 265.06 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:42:21 PM PDT 24
Peak memory 199892 kb
Host smart-39d18720-45bb-4077-9e15-0e594011cd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325003679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.325003679
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1640207057
Short name T695
Test name
Test status
Simulation time 116746320493 ps
CPU time 33.1 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 199596 kb
Host smart-27985205-dfae-4024-a455-667a86bb8862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640207057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1640207057
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.697000909
Short name T176
Test name
Test status
Simulation time 21241597161 ps
CPU time 32.54 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:27 PM PDT 24
Peak memory 199928 kb
Host smart-943ae9a7-9648-4ed6-bff4-82b761d3688f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697000909 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.697000909
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.20874876
Short name T777
Test name
Test status
Simulation time 95082554308 ps
CPU time 42.53 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 199908 kb
Host smart-9956cfaa-82ed-41ee-93cb-6c08be69865f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20874876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.20874876
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.464321367
Short name T1136
Test name
Test status
Simulation time 36246998906 ps
CPU time 16.05 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:10 PM PDT 24
Peak memory 200004 kb
Host smart-f406d8e7-93e2-41e8-9c28-9f2e1db2a6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464321367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.464321367
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.1946707072
Short name T768
Test name
Test status
Simulation time 36759444 ps
CPU time 0.58 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 195608 kb
Host smart-53847379-73ce-4996-8d2c-d5254052077f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946707072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.1946707072
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.2987222934
Short name T628
Test name
Test status
Simulation time 119212242478 ps
CPU time 39.27 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:40 PM PDT 24
Peak memory 199908 kb
Host smart-bdd4c7a7-45c3-481f-8411-be68dd2d9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987222934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.2987222934
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2451746881
Short name T802
Test name
Test status
Simulation time 35467235994 ps
CPU time 54.72 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:36:38 PM PDT 24
Peak memory 199724 kb
Host smart-faa3f06d-e35f-4446-b277-7af4c88fa001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451746881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2451746881
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.3422208242
Short name T1062
Test name
Test status
Simulation time 92873819191 ps
CPU time 32.57 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 200012 kb
Host smart-42c8f0c6-4220-4d68-9709-35ee49459778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422208242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.3422208242
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.291922837
Short name T534
Test name
Test status
Simulation time 47800129664 ps
CPU time 22.59 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 200016 kb
Host smart-5b5cdaa6-a99a-40ca-91f2-3af649e7a69e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291922837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.291922837
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.1204793835
Short name T411
Test name
Test status
Simulation time 55230196596 ps
CPU time 589.27 seconds
Started Aug 02 05:35:50 PM PDT 24
Finished Aug 02 05:45:40 PM PDT 24
Peak memory 199952 kb
Host smart-f20192e2-ce87-4224-ad04-a7cf11f20a19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1204793835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.1204793835
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.1451199641
Short name T967
Test name
Test status
Simulation time 5030299672 ps
CPU time 5.26 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:04 PM PDT 24
Peak memory 198936 kb
Host smart-2c336507-5cf1-49fb-8267-287bc6dcc367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451199641 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.1451199641
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.1600785921
Short name T1049
Test name
Test status
Simulation time 62817089213 ps
CPU time 51.61 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 198488 kb
Host smart-a08ea614-44da-4560-b3d9-57192985a73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600785921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.1600785921
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.2083789922
Short name T864
Test name
Test status
Simulation time 25766057082 ps
CPU time 1428.93 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:59:37 PM PDT 24
Peak memory 200020 kb
Host smart-9f9976df-843c-4564-af5f-dbe84e688e09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083789922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.2083789922
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.750766274
Short name T691
Test name
Test status
Simulation time 5199540415 ps
CPU time 38.29 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 198628 kb
Host smart-1aad8ce7-cbcc-47ff-93ef-f8fb01952b3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=750766274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.750766274
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1545636753
Short name T597
Test name
Test status
Simulation time 14886161373 ps
CPU time 7.31 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:35:49 PM PDT 24
Peak memory 199756 kb
Host smart-a8b2bc12-5cb2-43ef-a299-7a26e26e604a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545636753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1545636753
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.2799887395
Short name T668
Test name
Test status
Simulation time 1811080495 ps
CPU time 2 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 195448 kb
Host smart-8f78691b-b92f-401a-81c1-98dd947604fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799887395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.2799887395
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.645504601
Short name T1121
Test name
Test status
Simulation time 5763144445 ps
CPU time 8.91 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 199160 kb
Host smart-4bc8f939-7614-4f72-baab-8d2c05fb4110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645504601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.645504601
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.539451836
Short name T153
Test name
Test status
Simulation time 36883893912 ps
CPU time 28.33 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 199916 kb
Host smart-8762e09c-f76e-461b-8da6-eead9896e6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539451836 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.539451836
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.2816513378
Short name T1024
Test name
Test status
Simulation time 2270176568 ps
CPU time 1.59 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 198680 kb
Host smart-94794465-975c-4300-afc9-887d46df523d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816513378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.2816513378
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3144421023
Short name T948
Test name
Test status
Simulation time 63550495520 ps
CPU time 176.24 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:38:55 PM PDT 24
Peak memory 199980 kb
Host smart-02d3129b-ef5b-4e52-a3f9-7c9dba4c6989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144421023 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3144421023
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.88021391
Short name T739
Test name
Test status
Simulation time 136662883162 ps
CPU time 20.65 seconds
Started Aug 02 05:37:58 PM PDT 24
Finished Aug 02 05:38:19 PM PDT 24
Peak memory 199956 kb
Host smart-c7fe9990-4f64-45b7-ba3c-ec47c538c8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88021391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.88021391
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.1903815798
Short name T984
Test name
Test status
Simulation time 117054483942 ps
CPU time 78.23 seconds
Started Aug 02 05:37:52 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 199984 kb
Host smart-270794c0-94ea-4d94-a3b1-e3c7315189ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903815798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.1903815798
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.2662793647
Short name T92
Test name
Test status
Simulation time 97012194213 ps
CPU time 32.89 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199916 kb
Host smart-6ce3e652-59d5-4ca3-93bd-8da1f16c4f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662793647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.2662793647
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.1473353129
Short name T1161
Test name
Test status
Simulation time 22114468338 ps
CPU time 9.85 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:04 PM PDT 24
Peak memory 199908 kb
Host smart-ee894e92-b570-4ff8-b59d-87a9274a0bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473353129 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.1473353129
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.2874964530
Short name T109
Test name
Test status
Simulation time 117041302435 ps
CPU time 44.76 seconds
Started Aug 02 05:37:57 PM PDT 24
Finished Aug 02 05:38:42 PM PDT 24
Peak memory 199904 kb
Host smart-843c3e26-e513-4a12-82db-28c16810ca2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874964530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.2874964530
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.1960047627
Short name T753
Test name
Test status
Simulation time 96323498635 ps
CPU time 95 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 199976 kb
Host smart-a31ccce4-f88b-4bf0-a223-560018190896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960047627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.1960047627
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1432446750
Short name T606
Test name
Test status
Simulation time 27972533229 ps
CPU time 12.43 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:08 PM PDT 24
Peak memory 199984 kb
Host smart-3377672b-6ee7-416c-8005-178a6c7ebe0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432446750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1432446750
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.2222918980
Short name T382
Test name
Test status
Simulation time 13968066 ps
CPU time 0.56 seconds
Started Aug 02 05:36:04 PM PDT 24
Finished Aug 02 05:36:04 PM PDT 24
Peak memory 195680 kb
Host smart-51a0508c-3bdd-4233-9a09-e302b193b89a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222918980 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.2222918980
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.395935288
Short name T496
Test name
Test status
Simulation time 20350149706 ps
CPU time 36.24 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 199980 kb
Host smart-86595b78-f7f2-490b-bd78-16321e72dde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395935288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.395935288
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.3906162893
Short name T859
Test name
Test status
Simulation time 14846884590 ps
CPU time 14.63 seconds
Started Aug 02 05:35:48 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 200000 kb
Host smart-951f3b2c-e984-43ad-a852-74bfaf897525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906162893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.3906162893
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_intr.4034118392
Short name T867
Test name
Test status
Simulation time 28678763940 ps
CPU time 28.13 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:36:24 PM PDT 24
Peak memory 200000 kb
Host smart-c10cfcea-ab8d-45f7-9bf1-7264d0364f8f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034118392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.4034118392
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.132850364
Short name T578
Test name
Test status
Simulation time 35257575769 ps
CPU time 156.42 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:38:30 PM PDT 24
Peak memory 200000 kb
Host smart-eb0d69ad-d886-475a-9a81-546bb2b1cecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132850364 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.132850364
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1382139542
Short name T1113
Test name
Test status
Simulation time 5170759213 ps
CPU time 9.01 seconds
Started Aug 02 05:35:42 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 197268 kb
Host smart-99a53dfa-e844-4c55-98f6-5e8cb046218c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382139542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1382139542
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.3450440202
Short name T1106
Test name
Test status
Simulation time 17831359378 ps
CPU time 16.66 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 200084 kb
Host smart-fdd9775a-98fc-410c-b0d4-ea55420118f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450440202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.3450440202
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2376322851
Short name T452
Test name
Test status
Simulation time 7810578990 ps
CPU time 177.23 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:38:54 PM PDT 24
Peak memory 199980 kb
Host smart-481783ec-3875-43ee-9705-b2bc6e9c9ea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376322851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2376322851
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.1957429851
Short name T1099
Test name
Test status
Simulation time 4270030649 ps
CPU time 2.38 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 198132 kb
Host smart-0427c80f-2997-4448-a869-6cb3fc5a84fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1957429851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.1957429851
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.2394379604
Short name T839
Test name
Test status
Simulation time 62758029671 ps
CPU time 48.86 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:36:42 PM PDT 24
Peak memory 199788 kb
Host smart-312c9bf6-c15d-4656-981b-042d345ceb39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394379604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.2394379604
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.224543905
Short name T706
Test name
Test status
Simulation time 5208695474 ps
CPU time 2.78 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 196564 kb
Host smart-bb4a05e1-1692-4e31-86da-92471d33dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224543905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.224543905
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.1115149061
Short name T815
Test name
Test status
Simulation time 5491185600 ps
CPU time 6.61 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 199728 kb
Host smart-d99e625a-92df-4579-89dc-fed52d3237b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115149061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.1115149061
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.837824434
Short name T329
Test name
Test status
Simulation time 148732585293 ps
CPU time 108.74 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:37:43 PM PDT 24
Peak memory 199936 kb
Host smart-8900df6a-019d-42fd-87a4-6830dcd9541c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837824434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.837824434
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.4057870430
Short name T890
Test name
Test status
Simulation time 388491789763 ps
CPU time 698.48 seconds
Started Aug 02 05:36:05 PM PDT 24
Finished Aug 02 05:47:43 PM PDT 24
Peak memory 224780 kb
Host smart-13ab442f-261d-4bfb-8e61-042f1accb455
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057870430 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.4057870430
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.1439660632
Short name T499
Test name
Test status
Simulation time 324058414 ps
CPU time 1.8 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 198776 kb
Host smart-97806e39-418a-4941-83ce-652e61ba31b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439660632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.1439660632
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1961674460
Short name T676
Test name
Test status
Simulation time 18756721319 ps
CPU time 8.98 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 199852 kb
Host smart-1cf8be27-9e6c-49b6-b2f8-b47c15a747aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961674460 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1961674460
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.303042725
Short name T1012
Test name
Test status
Simulation time 56476036666 ps
CPU time 133.99 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:40:10 PM PDT 24
Peak memory 199952 kb
Host smart-951e1424-94ee-4cc4-b764-268b05f254e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303042725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.303042725
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.594595782
Short name T9
Test name
Test status
Simulation time 157312685547 ps
CPU time 313.62 seconds
Started Aug 02 05:37:58 PM PDT 24
Finished Aug 02 05:43:11 PM PDT 24
Peak memory 199960 kb
Host smart-38b7e6ab-c538-4383-9a3b-b7d467bc1b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594595782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.594595782
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.3634443864
Short name T470
Test name
Test status
Simulation time 115313500323 ps
CPU time 21.85 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 199936 kb
Host smart-67509f66-813d-46bf-a0d3-259a855dc3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634443864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.3634443864
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.1612567040
Short name T830
Test name
Test status
Simulation time 17786590758 ps
CPU time 28.22 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:23 PM PDT 24
Peak memory 199900 kb
Host smart-ea6c6a57-45c7-406d-949f-5f57080fb1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612567040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.1612567040
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.2417651567
Short name T953
Test name
Test status
Simulation time 19051238352 ps
CPU time 8.55 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:05 PM PDT 24
Peak memory 199904 kb
Host smart-7fb30ffa-789b-4e3a-b3a5-74ebeacf183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417651567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.2417651567
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.2832199206
Short name T191
Test name
Test status
Simulation time 75601029625 ps
CPU time 18.88 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:15 PM PDT 24
Peak memory 199672 kb
Host smart-70ccfa28-0018-430e-8d29-3f3ca73850da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832199206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.2832199206
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3221115696
Short name T55
Test name
Test status
Simulation time 36044155828 ps
CPU time 52.38 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 199948 kb
Host smart-a3e54815-1574-401e-9552-57da028dcbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221115696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3221115696
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.1125981131
Short name T338
Test name
Test status
Simulation time 106404066 ps
CPU time 0.56 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 195388 kb
Host smart-7cee12f2-9768-49e7-80d7-0ec7f6650f2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125981131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.1125981131
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.3454862924
Short name T476
Test name
Test status
Simulation time 34607401775 ps
CPU time 30.22 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 199888 kb
Host smart-c28efd46-557e-47af-a067-3962ba01d477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454862924 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.3454862924
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2215288263
Short name T500
Test name
Test status
Simulation time 46989226849 ps
CPU time 79.34 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:37:15 PM PDT 24
Peak memory 200004 kb
Host smart-8aac06ee-242f-489b-b6ee-2ef5341946dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215288263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2215288263
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.1767310782
Short name T196
Test name
Test status
Simulation time 40156503823 ps
CPU time 13.97 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:10 PM PDT 24
Peak memory 199916 kb
Host smart-b3cecc77-667a-4b7d-b384-ed6efdd62855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767310782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.1767310782
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.2201652458
Short name T941
Test name
Test status
Simulation time 38040192667 ps
CPU time 67.56 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 199752 kb
Host smart-f19fe7bf-636d-4eb9-beb0-6c98ecd9922a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201652458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.2201652458
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.1503461521
Short name T679
Test name
Test status
Simulation time 138489180019 ps
CPU time 329.75 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:41:23 PM PDT 24
Peak memory 200008 kb
Host smart-32dc0f62-61b3-4e8a-b669-04a7214b390a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503461521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.1503461521
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.3530773901
Short name T1100
Test name
Test status
Simulation time 1273699634 ps
CPU time 4.03 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 198428 kb
Host smart-422de4c7-75d5-493c-86f6-134138d491bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530773901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.3530773901
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.490007458
Short name T1048
Test name
Test status
Simulation time 12019131393 ps
CPU time 12.33 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 197648 kb
Host smart-e6657d78-c3b4-4d60-a992-d644ea8427e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490007458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.490007458
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.1457863128
Short name T1006
Test name
Test status
Simulation time 23012140247 ps
CPU time 326.73 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:41:23 PM PDT 24
Peak memory 199964 kb
Host smart-10e8bc57-db43-43cc-9101-aba46bf92c93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1457863128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.1457863128
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.593685519
Short name T618
Test name
Test status
Simulation time 6329096698 ps
CPU time 55.93 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:55 PM PDT 24
Peak memory 198944 kb
Host smart-23bf99f5-d967-4777-a317-9b73c7eff2ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=593685519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.593685519
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.3589850858
Short name T567
Test name
Test status
Simulation time 44200066482 ps
CPU time 95.29 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:37:27 PM PDT 24
Peak memory 199920 kb
Host smart-29fb30d9-2611-4bcb-aa7c-3cfb60fafaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589850858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.3589850858
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.1447213036
Short name T966
Test name
Test status
Simulation time 40665889364 ps
CPU time 17.16 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 195788 kb
Host smart-bb7f7c6c-9245-4407-907e-6d1a63426884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447213036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.1447213036
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.3931320146
Short name T289
Test name
Test status
Simulation time 695986338 ps
CPU time 2.64 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 199332 kb
Host smart-0d9b65ca-77b0-4267-8989-b039722b4c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931320146 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.3931320146
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.3480730692
Short name T434
Test name
Test status
Simulation time 167370412633 ps
CPU time 148.51 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 215868 kb
Host smart-447a4870-ddce-4fe1-ba07-a104a66511ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480730692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.3480730692
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_stress_all_with_rand_reset.1107087931
Short name T59
Test name
Test status
Simulation time 1416239347024 ps
CPU time 1112.72 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:54:32 PM PDT 24
Peak memory 226724 kb
Host smart-92f2baee-7691-4166-adc8-f69bb3c187d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107087931 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 17.uart_stress_all_with_rand_reset.1107087931
Directory /workspace/17.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1990842660
Short name T665
Test name
Test status
Simulation time 1475940877 ps
CPU time 1.47 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 198880 kb
Host smart-3b0aad74-4265-434a-8a26-8279c8eec3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990842660 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1990842660
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.38111948
Short name T463
Test name
Test status
Simulation time 283664581046 ps
CPU time 143.13 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:40:17 PM PDT 24
Peak memory 200000 kb
Host smart-cb0c9e7e-efda-4e64-a9a8-1135647acade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38111948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.38111948
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.396308675
Short name T1166
Test name
Test status
Simulation time 4347933756 ps
CPU time 2.62 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:37:59 PM PDT 24
Peak memory 199988 kb
Host smart-ff817baa-d10e-408a-bf2c-0efae48b2999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396308675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.396308675
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.2926694817
Short name T1025
Test name
Test status
Simulation time 116082829344 ps
CPU time 40.77 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 200020 kb
Host smart-d3878748-c811-45ec-a49a-b94daa21ba52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926694817 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.2926694817
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.1263952764
Short name T180
Test name
Test status
Simulation time 129395564811 ps
CPU time 122.78 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:39:59 PM PDT 24
Peak memory 199936 kb
Host smart-1e29aa2d-0a0e-4720-b74f-9f3ddf847429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263952764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.1263952764
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.3248445788
Short name T551
Test name
Test status
Simulation time 29038641273 ps
CPU time 21.93 seconds
Started Aug 02 05:37:55 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 198464 kb
Host smart-7f7c0e47-0edf-43ce-8189-116274efc4a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248445788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.3248445788
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.1064318385
Short name T226
Test name
Test status
Simulation time 90759491210 ps
CPU time 33.43 seconds
Started Aug 02 05:37:56 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 199892 kb
Host smart-0a72df3d-be84-4ffb-a8cd-f8beb09b7d6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064318385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.1064318385
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.4236807491
Short name T208
Test name
Test status
Simulation time 115295323632 ps
CPU time 91.41 seconds
Started Aug 02 05:37:57 PM PDT 24
Finished Aug 02 05:39:28 PM PDT 24
Peak memory 199912 kb
Host smart-2c457a76-d2a2-47dc-afb3-c1291f0a0c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236807491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.4236807491
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.3797937126
Short name T1125
Test name
Test status
Simulation time 29915011344 ps
CPU time 16.5 seconds
Started Aug 02 05:37:54 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 199944 kb
Host smart-4e85e407-85b2-424d-9e8a-8d17e761d25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797937126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.3797937126
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2556275031
Short name T24
Test name
Test status
Simulation time 24122342 ps
CPU time 0.58 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 195400 kb
Host smart-75c1fd90-74c8-4049-be62-2903cb18ede0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556275031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2556275031
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.259682145
Short name T588
Test name
Test status
Simulation time 110211920395 ps
CPU time 166.63 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 200020 kb
Host smart-d13a40ec-8d78-462c-8ac3-ebac043e8631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259682145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.259682145
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.1653489973
Short name T1030
Test name
Test status
Simulation time 128394159397 ps
CPU time 189.18 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:39:01 PM PDT 24
Peak memory 200032 kb
Host smart-f4bb6916-24bc-4c43-a6f2-c8e420f6a81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653489973 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.1653489973
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.4066885302
Short name T651
Test name
Test status
Simulation time 77961154692 ps
CPU time 116.83 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:37:55 PM PDT 24
Peak memory 199988 kb
Host smart-6ce12797-52ce-480a-86c7-1c40f62f7152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066885302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.4066885302
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.3016640972
Short name T1079
Test name
Test status
Simulation time 6914471264 ps
CPU time 5.86 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 196600 kb
Host smart-f22af86c-715d-48a7-8413-192d37444e5c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016640972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.3016640972
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1931245262
Short name T738
Test name
Test status
Simulation time 142026268622 ps
CPU time 642.88 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:46:38 PM PDT 24
Peak memory 199948 kb
Host smart-d893f7b2-dfb2-454d-8c19-5ea93caabfa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1931245262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1931245262
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.630155010
Short name T336
Test name
Test status
Simulation time 5936110015 ps
CPU time 4.45 seconds
Started Aug 02 05:36:04 PM PDT 24
Finished Aug 02 05:36:08 PM PDT 24
Peak memory 198740 kb
Host smart-50de96ac-6883-4dbd-95bd-20c070d55d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630155010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.630155010
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.4199599386
Short name T1152
Test name
Test status
Simulation time 100939945046 ps
CPU time 175.43 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 198928 kb
Host smart-eb5247cd-e863-45e0-bcb2-9c11cb0221e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199599386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.4199599386
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.2739333911
Short name T829
Test name
Test status
Simulation time 16162581665 ps
CPU time 460.8 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:43:34 PM PDT 24
Peak memory 199912 kb
Host smart-d1f81df4-0274-486f-9535-58f523d0eca6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2739333911 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.2739333911
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.323484049
Short name T622
Test name
Test status
Simulation time 6701621859 ps
CPU time 6.22 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 197840 kb
Host smart-b92e7d6f-83b8-47ce-9200-c3d5f5a0b0d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=323484049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.323484049
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.4051228752
Short name T436
Test name
Test status
Simulation time 18601291479 ps
CPU time 13.93 seconds
Started Aug 02 05:36:03 PM PDT 24
Finished Aug 02 05:36:17 PM PDT 24
Peak memory 199960 kb
Host smart-be8d7947-2287-46c0-a275-1a524de2a2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051228752 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.4051228752
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.2803950211
Short name T730
Test name
Test status
Simulation time 1291017905 ps
CPU time 1.16 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:52 PM PDT 24
Peak memory 195480 kb
Host smart-c2e38c31-17f5-4cdb-94e3-8491546a0ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803950211 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.2803950211
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.4173548303
Short name T278
Test name
Test status
Simulation time 122502748 ps
CPU time 0.74 seconds
Started Aug 02 05:36:14 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 197004 kb
Host smart-f53461df-deab-4185-83f9-27c79aa6e243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173548303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.4173548303
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.3821941331
Short name T807
Test name
Test status
Simulation time 106696696513 ps
CPU time 395.82 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:42:33 PM PDT 24
Peak memory 216460 kb
Host smart-b2dadfcc-4a76-4841-9e43-24bf1eec76c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821941331 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.3821941331
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.2369445416
Short name T828
Test name
Test status
Simulation time 15291632581 ps
CPU time 6.78 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 199992 kb
Host smart-524c6c9a-9e29-4c24-a05d-058616bb32a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369445416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.2369445416
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1025433217
Short name T107
Test name
Test status
Simulation time 97432356683 ps
CPU time 28.15 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 199976 kb
Host smart-1857bda2-42c4-478e-a222-ee5625df8c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025433217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1025433217
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.4270353001
Short name T825
Test name
Test status
Simulation time 22580119558 ps
CPU time 44.89 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 199996 kb
Host smart-35070516-c586-4048-a275-b146356374d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270353001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.4270353001
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.4211305667
Short name T194
Test name
Test status
Simulation time 110528528431 ps
CPU time 44.65 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:51 PM PDT 24
Peak memory 199988 kb
Host smart-192fa140-cf71-49be-b3a3-c7eaace54a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211305667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.4211305667
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.2469176436
Short name T951
Test name
Test status
Simulation time 48969024474 ps
CPU time 18.36 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 200028 kb
Host smart-a445f811-9942-4545-8a1b-7d1edf6c5d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469176436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.2469176436
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.2400775132
Short name T604
Test name
Test status
Simulation time 40345246157 ps
CPU time 27.16 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199964 kb
Host smart-20d6242c-04fd-4932-9e35-6ee8c093b5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400775132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.2400775132
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.3504128987
Short name T165
Test name
Test status
Simulation time 79668322374 ps
CPU time 60.99 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:39:04 PM PDT 24
Peak memory 199996 kb
Host smart-f14b24ac-43cc-4ef4-9e65-6d30e901afd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504128987 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.3504128987
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2609472189
Short name T119
Test name
Test status
Simulation time 43321864718 ps
CPU time 57.18 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:39:04 PM PDT 24
Peak memory 199980 kb
Host smart-e9ff3f7e-7e02-4ba6-87bb-f9bbef4d37a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609472189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2609472189
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.155543229
Short name T457
Test name
Test status
Simulation time 7276002170 ps
CPU time 11.84 seconds
Started Aug 02 05:38:16 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199800 kb
Host smart-a3b9520a-87e9-4790-961c-05a8283ccec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155543229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.155543229
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.2967914061
Short name T792
Test name
Test status
Simulation time 66508208416 ps
CPU time 26.16 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 199952 kb
Host smart-fb9550c3-54c1-4121-9fd4-32b75ce7e4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967914061 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.2967914061
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.4122736599
Short name T740
Test name
Test status
Simulation time 84080000 ps
CPU time 0.55 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 195348 kb
Host smart-72f7f98a-a12b-4146-b560-62ce1e39070a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122736599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.4122736599
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.1429030747
Short name T1014
Test name
Test status
Simulation time 71812818956 ps
CPU time 35.22 seconds
Started Aug 02 05:36:09 PM PDT 24
Finished Aug 02 05:36:44 PM PDT 24
Peak memory 199924 kb
Host smart-91d65c54-12b1-4895-87cf-9feb1e737497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429030747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.1429030747
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.1136501970
Short name T149
Test name
Test status
Simulation time 18297454437 ps
CPU time 15.78 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:36:24 PM PDT 24
Peak memory 199968 kb
Host smart-c04e225c-f9e3-45c6-9e50-615efebf622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136501970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.1136501970
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.3769500492
Short name T858
Test name
Test status
Simulation time 57677930597 ps
CPU time 22.22 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 199876 kb
Host smart-e0a6df9a-b258-4a1b-8c67-4c4be26ad695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769500492 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.3769500492
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.373996547
Short name T294
Test name
Test status
Simulation time 70965991910 ps
CPU time 68.1 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 199924 kb
Host smart-166928d9-d5f6-43c0-b765-0ebe066a4c1e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373996547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.373996547
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.3398926293
Short name T277
Test name
Test status
Simulation time 126934818323 ps
CPU time 429 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:43:08 PM PDT 24
Peak memory 199920 kb
Host smart-61aadb98-fbe0-442b-9b49-0cfe69aa49fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3398926293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.3398926293
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.2758502315
Short name T445
Test name
Test status
Simulation time 5286943659 ps
CPU time 5.91 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:57 PM PDT 24
Peak memory 199956 kb
Host smart-4904053b-d1da-454c-b72c-c604f2ceeab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758502315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.2758502315
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.760297763
Short name T868
Test name
Test status
Simulation time 236323931611 ps
CPU time 37.4 seconds
Started Aug 02 05:36:03 PM PDT 24
Finished Aug 02 05:36:40 PM PDT 24
Peak memory 208332 kb
Host smart-ec59b99b-260d-455f-9725-4b7a4058e49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760297763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.760297763
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.4013613918
Short name T242
Test name
Test status
Simulation time 12174778011 ps
CPU time 689.28 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:47:25 PM PDT 24
Peak memory 199972 kb
Host smart-9f795b4e-00e6-40f6-b0d1-e1e03be93081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013613918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.4013613918
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.1734091345
Short name T708
Test name
Test status
Simulation time 4246138597 ps
CPU time 5.25 seconds
Started Aug 02 05:35:51 PM PDT 24
Finished Aug 02 05:35:57 PM PDT 24
Peak memory 198972 kb
Host smart-d6eb6020-8d8d-4e37-ab50-0c27506c08c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1734091345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.1734091345
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.3667004748
Short name T796
Test name
Test status
Simulation time 52936468910 ps
CPU time 20.38 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 199160 kb
Host smart-2a007512-b309-41a9-8726-0a4b5e4b7195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667004748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.3667004748
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.3986964021
Short name T791
Test name
Test status
Simulation time 34888744339 ps
CPU time 29.68 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 195840 kb
Host smart-2465595c-3bbd-4a85-941a-17c03259e0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986964021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.3986964021
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.1796889615
Short name T281
Test name
Test status
Simulation time 5531379414 ps
CPU time 5.92 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 199936 kb
Host smart-7e773557-ee77-427d-80ff-04c744665212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796889615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.1796889615
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all.129021477
Short name T729
Test name
Test status
Simulation time 146736796907 ps
CPU time 119.35 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 199996 kb
Host smart-4b1fd9c8-4c15-47b0-b643-259ca0eba57b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129021477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.129021477
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.2622707661
Short name T42
Test name
Test status
Simulation time 94759795773 ps
CPU time 1045.85 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:53:22 PM PDT 24
Peak memory 224676 kb
Host smart-8ded9daf-5cee-43d3-bb9c-7805aa2d025f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622707661 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.2622707661
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.3512840261
Short name T800
Test name
Test status
Simulation time 6054269955 ps
CPU time 32.12 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 199548 kb
Host smart-facc09f5-563b-4320-a6fd-af0296eb6bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512840261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.3512840261
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.4195309545
Short name T928
Test name
Test status
Simulation time 39502858798 ps
CPU time 32.28 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 199880 kb
Host smart-34871438-f89b-4fa3-9ddb-6fbe74fa0b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195309545 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.4195309545
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3170578556
Short name T841
Test name
Test status
Simulation time 102521098389 ps
CPU time 70.67 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:39:16 PM PDT 24
Peak memory 199968 kb
Host smart-db1c9c65-ae98-4c8e-9f35-7dca09a93f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170578556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3170578556
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.2564833995
Short name T871
Test name
Test status
Simulation time 84654654523 ps
CPU time 58.76 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:39:13 PM PDT 24
Peak memory 199896 kb
Host smart-e01eaaa9-c37b-4724-a3b3-0c2e1e079802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564833995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.2564833995
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.2673332266
Short name T1068
Test name
Test status
Simulation time 18962638498 ps
CPU time 40.98 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 200012 kb
Host smart-1b9146c1-5f9d-4f1f-8b88-1bb29e77d6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673332266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.2673332266
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.1858245748
Short name T620
Test name
Test status
Simulation time 24042687247 ps
CPU time 31.89 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 199860 kb
Host smart-e0e6498a-496d-4444-abd7-43dd0bc5d51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858245748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.1858245748
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.4155204245
Short name T805
Test name
Test status
Simulation time 15977610008 ps
CPU time 31.35 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:39 PM PDT 24
Peak memory 199912 kb
Host smart-798359fd-7fe7-4642-946f-44324df2c166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155204245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.4155204245
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.4181353739
Short name T488
Test name
Test status
Simulation time 15496377351 ps
CPU time 7.24 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:38:12 PM PDT 24
Peak memory 199924 kb
Host smart-4903ae4c-faa8-4a2c-9f20-253f7f301205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181353739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.4181353739
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.1303528000
Short name T202
Test name
Test status
Simulation time 49976446431 ps
CPU time 77.02 seconds
Started Aug 02 05:38:08 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 200008 kb
Host smart-b2766474-e435-402b-b548-d53a47e052e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303528000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.1303528000
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3695537966
Short name T494
Test name
Test status
Simulation time 27435622 ps
CPU time 0.54 seconds
Started Aug 02 05:35:14 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 195368 kb
Host smart-b2627f93-57ed-4c82-b7d5-4b9833dd9429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695537966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3695537966
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.3783558392
Short name T132
Test name
Test status
Simulation time 52484145592 ps
CPU time 21.4 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:27 PM PDT 24
Peak memory 199892 kb
Host smart-9b1c5c4a-c3c5-4058-a3c4-14f832c48dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783558392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.3783558392
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.2327910614
Short name T639
Test name
Test status
Simulation time 69067810532 ps
CPU time 56.66 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 199884 kb
Host smart-10e5eb62-e2a1-42bd-b9e5-61e7216f3c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327910614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.2327910614
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2289561048
Short name T911
Test name
Test status
Simulation time 222900900679 ps
CPU time 307.23 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:40:38 PM PDT 24
Peak memory 199920 kb
Host smart-23c57d1f-23d9-4ff8-87e1-d1a9016ec60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289561048 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2289561048
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.746229742
Short name T998
Test name
Test status
Simulation time 41908854767 ps
CPU time 32.32 seconds
Started Aug 02 05:35:19 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 199932 kb
Host smart-41447b45-d3d2-4ba8-a14f-f9e5b1139e14
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746229742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.746229742
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.2976656346
Short name T769
Test name
Test status
Simulation time 149076809737 ps
CPU time 172.55 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:37:56 PM PDT 24
Peak memory 200016 kb
Host smart-ac4308a5-2f7b-4e76-8543-b43a3199b069
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2976656346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.2976656346
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.845090589
Short name T801
Test name
Test status
Simulation time 6791507895 ps
CPU time 12.8 seconds
Started Aug 02 05:35:02 PM PDT 24
Finished Aug 02 05:35:15 PM PDT 24
Peak memory 200004 kb
Host smart-05e64e81-378e-4fae-9b9d-8509a84495d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845090589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.845090589
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.3806185812
Short name T480
Test name
Test status
Simulation time 33080581727 ps
CPU time 56.07 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:36:17 PM PDT 24
Peak memory 199676 kb
Host smart-b5968205-68e4-4b41-8cfc-79cf5bf62a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806185812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.3806185812
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.1675687276
Short name T862
Test name
Test status
Simulation time 33168008924 ps
CPU time 179.7 seconds
Started Aug 02 05:35:18 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 199788 kb
Host smart-587d512e-6a8f-49eb-8cb5-b467ca383868
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1675687276 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.1675687276
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.1194091692
Short name T93
Test name
Test status
Simulation time 5055014265 ps
CPU time 20.76 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:40 PM PDT 24
Peak memory 199944 kb
Host smart-d7c70815-e5e1-4ec8-9b3e-8c4883bf0988
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1194091692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.1194091692
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.4107852410
Short name T923
Test name
Test status
Simulation time 39732442833 ps
CPU time 15.6 seconds
Started Aug 02 05:35:06 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 199784 kb
Host smart-40b0557b-4cbb-4773-b8bd-d0c40ef08398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107852410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.4107852410
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.53214496
Short name T1035
Test name
Test status
Simulation time 42048039692 ps
CPU time 66.55 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 196824 kb
Host smart-b7d7d278-6638-4cf5-96c5-c2c46ba72b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53214496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.53214496
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.3502368594
Short name T84
Test name
Test status
Simulation time 60538157 ps
CPU time 0.86 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:35:26 PM PDT 24
Peak memory 218524 kb
Host smart-b90a3949-20f1-40c6-bf8d-17670ad8a769
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502368594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.3502368594
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.3305014853
Short name T819
Test name
Test status
Simulation time 478831759 ps
CPU time 2.36 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 198912 kb
Host smart-ea6bc7e3-618e-43d3-9c25-d6116c39f21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305014853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.3305014853
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.3068986421
Short name T812
Test name
Test status
Simulation time 116662884556 ps
CPU time 190.42 seconds
Started Aug 02 05:35:13 PM PDT 24
Finished Aug 02 05:38:23 PM PDT 24
Peak memory 199864 kb
Host smart-d183701d-7a80-40a0-aa5c-0036bd6ebf51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068986421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.3068986421
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.4253540667
Short name T14
Test name
Test status
Simulation time 76158734049 ps
CPU time 475.17 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:43:29 PM PDT 24
Peak memory 208776 kb
Host smart-0d5e9c6e-1183-46a2-b0b3-32bb70db10ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253540667 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.4253540667
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3211084684
Short name T716
Test name
Test status
Simulation time 2528017113 ps
CPU time 2.15 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:35:38 PM PDT 24
Peak memory 198524 kb
Host smart-c66437ca-3bbb-492f-957d-5e8db34f9444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211084684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3211084684
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.3317514206
Short name T1036
Test name
Test status
Simulation time 40260530874 ps
CPU time 77.17 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:37:01 PM PDT 24
Peak memory 199856 kb
Host smart-8b1d7ed8-b5be-42b2-9fac-1d7a99034899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317514206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.3317514206
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.2883095678
Short name T1044
Test name
Test status
Simulation time 36430761 ps
CPU time 0.55 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 195364 kb
Host smart-f154c417-eb23-44e0-a7bc-8c79ac0ad6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883095678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.2883095678
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_full.2856056374
Short name T905
Test name
Test status
Simulation time 17984818707 ps
CPU time 16.7 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:16 PM PDT 24
Peak memory 199936 kb
Host smart-78a06376-8b1a-44d2-bf25-c68ece0cc46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856056374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.2856056374
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2230316662
Short name T1175
Test name
Test status
Simulation time 27899957898 ps
CPU time 11.94 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 199932 kb
Host smart-e03efec8-64ae-47bc-bfc6-24b4464501dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230316662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2230316662
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_intr.926841868
Short name T885
Test name
Test status
Simulation time 7746530045 ps
CPU time 4.34 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 199920 kb
Host smart-fad32b42-2f68-4991-8723-3262ebd7a6c8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926841868 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.926841868
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.428827753
Short name T556
Test name
Test status
Simulation time 73293384599 ps
CPU time 569.01 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:45:31 PM PDT 24
Peak memory 199988 kb
Host smart-895c95ec-3091-463b-83b6-03983ce9d2d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=428827753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.428827753
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2876496307
Short name T522
Test name
Test status
Simulation time 10759537937 ps
CPU time 4.73 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 199664 kb
Host smart-0e54cc95-e0d2-4531-8d93-d56bcd8f681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876496307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2876496307
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.498110807
Short name T331
Test name
Test status
Simulation time 233771389192 ps
CPU time 35.3 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 200160 kb
Host smart-1b6fb2d7-dad9-46f2-bd27-c67fef0f9ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498110807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.498110807
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.521373655
Short name T393
Test name
Test status
Simulation time 35482570532 ps
CPU time 108.83 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:38:04 PM PDT 24
Peak memory 199936 kb
Host smart-2a8675b8-705c-40b3-942a-5cf35b3df1f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521373655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.521373655
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.1156650607
Short name T804
Test name
Test status
Simulation time 5925473582 ps
CPU time 27.92 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:24 PM PDT 24
Peak memory 198240 kb
Host smart-9deee8be-2f4f-404d-be15-2f5bb4c0ff8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1156650607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.1156650607
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.2009138877
Short name T657
Test name
Test status
Simulation time 160763228939 ps
CPU time 148.55 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 200024 kb
Host smart-f3c85611-3985-4158-a2f9-1e39005d522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009138877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.2009138877
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.3228213087
Short name T333
Test name
Test status
Simulation time 3060150553 ps
CPU time 1.8 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 196496 kb
Host smart-85394a53-ead3-4942-a59a-0b7cd1e38962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228213087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.3228213087
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.195390865
Short name T468
Test name
Test status
Simulation time 5822738461 ps
CPU time 10.71 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 199600 kb
Host smart-2e3e253c-e4fe-4b2b-b17a-f4070bb080af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195390865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.195390865
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.2353854822
Short name T1173
Test name
Test status
Simulation time 171822161761 ps
CPU time 79.14 seconds
Started Aug 02 05:36:09 PM PDT 24
Finished Aug 02 05:37:28 PM PDT 24
Peak memory 199960 kb
Host smart-f11cf4ed-6a41-4b0e-9f7a-d27b4891d447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353854822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.2353854822
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.2565828918
Short name T61
Test name
Test status
Simulation time 162660219579 ps
CPU time 994.57 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:52:48 PM PDT 24
Peak memory 224856 kb
Host smart-134afbde-e8eb-48cd-a474-84e6b636c075
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565828918 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.2565828918
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.690984434
Short name T460
Test name
Test status
Simulation time 1041913269 ps
CPU time 1.59 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 198876 kb
Host smart-178edc4f-fb58-44f7-8fc4-45b3d8d63de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690984434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.690984434
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.1941503175
Short name T719
Test name
Test status
Simulation time 26748857720 ps
CPU time 16.1 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 200012 kb
Host smart-29467795-039a-4593-b7ce-ac4c4dbcefad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941503175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.1941503175
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.1012382881
Short name T774
Test name
Test status
Simulation time 89488358004 ps
CPU time 128.29 seconds
Started Aug 02 05:38:09 PM PDT 24
Finished Aug 02 05:40:17 PM PDT 24
Peak memory 199888 kb
Host smart-711c2d45-5f9f-46c1-a73c-06779909de7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012382881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.1012382881
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.2108020936
Short name T1019
Test name
Test status
Simulation time 29629767859 ps
CPU time 42.77 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 200048 kb
Host smart-2beb2e50-7d5e-46f8-b655-d8c5164d8088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108020936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.2108020936
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3979578473
Short name T999
Test name
Test status
Simulation time 24779707114 ps
CPU time 6.32 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 199788 kb
Host smart-51ff6be0-110d-4f6a-a734-f329fc15a0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979578473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3979578473
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1284629776
Short name T1032
Test name
Test status
Simulation time 10402815022 ps
CPU time 4.82 seconds
Started Aug 02 05:38:06 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 198904 kb
Host smart-5fc21391-427e-4f9c-b4c5-a25c8067d350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284629776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1284629776
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.229182154
Short name T993
Test name
Test status
Simulation time 79765050222 ps
CPU time 46.93 seconds
Started Aug 02 05:38:04 PM PDT 24
Finished Aug 02 05:38:51 PM PDT 24
Peak memory 199964 kb
Host smart-f174b7c9-f280-4c63-a889-5c9afe51f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229182154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.229182154
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4007176391
Short name T428
Test name
Test status
Simulation time 21646910080 ps
CPU time 21.51 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:38:27 PM PDT 24
Peak memory 200012 kb
Host smart-07541660-d811-481e-a1d9-cc96c000f7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007176391 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4007176391
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.2033448878
Short name T907
Test name
Test status
Simulation time 51161127519 ps
CPU time 14.61 seconds
Started Aug 02 05:38:06 PM PDT 24
Finished Aug 02 05:38:21 PM PDT 24
Peak memory 199692 kb
Host smart-36dbe019-ca68-43a2-b229-c3a3e5a6dca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033448878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.2033448878
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.2110925007
Short name T1090
Test name
Test status
Simulation time 19156916268 ps
CPU time 42.19 seconds
Started Aug 02 05:38:04 PM PDT 24
Finished Aug 02 05:38:46 PM PDT 24
Peak memory 199924 kb
Host smart-987a88dd-1683-4c7a-a093-14940bf7a806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110925007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.2110925007
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.1417778406
Short name T660
Test name
Test status
Simulation time 120114447164 ps
CPU time 337.07 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:43:45 PM PDT 24
Peak memory 199896 kb
Host smart-6b382280-7eba-495d-9734-98fb5f705c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417778406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.1417778406
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.34019946
Short name T634
Test name
Test status
Simulation time 12464590 ps
CPU time 0.55 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 195356 kb
Host smart-78ec12d4-a90b-4290-93c0-88a84e76ab0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34019946 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.34019946
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.2072608485
Short name T161
Test name
Test status
Simulation time 176653983260 ps
CPU time 64.31 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 199912 kb
Host smart-7c42e8ea-ab2d-413d-8727-ffbfd9f2fa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072608485 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.2072608485
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1753134580
Short name T549
Test name
Test status
Simulation time 27539460961 ps
CPU time 41.76 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:38 PM PDT 24
Peak memory 200000 kb
Host smart-5103d357-1c86-4e1d-b57c-373783fb7ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753134580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1753134580
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.3547215838
Short name T630
Test name
Test status
Simulation time 19593165582 ps
CPU time 28.58 seconds
Started Aug 02 05:36:04 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 199864 kb
Host smart-526277b8-1389-4530-9016-676a0768a67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547215838 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.3547215838
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.3247012802
Short name T262
Test name
Test status
Simulation time 20159855797 ps
CPU time 31.73 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:33 PM PDT 24
Peak memory 199756 kb
Host smart-ba83eed9-ffb1-4397-8a8b-dc8b8ed406f9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247012802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.3247012802
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2385026324
Short name T424
Test name
Test status
Simulation time 76451481646 ps
CPU time 222.05 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:39:49 PM PDT 24
Peak memory 199952 kb
Host smart-e9fce444-6480-45a1-8fcf-8ba05f2208b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2385026324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2385026324
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.1182200556
Short name T662
Test name
Test status
Simulation time 14874876093 ps
CPU time 12.76 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:19 PM PDT 24
Peak memory 199896 kb
Host smart-d6c35463-2173-4a71-960b-ff4e05a67461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182200556 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.1182200556
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1626633759
Short name T284
Test name
Test status
Simulation time 28870763316 ps
CPU time 25.84 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 199380 kb
Host smart-98586ab2-04dd-48cb-a5d5-a9f593de6e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626633759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1626633759
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.1845510663
Short name T275
Test name
Test status
Simulation time 12424132420 ps
CPU time 267.47 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:40:21 PM PDT 24
Peak memory 199980 kb
Host smart-63a90a80-e608-4b83-80c4-c0eb50b3aada
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1845510663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.1845510663
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.3022790621
Short name T1112
Test name
Test status
Simulation time 7904811214 ps
CPU time 16.45 seconds
Started Aug 02 05:36:09 PM PDT 24
Finished Aug 02 05:36:25 PM PDT 24
Peak memory 197736 kb
Host smart-1b08731d-847c-48cf-b83d-e617fd9068f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3022790621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.3022790621
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.3476890996
Short name T565
Test name
Test status
Simulation time 24512006174 ps
CPU time 19.91 seconds
Started Aug 02 05:35:54 PM PDT 24
Finished Aug 02 05:36:14 PM PDT 24
Peak memory 199704 kb
Host smart-d3e12a37-6fe7-49f6-b52e-30223debfcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476890996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.3476890996
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.3536945202
Short name T666
Test name
Test status
Simulation time 4525190034 ps
CPU time 2.47 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:36:10 PM PDT 24
Peak memory 195920 kb
Host smart-afacb4fb-5091-49a8-9836-293a2b1f5cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536945202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.3536945202
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.2004747927
Short name T108
Test name
Test status
Simulation time 11063733583 ps
CPU time 15.34 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:10 PM PDT 24
Peak memory 199472 kb
Host smart-b613b566-f729-4411-bedd-d8d327910480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004747927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.2004747927
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.2646634664
Short name T207
Test name
Test status
Simulation time 598223869298 ps
CPU time 373.17 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:42:12 PM PDT 24
Peak memory 200032 kb
Host smart-b1070fb4-86ff-4663-af03-4d4c6a037b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646634664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.2646634664
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.1369271132
Short name T1089
Test name
Test status
Simulation time 385133069791 ps
CPU time 1344.16 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:58:23 PM PDT 24
Peak memory 225324 kb
Host smart-eac934c3-67df-4b05-85c6-8a5401d7df46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369271132 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.1369271132
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.2087408279
Short name T521
Test name
Test status
Simulation time 525401511 ps
CPU time 2.15 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 198356 kb
Host smart-db93de92-0018-480c-962e-8e06ac8eaf11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087408279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.2087408279
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.2693621833
Short name T857
Test name
Test status
Simulation time 2191447208 ps
CPU time 2.43 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:08 PM PDT 24
Peak memory 197644 kb
Host smart-b4aa9ee8-0f1b-4ee7-9fa3-d79d60190fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693621833 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.2693621833
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.355560410
Short name T322
Test name
Test status
Simulation time 54166900856 ps
CPU time 22.09 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:38:27 PM PDT 24
Peak memory 199992 kb
Host smart-993f6279-ec24-47dd-9444-5fc5476ab51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355560410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.355560410
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.651062354
Short name T3
Test name
Test status
Simulation time 64375282195 ps
CPU time 46.46 seconds
Started Aug 02 05:38:09 PM PDT 24
Finished Aug 02 05:38:55 PM PDT 24
Peak memory 199904 kb
Host smart-b1086b9b-6c96-4eb9-9f54-bea3e83ccad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651062354 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.651062354
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.3937469089
Short name T778
Test name
Test status
Simulation time 42522117486 ps
CPU time 73.48 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 199852 kb
Host smart-78568a4f-517e-4591-8280-b69084a5ab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937469089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.3937469089
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2224201030
Short name T53
Test name
Test status
Simulation time 41990961522 ps
CPU time 27.15 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:38:33 PM PDT 24
Peak memory 199600 kb
Host smart-e05f37e6-9c41-4ec9-bc46-f834262ec37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224201030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2224201030
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3922050990
Short name T655
Test name
Test status
Simulation time 102551823336 ps
CPU time 48.94 seconds
Started Aug 02 05:38:06 PM PDT 24
Finished Aug 02 05:38:55 PM PDT 24
Peak memory 199940 kb
Host smart-8144f6b8-4c92-4025-958c-2703bbdb902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922050990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3922050990
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.1075721238
Short name T971
Test name
Test status
Simulation time 51043680172 ps
CPU time 62.24 seconds
Started Aug 02 05:38:05 PM PDT 24
Finished Aug 02 05:39:07 PM PDT 24
Peak memory 199992 kb
Host smart-651dbf55-bf4d-494a-8066-9eb22cdd3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075721238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.1075721238
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1317535052
Short name T535
Test name
Test status
Simulation time 114946336499 ps
CPU time 195.9 seconds
Started Aug 02 05:38:03 PM PDT 24
Finished Aug 02 05:41:19 PM PDT 24
Peak memory 199900 kb
Host smart-367a2d94-5723-4b3e-bb9c-f1ffc0eb0e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317535052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1317535052
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.1491018226
Short name T146
Test name
Test status
Simulation time 44284214842 ps
CPU time 63.85 seconds
Started Aug 02 05:38:06 PM PDT 24
Finished Aug 02 05:39:10 PM PDT 24
Peak memory 199748 kb
Host smart-52090d8b-f245-440b-82b1-f5d254c3fe09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491018226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.1491018226
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.2062926887
Short name T179
Test name
Test status
Simulation time 114562634590 ps
CPU time 165.39 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:41:00 PM PDT 24
Peak memory 199592 kb
Host smart-08593f2c-a6f7-49dc-aea5-a61744dd8f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062926887 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.2062926887
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.1118871322
Short name T683
Test name
Test status
Simulation time 245037580812 ps
CPU time 210.09 seconds
Started Aug 02 05:38:08 PM PDT 24
Finished Aug 02 05:41:38 PM PDT 24
Peak memory 200008 kb
Host smart-31c686a4-4d66-4c4a-b6bb-82477b4afcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118871322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.1118871322
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.2016104292
Short name T405
Test name
Test status
Simulation time 40049929 ps
CPU time 0.54 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 195384 kb
Host smart-37ce3fa6-59d7-4d21-9f76-7ababbfb6e3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016104292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.2016104292
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.4157835064
Short name T134
Test name
Test status
Simulation time 44020184892 ps
CPU time 64.21 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:37:16 PM PDT 24
Peak memory 199948 kb
Host smart-3afb0c6a-fefa-4fc4-9dd8-88b0aca55714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157835064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.4157835064
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.3826648420
Short name T995
Test name
Test status
Simulation time 21625994481 ps
CPU time 56.22 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 199680 kb
Host smart-9bed904b-1bbb-43bc-a1b2-d828460027b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826648420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.3826648420
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1923777455
Short name T714
Test name
Test status
Simulation time 180726164835 ps
CPU time 285.6 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:40:57 PM PDT 24
Peak memory 199992 kb
Host smart-f6e31d9a-03a3-4d3e-9a34-8a472b2f6324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923777455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1923777455
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.3567637576
Short name T309
Test name
Test status
Simulation time 708484881173 ps
CPU time 1110.3 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:54:27 PM PDT 24
Peak memory 199932 kb
Host smart-3e6a7b85-794a-4eac-88e5-a819d18b122c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567637576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.3567637576
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.334097430
Short name T1096
Test name
Test status
Simulation time 80222024006 ps
CPU time 569.77 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:45:36 PM PDT 24
Peak memory 199976 kb
Host smart-ca97c7ee-1d4a-4328-847d-336c776a49da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=334097430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.334097430
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3236363392
Short name T352
Test name
Test status
Simulation time 7086449118 ps
CPU time 6.4 seconds
Started Aug 02 05:36:05 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 198432 kb
Host smart-f8352982-90ec-4976-98dd-6fb0984232f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236363392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3236363392
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3314096979
Short name T90
Test name
Test status
Simulation time 31663259140 ps
CPU time 16.32 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:36:28 PM PDT 24
Peak memory 194528 kb
Host smart-995edffd-d291-4f65-94d2-e8f61a5aad6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314096979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3314096979
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.3781657652
Short name T784
Test name
Test status
Simulation time 22691965444 ps
CPU time 300.21 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:40:53 PM PDT 24
Peak memory 200008 kb
Host smart-318e900c-e172-4c8b-b885-2d1d8adfc1a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3781657652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.3781657652
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.2279608295
Short name T965
Test name
Test status
Simulation time 6042356504 ps
CPU time 52.77 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:36:50 PM PDT 24
Peak memory 197988 kb
Host smart-7759859d-e1dc-430d-b4e2-399ee8729b61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2279608295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.2279608295
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1997742134
Short name T541
Test name
Test status
Simulation time 13253938841 ps
CPU time 22.88 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 199960 kb
Host smart-6280d3c4-60e5-4fa3-852f-101f83b4872a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997742134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1997742134
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.1366861010
Short name T380
Test name
Test status
Simulation time 24735297077 ps
CPU time 41.14 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 195804 kb
Host smart-1ded29ff-62e2-4c4c-b6da-ef512501c200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366861010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.1366861010
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.1588463373
Short name T1043
Test name
Test status
Simulation time 470266040 ps
CPU time 1.14 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 198376 kb
Host smart-9c2fb056-f523-48c2-8c34-44cd5c3b73b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588463373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.1588463373
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.4058349607
Short name T519
Test name
Test status
Simulation time 65410796574 ps
CPU time 741.06 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:48:17 PM PDT 24
Peak memory 225452 kb
Host smart-677f9a2c-b7d3-4d86-911e-89a13dec8596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058349607 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.4058349607
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.4138892776
Short name T482
Test name
Test status
Simulation time 6892468270 ps
CPU time 15.52 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 199872 kb
Host smart-5d99cff9-ff33-477d-86de-503ae5f03986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138892776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.4138892776
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.1497131103
Short name T293
Test name
Test status
Simulation time 85004025098 ps
CPU time 127.36 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:38:06 PM PDT 24
Peak memory 199968 kb
Host smart-426e281d-8803-4661-a560-9ca8a8f6f700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497131103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.1497131103
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2636923665
Short name T213
Test name
Test status
Simulation time 110983965610 ps
CPU time 41.79 seconds
Started Aug 02 05:38:08 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 199916 kb
Host smart-0c04b802-9a27-4fbd-b1bc-5827ee4780d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636923665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2636923665
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.408899159
Short name T1029
Test name
Test status
Simulation time 167258427775 ps
CPU time 133.68 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:40:21 PM PDT 24
Peak memory 199952 kb
Host smart-bf770a5d-02d3-466e-96d2-326e43258f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408899159 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.408899159
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.98626106
Short name T860
Test name
Test status
Simulation time 31150557484 ps
CPU time 38.92 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:46 PM PDT 24
Peak memory 199728 kb
Host smart-ce038485-bd8a-4f8e-af2d-b0747bf2b77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98626106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.98626106
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.1536715462
Short name T166
Test name
Test status
Simulation time 99201075517 ps
CPU time 37.21 seconds
Started Aug 02 05:38:07 PM PDT 24
Finished Aug 02 05:38:45 PM PDT 24
Peak memory 199776 kb
Host smart-ffd85bae-628d-4866-9bc3-33c9952345b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536715462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.1536715462
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.1717041547
Short name T175
Test name
Test status
Simulation time 74760585210 ps
CPU time 21.84 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:36 PM PDT 24
Peak memory 199940 kb
Host smart-b9ef24cb-0227-49a4-b61e-a41b30443542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717041547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.1717041547
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3292676458
Short name T219
Test name
Test status
Simulation time 86196126438 ps
CPU time 47.31 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:39:02 PM PDT 24
Peak memory 199960 kb
Host smart-0c7ccb2e-f998-4351-b579-f4ad0a41aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292676458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3292676458
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.3019754509
Short name T469
Test name
Test status
Simulation time 11943792371 ps
CPU time 29.49 seconds
Started Aug 02 05:38:12 PM PDT 24
Finished Aug 02 05:38:42 PM PDT 24
Peak memory 199936 kb
Host smart-9def5b7c-37de-479e-b8a8-24c8ebc33864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019754509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.3019754509
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.4004948174
Short name T1170
Test name
Test status
Simulation time 13572924281 ps
CPU time 6.6 seconds
Started Aug 02 05:38:11 PM PDT 24
Finished Aug 02 05:38:18 PM PDT 24
Peak memory 199984 kb
Host smart-ffbae664-c1db-4c3a-81e3-83264df108b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004948174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.4004948174
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.3557967085
Short name T1031
Test name
Test status
Simulation time 47177031840 ps
CPU time 69.05 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 199936 kb
Host smart-e56fb7b5-5a33-4e6c-9ad2-40798060001b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557967085 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.3557967085
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.2835712329
Short name T1067
Test name
Test status
Simulation time 19880719 ps
CPU time 0.54 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 195400 kb
Host smart-dc4f90bf-195e-4965-af24-fb510413c6b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835712329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.2835712329
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.2871680539
Short name T310
Test name
Test status
Simulation time 179414113099 ps
CPU time 29.18 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:36:26 PM PDT 24
Peak memory 200072 kb
Host smart-2acf216a-8304-498b-8485-e891f890bfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871680539 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.2871680539
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.3995257744
Short name T118
Test name
Test status
Simulation time 17309537130 ps
CPU time 16.27 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:36:14 PM PDT 24
Peak memory 199868 kb
Host smart-9ab6e20b-54b3-464a-bf10-9e13abb8eb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995257744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.3995257744
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.2794599936
Short name T576
Test name
Test status
Simulation time 88087379013 ps
CPU time 41.66 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:36:50 PM PDT 24
Peak memory 199988 kb
Host smart-aa87a916-8070-4d99-b578-53c50eeae8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794599936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.2794599936
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.441038057
Short name T621
Test name
Test status
Simulation time 33429652995 ps
CPU time 57.9 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 200036 kb
Host smart-893721af-1486-48a7-8f73-58bb83c62345
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441038057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.441038057
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.2068255813
Short name T245
Test name
Test status
Simulation time 357111817782 ps
CPU time 360.86 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:42:03 PM PDT 24
Peak memory 199848 kb
Host smart-5505c382-82fe-44d7-bd48-b960643fbb72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068255813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.2068255813
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2359818416
Short name T371
Test name
Test status
Simulation time 1790756293 ps
CPU time 1.74 seconds
Started Aug 02 05:35:56 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 198184 kb
Host smart-7bda2f13-2475-44f0-8d5e-7497f51825f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359818416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2359818416
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.3568295582
Short name T844
Test name
Test status
Simulation time 26731327616 ps
CPU time 49.06 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:49 PM PDT 24
Peak memory 199692 kb
Host smart-8df93285-dfb6-4706-af45-35da1db0574e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568295582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.3568295582
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.4020577745
Short name T671
Test name
Test status
Simulation time 21055213074 ps
CPU time 1169.25 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:55:41 PM PDT 24
Peak memory 199996 kb
Host smart-9eb966fa-28d7-4930-b10b-5d561ec28c6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4020577745 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.4020577745
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.1649218593
Short name T619
Test name
Test status
Simulation time 8343056104 ps
CPU time 34.84 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 199204 kb
Host smart-751293b6-a211-49a0-b5a2-7a74d8070dda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1649218593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.1649218593
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.4050941342
Short name T481
Test name
Test status
Simulation time 11211451179 ps
CPU time 18.7 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:19 PM PDT 24
Peak memory 199808 kb
Host smart-f95ac65f-f9db-4c5c-97a9-d45f96807423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050941342 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.4050941342
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1130735397
Short name T518
Test name
Test status
Simulation time 3174766895 ps
CPU time 1.12 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 196548 kb
Host smart-7f2995c5-61dd-466a-ac42-4c4764b7f5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130735397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1130735397
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.3104353475
Short name T483
Test name
Test status
Simulation time 651227394 ps
CPU time 2.63 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 198448 kb
Host smart-74cefa7f-4af9-4be4-b380-ef99575b0ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104353475 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.3104353475
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.410500729
Short name T596
Test name
Test status
Simulation time 12112772914 ps
CPU time 12.11 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 199904 kb
Host smart-3b13b6e6-a970-4c23-97b6-f677c69cd266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410500729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.410500729
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.290805813
Short name T930
Test name
Test status
Simulation time 858121978 ps
CPU time 2.38 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 198376 kb
Host smart-21d862c5-fb71-48bc-9f9c-b9b1e9e1f5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290805813 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.290805813
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.1255141859
Short name T554
Test name
Test status
Simulation time 93593277727 ps
CPU time 94.95 seconds
Started Aug 02 05:36:05 PM PDT 24
Finished Aug 02 05:37:40 PM PDT 24
Peak memory 199960 kb
Host smart-5dd0d88d-01d6-4794-bffb-d8e15c2e84d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255141859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.1255141859
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2619174884
Short name T654
Test name
Test status
Simulation time 50974861994 ps
CPU time 20.14 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:35 PM PDT 24
Peak memory 199980 kb
Host smart-91d790f6-4aec-46f1-8609-7280d28a57a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619174884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2619174884
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.1189498612
Short name T1058
Test name
Test status
Simulation time 8599835587 ps
CPU time 12.81 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:38:26 PM PDT 24
Peak memory 199928 kb
Host smart-9d4ccfc7-77ef-4aeb-b324-2fefd4768e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189498612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.1189498612
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.3189838653
Short name T197
Test name
Test status
Simulation time 44494860254 ps
CPU time 64.55 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 199792 kb
Host smart-c5294183-cc1f-4dc3-a4cf-25b1ff50b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189838653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.3189838653
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.2563121338
Short name T319
Test name
Test status
Simulation time 25852952210 ps
CPU time 41.02 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 199888 kb
Host smart-6ab8afa7-33ea-4cb6-96c8-ea47778f482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563121338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.2563121338
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.852886754
Short name T850
Test name
Test status
Simulation time 40020243329 ps
CPU time 29.87 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 199596 kb
Host smart-f329049d-6296-4096-a394-fb1db844887f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852886754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.852886754
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.531011334
Short name T10
Test name
Test status
Simulation time 33439138028 ps
CPU time 15.64 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:38:30 PM PDT 24
Peak memory 199872 kb
Host smart-86ba3ec1-ea15-42fc-8250-a4536a8b3aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531011334 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.531011334
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.1450879052
Short name T298
Test name
Test status
Simulation time 36551732417 ps
CPU time 12.06 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:38:25 PM PDT 24
Peak memory 200008 kb
Host smart-08df92df-176a-44a5-b090-7ca0563a9785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450879052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.1450879052
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.4047851782
Short name T1176
Test name
Test status
Simulation time 22603380998 ps
CPU time 21.65 seconds
Started Aug 02 05:38:18 PM PDT 24
Finished Aug 02 05:38:40 PM PDT 24
Peak memory 199776 kb
Host smart-f6aea4cd-5388-4616-96cc-ebf2d781c871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047851782 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.4047851782
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.3190763672
Short name T929
Test name
Test status
Simulation time 40266018715 ps
CPU time 62.07 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:39:16 PM PDT 24
Peak memory 199960 kb
Host smart-530a17a0-f2f5-40d6-81a2-34bfe7b73524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190763672 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.3190763672
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.2888409324
Short name T509
Test name
Test status
Simulation time 16105920 ps
CPU time 0.57 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 194344 kb
Host smart-08648d0c-66f3-4c6e-8361-05970d24ad3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888409324 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.2888409324
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.1399785308
Short name T4
Test name
Test status
Simulation time 62357462623 ps
CPU time 53.42 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:37:18 PM PDT 24
Peak memory 199952 kb
Host smart-e80fdb4e-0ffc-404d-9d30-500fdbcaa2cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399785308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.1399785308
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2117768590
Short name T1172
Test name
Test status
Simulation time 19932617528 ps
CPU time 21.41 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 199920 kb
Host smart-44e2f4b3-5f9c-40e7-a4cd-ed5fe4d87e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117768590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2117768590
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_intr.2295967725
Short name T110
Test name
Test status
Simulation time 57263271053 ps
CPU time 99.9 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:37:40 PM PDT 24
Peak memory 199996 kb
Host smart-54fff80e-8bfc-422d-839a-5c7670a8a74f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295967725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.2295967725
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.520463261
Short name T809
Test name
Test status
Simulation time 123292584535 ps
CPU time 926.92 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:51:39 PM PDT 24
Peak memory 200028 kb
Host smart-8466c5d1-d60d-4f3b-97ec-5df5757e533a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=520463261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.520463261
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3727063666
Short name T617
Test name
Test status
Simulation time 2498211609 ps
CPU time 4.73 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 198152 kb
Host smart-60ff06db-5361-4104-8d86-fbf8299ab236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727063666 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3727063666
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.3806692599
Short name T690
Test name
Test status
Simulation time 32794473618 ps
CPU time 53.67 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 198748 kb
Host smart-f215e1be-fd15-4383-8adc-059850963fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806692599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.3806692599
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2550617151
Short name T873
Test name
Test status
Simulation time 15005509165 ps
CPU time 771.45 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:48:51 PM PDT 24
Peak memory 199992 kb
Host smart-4c14e221-19cb-40cb-88d9-57797338d849
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2550617151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2550617151
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.1881886998
Short name T937
Test name
Test status
Simulation time 7555195242 ps
CPU time 11.6 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:17 PM PDT 24
Peak memory 199116 kb
Host smart-4a7157d7-e296-481f-98f8-64deb94070a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881886998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.1881886998
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.124777232
Short name T407
Test name
Test status
Simulation time 64623557136 ps
CPU time 121.37 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:38:09 PM PDT 24
Peak memory 199964 kb
Host smart-b3f5680f-aa47-47bb-b85c-6c79ce5b95bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124777232 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.124777232
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.874004528
Short name T1080
Test name
Test status
Simulation time 5165093561 ps
CPU time 7.78 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:09 PM PDT 24
Peak memory 196164 kb
Host smart-6fae059e-9e1a-4e81-b960-e9d2ef1aff68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874004528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.874004528
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.418056859
Short name T946
Test name
Test status
Simulation time 5425689820 ps
CPU time 11.6 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 199716 kb
Host smart-393307cb-560c-4a34-85d1-355b54e77864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418056859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.418056859
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2064798072
Short name T492
Test name
Test status
Simulation time 417230714664 ps
CPU time 269.08 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 199992 kb
Host smart-90ee6ec3-4f2e-4b25-a694-6e63acfcc85c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064798072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2064798072
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.123224817
Short name T988
Test name
Test status
Simulation time 62936133287 ps
CPU time 368.02 seconds
Started Aug 02 05:36:10 PM PDT 24
Finished Aug 02 05:42:20 PM PDT 24
Peak memory 208296 kb
Host smart-b958e5c8-a519-4e43-98cd-fd3b88e004f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123224817 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.123224817
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.1556773209
Short name T287
Test name
Test status
Simulation time 13045453097 ps
CPU time 21.74 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 199936 kb
Host smart-784a33a0-fca8-4966-9059-f40306c0f898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556773209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.1556773209
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3185991543
Short name T979
Test name
Test status
Simulation time 17982785008 ps
CPU time 13.62 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:14 PM PDT 24
Peak memory 197724 kb
Host smart-37e33649-ed47-4871-a846-4d5608086c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185991543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3185991543
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.4001295359
Short name T1034
Test name
Test status
Simulation time 47375817754 ps
CPU time 72.39 seconds
Started Aug 02 05:38:18 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 199772 kb
Host smart-57f5979b-b118-4aa7-be91-8d9da618d2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001295359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.4001295359
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1321552891
Short name T575
Test name
Test status
Simulation time 30758461072 ps
CPU time 29.27 seconds
Started Aug 02 05:38:18 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 199716 kb
Host smart-57c4cde6-05d0-4fd1-8390-bb9d0a7a5964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321552891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1321552891
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.608013162
Short name T453
Test name
Test status
Simulation time 91646028284 ps
CPU time 143.36 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:40:39 PM PDT 24
Peak memory 199988 kb
Host smart-5c545063-9e57-497c-9805-9a75c123ac01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608013162 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.608013162
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3463815008
Short name T88
Test name
Test status
Simulation time 86924515640 ps
CPU time 33.38 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 199984 kb
Host smart-b5f600b4-099f-4069-a86d-cd5006865079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463815008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3463815008
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1848830389
Short name T1017
Test name
Test status
Simulation time 25902225398 ps
CPU time 22.59 seconds
Started Aug 02 05:38:14 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 199928 kb
Host smart-a574c170-1958-49ab-a60d-43f8deceb829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848830389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1848830389
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.1601317775
Short name T640
Test name
Test status
Simulation time 157027901081 ps
CPU time 59.18 seconds
Started Aug 02 05:38:11 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 200012 kb
Host smart-7b43b6a1-f264-4de2-af3a-2d00d43c8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601317775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.1601317775
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.3860191202
Short name T439
Test name
Test status
Simulation time 173047739132 ps
CPU time 130.74 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:40:26 PM PDT 24
Peak memory 199976 kb
Host smart-f8823f66-ffbe-45ae-84e7-4d5cef4eafd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860191202 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.3860191202
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3671277312
Short name T813
Test name
Test status
Simulation time 93376846201 ps
CPU time 66.14 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:39:21 PM PDT 24
Peak memory 200016 kb
Host smart-f09ccb74-c5aa-4493-b7e1-007d3e56daee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671277312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3671277312
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.1262277263
Short name T1076
Test name
Test status
Simulation time 82668384784 ps
CPU time 59.78 seconds
Started Aug 02 05:38:15 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 199976 kb
Host smart-4f3f37f0-7eef-43e3-babc-5866142cf079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262277263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.1262277263
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.2543380299
Short name T1179
Test name
Test status
Simulation time 10927408 ps
CPU time 0.53 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 194368 kb
Host smart-c994381e-3000-4d62-8d71-e3cb5bca0173
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543380299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.2543380299
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.3916045935
Short name T72
Test name
Test status
Simulation time 152747332427 ps
CPU time 130.35 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 199960 kb
Host smart-a7b8967b-99b6-4abb-b5b0-97100694afb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916045935 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.3916045935
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2447236699
Short name T920
Test name
Test status
Simulation time 84926069773 ps
CPU time 52.97 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 199924 kb
Host smart-1189d117-3430-4d75-8fe1-8723cee1aaf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447236699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2447236699
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.1928606478
Short name T954
Test name
Test status
Simulation time 33940102504 ps
CPU time 142.17 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 199984 kb
Host smart-dad7dc32-6523-4b2c-bf15-2356a5279a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928606478 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.1928606478
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_intr.1381726173
Short name T1109
Test name
Test status
Simulation time 15250811708 ps
CPU time 20.16 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 197696 kb
Host smart-43bc01dc-065f-4b34-9947-8c7f45245e81
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381726173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1381726173
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.2391653736
Short name T402
Test name
Test status
Simulation time 90214480185 ps
CPU time 455.13 seconds
Started Aug 02 05:36:17 PM PDT 24
Finished Aug 02 05:43:52 PM PDT 24
Peak memory 199744 kb
Host smart-7897cd4a-622e-43e5-8964-3e8e10351204
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2391653736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.2391653736
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2295414786
Short name T18
Test name
Test status
Simulation time 7675806160 ps
CPU time 6.94 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 199616 kb
Host smart-13effbba-b62a-4e30-9a47-41c55f11678d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295414786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2295414786
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.1061640350
Short name T875
Test name
Test status
Simulation time 102444567070 ps
CPU time 104.19 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:37:52 PM PDT 24
Peak memory 208032 kb
Host smart-dbb700b6-ba2e-489f-b2a4-b0eb504b5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061640350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.1061640350
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.337880147
Short name T970
Test name
Test status
Simulation time 13077266949 ps
CPU time 406.24 seconds
Started Aug 02 05:36:14 PM PDT 24
Finished Aug 02 05:43:01 PM PDT 24
Peak memory 199960 kb
Host smart-a7104388-7061-40eb-b572-d44fc6cd7b72
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=337880147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.337880147
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.850455954
Short name T883
Test name
Test status
Simulation time 1273718767 ps
CPU time 2.64 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:03 PM PDT 24
Peak memory 198244 kb
Host smart-eed49915-2275-46d1-8395-9c2faa2e5f7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=850455954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.850455954
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.2447954491
Short name T1093
Test name
Test status
Simulation time 20200184799 ps
CPU time 48.06 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 199516 kb
Host smart-a22eb9cc-6079-4927-aa99-773ee8d31c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447954491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.2447954491
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.1771388698
Short name T359
Test name
Test status
Simulation time 4866360105 ps
CPU time 1.34 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:36:16 PM PDT 24
Peak memory 196580 kb
Host smart-ba2d1a2f-0fdb-4d0d-a784-4a41c37c5e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771388698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.1771388698
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.124900997
Short name T816
Test name
Test status
Simulation time 454294867 ps
CPU time 1.47 seconds
Started Aug 02 05:36:19 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 198732 kb
Host smart-b8fa77dd-ef5b-44d1-84cc-60d51b5ff9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124900997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.124900997
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.3906947454
Short name T1116
Test name
Test status
Simulation time 211057324720 ps
CPU time 305.94 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:41:29 PM PDT 24
Peak memory 199932 kb
Host smart-1af2f653-1de0-405a-b4b8-4fb894f2be22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906947454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.3906947454
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.2502716680
Short name T728
Test name
Test status
Simulation time 6899697171 ps
CPU time 31.75 seconds
Started Aug 02 05:36:07 PM PDT 24
Finished Aug 02 05:36:39 PM PDT 24
Peak memory 199816 kb
Host smart-f79223ad-c56d-4aa3-ad70-75c3079eb0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502716680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.2502716680
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.1663931355
Short name T779
Test name
Test status
Simulation time 73648912614 ps
CPU time 119.03 seconds
Started Aug 02 05:36:08 PM PDT 24
Finished Aug 02 05:38:07 PM PDT 24
Peak memory 200068 kb
Host smart-21044a71-39a9-4aed-9242-ae1fce60f249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663931355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.1663931355
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.1910484772
Short name T259
Test name
Test status
Simulation time 76861445411 ps
CPU time 8.05 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:38:21 PM PDT 24
Peak memory 199968 kb
Host smart-cc1e97b3-0b68-4083-9392-28f2caa54c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910484772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.1910484772
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.2140866916
Short name T684
Test name
Test status
Simulation time 25175219160 ps
CPU time 73.97 seconds
Started Aug 02 05:38:13 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 199968 kb
Host smart-9d03edf9-e2a2-40cd-ae2b-4081d732b84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140866916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.2140866916
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3319987719
Short name T1111
Test name
Test status
Simulation time 54389760179 ps
CPU time 77.3 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 199948 kb
Host smart-9ca518c1-db40-4e29-948c-55767d1937c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319987719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3319987719
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3725453104
Short name T170
Test name
Test status
Simulation time 130925443252 ps
CPU time 233.19 seconds
Started Aug 02 05:38:23 PM PDT 24
Finished Aug 02 05:42:17 PM PDT 24
Peak memory 200004 kb
Host smart-82a27fd3-632b-41ff-b5c5-daf15d3ca54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725453104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3725453104
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.3507350344
Short name T848
Test name
Test status
Simulation time 14346425841 ps
CPU time 28.76 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:38:53 PM PDT 24
Peak memory 199952 kb
Host smart-a3f30d37-512d-4bb8-9b41-f7763a546bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507350344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.3507350344
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.3775965796
Short name T1070
Test name
Test status
Simulation time 35368793288 ps
CPU time 28.62 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:38:54 PM PDT 24
Peak memory 199732 kb
Host smart-0bf3707a-0c78-4c87-a0c8-52b35508b156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775965796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.3775965796
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1159205318
Short name T1074
Test name
Test status
Simulation time 135022715671 ps
CPU time 48.68 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:39:13 PM PDT 24
Peak memory 199948 kb
Host smart-d907fb9f-74ab-4205-b773-3e7be06488a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159205318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1159205318
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.1763779572
Short name T1101
Test name
Test status
Simulation time 35578339927 ps
CPU time 15.69 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:38:40 PM PDT 24
Peak memory 199896 kb
Host smart-1325665e-3439-47ad-b80f-75de496c1b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763779572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.1763779572
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3061427711
Short name T203
Test name
Test status
Simulation time 57496101369 ps
CPU time 28.52 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:38:53 PM PDT 24
Peak memory 200000 kb
Host smart-a471908c-25ca-418a-92bc-0107facfbe78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061427711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3061427711
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.2412974861
Short name T1120
Test name
Test status
Simulation time 21282195 ps
CPU time 0.54 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:36:28 PM PDT 24
Peak memory 195488 kb
Host smart-410aaef3-f2cd-422a-b545-5e424d8ba7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412974861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.2412974861
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.4237014366
Short name T913
Test name
Test status
Simulation time 69608460113 ps
CPU time 56.22 seconds
Started Aug 02 05:36:25 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 199952 kb
Host smart-abf9add3-aac6-4dc2-9315-7bce2b73f9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237014366 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.4237014366
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.3962426328
Short name T253
Test name
Test status
Simulation time 65802248801 ps
CPU time 148.77 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199896 kb
Host smart-487d8d0e-9ba2-4dba-a461-2cbe639a13ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962426328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.3962426328
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.706852026
Short name T674
Test name
Test status
Simulation time 14554275325 ps
CPU time 22.88 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:36:20 PM PDT 24
Peak memory 200020 kb
Host smart-36f352c5-61e9-4ea0-a47d-bc1ecfc28641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706852026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.706852026
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.1101565567
Short name T773
Test name
Test status
Simulation time 14462233697 ps
CPU time 5.99 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:12 PM PDT 24
Peak memory 196248 kb
Host smart-c012acd7-4963-4fab-8e4f-f296bb8cec6a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101565567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.1101565567
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.3458690108
Short name T360
Test name
Test status
Simulation time 94532275741 ps
CPU time 456.21 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:43:32 PM PDT 24
Peak memory 199952 kb
Host smart-03ce4342-f06f-4d60-807a-0831383b01dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458690108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.3458690108
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.226357638
Short name T605
Test name
Test status
Simulation time 9668888474 ps
CPU time 14.93 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 198104 kb
Host smart-e1693721-6f93-4fe7-a97a-9ea5e6144c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226357638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.226357638
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3537583395
Short name T908
Test name
Test status
Simulation time 334795750684 ps
CPU time 42.03 seconds
Started Aug 02 05:36:17 PM PDT 24
Finished Aug 02 05:36:59 PM PDT 24
Peak memory 200028 kb
Host smart-389af014-f38c-4805-9295-6c38b63ab695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537583395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3537583395
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.3900519006
Short name T957
Test name
Test status
Simulation time 16230229535 ps
CPU time 993.79 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:52:46 PM PDT 24
Peak memory 200000 kb
Host smart-fcb1f3c6-e7dd-4d42-8cdc-73465dea99ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3900519006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.3900519006
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.138451217
Short name T783
Test name
Test status
Simulation time 1395066789 ps
CPU time 1.02 seconds
Started Aug 02 05:36:03 PM PDT 24
Finished Aug 02 05:36:04 PM PDT 24
Peak memory 195536 kb
Host smart-e8cf5118-9f07-4e86-ba6f-f315ee76482c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=138451217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.138451217
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.617887194
Short name T532
Test name
Test status
Simulation time 160222816557 ps
CPU time 15.81 seconds
Started Aug 02 05:36:20 PM PDT 24
Finished Aug 02 05:36:36 PM PDT 24
Peak memory 199760 kb
Host smart-88221c1b-2ac9-46a6-b253-7eccd3bc3cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617887194 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.617887194
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1654537299
Short name T1015
Test name
Test status
Simulation time 3935695993 ps
CPU time 6.03 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:08 PM PDT 24
Peak memory 196836 kb
Host smart-243bece2-6129-4423-add3-f762ec8c96e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654537299 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1654537299
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.1850592101
Short name T1069
Test name
Test status
Simulation time 140355640 ps
CPU time 0.78 seconds
Started Aug 02 05:36:17 PM PDT 24
Finished Aug 02 05:36:18 PM PDT 24
Peak memory 197244 kb
Host smart-729ca6f1-9dd4-4f0d-848c-7f64846d359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850592101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.1850592101
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.2474547716
Short name T237
Test name
Test status
Simulation time 233412682489 ps
CPU time 96.44 seconds
Started Aug 02 05:36:18 PM PDT 24
Finished Aug 02 05:37:54 PM PDT 24
Peak memory 199972 kb
Host smart-b1818f20-3926-4260-b770-5864320ae468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474547716 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.2474547716
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1641967294
Short name T311
Test name
Test status
Simulation time 87478648109 ps
CPU time 180.26 seconds
Started Aug 02 05:36:10 PM PDT 24
Finished Aug 02 05:39:12 PM PDT 24
Peak memory 208620 kb
Host smart-b8a98058-c427-4483-b32e-4ae33eee396e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641967294 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1641967294
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.2066373693
Short name T906
Test name
Test status
Simulation time 7548973712 ps
CPU time 10.37 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 199812 kb
Host smart-60ba92f4-9cf0-4049-98e5-dc18f61b2927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066373693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.2066373693
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.914069999
Short name T327
Test name
Test status
Simulation time 81790591854 ps
CPU time 66.41 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 199928 kb
Host smart-95a2d386-e6a0-4c72-9e48-26e2f2819f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914069999 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.914069999
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.844719283
Short name T924
Test name
Test status
Simulation time 130558242008 ps
CPU time 59.56 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 199968 kb
Host smart-589c8e5c-c6c0-4708-9ef2-3a28fc6d147f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844719283 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.844719283
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.4133006104
Short name T584
Test name
Test status
Simulation time 101019057126 ps
CPU time 67.72 seconds
Started Aug 02 05:38:23 PM PDT 24
Finished Aug 02 05:39:31 PM PDT 24
Peak memory 199904 kb
Host smart-1848b541-885f-4888-86a0-8ca9f4699e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133006104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.4133006104
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3384748599
Short name T726
Test name
Test status
Simulation time 55293602095 ps
CPU time 17.21 seconds
Started Aug 02 05:38:23 PM PDT 24
Finished Aug 02 05:38:40 PM PDT 24
Peak memory 200068 kb
Host smart-0a072e5a-b279-49e1-9287-c61613310f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384748599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3384748599
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3317730864
Short name T1002
Test name
Test status
Simulation time 49873281902 ps
CPU time 79.96 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:39:44 PM PDT 24
Peak memory 199968 kb
Host smart-7aa60f75-7629-4f33-b80b-0780ffd53a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317730864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3317730864
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.1106963258
Short name T798
Test name
Test status
Simulation time 51024878438 ps
CPU time 53.33 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 199952 kb
Host smart-2e3ed6ca-b4a8-4b91-a807-bc267751100a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106963258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.1106963258
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3019919429
Short name T171
Test name
Test status
Simulation time 30397240782 ps
CPU time 44.33 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:39:10 PM PDT 24
Peak memory 199968 kb
Host smart-e9a72f7f-b9a6-4c71-bc49-0c2fd2767143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019919429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3019919429
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.1248223637
Short name T722
Test name
Test status
Simulation time 125891805880 ps
CPU time 180.53 seconds
Started Aug 02 05:38:23 PM PDT 24
Finished Aug 02 05:41:24 PM PDT 24
Peak memory 199992 kb
Host smart-32a1492c-39e5-4e82-8283-f0374efeb7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248223637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.1248223637
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3290683816
Short name T992
Test name
Test status
Simulation time 97746572963 ps
CPU time 72.8 seconds
Started Aug 02 05:38:25 PM PDT 24
Finished Aug 02 05:39:38 PM PDT 24
Peak memory 199984 kb
Host smart-1342b5da-a322-4aba-bb1c-3a1ef4ef695e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290683816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3290683816
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.2438799042
Short name T225
Test name
Test status
Simulation time 98789926427 ps
CPU time 88.73 seconds
Started Aug 02 05:38:22 PM PDT 24
Finished Aug 02 05:39:51 PM PDT 24
Peak memory 199920 kb
Host smart-29833b48-ca69-485a-8b24-b0ab732369f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438799042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.2438799042
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.4222204450
Short name T607
Test name
Test status
Simulation time 33153367 ps
CPU time 0.55 seconds
Started Aug 02 05:36:19 PM PDT 24
Finished Aug 02 05:36:20 PM PDT 24
Peak memory 195420 kb
Host smart-c61dea59-a9ef-4891-b60b-3ceebbf21348
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222204450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.4222204450
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4107713158
Short name T917
Test name
Test status
Simulation time 60222230555 ps
CPU time 51.37 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:37:13 PM PDT 24
Peak memory 199952 kb
Host smart-f872fa44-ce21-481d-a569-e832fa24cc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107713158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4107713158
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.1177522387
Short name T467
Test name
Test status
Simulation time 45952356650 ps
CPU time 21.41 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 199260 kb
Host smart-14d32a7f-ca1a-4532-b69b-07b2cdf4b81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177522387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.1177522387
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.684328466
Short name T564
Test name
Test status
Simulation time 160464437290 ps
CPU time 345.53 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:41:43 PM PDT 24
Peak memory 199920 kb
Host smart-21c542b6-26a1-4413-9a40-cd9f0b062cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684328466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.684328466
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.1517955458
Short name T790
Test name
Test status
Simulation time 5247621862 ps
CPU time 7.38 seconds
Started Aug 02 05:36:06 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 196704 kb
Host smart-d6b1e72e-4a24-4bd0-b2eb-55dd712bf010
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517955458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.1517955458
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.697879358
Short name T863
Test name
Test status
Simulation time 189511421612 ps
CPU time 485.19 seconds
Started Aug 02 05:35:57 PM PDT 24
Finished Aug 02 05:44:03 PM PDT 24
Peak memory 199964 kb
Host smart-0c8526d7-62f2-4707-b0a0-6bbfc7fca617
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697879358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.697879358
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.1072295899
Short name T358
Test name
Test status
Simulation time 9081905903 ps
CPU time 26.22 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:36:39 PM PDT 24
Peak memory 199936 kb
Host smart-6a3bfa30-902b-48c9-b50b-c66c8505cc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072295899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.1072295899
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.872032236
Short name T720
Test name
Test status
Simulation time 127321421018 ps
CPU time 52.56 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 208308 kb
Host smart-cf9ba5db-9f4f-4731-9a7b-0a587ffd1a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872032236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.872032236
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.2280173840
Short name T847
Test name
Test status
Simulation time 16349043719 ps
CPU time 421.55 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:43:14 PM PDT 24
Peak memory 199968 kb
Host smart-ae5458e2-df4d-44c4-a639-e9999b09ece5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2280173840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.2280173840
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.3911648228
Short name T599
Test name
Test status
Simulation time 2663534428 ps
CPU time 5.25 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 198368 kb
Host smart-533ff005-fbdd-47d0-b2c7-983b5a2e31dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911648228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.3911648228
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.50623172
Short name T296
Test name
Test status
Simulation time 71387181289 ps
CPU time 45.95 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:36:59 PM PDT 24
Peak memory 199888 kb
Host smart-5239198b-7be3-494a-b13f-2abc2697d414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50623172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.50623172
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.1561352308
Short name T702
Test name
Test status
Simulation time 2009186719 ps
CPU time 3.17 seconds
Started Aug 02 05:36:10 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 195468 kb
Host smart-1c3e2945-4a89-4ed3-affc-a34d08842d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561352308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.1561352308
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2354968772
Short name T1148
Test name
Test status
Simulation time 542282927 ps
CPU time 2.01 seconds
Started Aug 02 05:36:14 PM PDT 24
Finished Aug 02 05:36:16 PM PDT 24
Peak memory 199224 kb
Host smart-47b9bac2-6f77-4c37-8c04-de4288b1fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354968772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2354968772
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.1265579747
Short name T707
Test name
Test status
Simulation time 186806910788 ps
CPU time 1225.46 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:56:25 PM PDT 24
Peak memory 199964 kb
Host smart-fd5e2c1c-6994-4dd9-936b-31f1471d3f5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265579747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.1265579747
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1110767669
Short name T842
Test name
Test status
Simulation time 71567817578 ps
CPU time 164.19 seconds
Started Aug 02 05:36:17 PM PDT 24
Finished Aug 02 05:39:01 PM PDT 24
Peak memory 212988 kb
Host smart-5bfc3a61-3dc9-4acb-82a7-da227e2c91e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110767669 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1110767669
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.875076633
Short name T501
Test name
Test status
Simulation time 6450273565 ps
CPU time 20.25 seconds
Started Aug 02 05:36:11 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 199976 kb
Host smart-b583811f-87bb-4ebe-934e-1f85c236a220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875076633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.875076633
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.895736524
Short name T274
Test name
Test status
Simulation time 40217798670 ps
CPU time 17.53 seconds
Started Aug 02 05:35:55 PM PDT 24
Finished Aug 02 05:36:13 PM PDT 24
Peak memory 199984 kb
Host smart-cfe0319a-f857-4e0c-b679-8e9a83039a6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895736524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.895736524
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2497701216
Short name T410
Test name
Test status
Simulation time 119963596543 ps
CPU time 134.55 seconds
Started Aug 02 05:38:23 PM PDT 24
Finished Aug 02 05:40:38 PM PDT 24
Peak memory 199968 kb
Host smart-8ed47714-1155-4390-ac92-ef8b86d2e5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497701216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2497701216
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.804952978
Short name T210
Test name
Test status
Simulation time 20138489824 ps
CPU time 34.46 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:38:59 PM PDT 24
Peak memory 199976 kb
Host smart-0818f4dd-a87c-44fb-b845-1c4f8f2a20b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804952978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.804952978
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.1611893915
Short name T484
Test name
Test status
Simulation time 14171641053 ps
CPU time 11.17 seconds
Started Aug 02 05:38:27 PM PDT 24
Finished Aug 02 05:38:38 PM PDT 24
Peak memory 199932 kb
Host smart-2944e42d-af06-454b-8a91-c0f48e9d6d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611893915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.1611893915
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.3374947625
Short name T915
Test name
Test status
Simulation time 48354317039 ps
CPU time 67.71 seconds
Started Aug 02 05:38:24 PM PDT 24
Finished Aug 02 05:39:32 PM PDT 24
Peak memory 199912 kb
Host smart-f0719f2f-28ae-47b8-8953-9779e0542377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374947625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.3374947625
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3915622835
Short name T1165
Test name
Test status
Simulation time 180719502536 ps
CPU time 247.06 seconds
Started Aug 02 05:38:26 PM PDT 24
Finished Aug 02 05:42:33 PM PDT 24
Peak memory 199912 kb
Host smart-962986da-0a17-4c97-a3c5-8e74390b9644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915622835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3915622835
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2253523547
Short name T234
Test name
Test status
Simulation time 15751093047 ps
CPU time 17 seconds
Started Aug 02 05:38:22 PM PDT 24
Finished Aug 02 05:38:40 PM PDT 24
Peak memory 199988 kb
Host smart-1b10abc9-360a-4c3f-a6dc-52755e16d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253523547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2253523547
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3895836229
Short name T760
Test name
Test status
Simulation time 119453060861 ps
CPU time 196.84 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:41:52 PM PDT 24
Peak memory 199924 kb
Host smart-042b9ad3-0544-481d-a842-c2db3d6fe29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895836229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3895836229
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.4287761363
Short name T471
Test name
Test status
Simulation time 88312013794 ps
CPU time 14.74 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 199976 kb
Host smart-285931d9-151c-4a39-a548-cf7d1567ac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287761363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.4287761363
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1959182170
Short name T511
Test name
Test status
Simulation time 8699444633 ps
CPU time 15.21 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 199988 kb
Host smart-f68e49ee-e14e-426d-9af1-584a6fb6be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959182170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1959182170
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.3012305698
Short name T645
Test name
Test status
Simulation time 56281574 ps
CPU time 0.54 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 195400 kb
Host smart-0407f696-a725-4a8c-b8e4-272cc5dee84d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012305698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.3012305698
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.884994792
Short name T721
Test name
Test status
Simulation time 40876728116 ps
CPU time 13.93 seconds
Started Aug 02 05:36:29 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 199812 kb
Host smart-2f295136-5c05-4018-a93b-dd9a88a1b0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884994792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.884994792
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2656681665
Short name T1094
Test name
Test status
Simulation time 26159758514 ps
CPU time 13.27 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:36:26 PM PDT 24
Peak memory 198324 kb
Host smart-3c87f776-0618-4e48-8220-e30d773b51d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656681665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2656681665
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1926017523
Short name T347
Test name
Test status
Simulation time 12272153277 ps
CPU time 5.93 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 199876 kb
Host smart-40c4610d-71bf-4f11-b43a-c9fb6a491bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926017523 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1926017523
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.1647340181
Short name T415
Test name
Test status
Simulation time 40051248213 ps
CPU time 11.16 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 199808 kb
Host smart-48beb7aa-8fef-47e8-974f-979260742db5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647340181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.1647340181
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.2083218079
Short name T891
Test name
Test status
Simulation time 75643307576 ps
CPU time 582.48 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:46:05 PM PDT 24
Peak memory 200024 kb
Host smart-553c658a-4368-462a-8781-1fdfa4ce84af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083218079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.2083218079
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.269917600
Short name T335
Test name
Test status
Simulation time 13321032135 ps
CPU time 6.74 seconds
Started Aug 02 05:36:15 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 195992 kb
Host smart-cc25898c-1ef1-4f36-bbbf-404d13994bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269917600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.269917600
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.340783603
Short name T826
Test name
Test status
Simulation time 100274896801 ps
CPU time 65.49 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:37:29 PM PDT 24
Peak memory 209420 kb
Host smart-f4e730e9-4eb7-4158-a6c1-a9381f95824a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340783603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.340783603
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.3079760603
Short name T308
Test name
Test status
Simulation time 21075291219 ps
CPU time 56.08 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:37:17 PM PDT 24
Peak memory 199960 kb
Host smart-9e12bab9-c43c-405e-ba2f-8a236a5f0cd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079760603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.3079760603
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.10706581
Short name T386
Test name
Test status
Simulation time 6767904969 ps
CPU time 49.15 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:37:12 PM PDT 24
Peak memory 199052 kb
Host smart-b63a391b-5fd6-48b1-9343-84d1bb4445d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10706581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.10706581
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.1772360258
Short name T1115
Test name
Test status
Simulation time 381394444069 ps
CPU time 45.84 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:37:10 PM PDT 24
Peak memory 200000 kb
Host smart-32f88c43-ef30-4f0a-987d-b4ce7ed74325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772360258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.1772360258
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.2062175248
Short name T11
Test name
Test status
Simulation time 581990789 ps
CPU time 0.84 seconds
Started Aug 02 05:36:19 PM PDT 24
Finished Aug 02 05:36:25 PM PDT 24
Peak memory 195476 kb
Host smart-8ae8065b-1419-47c8-9805-d4a0076be903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062175248 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.2062175248
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.364222827
Short name T419
Test name
Test status
Simulation time 5552339618 ps
CPU time 34.24 seconds
Started Aug 02 05:36:00 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 199896 kb
Host smart-694cf915-9e0c-4c46-9076-48eaee0c6cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364222827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.364222827
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.4043425891
Short name T789
Test name
Test status
Simulation time 87862941024 ps
CPU time 883.53 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:51:11 PM PDT 24
Peak memory 216476 kb
Host smart-eb318822-fe6b-401e-84ff-b3a09f30ade3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043425891 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.4043425891
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.768340333
Short name T879
Test name
Test status
Simulation time 1141091519 ps
CPU time 3.46 seconds
Started Aug 02 05:36:30 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 199292 kb
Host smart-a5779771-4f4b-47fa-badb-c42ae23b96a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768340333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.768340333
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1442876001
Short name T562
Test name
Test status
Simulation time 81962608346 ps
CPU time 165.51 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:38:58 PM PDT 24
Peak memory 199888 kb
Host smart-d36e729f-4518-4e9d-926b-b8cd8afc7a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442876001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1442876001
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.966573646
Short name T123
Test name
Test status
Simulation time 131336617387 ps
CPU time 189.43 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:41:44 PM PDT 24
Peak memory 199912 kb
Host smart-30295906-9ef7-4628-a1ea-e4066a455a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966573646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.966573646
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.849112451
Short name T1075
Test name
Test status
Simulation time 33646909786 ps
CPU time 13.67 seconds
Started Aug 02 05:38:39 PM PDT 24
Finished Aug 02 05:38:53 PM PDT 24
Peak memory 199952 kb
Host smart-3fb8e4ff-a3c0-40b7-8cf6-6b71b2790e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849112451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.849112451
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.1038977804
Short name T186
Test name
Test status
Simulation time 41614508805 ps
CPU time 36.36 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:39:13 PM PDT 24
Peak memory 199964 kb
Host smart-f9961dcd-7ae9-4333-b4d4-a39cd5a0cea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038977804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.1038977804
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.609883280
Short name T903
Test name
Test status
Simulation time 37184689513 ps
CPU time 80.13 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:39:56 PM PDT 24
Peak memory 200000 kb
Host smart-dfc91ca9-0996-4844-baf4-ee2880de116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609883280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.609883280
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.738270854
Short name T54
Test name
Test status
Simulation time 17312213104 ps
CPU time 27.31 seconds
Started Aug 02 05:38:37 PM PDT 24
Finished Aug 02 05:39:04 PM PDT 24
Peak memory 199928 kb
Host smart-cb90d07a-46cb-4276-8a5e-fbc2f4ba9a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738270854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.738270854
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.1791183972
Short name T442
Test name
Test status
Simulation time 60500514404 ps
CPU time 34.6 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:39:11 PM PDT 24
Peak memory 200012 kb
Host smart-a1d7371a-b651-4138-a1d8-7a38c7c99722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791183972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.1791183972
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.4048792204
Short name T888
Test name
Test status
Simulation time 43403523592 ps
CPU time 82.26 seconds
Started Aug 02 05:38:40 PM PDT 24
Finished Aug 02 05:40:03 PM PDT 24
Peak memory 199968 kb
Host smart-95a0116b-ca80-4b9a-b1da-228dd7d81037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048792204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.4048792204
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.3812570220
Short name T747
Test name
Test status
Simulation time 21838415095 ps
CPU time 8.83 seconds
Started Aug 02 05:38:39 PM PDT 24
Finished Aug 02 05:38:48 PM PDT 24
Peak memory 199968 kb
Host smart-98275056-9753-4ea6-81f9-4e9b6ba425eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812570220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.3812570220
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.3850518131
Short name T750
Test name
Test status
Simulation time 34327274 ps
CPU time 0.58 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:36:22 PM PDT 24
Peak memory 195344 kb
Host smart-cb6de229-07b4-4151-84ae-b49cf9eb8a5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850518131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.3850518131
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2341542369
Short name T472
Test name
Test status
Simulation time 113432483798 ps
CPU time 16.17 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:18 PM PDT 24
Peak memory 199972 kb
Host smart-30a7a2d5-13c0-4020-89a8-4dcc5eb88a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341542369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2341542369
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3319100951
Short name T121
Test name
Test status
Simulation time 70409195237 ps
CPU time 119.42 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:38:13 PM PDT 24
Peak memory 200024 kb
Host smart-736b84a5-b19d-4970-b433-cf967f454162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319100951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3319100951
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_intr.3336736487
Short name T880
Test name
Test status
Simulation time 150246015550 ps
CPU time 198.02 seconds
Started Aug 02 05:36:18 PM PDT 24
Finished Aug 02 05:39:36 PM PDT 24
Peak memory 199984 kb
Host smart-b3009155-4b37-4668-8387-a3362c81e9a2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336736487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.3336736487
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.3600139499
Short name T758
Test name
Test status
Simulation time 70772605829 ps
CPU time 490.8 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:44:24 PM PDT 24
Peak memory 199928 kb
Host smart-0ea08160-e666-4141-994c-5e27e12849dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3600139499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.3600139499
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.1863509406
Short name T369
Test name
Test status
Simulation time 3930596076 ps
CPU time 2.46 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 197980 kb
Host smart-0d6aee2c-ce96-4801-b3aa-6de9a337d655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863509406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.1863509406
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.3199535753
Short name T1168
Test name
Test status
Simulation time 63327047125 ps
CPU time 7.29 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:36:20 PM PDT 24
Peak memory 193968 kb
Host smart-8232836b-fbe9-448b-9dc8-de97cad40286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199535753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.3199535753
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.131421311
Short name T339
Test name
Test status
Simulation time 11930504752 ps
CPU time 386.66 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 199928 kb
Host smart-efafdcb5-1812-49ac-bde6-7f02f36df818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=131421311 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.131421311
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1178512629
Short name T694
Test name
Test status
Simulation time 4873542711 ps
CPU time 10.49 seconds
Started Aug 02 05:36:18 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 199016 kb
Host smart-97938353-f7ea-4b32-8b27-1df2ad1d29af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178512629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1178512629
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.3202848706
Short name T162
Test name
Test status
Simulation time 35555843306 ps
CPU time 60.97 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:37:24 PM PDT 24
Peak memory 199972 kb
Host smart-2e1af6d7-d0ea-4a8e-b721-cad10ca841b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202848706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.3202848706
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.3464373566
Short name T613
Test name
Test status
Simulation time 5265643370 ps
CPU time 8.94 seconds
Started Aug 02 05:36:32 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 196128 kb
Host smart-15a90b6f-1eea-4495-b1f0-fd6c3610947d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464373566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.3464373566
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.3263889685
Short name T866
Test name
Test status
Simulation time 457948154 ps
CPU time 1.53 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:36:26 PM PDT 24
Peak memory 199104 kb
Host smart-34ee6db4-33ef-4030-8041-4c70c835a3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263889685 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.3263889685
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.3316790638
Short name T1011
Test name
Test status
Simulation time 295376179610 ps
CPU time 1539.9 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 06:01:42 PM PDT 24
Peak memory 215712 kb
Host smart-fd7028e3-f657-497f-aa9b-a818d2441138
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316790638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.3316790638
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.1987262963
Short name T97
Test name
Test status
Simulation time 168267432299 ps
CPU time 442.19 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:43:45 PM PDT 24
Peak memory 224792 kb
Host smart-77ee8954-1dad-4228-af2e-174e3cf1ed67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987262963 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.1987262963
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.155470797
Short name T1144
Test name
Test status
Simulation time 1237852590 ps
CPU time 2.51 seconds
Started Aug 02 05:36:04 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 199388 kb
Host smart-29100c68-1088-443b-9c30-8051ce8fe674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155470797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.155470797
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/29.uart_tx_rx.2197094071
Short name T421
Test name
Test status
Simulation time 25103841886 ps
CPU time 8.38 seconds
Started Aug 02 05:36:12 PM PDT 24
Finished Aug 02 05:36:21 PM PDT 24
Peak memory 199304 kb
Host smart-82eca67f-94d0-4a29-be82-f21f44b9c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197094071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.2197094071
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.2269163111
Short name T174
Test name
Test status
Simulation time 64235534949 ps
CPU time 140.16 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:40:56 PM PDT 24
Peak memory 199924 kb
Host smart-836dfb76-fafe-4acd-96a9-e3ccf4c3de01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269163111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.2269163111
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.886073267
Short name T898
Test name
Test status
Simulation time 21398467111 ps
CPU time 15.42 seconds
Started Aug 02 05:38:37 PM PDT 24
Finished Aug 02 05:38:53 PM PDT 24
Peak memory 198184 kb
Host smart-87b1b4db-d9dc-4643-8ca9-89e6a65506ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886073267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.886073267
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.2328573992
Short name T230
Test name
Test status
Simulation time 43256720071 ps
CPU time 40.22 seconds
Started Aug 02 05:38:35 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 199884 kb
Host smart-3d7a4428-2140-41bd-bcfa-ffbfe0b338df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328573992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.2328573992
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3680000373
Short name T803
Test name
Test status
Simulation time 11975632524 ps
CPU time 20.2 seconds
Started Aug 02 05:38:34 PM PDT 24
Finished Aug 02 05:38:54 PM PDT 24
Peak memory 200012 kb
Host smart-bb796429-160c-481b-8086-5aae35dfcfc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680000373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3680000373
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.3470928640
Short name T232
Test name
Test status
Simulation time 6827501270 ps
CPU time 25.97 seconds
Started Aug 02 05:38:34 PM PDT 24
Finished Aug 02 05:39:00 PM PDT 24
Peak memory 199944 kb
Host smart-9206db17-5228-45fd-82dc-3b8c30786106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470928640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.3470928640
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.1159730677
Short name T328
Test name
Test status
Simulation time 44739964198 ps
CPU time 27.08 seconds
Started Aug 02 05:38:36 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 199948 kb
Host smart-acf9579b-357f-45b2-aeae-4ce44d1359c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159730677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.1159730677
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.365975388
Short name T324
Test name
Test status
Simulation time 31146681764 ps
CPU time 49.6 seconds
Started Aug 02 05:38:34 PM PDT 24
Finished Aug 02 05:39:24 PM PDT 24
Peak memory 200000 kb
Host smart-23222fe9-b286-4ee6-9844-52674e5d30c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365975388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.365975388
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.1320178243
Short name T742
Test name
Test status
Simulation time 9415592882 ps
CPU time 11.02 seconds
Started Aug 02 05:38:32 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 199932 kb
Host smart-bc6a6e27-a799-4d80-b4cc-ac20bfbdbcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320178243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.1320178243
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.3994118431
Short name T994
Test name
Test status
Simulation time 136586378006 ps
CPU time 112.2 seconds
Started Aug 02 05:38:34 PM PDT 24
Finished Aug 02 05:40:27 PM PDT 24
Peak memory 200004 kb
Host smart-d9bdaf91-1bcf-49a7-991b-48f06f676727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994118431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.3994118431
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.3782416253
Short name T603
Test name
Test status
Simulation time 12277939 ps
CPU time 0.57 seconds
Started Aug 02 05:35:27 PM PDT 24
Finished Aug 02 05:35:28 PM PDT 24
Peak memory 195652 kb
Host smart-d85da0fb-24fb-4ea0-b677-d18ba9698aeb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782416253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.3782416253
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.1059518690
Short name T290
Test name
Test status
Simulation time 80971923063 ps
CPU time 24.17 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:35:58 PM PDT 24
Peak memory 199988 kb
Host smart-745b06c2-3678-4f28-aed9-09b88b0087f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059518690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.1059518690
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.509775309
Short name T835
Test name
Test status
Simulation time 68592427102 ps
CPU time 46.13 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:36:11 PM PDT 24
Peak memory 199904 kb
Host smart-d98b965d-46cf-45c7-8d25-1edc06915a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509775309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.509775309
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.210169778
Short name T1047
Test name
Test status
Simulation time 47051965818 ps
CPU time 87.71 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:36:32 PM PDT 24
Peak memory 199944 kb
Host smart-a078d40d-0d0d-40e5-9c83-06415effc06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210169778 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.210169778
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.141573654
Short name T429
Test name
Test status
Simulation time 47208133437 ps
CPU time 17.95 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:35:54 PM PDT 24
Peak memory 199952 kb
Host smart-dcdfd789-3cfa-4247-b4ca-ef2ebf0a5cdc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141573654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.141573654
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.1105000150
Short name T756
Test name
Test status
Simulation time 127207068388 ps
CPU time 276.3 seconds
Started Aug 02 05:35:27 PM PDT 24
Finished Aug 02 05:40:04 PM PDT 24
Peak memory 199936 kb
Host smart-576877ba-046e-44ff-b456-c10490932f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105000150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.1105000150
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.860385266
Short name T498
Test name
Test status
Simulation time 415325246 ps
CPU time 1.14 seconds
Started Aug 02 05:35:23 PM PDT 24
Finished Aug 02 05:35:24 PM PDT 24
Peak memory 198068 kb
Host smart-548ecbdb-6874-42ce-b318-1eb7dd973387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860385266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.860385266
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1647596610
Short name T878
Test name
Test status
Simulation time 80833150954 ps
CPU time 59.94 seconds
Started Aug 02 05:35:24 PM PDT 24
Finished Aug 02 05:36:25 PM PDT 24
Peak memory 200112 kb
Host smart-9b6ab5a6-b4c1-44d8-8686-cc597608fed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647596610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1647596610
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.3067514444
Short name T717
Test name
Test status
Simulation time 33189549173 ps
CPU time 313.28 seconds
Started Aug 02 05:35:53 PM PDT 24
Finished Aug 02 05:41:06 PM PDT 24
Peak memory 199964 kb
Host smart-a7a3b23c-f6c3-410b-a105-6d1752c3e8b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067514444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.3067514444
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.671147399
Short name T435
Test name
Test status
Simulation time 6347724897 ps
CPU time 42.61 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 198132 kb
Host smart-dc2667b0-284f-43bc-acff-ad6f86b7109f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=671147399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.671147399
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.1288067724
Short name T159
Test name
Test status
Simulation time 39707606945 ps
CPU time 17.73 seconds
Started Aug 02 05:35:17 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 198532 kb
Host smart-09653e38-9b90-4666-baea-6c48f24d21ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288067724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.1288067724
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.359502579
Short name T763
Test name
Test status
Simulation time 3612721382 ps
CPU time 3.66 seconds
Started Aug 02 05:35:03 PM PDT 24
Finished Aug 02 05:35:07 PM PDT 24
Peak memory 196544 kb
Host smart-574010ef-e882-40c2-bdcf-dccd64234461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359502579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.359502579
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.2906720020
Short name T83
Test name
Test status
Simulation time 39684994 ps
CPU time 0.77 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:21 PM PDT 24
Peak memory 218424 kb
Host smart-db7821d0-1aaa-48cf-a1c9-cf76b1629c08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906720020 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.2906720020
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.24446997
Short name T1132
Test name
Test status
Simulation time 11095898957 ps
CPU time 36.04 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 199824 kb
Host smart-d16832a0-ec31-46a6-bac6-f7975f2afd07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24446997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.24446997
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.4149586069
Short name T540
Test name
Test status
Simulation time 29037433713 ps
CPU time 61.76 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:36:23 PM PDT 24
Peak memory 199784 kb
Host smart-eed82e2f-cd33-4c5a-8172-1b4cf14fd38c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149586069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.4149586069
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.1156412218
Short name T1087
Test name
Test status
Simulation time 1634116435 ps
CPU time 3.67 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:35:53 PM PDT 24
Peak memory 199792 kb
Host smart-bc975ddc-fb99-40ad-b6dd-ffb80d10d688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156412218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.1156412218
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.2998848642
Short name T574
Test name
Test status
Simulation time 20587408196 ps
CPU time 32.09 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 200028 kb
Host smart-5ddf233c-65f7-43a3-a1f7-c2a9a48fd6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998848642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.2998848642
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3803250944
Short name T1156
Test name
Test status
Simulation time 11006760 ps
CPU time 0.57 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:36:28 PM PDT 24
Peak memory 194800 kb
Host smart-4601354f-fcb8-4cbd-bb44-48e75f2d6b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803250944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3803250944
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.209631267
Short name T892
Test name
Test status
Simulation time 68798132619 ps
CPU time 55.62 seconds
Started Aug 02 05:36:09 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 200004 kb
Host smart-6d964ebf-6ca1-47dc-8264-ea3f2ddcb2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209631267 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.209631267
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.1057009133
Short name T449
Test name
Test status
Simulation time 197919254510 ps
CPU time 52.63 seconds
Started Aug 02 05:36:18 PM PDT 24
Finished Aug 02 05:37:11 PM PDT 24
Peak memory 200052 kb
Host smart-9c1921d2-f52d-4684-b66b-b8e49ca499ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057009133 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.1057009133
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.3259991657
Short name T919
Test name
Test status
Simulation time 168415729485 ps
CPU time 569.4 seconds
Started Aug 02 05:36:23 PM PDT 24
Finished Aug 02 05:45:52 PM PDT 24
Peak memory 199852 kb
Host smart-23bac3c1-fb5a-4d47-aefc-b4374250b2f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259991657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.3259991657
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.1844638600
Short name T1026
Test name
Test status
Simulation time 941331573 ps
CPU time 1.02 seconds
Started Aug 02 05:36:19 PM PDT 24
Finished Aug 02 05:36:20 PM PDT 24
Peak memory 196840 kb
Host smart-26e71cdb-5532-40fe-ab5d-e409dc1566f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844638600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.1844638600
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.4103482575
Short name T263
Test name
Test status
Simulation time 105071227880 ps
CPU time 42.83 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 199844 kb
Host smart-40b5092d-1bb7-49b8-b04b-06af8876362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103482575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.4103482575
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.24252355
Short name T956
Test name
Test status
Simulation time 8429055339 ps
CPU time 89.12 seconds
Started Aug 02 05:36:25 PM PDT 24
Finished Aug 02 05:37:55 PM PDT 24
Peak memory 199992 kb
Host smart-fe5d95d4-352b-4a35-8828-7447306bd573
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=24252355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.24252355
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.4038115136
Short name T1078
Test name
Test status
Simulation time 5544054632 ps
CPU time 10.96 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:37 PM PDT 24
Peak memory 198164 kb
Host smart-1600e489-4e82-4e38-97af-53f4e7b8710f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038115136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.4038115136
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2958686198
Short name T590
Test name
Test status
Simulation time 118756566385 ps
CPU time 202.28 seconds
Started Aug 02 05:36:13 PM PDT 24
Finished Aug 02 05:39:35 PM PDT 24
Peak memory 200008 kb
Host smart-86503dad-4b0e-49e6-a873-eaf21c52984e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958686198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2958686198
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.3829072269
Short name T759
Test name
Test status
Simulation time 1627536989 ps
CPU time 1.17 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:36:24 PM PDT 24
Peak memory 195560 kb
Host smart-9ab9005b-3294-46c0-b8b1-3145e902c662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829072269 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.3829072269
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2417105320
Short name T646
Test name
Test status
Simulation time 5727753899 ps
CPU time 23.06 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 199832 kb
Host smart-ab302119-f200-4599-bdf9-0c22147c272c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417105320 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2417105320
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3256848633
Short name T786
Test name
Test status
Simulation time 514126142511 ps
CPU time 690 seconds
Started Aug 02 05:36:28 PM PDT 24
Finished Aug 02 05:47:58 PM PDT 24
Peak memory 230684 kb
Host smart-ae890edd-3d23-4bf4-afa7-e25e8a634020
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256848633 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3256848633
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.1367371145
Short name T355
Test name
Test status
Simulation time 1034380061 ps
CPU time 2.6 seconds
Started Aug 02 05:36:29 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 199936 kb
Host smart-25766fbe-e111-4603-9c70-0622213cd6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367371145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.1367371145
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2844548326
Short name T681
Test name
Test status
Simulation time 60366316879 ps
CPU time 97.53 seconds
Started Aug 02 05:36:20 PM PDT 24
Finished Aug 02 05:37:58 PM PDT 24
Peak memory 199912 kb
Host smart-28d1a723-9d77-4c32-9dde-1b2222dfb43c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844548326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2844548326
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.4251057978
Short name T1150
Test name
Test status
Simulation time 33482536 ps
CPU time 0.56 seconds
Started Aug 02 05:36:28 PM PDT 24
Finished Aug 02 05:36:28 PM PDT 24
Peak memory 195668 kb
Host smart-06ce12f0-d1a8-44f8-82fd-910c0bdf8232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251057978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.4251057978
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.3785193435
Short name T271
Test name
Test status
Simulation time 71753405260 ps
CPU time 121.59 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:38:25 PM PDT 24
Peak memory 199808 kb
Host smart-2feb1aaf-db3a-4c3d-aca1-723f45a713f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785193435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.3785193435
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.4183863629
Short name T1145
Test name
Test status
Simulation time 83926982130 ps
CPU time 140.51 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:38:41 PM PDT 24
Peak memory 199960 kb
Host smart-466784f1-f901-4528-9667-0d9f78de9f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183863629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.4183863629
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.4191134853
Short name T443
Test name
Test status
Simulation time 16643495330 ps
CPU time 16.74 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:36:39 PM PDT 24
Peak memory 199956 kb
Host smart-e48385f3-6b33-45ae-a0b2-1e5e5ca9926b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191134853 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.4191134853
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.868359050
Short name T370
Test name
Test status
Simulation time 22017339636 ps
CPU time 29.38 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:36:54 PM PDT 24
Peak memory 198144 kb
Host smart-f3aa8c4c-5512-49df-92ac-06b2e5abcdca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868359050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.868359050
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.2593720180
Short name T491
Test name
Test status
Simulation time 96809406810 ps
CPU time 507.1 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:44:53 PM PDT 24
Peak memory 199976 kb
Host smart-c7555ed6-463d-40aa-87b1-03826b3aa940
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593720180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.2593720180
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.2572131421
Short name T423
Test name
Test status
Simulation time 11511369141 ps
CPU time 7.12 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 199920 kb
Host smart-bf231ef5-1936-4d68-b85e-94d395675751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572131421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.2572131421
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3223984087
Short name T387
Test name
Test status
Simulation time 53686690488 ps
CPU time 46.48 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 199568 kb
Host smart-7c83b8a4-c9f6-481b-be85-a5b4af6761a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223984087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3223984087
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.4233024966
Short name T638
Test name
Test status
Simulation time 5528441073 ps
CPU time 170.41 seconds
Started Aug 02 05:36:31 PM PDT 24
Finished Aug 02 05:39:22 PM PDT 24
Peak memory 200016 kb
Host smart-a17eddb4-b98a-405b-abb3-f57f986e7ae4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4233024966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.4233024966
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.4065625571
Short name T794
Test name
Test status
Simulation time 6046368901 ps
CPU time 54.45 seconds
Started Aug 02 05:36:33 PM PDT 24
Finished Aug 02 05:37:27 PM PDT 24
Peak memory 198248 kb
Host smart-39014afd-79e1-42a6-a858-e39e06de55f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4065625571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.4065625571
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1501492246
Short name T788
Test name
Test status
Simulation time 32297974994 ps
CPU time 67.29 seconds
Started Aug 02 05:36:21 PM PDT 24
Finished Aug 02 05:37:29 PM PDT 24
Peak memory 199996 kb
Host smart-02583670-37b4-418e-b9f7-718cc8b2733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501492246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1501492246
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.411484109
Short name T580
Test name
Test status
Simulation time 4738320741 ps
CPU time 1.48 seconds
Started Aug 02 05:36:28 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 196772 kb
Host smart-1e370d9d-28b1-4968-808c-401efe83bac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411484109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.411484109
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.1265018493
Short name T334
Test name
Test status
Simulation time 6257408585 ps
CPU time 17.05 seconds
Started Aug 02 05:36:19 PM PDT 24
Finished Aug 02 05:36:37 PM PDT 24
Peak memory 199076 kb
Host smart-5af67e16-b031-4d9f-ba05-33e9831d7c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265018493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.1265018493
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.3079439700
Short name T376
Test name
Test status
Simulation time 1042690562 ps
CPU time 1.78 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 197988 kb
Host smart-c1608b6d-96c8-4e26-bac2-e833453ef06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079439700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.3079439700
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_alert_test.2858526264
Short name T1088
Test name
Test status
Simulation time 108893839 ps
CPU time 0.55 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:27 PM PDT 24
Peak memory 195352 kb
Host smart-67fc5893-79f6-42bf-85bd-f403e7a3850b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858526264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2858526264
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.3173400004
Short name T770
Test name
Test status
Simulation time 50300895601 ps
CPU time 40.86 seconds
Started Aug 02 05:36:25 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 199924 kb
Host smart-730b7a65-0047-47b6-8bcc-eaa7ddc6aa0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173400004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.3173400004
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.2712495196
Short name T696
Test name
Test status
Simulation time 48899199120 ps
CPU time 7.01 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:33 PM PDT 24
Peak memory 199948 kb
Host smart-dc01dd70-697d-4d7e-bd4d-10bd64f737d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712495196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.2712495196
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1403104901
Short name T266
Test name
Test status
Simulation time 100115032131 ps
CPU time 144.85 seconds
Started Aug 02 05:36:31 PM PDT 24
Finished Aug 02 05:38:56 PM PDT 24
Peak memory 199988 kb
Host smart-d8c8417f-da67-47c8-adf0-cc5ffd0724ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403104901 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1403104901
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.2996279810
Short name T663
Test name
Test status
Simulation time 10431248910 ps
CPU time 6 seconds
Started Aug 02 05:36:31 PM PDT 24
Finished Aug 02 05:36:37 PM PDT 24
Peak memory 199900 kb
Host smart-17647055-b4d3-46bc-b9ab-fa8cbd66aab9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996279810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.2996279810
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.1784550642
Short name T1160
Test name
Test status
Simulation time 139508077700 ps
CPU time 955.98 seconds
Started Aug 02 05:36:34 PM PDT 24
Finished Aug 02 05:52:30 PM PDT 24
Peak memory 200032 kb
Host smart-69380bd7-7597-4abe-80cc-2048b647c63b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784550642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.1784550642
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3663532422
Short name T795
Test name
Test status
Simulation time 8451436337 ps
CPU time 9.04 seconds
Started Aug 02 05:36:24 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 198840 kb
Host smart-fcc22a87-a9d5-4e58-9851-f98e90fb14b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663532422 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3663532422
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.3834874816
Short name T743
Test name
Test status
Simulation time 7365515364 ps
CPU time 12.49 seconds
Started Aug 02 05:36:32 PM PDT 24
Finished Aug 02 05:36:45 PM PDT 24
Peak memory 199872 kb
Host smart-24325d8a-7393-4acf-b1a5-ec38c854a90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834874816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.3834874816
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.3387627796
Short name T260
Test name
Test status
Simulation time 24136080166 ps
CPU time 341.02 seconds
Started Aug 02 05:36:31 PM PDT 24
Finished Aug 02 05:42:12 PM PDT 24
Peak memory 199952 kb
Host smart-84e12f9e-7e40-4998-8630-6f7dcb98d2ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3387627796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.3387627796
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.780553239
Short name T916
Test name
Test status
Simulation time 2970512230 ps
CPU time 5.93 seconds
Started Aug 02 05:36:28 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 198236 kb
Host smart-fe7a284e-5f36-45d0-b344-0a8fbf0d40aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=780553239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.780553239
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.2440390039
Short name T608
Test name
Test status
Simulation time 162555274379 ps
CPU time 169.41 seconds
Started Aug 02 05:36:17 PM PDT 24
Finished Aug 02 05:39:07 PM PDT 24
Peak memory 199980 kb
Host smart-77ac2d60-4a01-4a2a-9e7e-e493bd3cf10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440390039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.2440390039
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2600570779
Short name T299
Test name
Test status
Simulation time 5496906362 ps
CPU time 9 seconds
Started Aug 02 05:36:22 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 196520 kb
Host smart-3473a4d8-1bfa-4cd8-bf37-b53b340486a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600570779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2600570779
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.1946322086
Short name T1072
Test name
Test status
Simulation time 566553015 ps
CPU time 1.88 seconds
Started Aug 02 05:36:32 PM PDT 24
Finished Aug 02 05:36:34 PM PDT 24
Peak memory 199940 kb
Host smart-779fb936-4532-4754-8c06-19fb97f9ad8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946322086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.1946322086
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.212542757
Short name T238
Test name
Test status
Simulation time 196006608243 ps
CPU time 78.65 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 199976 kb
Host smart-340f4e35-c8ad-44c1-ba9d-d3322f1b07f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212542757 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.212542757
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.379606876
Short name T595
Test name
Test status
Simulation time 129060814193 ps
CPU time 649.13 seconds
Started Aug 02 05:36:35 PM PDT 24
Finished Aug 02 05:47:24 PM PDT 24
Peak memory 228060 kb
Host smart-e01cd4ae-aa0c-496e-824e-6c0a33072b39
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379606876 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.379606876
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.2845537881
Short name T553
Test name
Test status
Simulation time 2501694068 ps
CPU time 2.16 seconds
Started Aug 02 05:36:28 PM PDT 24
Finished Aug 02 05:36:30 PM PDT 24
Peak memory 198676 kb
Host smart-1315ac33-cad5-47c3-a03d-2e0c8b424e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845537881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.2845537881
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.700005449
Short name T493
Test name
Test status
Simulation time 215387788445 ps
CPU time 32.59 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:59 PM PDT 24
Peak memory 199988 kb
Host smart-882b8d1a-53d2-46fe-8e66-3782e3ac7bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700005449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.700005449
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.1525143678
Short name T686
Test name
Test status
Simulation time 15290476 ps
CPU time 0.62 seconds
Started Aug 02 05:36:34 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 195628 kb
Host smart-5ebfe188-8cb5-41d5-bf51-8745ca67cb22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525143678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.1525143678
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.3904831363
Short name T1177
Test name
Test status
Simulation time 158836133623 ps
CPU time 93.7 seconds
Started Aug 02 05:36:36 PM PDT 24
Finished Aug 02 05:38:10 PM PDT 24
Peak memory 200016 kb
Host smart-770529ce-59a0-4ead-a937-05cd4f54a17d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904831363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.3904831363
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.1800162717
Short name T678
Test name
Test status
Simulation time 45526722367 ps
CPU time 35.9 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 199980 kb
Host smart-07ccc03f-4a45-467b-a7da-e6bbd5a34a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800162717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.1800162717
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.3133422058
Short name T506
Test name
Test status
Simulation time 47421964559 ps
CPU time 19.74 seconds
Started Aug 02 05:36:36 PM PDT 24
Finished Aug 02 05:36:56 PM PDT 24
Peak memory 199916 kb
Host smart-859b4574-acd8-4aeb-aeef-8ab186bc7dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133422058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.3133422058
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.56643506
Short name T1149
Test name
Test status
Simulation time 10328074758 ps
CPU time 14.68 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:36:42 PM PDT 24
Peak memory 196848 kb
Host smart-14c0b47a-eaf9-4d12-a6f6-877e0c34298d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56643506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.56643506
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.4246422675
Short name T744
Test name
Test status
Simulation time 135694181219 ps
CPU time 487.26 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:44:46 PM PDT 24
Peak memory 199700 kb
Host smart-ea57fb6b-2e95-4fa7-9d46-c47e26262a2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4246422675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.4246422675
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.804479978
Short name T314
Test name
Test status
Simulation time 6979842541 ps
CPU time 8.77 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 198448 kb
Host smart-b363f1d7-86ac-482d-aa47-4e0fd3028b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804479978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.804479978
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.4200106481
Short name T401
Test name
Test status
Simulation time 68458584363 ps
CPU time 318.09 seconds
Started Aug 02 05:36:37 PM PDT 24
Finished Aug 02 05:41:55 PM PDT 24
Peak memory 208308 kb
Host smart-c4afc4f6-4925-4136-ab11-5a75b2cade42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200106481 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.4200106481
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.1906418918
Short name T36
Test name
Test status
Simulation time 6171737347 ps
CPU time 333.52 seconds
Started Aug 02 05:36:32 PM PDT 24
Finished Aug 02 05:42:05 PM PDT 24
Peak memory 199968 kb
Host smart-285cc2bc-25c5-4061-a1a9-6a38ceba0169
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906418918 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.1906418918
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.2393346634
Short name T656
Test name
Test status
Simulation time 5521553664 ps
CPU time 3.87 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:36:42 PM PDT 24
Peak memory 198280 kb
Host smart-1f223333-1424-481e-a847-5fd1b267280c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393346634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.2393346634
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.1764165888
Short name T316
Test name
Test status
Simulation time 65642840508 ps
CPU time 54.71 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:37:42 PM PDT 24
Peak memory 199960 kb
Host smart-af13cfa9-3985-43af-83c7-83c9f9553e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764165888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.1764165888
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.562727859
Short name T1130
Test name
Test status
Simulation time 3447786016 ps
CPU time 5.53 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 196548 kb
Host smart-8f3eec78-6199-4fcc-933b-58370ba77e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562727859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.562727859
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.3703020885
Short name T1123
Test name
Test status
Simulation time 1041878330 ps
CPU time 1.1 seconds
Started Aug 02 05:36:52 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 198604 kb
Host smart-a3e4906d-e562-4ced-8bf1-c7d4a6c4d828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703020885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.3703020885
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all.3614159810
Short name T510
Test name
Test status
Simulation time 275133699227 ps
CPU time 251.59 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:41:01 PM PDT 24
Peak memory 200132 kb
Host smart-c222ecea-bd2c-4bf4-b29b-502b66459bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614159810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.3614159810
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.2190388703
Short name T602
Test name
Test status
Simulation time 53815836888 ps
CPU time 859.4 seconds
Started Aug 02 05:36:32 PM PDT 24
Finished Aug 02 05:50:51 PM PDT 24
Peak memory 224836 kb
Host smart-68d93aed-2535-454b-b21c-8eed4c3ed69f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190388703 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.2190388703
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.2591697654
Short name T833
Test name
Test status
Simulation time 1541793320 ps
CPU time 1.63 seconds
Started Aug 02 05:36:29 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 198716 kb
Host smart-e9e2adb1-eca1-42a8-8a5f-bf80f9789e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591697654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.2591697654
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.1567516686
Short name T749
Test name
Test status
Simulation time 129785846905 ps
CPU time 86.04 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:38:06 PM PDT 24
Peak memory 200000 kb
Host smart-b746b349-ed7a-426b-91c7-8f4444fa8fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567516686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.1567516686
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.1447042802
Short name T406
Test name
Test status
Simulation time 14511552 ps
CPU time 0.56 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 195696 kb
Host smart-f447a2cf-772c-46bf-bfb3-2dc6943d4f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447042802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.1447042802
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.4096283278
Short name T285
Test name
Test status
Simulation time 69070087601 ps
CPU time 26.44 seconds
Started Aug 02 05:36:39 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 199948 kb
Host smart-7078d95b-bb23-42e2-8c97-57e978c254a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096283278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.4096283278
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.467883497
Short name T976
Test name
Test status
Simulation time 70078363936 ps
CPU time 60.99 seconds
Started Aug 02 05:36:35 PM PDT 24
Finished Aug 02 05:37:36 PM PDT 24
Peak memory 200020 kb
Host smart-893cba24-7a10-4500-b767-47c9422b4f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467883497 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.467883497
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1598993604
Short name T978
Test name
Test status
Simulation time 58098232967 ps
CPU time 144.87 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:38:52 PM PDT 24
Peak memory 199960 kb
Host smart-7059b26d-713b-4cf4-b136-af6486141c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598993604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1598993604
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_intr.2822099365
Short name T318
Test name
Test status
Simulation time 56758465704 ps
CPU time 51.82 seconds
Started Aug 02 05:36:43 PM PDT 24
Finished Aug 02 05:37:35 PM PDT 24
Peak memory 199704 kb
Host smart-5459a007-12c8-4544-92a0-113e190e9bee
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822099365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.2822099365
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3361162301
Short name T1000
Test name
Test status
Simulation time 129446862559 ps
CPU time 390.02 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:42:57 PM PDT 24
Peak memory 199980 kb
Host smart-20be8859-e95b-4efa-9705-0ef1b0bb56ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3361162301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3361162301
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.944919060
Short name T1092
Test name
Test status
Simulation time 9950217175 ps
CPU time 18.44 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:36:59 PM PDT 24
Peak memory 199968 kb
Host smart-f98aa35b-1fff-4e52-9702-c4c9abccedf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944919060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.944919060
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.3582911961
Short name T106
Test name
Test status
Simulation time 83946427471 ps
CPU time 77.34 seconds
Started Aug 02 05:36:27 PM PDT 24
Finished Aug 02 05:37:44 PM PDT 24
Peak memory 200108 kb
Host smart-263888e1-cf96-42a5-8557-4165ea21b214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582911961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.3582911961
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.4158385979
Short name T403
Test name
Test status
Simulation time 12010916893 ps
CPU time 717.68 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:48:36 PM PDT 24
Peak memory 199936 kb
Host smart-f241e8ea-113d-4ca0-8a1b-df79774dd096
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4158385979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.4158385979
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2305432985
Short name T342
Test name
Test status
Simulation time 5101473473 ps
CPU time 12.35 seconds
Started Aug 02 05:36:34 PM PDT 24
Finished Aug 02 05:36:46 PM PDT 24
Peak memory 197552 kb
Host smart-a6611772-649e-40fd-a18d-0a78cc50f541
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2305432985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2305432985
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.2244541579
Short name T1020
Test name
Test status
Simulation time 113878798432 ps
CPU time 123.71 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:38:45 PM PDT 24
Peak memory 199908 kb
Host smart-11f8dbb3-2996-42ca-a65a-40f4d1533ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244541579 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.2244541579
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3884448667
Short name T589
Test name
Test status
Simulation time 2116435518 ps
CPU time 3.43 seconds
Started Aug 02 05:36:31 PM PDT 24
Finished Aug 02 05:36:35 PM PDT 24
Peak memory 195668 kb
Host smart-bf0899e9-d91b-4377-8212-1770ca2924ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884448667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3884448667
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.221782892
Short name T257
Test name
Test status
Simulation time 669951168 ps
CPU time 2.53 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 198416 kb
Host smart-5acb4df4-d063-414b-8a99-6333180eeaa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221782892 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.221782892
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all.3375286512
Short name T882
Test name
Test status
Simulation time 182657559032 ps
CPU time 569.72 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:46:10 PM PDT 24
Peak memory 199928 kb
Host smart-882c903d-cd92-4558-945a-2f962beea2ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375286512 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.3375286512
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.1877305831
Short name T1174
Test name
Test status
Simulation time 164262176856 ps
CPU time 361.36 seconds
Started Aug 02 05:36:26 PM PDT 24
Finished Aug 02 05:42:28 PM PDT 24
Peak memory 216484 kb
Host smart-34f3aef6-f8d0-4a7b-8fc8-ace08049e3a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877305831 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.1877305831
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.3458525381
Short name T583
Test name
Test status
Simulation time 1648898520 ps
CPU time 1.73 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 198612 kb
Host smart-0a82dc62-b593-438d-b60c-0333d3cc7a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458525381 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.3458525381
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.1195071939
Short name T261
Test name
Test status
Simulation time 44051529161 ps
CPU time 100.78 seconds
Started Aug 02 05:36:30 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 200008 kb
Host smart-d4af4544-9aff-4705-9207-38b3fb3459c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195071939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.1195071939
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.4114233308
Short name T345
Test name
Test status
Simulation time 33984906 ps
CPU time 0.57 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:36:40 PM PDT 24
Peak memory 195400 kb
Host smart-f636eea3-7f0a-4e25-9c6b-75196655cd5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114233308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.4114233308
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.3588292950
Short name T133
Test name
Test status
Simulation time 31895042142 ps
CPU time 38.11 seconds
Started Aug 02 05:36:44 PM PDT 24
Finished Aug 02 05:37:22 PM PDT 24
Peak memory 199996 kb
Host smart-ba479d0e-cee4-4e48-8fe5-5b1f166f800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588292950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.3588292950
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.3825753828
Short name T693
Test name
Test status
Simulation time 93909847755 ps
CPU time 36.45 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:37:18 PM PDT 24
Peak memory 199992 kb
Host smart-c6e41510-ae16-44f3-818e-40e0b071dff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825753828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.3825753828
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.2965186438
Short name T598
Test name
Test status
Simulation time 308496993784 ps
CPU time 23.14 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:37:17 PM PDT 24
Peak memory 199872 kb
Host smart-c56a1053-b6a0-4923-8724-effaa1f21ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965186438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.2965186438
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.3175235474
Short name T105
Test name
Test status
Simulation time 16884355329 ps
CPU time 7.54 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:36:49 PM PDT 24
Peak memory 197552 kb
Host smart-f06b2ddc-123a-44d4-ac10-921f74e7a791
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175235474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.3175235474
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.3977944643
Short name T426
Test name
Test status
Simulation time 81750405596 ps
CPU time 291.69 seconds
Started Aug 02 05:36:52 PM PDT 24
Finished Aug 02 05:41:44 PM PDT 24
Peak memory 199920 kb
Host smart-7eb3ec3c-c29c-4dff-9e6c-eb5ea60fe0ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3977944643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.3977944643
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3172503514
Short name T940
Test name
Test status
Simulation time 6295444586 ps
CPU time 3.07 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:36:57 PM PDT 24
Peak memory 198824 kb
Host smart-d41d335f-63d2-49a2-a5ef-b136a5c65beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172503514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3172503514
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.1212984603
Short name T1016
Test name
Test status
Simulation time 226017102254 ps
CPU time 38.16 seconds
Started Aug 02 05:36:35 PM PDT 24
Finished Aug 02 05:37:14 PM PDT 24
Peak memory 200108 kb
Host smart-17814c1d-f974-4690-9de3-01c85a816401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212984603 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.1212984603
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.158481697
Short name T269
Test name
Test status
Simulation time 18382464082 ps
CPU time 106.81 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199972 kb
Host smart-698d78bf-b9c3-4291-88b9-eb34b4647451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=158481697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.158481697
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.4038588000
Short name T874
Test name
Test status
Simulation time 2012179213 ps
CPU time 9.78 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:36:55 PM PDT 24
Peak memory 197976 kb
Host smart-27355077-704b-4442-9a05-9f78599cc3ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4038588000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.4038588000
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.4240126510
Short name T902
Test name
Test status
Simulation time 3701896938 ps
CPU time 2.19 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:36:43 PM PDT 24
Peak memory 196080 kb
Host smart-bc8987f3-05f0-4dfb-bffb-f1a5b16fc3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240126510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.4240126510
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.3612912712
Short name T523
Test name
Test status
Simulation time 673572945 ps
CPU time 1.53 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:36:44 PM PDT 24
Peak memory 198868 kb
Host smart-0d410a9f-a744-4e48-9900-2cc45e0adf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612912712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.3612912712
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.2841111315
Short name T1060
Test name
Test status
Simulation time 37690025241 ps
CPU time 846.31 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:50:57 PM PDT 24
Peak memory 215948 kb
Host smart-10b37d2f-cf59-4053-b510-f124caccd907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841111315 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.2841111315
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.3012283152
Short name T959
Test name
Test status
Simulation time 4838994606 ps
CPU time 1.92 seconds
Started Aug 02 05:36:39 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 198684 kb
Host smart-6afd8c41-c906-49fe-ba0e-ec2869219b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012283152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.3012283152
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.3435001181
Short name T947
Test name
Test status
Simulation time 9295421873 ps
CPU time 4.22 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 197560 kb
Host smart-fa2cea30-b8d9-42b9-a714-b793f81c78f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435001181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.3435001181
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.2263584819
Short name T785
Test name
Test status
Simulation time 29100664 ps
CPU time 0.56 seconds
Started Aug 02 05:36:44 PM PDT 24
Finished Aug 02 05:36:45 PM PDT 24
Peak memory 195608 kb
Host smart-6be7ec54-82ff-4eff-b96f-32a372cfac94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263584819 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.2263584819
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.2660183109
Short name T147
Test name
Test status
Simulation time 113029863845 ps
CPU time 46.55 seconds
Started Aug 02 05:36:34 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 199920 kb
Host smart-694896a4-f69a-432b-ab98-473a5516b961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660183109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.2660183109
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.1203453163
Short name T379
Test name
Test status
Simulation time 44925608105 ps
CPU time 14.39 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:36:59 PM PDT 24
Peak memory 200016 kb
Host smart-307b8548-f419-41ae-b2eb-89ac070495ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203453163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.1203453163
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.3365058997
Short name T321
Test name
Test status
Simulation time 96484062237 ps
CPU time 29.39 seconds
Started Aug 02 05:36:37 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 199928 kb
Host smart-86a3d542-dcc5-42db-8cc8-93d0d8514cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365058997 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.3365058997
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.3776615984
Short name T631
Test name
Test status
Simulation time 9247864088 ps
CPU time 14.17 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:37:00 PM PDT 24
Peak memory 199932 kb
Host smart-b6988424-5fd2-4771-8822-bfdda481872d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776615984 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.3776615984
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.2451526947
Short name T851
Test name
Test status
Simulation time 227668167701 ps
CPU time 248.75 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:40:57 PM PDT 24
Peak memory 199948 kb
Host smart-72382da3-69ee-457e-ae7b-d3e0716f7fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2451526947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.2451526947
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.971923748
Short name T832
Test name
Test status
Simulation time 12309965179 ps
CPU time 12.56 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 199848 kb
Host smart-f2964ca6-b08a-459b-9f8d-2ecdd3bd6f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971923748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.971923748
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.687161464
Short name T1009
Test name
Test status
Simulation time 18375854635 ps
CPU time 28.25 seconds
Started Aug 02 05:36:36 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 198476 kb
Host smart-95e4563c-31c4-4775-bb4d-36273531d9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687161464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.687161464
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.2881208399
Short name T1127
Test name
Test status
Simulation time 15886975421 ps
CPU time 721.27 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:48:52 PM PDT 24
Peak memory 199884 kb
Host smart-577e8048-3bde-40b0-9533-e095e7177fe7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881208399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.2881208399
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3530331574
Short name T1147
Test name
Test status
Simulation time 5398092872 ps
CPU time 37.33 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 198796 kb
Host smart-d11d91e1-bfb6-40ba-b032-c425e48bd422
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530331574 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3530331574
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.1757955046
Short name T746
Test name
Test status
Simulation time 74154383149 ps
CPU time 275.04 seconds
Started Aug 02 05:36:37 PM PDT 24
Finished Aug 02 05:41:12 PM PDT 24
Peak memory 199904 kb
Host smart-2c97630f-30b1-46f4-b37a-3a239263f76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757955046 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.1757955046
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.2471977721
Short name T715
Test name
Test status
Simulation time 35163619373 ps
CPU time 9.8 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 196024 kb
Host smart-4b83ac12-4d84-4b51-b0a3-424270542e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471977721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.2471977721
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.4143058236
Short name T964
Test name
Test status
Simulation time 131925004 ps
CPU time 0.74 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 196936 kb
Host smart-f77f4272-6d87-4b45-b338-5686f3b6c2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143058236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.4143058236
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_stress_all.1710649671
Short name T304
Test name
Test status
Simulation time 31068177203 ps
CPU time 54.21 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:37:33 PM PDT 24
Peak memory 199960 kb
Host smart-fe7aab0f-0f6c-412a-a762-e8033a4861d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710649671 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.1710649671
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.3097544960
Short name T41
Test name
Test status
Simulation time 55726096827 ps
CPU time 267.06 seconds
Started Aug 02 05:36:36 PM PDT 24
Finished Aug 02 05:41:04 PM PDT 24
Peak memory 208404 kb
Host smart-b8001611-cc6d-4fc1-858f-60ab030e0725
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097544960 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.3097544960
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.1303041104
Short name T701
Test name
Test status
Simulation time 825549576 ps
CPU time 1.34 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 197896 kb
Host smart-2ae0e8a4-7dcc-4bea-b500-de323f7bec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303041104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.1303041104
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.1710916378
Short name T977
Test name
Test status
Simulation time 47439400104 ps
CPU time 116.9 seconds
Started Aug 02 05:36:44 PM PDT 24
Finished Aug 02 05:38:41 PM PDT 24
Peak memory 200024 kb
Host smart-59e35c71-16bc-426d-af44-147c2286c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710916378 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.1710916378
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.749004744
Short name T944
Test name
Test status
Simulation time 16251380 ps
CPU time 0.59 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 195396 kb
Host smart-82f6c47b-4d58-4cfa-b17c-8049659df87d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749004744 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.749004744
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.2248433522
Short name T592
Test name
Test status
Simulation time 24202445199 ps
CPU time 43.93 seconds
Started Aug 02 05:36:34 PM PDT 24
Finished Aug 02 05:37:18 PM PDT 24
Peak memory 199868 kb
Host smart-eb549693-0f35-4e00-953d-71bed0364fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248433522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.2248433522
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.1193143786
Short name T1028
Test name
Test status
Simulation time 45115870324 ps
CPU time 75.64 seconds
Started Aug 02 05:36:38 PM PDT 24
Finished Aug 02 05:37:54 PM PDT 24
Peak memory 199944 kb
Host smart-473edb67-dd15-4226-afeb-f25196720d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193143786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.1193143786
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.4035506294
Short name T899
Test name
Test status
Simulation time 253200031620 ps
CPU time 113.47 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:38:47 PM PDT 24
Peak memory 199988 kb
Host smart-4d22d226-6318-4a7a-af34-32cb7cc33137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035506294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.4035506294
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.359396198
Short name T547
Test name
Test status
Simulation time 183647720768 ps
CPU time 52.25 seconds
Started Aug 02 05:36:43 PM PDT 24
Finished Aug 02 05:37:35 PM PDT 24
Peak memory 198064 kb
Host smart-cf5f7839-cc97-4643-9f22-2dc4f7083fae
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359396198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.359396198
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.4202801341
Short name T303
Test name
Test status
Simulation time 63692364510 ps
CPU time 208.04 seconds
Started Aug 02 05:36:35 PM PDT 24
Finished Aug 02 05:40:03 PM PDT 24
Peak memory 199872 kb
Host smart-3ff345da-8f1f-4456-8e55-4ac1f67330f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202801341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.4202801341
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.2107448268
Short name T818
Test name
Test status
Simulation time 639266464 ps
CPU time 2.65 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:36:42 PM PDT 24
Peak memory 199956 kb
Host smart-0a9cb722-9af6-4e11-a888-a47cdf0551c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107448268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.2107448268
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.1432898035
Short name T981
Test name
Test status
Simulation time 88060862315 ps
CPU time 36.88 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:37:17 PM PDT 24
Peak memory 198428 kb
Host smart-9995c55c-2186-44de-b942-250426363cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432898035 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.1432898035
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_perf.356502708
Short name T772
Test name
Test status
Simulation time 17423357673 ps
CPU time 244.99 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:40:50 PM PDT 24
Peak memory 199820 kb
Host smart-069d8541-40c8-4905-9f88-f0d78a10ac0b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=356502708 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.356502708
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.3859813510
Short name T104
Test name
Test status
Simulation time 5590919101 ps
CPU time 3.43 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 198696 kb
Host smart-738b18e0-86dc-4e7f-b731-a5d3fafafbd3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3859813510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.3859813510
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.4182229609
Short name T958
Test name
Test status
Simulation time 281101424728 ps
CPU time 383.77 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:43:11 PM PDT 24
Peak memory 199992 kb
Host smart-bb2b05b1-ad97-4730-be3b-03806b17000c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182229609 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.4182229609
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.3820679788
Short name T388
Test name
Test status
Simulation time 4143328815 ps
CPU time 3.19 seconds
Started Aug 02 05:36:36 PM PDT 24
Finished Aug 02 05:36:39 PM PDT 24
Peak memory 196300 kb
Host smart-6f1e0ef2-79d8-4cc1-aa54-1e1f05a5756f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820679788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.3820679788
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.2623463707
Short name T524
Test name
Test status
Simulation time 579425264 ps
CPU time 1.47 seconds
Started Aug 02 05:36:35 PM PDT 24
Finished Aug 02 05:36:37 PM PDT 24
Peak memory 198328 kb
Host smart-617838f8-b6a0-40bd-9ffa-23e92600d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623463707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.2623463707
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.3306269781
Short name T87
Test name
Test status
Simulation time 262195909707 ps
CPU time 1352.62 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:59:13 PM PDT 24
Peak memory 199964 kb
Host smart-39e245b8-cfa2-45b7-99d9-9114d41f98d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306269781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.3306269781
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.3962400893
Short name T30
Test name
Test status
Simulation time 102247875581 ps
CPU time 1481.66 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 06:01:23 PM PDT 24
Peak memory 216524 kb
Host smart-74efc041-aa66-43ff-8f15-e6ae68464332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962400893 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.3962400893
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.1811896315
Short name T827
Test name
Test status
Simulation time 13552996637 ps
CPU time 22.67 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 199976 kb
Host smart-ab9c3f9d-55fb-4091-998d-2c860fc65669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811896315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.1811896315
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2396319963
Short name T239
Test name
Test status
Simulation time 114443883328 ps
CPU time 240.96 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:40:41 PM PDT 24
Peak memory 200016 kb
Host smart-f374a217-2c52-47a3-aeb5-584a83597bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396319963 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2396319963
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4015982302
Short name T544
Test name
Test status
Simulation time 12101045 ps
CPU time 0.56 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 194624 kb
Host smart-b3ea97ca-ae21-4a0c-8667-f43d1e053327
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015982302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4015982302
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.3390916032
Short name T490
Test name
Test status
Simulation time 120277889558 ps
CPU time 195.89 seconds
Started Aug 02 05:36:51 PM PDT 24
Finished Aug 02 05:40:07 PM PDT 24
Peak memory 199988 kb
Host smart-cf7cc7db-61b4-41b0-8402-5cfffc1ad9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390916032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.3390916032
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.1830049319
Short name T685
Test name
Test status
Simulation time 80560743369 ps
CPU time 31.67 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:37:25 PM PDT 24
Peak memory 199936 kb
Host smart-03200014-00de-45dc-8010-a2a4cd16529f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830049319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.1830049319
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.3453538875
Short name T315
Test name
Test status
Simulation time 106484183272 ps
CPU time 167.5 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 199932 kb
Host smart-2a9dd5b4-0575-4ff2-9daf-1ae4d0fdde0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453538875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.3453538875
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2318683538
Short name T670
Test name
Test status
Simulation time 30128941715 ps
CPU time 42.09 seconds
Started Aug 02 05:36:52 PM PDT 24
Finished Aug 02 05:37:34 PM PDT 24
Peak memory 196972 kb
Host smart-7e97a673-ed1e-41d5-8552-709dbebc755b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318683538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2318683538
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.64349398
Short name T337
Test name
Test status
Simulation time 108382653202 ps
CPU time 428.92 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:43:55 PM PDT 24
Peak memory 199912 kb
Host smart-44b04361-1c42-413c-8bdd-f566ea2dbdff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=64349398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.64349398
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.366972538
Short name T894
Test name
Test status
Simulation time 13076804818 ps
CPU time 21.09 seconds
Started Aug 02 05:36:44 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 199404 kb
Host smart-96c181cd-1452-43a6-8842-a2df3aa300ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366972538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.366972538
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.3403765036
Short name T243
Test name
Test status
Simulation time 181030316508 ps
CPU time 93.16 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:38:24 PM PDT 24
Peak memory 199456 kb
Host smart-bb318528-def3-4e13-a82c-0625157625aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403765036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.3403765036
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.445936927
Short name T502
Test name
Test status
Simulation time 38217431310 ps
CPU time 602.77 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:46:45 PM PDT 24
Peak memory 199928 kb
Host smart-14ca3668-0435-49b6-a24a-2e0214c576ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445936927 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.445936927
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.119302433
Short name T451
Test name
Test status
Simulation time 2870813740 ps
CPU time 23.35 seconds
Started Aug 02 05:36:51 PM PDT 24
Finished Aug 02 05:37:15 PM PDT 24
Peak memory 199044 kb
Host smart-8e7df872-eabc-4192-9ff9-2f45da920fc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=119302433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.119302433
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.2560933755
Short name T306
Test name
Test status
Simulation time 136325371272 ps
CPU time 49.24 seconds
Started Aug 02 05:36:44 PM PDT 24
Finished Aug 02 05:37:34 PM PDT 24
Peak memory 199396 kb
Host smart-496ece99-4dde-482b-b57d-cdab7ba9ef57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560933755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.2560933755
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.3233094905
Short name T1141
Test name
Test status
Simulation time 3367009543 ps
CPU time 1.51 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:36:52 PM PDT 24
Peak memory 196532 kb
Host smart-fb5f46d5-927a-486e-b0ed-b36a0445ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233094905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.3233094905
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2873484026
Short name T667
Test name
Test status
Simulation time 626386436 ps
CPU time 2.81 seconds
Started Aug 02 05:36:43 PM PDT 24
Finished Aug 02 05:36:46 PM PDT 24
Peak memory 199624 kb
Host smart-ae7b8ecd-4146-446e-8ed5-f3f35d5e1cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873484026 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2873484026
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.3305804928
Short name T288
Test name
Test status
Simulation time 230061468360 ps
CPU time 1482.75 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 06:01:24 PM PDT 24
Peak memory 199940 kb
Host smart-36d6076c-cae8-4ee0-b3b2-2febed116369
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305804928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.3305804928
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.1795720455
Short name T154
Test name
Test status
Simulation time 1115043067119 ps
CPU time 1231.67 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:57:14 PM PDT 24
Peak memory 229196 kb
Host smart-dc96f67d-3d20-4d64-a167-c1b169fc724a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795720455 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.1795720455
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2580680951
Short name T286
Test name
Test status
Simulation time 806219199 ps
CPU time 2.39 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:36:45 PM PDT 24
Peak memory 199144 kb
Host smart-ea3c0274-f8d4-4e86-b44c-107bff4a03dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580680951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2580680951
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2544397713
Short name T1018
Test name
Test status
Simulation time 19987455000 ps
CPU time 17.39 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 199576 kb
Host smart-7ddc9f9e-ca1d-4b72-866e-03bd3d1244ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544397713 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2544397713
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.4056842958
Short name T1001
Test name
Test status
Simulation time 12807129 ps
CPU time 0.59 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:36:47 PM PDT 24
Peak memory 195008 kb
Host smart-2a768f6b-f280-4de0-a7f3-bb2f44451e89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056842958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.4056842958
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.1165326746
Short name T520
Test name
Test status
Simulation time 35355150667 ps
CPU time 29.82 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:37:31 PM PDT 24
Peak memory 200028 kb
Host smart-5f269f3e-b387-4662-9cc1-fcc34437a7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165326746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.1165326746
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.2139554797
Short name T157
Test name
Test status
Simulation time 9411947486 ps
CPU time 16.86 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 199808 kb
Host smart-30ef7524-e321-4ae8-ae4d-51d76d4b2c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139554797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.2139554797
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.1545599502
Short name T877
Test name
Test status
Simulation time 90312069390 ps
CPU time 38.16 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 199920 kb
Host smart-a4ec8d9f-bb36-41cd-b4df-ab40d3555c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545599502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.1545599502
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/39.uart_intr.4023122765
Short name T454
Test name
Test status
Simulation time 13479245542 ps
CPU time 21.95 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 197004 kb
Host smart-9f3266c7-4100-400f-af10-cab06304d952
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023122765 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.4023122765
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.1470697743
Short name T542
Test name
Test status
Simulation time 95177895546 ps
CPU time 170.66 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:39:33 PM PDT 24
Peak memory 199972 kb
Host smart-58fe1fa0-df00-44b6-bf41-29b460abafab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1470697743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.1470697743
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/39.uart_loopback.925967008
Short name T390
Test name
Test status
Simulation time 10598220158 ps
CPU time 21.27 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:37:10 PM PDT 24
Peak memory 200000 kb
Host smart-19622147-9cb6-4dda-8e89-189f4a7d7886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925967008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.925967008
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.809170436
Short name T869
Test name
Test status
Simulation time 183973050105 ps
CPU time 154.43 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 208324 kb
Host smart-6027a9cb-de78-466b-a49d-d6ede03c5705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809170436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.809170436
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.160033625
Short name T650
Test name
Test status
Simulation time 12083418809 ps
CPU time 106.91 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:38:29 PM PDT 24
Peak memory 199992 kb
Host smart-debb0d20-1630-4458-9a7d-849ae6649308
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=160033625 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.160033625
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1747575006
Short name T934
Test name
Test status
Simulation time 5721745150 ps
CPU time 46.29 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:37:31 PM PDT 24
Peak memory 198656 kb
Host smart-8bdfce3d-2b13-4bd9-8b35-a5b79eb5a05c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1747575006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1747575006
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3403265881
Short name T1133
Test name
Test status
Simulation time 160265178042 ps
CPU time 183.74 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:39:46 PM PDT 24
Peak memory 200012 kb
Host smart-dc0e2517-9c0f-4998-afc7-11de2cce23a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403265881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3403265881
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.337970050
Short name T1098
Test name
Test status
Simulation time 3134909751 ps
CPU time 1.79 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 196052 kb
Host smart-03466648-2f69-4777-a357-033f8b31cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337970050 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.337970050
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.2366805982
Short name T344
Test name
Test status
Simulation time 440680682 ps
CPU time 1.66 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:36:55 PM PDT 24
Peak memory 198412 kb
Host smart-282f5bc8-8fba-4d30-8e98-43255bcace25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366805982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.2366805982
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.3526633651
Short name T430
Test name
Test status
Simulation time 200452206955 ps
CPU time 1368.71 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:59:49 PM PDT 24
Peak memory 199984 kb
Host smart-92658012-04eb-4c15-bc62-5a7bfa6593d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526633651 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.3526633651
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.3542847533
Short name T58
Test name
Test status
Simulation time 243073810462 ps
CPU time 1061.07 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:54:24 PM PDT 24
Peak memory 224764 kb
Host smart-7454739c-ef21-4058-bd2f-b827aa32a073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542847533 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.3542847533
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.2973586084
Short name T581
Test name
Test status
Simulation time 6343417513 ps
CPU time 20.31 seconds
Started Aug 02 05:36:54 PM PDT 24
Finished Aug 02 05:37:15 PM PDT 24
Peak memory 199232 kb
Host smart-e88482ec-e20d-4920-8711-869e88ab8208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973586084 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.2973586084
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.4158175658
Short name T323
Test name
Test status
Simulation time 8105669513 ps
CPU time 11.2 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:36:57 PM PDT 24
Peak memory 199972 kb
Host smart-50a3c287-43de-4685-b396-385c8a1756b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158175658 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.4158175658
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.4068140012
Short name T577
Test name
Test status
Simulation time 12319229 ps
CPU time 0.55 seconds
Started Aug 02 05:35:52 PM PDT 24
Finished Aug 02 05:35:53 PM PDT 24
Peak memory 195332 kb
Host smart-de05d399-4ffa-4151-af0f-5f81505165e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068140012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.4068140012
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.2032055008
Short name T570
Test name
Test status
Simulation time 42916195125 ps
CPU time 13.96 seconds
Started Aug 02 05:35:28 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 199988 kb
Host smart-e146c6f5-b38b-42be-8d59-80950aa19135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032055008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.2032055008
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.3008004879
Short name T1064
Test name
Test status
Simulation time 63706168114 ps
CPU time 30.44 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:36:06 PM PDT 24
Peak memory 199652 kb
Host smart-7c9dacd4-6994-4340-9e32-23ee66625b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008004879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.3008004879
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.3946528382
Short name T503
Test name
Test status
Simulation time 158752537706 ps
CPU time 61.07 seconds
Started Aug 02 05:35:15 PM PDT 24
Finished Aug 02 05:36:17 PM PDT 24
Peak memory 199924 kb
Host smart-531db0aa-3827-4385-936a-777b09267e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946528382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.3946528382
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.78477290
Short name T571
Test name
Test status
Simulation time 54243119890 ps
CPU time 12.06 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 200024 kb
Host smart-edb5359e-1ccf-4dc8-903e-fb75f05c1b7a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78477290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.78477290
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1418565917
Short name T56
Test name
Test status
Simulation time 135130970538 ps
CPU time 598.02 seconds
Started Aug 02 05:35:26 PM PDT 24
Finished Aug 02 05:45:24 PM PDT 24
Peak memory 199964 kb
Host smart-951e5517-742b-4a3d-b03f-d791e894e8b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418565917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1418565917
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.1375289531
Short name T1129
Test name
Test status
Simulation time 669784252 ps
CPU time 1.57 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 197544 kb
Host smart-4ac7e79f-ed98-45c8-83e8-183fd6d174f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375289531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.1375289531
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.862847933
Short name T497
Test name
Test status
Simulation time 3428475430 ps
CPU time 2.53 seconds
Started Aug 02 05:35:29 PM PDT 24
Finished Aug 02 05:35:32 PM PDT 24
Peak memory 198476 kb
Host smart-e52c45eb-f791-4588-8bc7-8d33459d2356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862847933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.862847933
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.3795741775
Short name T853
Test name
Test status
Simulation time 6333214386 ps
CPU time 371.3 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:41:47 PM PDT 24
Peak memory 199996 kb
Host smart-c2c4a51e-013b-455e-ad8a-dadca3d847ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3795741775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.3795741775
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.4089260385
Short name T1097
Test name
Test status
Simulation time 7766109597 ps
CPU time 12.28 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:35:44 PM PDT 24
Peak memory 198744 kb
Host smart-c5cb7a53-03c0-4dde-8439-8d059ac1d4a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089260385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.4089260385
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.1491652957
Short name T927
Test name
Test status
Simulation time 4488877548 ps
CPU time 2.25 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:35:36 PM PDT 24
Peak memory 196144 kb
Host smart-535375f2-d5a9-4750-88ee-c5a1145bcbd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491652957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.1491652957
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_sec_cm.4067070996
Short name T27
Test name
Test status
Simulation time 31682307 ps
CPU time 0.74 seconds
Started Aug 02 05:35:25 PM PDT 24
Finished Aug 02 05:35:26 PM PDT 24
Peak memory 218424 kb
Host smart-20f77d29-c876-445b-8926-e620429a9381
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067070996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.4067070996
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/4.uart_smoke.909691488
Short name T385
Test name
Test status
Simulation time 497785367 ps
CPU time 1.47 seconds
Started Aug 02 05:35:04 PM PDT 24
Finished Aug 02 05:35:06 PM PDT 24
Peak memory 198308 kb
Host smart-62711500-5944-4d8e-9d1e-b04a376acf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909691488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.909691488
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2813956967
Short name T241
Test name
Test status
Simulation time 123222881514 ps
CPU time 117.23 seconds
Started Aug 02 05:35:23 PM PDT 24
Finished Aug 02 05:37:20 PM PDT 24
Peak memory 208208 kb
Host smart-3300fec2-7e7f-49ab-a832-12b0343695f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813956967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2813956967
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.4156169901
Short name T39
Test name
Test status
Simulation time 200374906839 ps
CPU time 676.55 seconds
Started Aug 02 05:35:26 PM PDT 24
Finished Aug 02 05:46:43 PM PDT 24
Peak memory 224832 kb
Host smart-ef5f1e7a-0994-4100-89bf-fe78950f8fc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156169901 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.4156169901
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3689651957
Short name T363
Test name
Test status
Simulation time 957452839 ps
CPU time 4.06 seconds
Started Aug 02 05:35:19 PM PDT 24
Finished Aug 02 05:35:23 PM PDT 24
Peak memory 198948 kb
Host smart-ed2e09d6-bff6-496b-8be2-6b77920cc0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689651957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3689651957
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.1667705858
Short name T1158
Test name
Test status
Simulation time 8840741276 ps
CPU time 5.03 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:35:21 PM PDT 24
Peak memory 200008 kb
Host smart-4f293fad-d5ab-42c2-98a9-64f70cdfe698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667705858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.1667705858
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3618982669
Short name T343
Test name
Test status
Simulation time 71774636 ps
CPU time 0.54 seconds
Started Aug 02 05:36:41 PM PDT 24
Finished Aug 02 05:36:41 PM PDT 24
Peak memory 195672 kb
Host smart-e7b42c34-b818-4f5d-84a2-2dd3e1b409fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618982669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3618982669
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3394620338
Short name T896
Test name
Test status
Simulation time 130676315240 ps
CPU time 180.11 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:39:47 PM PDT 24
Peak memory 200024 kb
Host smart-e5974c6d-e1c7-4720-9f63-3fde78e031b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394620338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3394620338
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.2316516256
Short name T754
Test name
Test status
Simulation time 125087925237 ps
CPU time 168.48 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:39:36 PM PDT 24
Peak memory 199656 kb
Host smart-8a50e239-cf31-4181-a2b5-2385eeebf67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316516256 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.2316516256
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.2814740351
Short name T167
Test name
Test status
Simulation time 73185280351 ps
CPU time 62.1 seconds
Started Aug 02 05:36:40 PM PDT 24
Finished Aug 02 05:37:42 PM PDT 24
Peak memory 199884 kb
Host smart-c39d91a3-13dd-49e4-a013-4a996ad443d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814740351 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.2814740351
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.3107310053
Short name T366
Test name
Test status
Simulation time 43425432696 ps
CPU time 59.01 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:37:45 PM PDT 24
Peak memory 199184 kb
Host smart-cfe471d4-866c-4247-8585-34ed5f6d1021
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107310053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.3107310053
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3032296000
Short name T432
Test name
Test status
Simulation time 163790258767 ps
CPU time 1502.2 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 06:01:50 PM PDT 24
Peak memory 199672 kb
Host smart-0c53216d-8c04-4be0-816e-6b72d5429c40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3032296000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3032296000
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.78392525
Short name T901
Test name
Test status
Simulation time 13007791943 ps
CPU time 25.54 seconds
Started Aug 02 05:36:52 PM PDT 24
Finished Aug 02 05:37:18 PM PDT 24
Peak memory 199628 kb
Host smart-a9f47d26-424a-4e12-bc9d-5692cc5660f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78392525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.78392525
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1255176445
Short name T700
Test name
Test status
Simulation time 102171418414 ps
CPU time 166.59 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 208336 kb
Host smart-35155fb7-d7cb-48ad-9ade-52e24bb7faf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255176445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1255176445
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.692525310
Short name T458
Test name
Test status
Simulation time 18179829649 ps
CPU time 998.78 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:53:24 PM PDT 24
Peak memory 199964 kb
Host smart-63d8211d-6879-442a-b2aa-c87b6e8514e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=692525310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.692525310
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3764486544
Short name T552
Test name
Test status
Simulation time 8429609251 ps
CPU time 17.87 seconds
Started Aug 02 05:36:42 PM PDT 24
Finished Aug 02 05:37:00 PM PDT 24
Peak memory 198096 kb
Host smart-b597fb3f-3591-4cc3-84cb-55eda0ced73a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3764486544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3764486544
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.2235172099
Short name T973
Test name
Test status
Simulation time 20207466081 ps
CPU time 15.74 seconds
Started Aug 02 05:36:45 PM PDT 24
Finished Aug 02 05:37:01 PM PDT 24
Peak memory 199900 kb
Host smart-e763d954-012f-4117-a844-f7847fe72d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235172099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.2235172099
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.2425506548
Short name T751
Test name
Test status
Simulation time 2746301502 ps
CPU time 1.64 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:36:48 PM PDT 24
Peak memory 196496 kb
Host smart-9aabaf2f-016c-4000-ae32-f1ff3c201a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425506548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.2425506548
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3621029077
Short name T437
Test name
Test status
Simulation time 338069969 ps
CPU time 1 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:36:54 PM PDT 24
Peak memory 198660 kb
Host smart-787a501f-cb24-4266-a083-d2a955e79267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621029077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3621029077
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.644197924
Short name T211
Test name
Test status
Simulation time 97107376858 ps
CPU time 679.33 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:48:05 PM PDT 24
Peak memory 212352 kb
Host smart-6e706548-1917-43e7-8c92-7dff9908246c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644197924 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.644197924
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.961091425
Short name T447
Test name
Test status
Simulation time 1585213421 ps
CPU time 4.56 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 198176 kb
Host smart-4d86ba9f-18d8-41a3-95bb-2a5e1aab8db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961091425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.961091425
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.119385702
Short name T884
Test name
Test status
Simulation time 56244754059 ps
CPU time 107.49 seconds
Started Aug 02 05:36:43 PM PDT 24
Finished Aug 02 05:38:30 PM PDT 24
Peak memory 199924 kb
Host smart-4a0c5a3e-f87a-48d7-97ad-a2c3fc420563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119385702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.119385702
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.3936843588
Short name T82
Test name
Test status
Simulation time 21905478 ps
CPU time 0.64 seconds
Started Aug 02 05:36:51 PM PDT 24
Finished Aug 02 05:36:52 PM PDT 24
Peak memory 195352 kb
Host smart-6b3e385f-c8e1-4113-a00b-fc461d976a78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936843588 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.3936843588
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.3501492022
Short name T474
Test name
Test status
Simulation time 33374396738 ps
CPU time 13.82 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 200000 kb
Host smart-563c6062-1494-42bd-954b-1b2ecd00049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501492022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.3501492022
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.3306899321
Short name T475
Test name
Test status
Simulation time 85746568503 ps
CPU time 161.27 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:39:29 PM PDT 24
Peak memory 199944 kb
Host smart-b39e4375-5143-4178-8dc7-ee6c06743054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306899321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.3306899321
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_intr.2797147709
Short name T1086
Test name
Test status
Simulation time 40744552538 ps
CPU time 5.68 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:13 PM PDT 24
Peak memory 199944 kb
Host smart-6b74a0fe-73de-4758-a538-356d9b49454e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797147709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.2797147709
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.381466217
Short name T852
Test name
Test status
Simulation time 88869915887 ps
CPU time 543.25 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:46:04 PM PDT 24
Peak memory 199924 kb
Host smart-c6007446-9dc2-4f0e-84c8-54f2efd0aa1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=381466217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.381466217
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.3687547633
Short name T527
Test name
Test status
Simulation time 8816106489 ps
CPU time 6.59 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:36:54 PM PDT 24
Peak memory 198416 kb
Host smart-a40bccad-373b-4f53-a4c5-50757c45476c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687547633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.3687547633
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.2258059199
Short name T775
Test name
Test status
Simulation time 73414761035 ps
CPU time 28.29 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:37:22 PM PDT 24
Peak memory 198868 kb
Host smart-a70cc36d-385c-4beb-b27a-08d04d014010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258059199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.2258059199
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.3595694962
Short name T1151
Test name
Test status
Simulation time 12089199086 ps
CPU time 106.42 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:38:36 PM PDT 24
Peak memory 200008 kb
Host smart-28c9feef-ec89-43e7-bcea-3f98a4b73624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595694962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.3595694962
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.292288555
Short name T659
Test name
Test status
Simulation time 1387617161 ps
CPU time 1.71 seconds
Started Aug 02 05:36:51 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 196612 kb
Host smart-a4afd75e-d703-4e44-8b6b-f745fb2ae597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=292288555 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.292288555
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.3557294552
Short name T1108
Test name
Test status
Simulation time 167932109024 ps
CPU time 103.79 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:38:49 PM PDT 24
Peak memory 199920 kb
Host smart-f3ed94d2-7f89-4675-a700-1a82166bd4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557294552 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.3557294552
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.2039033123
Short name T85
Test name
Test status
Simulation time 1986445279 ps
CPU time 3.47 seconds
Started Aug 02 05:36:59 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 195696 kb
Host smart-325aa8a3-4862-4626-a872-08ea19dec3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039033123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.2039033123
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2092628399
Short name T897
Test name
Test status
Simulation time 479179086 ps
CPU time 2.2 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:36:52 PM PDT 24
Peak memory 199080 kb
Host smart-1566e9a4-effc-4c75-b0df-a0b1f1181685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092628399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2092628399
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.577807110
Short name T136
Test name
Test status
Simulation time 156830924698 ps
CPU time 506.8 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:45:20 PM PDT 24
Peak memory 199996 kb
Host smart-2986e5b8-f4d8-400a-ac7d-a42816aa4597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577807110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.577807110
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.3883749823
Short name T932
Test name
Test status
Simulation time 46499929805 ps
CPU time 554.25 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:46:01 PM PDT 24
Peak memory 215572 kb
Host smart-efeae17a-c465-4692-9004-4bfb7cfa5c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883749823 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.3883749823
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.2319910944
Short name T400
Test name
Test status
Simulation time 674679305 ps
CPU time 2.51 seconds
Started Aug 02 05:37:09 PM PDT 24
Finished Aug 02 05:37:12 PM PDT 24
Peak memory 199856 kb
Host smart-3c431c7c-2a71-4e6d-8f3a-bcdea596635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319910944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.2319910944
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.1390757850
Short name T836
Test name
Test status
Simulation time 99728642622 ps
CPU time 43.84 seconds
Started Aug 02 05:37:06 PM PDT 24
Finished Aug 02 05:37:50 PM PDT 24
Peak memory 199924 kb
Host smart-f8e06a21-ad86-4986-846a-9ea880470683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390757850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.1390757850
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.1517895441
Short name T473
Test name
Test status
Simulation time 15981569 ps
CPU time 0.56 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 195620 kb
Host smart-eebe0f9c-b278-46df-94b3-66a49b04ef6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517895441 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.1517895441
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3611892998
Short name T1061
Test name
Test status
Simulation time 41117449123 ps
CPU time 23.49 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:37:12 PM PDT 24
Peak memory 199952 kb
Host smart-fd58391a-03b2-41df-843a-e6d7b00a0853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611892998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3611892998
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.1507734431
Short name T489
Test name
Test status
Simulation time 72414097640 ps
CPU time 15.33 seconds
Started Aug 02 05:36:47 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 200028 kb
Host smart-b2a1f04b-99ef-49a2-9e73-e4bff8394b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507734431 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.1507734431
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.415457662
Short name T195
Test name
Test status
Simulation time 161166964298 ps
CPU time 114.59 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 200004 kb
Host smart-69ee1700-0fa2-4bfc-af7b-c4cb02e10507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415457662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.415457662
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.2060048001
Short name T276
Test name
Test status
Simulation time 21806739485 ps
CPU time 8.47 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:36:56 PM PDT 24
Peak memory 199812 kb
Host smart-4760801f-7213-448e-abc2-64ee8b6f311c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060048001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.2060048001
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.2463833872
Short name T384
Test name
Test status
Simulation time 120882552187 ps
CPU time 941.54 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:52:31 PM PDT 24
Peak memory 200000 kb
Host smart-8384aed7-22ac-4a61-94df-71fdb1a74861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2463833872 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.2463833872
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.703250386
Short name T579
Test name
Test status
Simulation time 2433275022 ps
CPU time 1.77 seconds
Started Aug 02 05:36:49 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 196264 kb
Host smart-779c9670-94d6-4b44-938e-2b8d22552b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703250386 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.703250386
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.3029588682
Short name T823
Test name
Test status
Simulation time 14704369220 ps
CPU time 23.12 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:37:14 PM PDT 24
Peak memory 198792 kb
Host smart-6f64e9da-4427-4f3c-b0ee-cd9f681ba18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029588682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.3029588682
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_perf.3460887187
Short name T330
Test name
Test status
Simulation time 15259109914 ps
CPU time 232.96 seconds
Started Aug 02 05:36:54 PM PDT 24
Finished Aug 02 05:40:47 PM PDT 24
Peak memory 200016 kb
Host smart-229cda9a-33f0-426e-ac10-61ef8d422a8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3460887187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.3460887187
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.51920621
Short name T652
Test name
Test status
Simulation time 8255153292 ps
CPU time 66.68 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:37:59 PM PDT 24
Peak memory 197808 kb
Host smart-7d4720dc-6ded-400e-a308-37907ca7b939
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=51920621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.51920621
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.989052171
Short name T745
Test name
Test status
Simulation time 110593617812 ps
CPU time 133.32 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 199900 kb
Host smart-ac5b9200-d431-442f-bd05-6e8badce42e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989052171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.989052171
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1264786513
Short name T349
Test name
Test status
Simulation time 5290499719 ps
CPU time 1.54 seconds
Started Aug 02 05:36:50 PM PDT 24
Finished Aug 02 05:36:51 PM PDT 24
Peak memory 196268 kb
Host smart-4fc30ebb-ede3-4c14-9f5d-052142a0ad58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264786513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1264786513
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.1431131154
Short name T353
Test name
Test status
Simulation time 927767011 ps
CPU time 4.98 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 199900 kb
Host smart-995e2a30-05c0-4257-9d42-7c631ba3bcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431131154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.1431131154
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.863312
Short name T413
Test name
Test status
Simulation time 469604677919 ps
CPU time 408.34 seconds
Started Aug 02 05:36:48 PM PDT 24
Finished Aug 02 05:43:37 PM PDT 24
Peak memory 199996 kb
Host smart-833daf60-6f34-410c-a6c5-873152861040
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.863312
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.787549339
Short name T983
Test name
Test status
Simulation time 63515681608 ps
CPU time 1028.3 seconds
Started Aug 02 05:36:53 PM PDT 24
Finished Aug 02 05:54:02 PM PDT 24
Peak memory 224756 kb
Host smart-d2f35bfd-0f27-4d5c-82c6-b51751aa5b7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787549339 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.787549339
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.468267131
Short name T1066
Test name
Test status
Simulation time 1561056242 ps
CPU time 3.03 seconds
Started Aug 02 05:36:51 PM PDT 24
Finished Aug 02 05:36:54 PM PDT 24
Peak memory 199824 kb
Host smart-2ed29b0d-bbb8-4503-9fec-51d5799d5499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468267131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.468267131
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/42.uart_tx_rx.632027418
Short name T427
Test name
Test status
Simulation time 133703308760 ps
CPU time 138.59 seconds
Started Aug 02 05:36:46 PM PDT 24
Finished Aug 02 05:39:05 PM PDT 24
Peak memory 199988 kb
Host smart-99f99ac2-b3e4-42d0-a91d-c9fa3ae6890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632027418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.632027418
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/43.uart_alert_test.464211103
Short name T644
Test name
Test status
Simulation time 147731626 ps
CPU time 0.55 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 195392 kb
Host smart-7f413ae6-7cfe-4af2-b4da-523300d3ff25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464211103 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.464211103
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.1928308985
Short name T610
Test name
Test status
Simulation time 85310603378 ps
CPU time 37.46 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:37:37 PM PDT 24
Peak memory 199980 kb
Host smart-46c40f36-4e52-4aaa-9ea3-564f3881b62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928308985 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.1928308985
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.1740087308
Short name T1171
Test name
Test status
Simulation time 42702300876 ps
CPU time 44.54 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 199992 kb
Host smart-dddd487b-b99f-42ca-8365-d30dc72b8f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740087308 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.1740087308
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.1087551210
Short name T130
Test name
Test status
Simulation time 17733814401 ps
CPU time 25.78 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:37:26 PM PDT 24
Peak memory 199976 kb
Host smart-8b920c07-58a5-4295-97ec-e069cfefdf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087551210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.1087551210
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.4291728143
Short name T950
Test name
Test status
Simulation time 6476276827 ps
CPU time 9.58 seconds
Started Aug 02 05:36:56 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 196752 kb
Host smart-375af518-57b6-44cc-b590-c9dd506a94d8
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291728143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.4291728143
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.4082835360
Short name T395
Test name
Test status
Simulation time 89770467723 ps
CPU time 251.66 seconds
Started Aug 02 05:36:54 PM PDT 24
Finished Aug 02 05:41:06 PM PDT 24
Peak memory 199976 kb
Host smart-968c22d3-77a1-4b2b-aa4a-b8be579f6663
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4082835360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.4082835360
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.2453428377
Short name T486
Test name
Test status
Simulation time 9453196701 ps
CPU time 4.8 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 198820 kb
Host smart-5109be8b-5fa5-41d4-98c1-65c9b6408a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453428377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.2453428377
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.254672959
Short name T1122
Test name
Test status
Simulation time 55671158333 ps
CPU time 20.88 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 199728 kb
Host smart-97d95868-8ffd-4a38-a946-5e22505645c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254672959 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.254672959
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.1244642030
Short name T935
Test name
Test status
Simulation time 21605123736 ps
CPU time 1131.3 seconds
Started Aug 02 05:36:56 PM PDT 24
Finished Aug 02 05:55:48 PM PDT 24
Peak memory 199936 kb
Host smart-c686a8c4-6f5e-4d51-a3b2-ec64edbdacb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1244642030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.1244642030
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.1989910865
Short name T425
Test name
Test status
Simulation time 2113058856 ps
CPU time 12.51 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:37:10 PM PDT 24
Peak memory 197912 kb
Host smart-8abbda1c-3522-451f-956b-5cb7354af65f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1989910865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.1989910865
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.4081400769
Short name T817
Test name
Test status
Simulation time 57158505772 ps
CPU time 36.69 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:37:35 PM PDT 24
Peak memory 199532 kb
Host smart-f6e87adb-9920-4dec-8e46-0ca109bdd5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081400769 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.4081400769
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.4070492756
Short name T464
Test name
Test status
Simulation time 4385474049 ps
CPU time 1.14 seconds
Started Aug 02 05:36:55 PM PDT 24
Finished Aug 02 05:36:57 PM PDT 24
Peak memory 196312 kb
Host smart-2d98b509-8a5c-4124-a38f-45c523df3e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070492756 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.4070492756
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.3877107939
Short name T525
Test name
Test status
Simulation time 5636332905 ps
CPU time 4 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:37:02 PM PDT 24
Peak memory 200008 kb
Host smart-6d4b0901-193a-4866-b886-590596925b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877107939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.3877107939
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.2109722237
Short name T1140
Test name
Test status
Simulation time 235824419531 ps
CPU time 81.21 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:38:20 PM PDT 24
Peak memory 199960 kb
Host smart-b29d85fa-ab85-4263-bdcc-bc7d4179233d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109722237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.2109722237
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.3570623892
Short name T31
Test name
Test status
Simulation time 31091522540 ps
CPU time 358.54 seconds
Started Aug 02 05:36:56 PM PDT 24
Finished Aug 02 05:42:54 PM PDT 24
Peak memory 216516 kb
Host smart-ead2a90f-5815-40a7-863d-1522158bb1ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570623892 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.3570623892
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3240865272
Short name T586
Test name
Test status
Simulation time 6332104472 ps
CPU time 26.07 seconds
Started Aug 02 05:36:59 PM PDT 24
Finished Aug 02 05:37:25 PM PDT 24
Peak memory 199932 kb
Host smart-3ec5e01d-ae33-4dee-9a17-db3789e38672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240865272 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3240865272
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.1571448240
Short name T307
Test name
Test status
Simulation time 49217294658 ps
CPU time 74.47 seconds
Started Aug 02 05:37:00 PM PDT 24
Finished Aug 02 05:38:15 PM PDT 24
Peak memory 199944 kb
Host smart-bb197cac-d5af-4c1e-b814-ede4090bbdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571448240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.1571448240
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.30278712
Short name T392
Test name
Test status
Simulation time 22140107 ps
CPU time 0.58 seconds
Started Aug 02 05:37:02 PM PDT 24
Finished Aug 02 05:37:03 PM PDT 24
Peak memory 195332 kb
Host smart-ecfc0a13-ebd0-4de9-ab30-5b57556881cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30278712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.30278712
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.3243444032
Short name T508
Test name
Test status
Simulation time 162849876636 ps
CPU time 245.22 seconds
Started Aug 02 05:36:59 PM PDT 24
Finished Aug 02 05:41:04 PM PDT 24
Peak memory 199952 kb
Host smart-bdc567b3-1585-448e-abb6-e585023043b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243444032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.3243444032
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.4068163009
Short name T374
Test name
Test status
Simulation time 19287216546 ps
CPU time 12.12 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:37:17 PM PDT 24
Peak memory 199728 kb
Host smart-346201cc-fd77-475e-813c-54cdf333ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068163009 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.4068163009
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.290081158
Short name T572
Test name
Test status
Simulation time 14131223179 ps
CPU time 18.88 seconds
Started Aug 02 05:36:56 PM PDT 24
Finished Aug 02 05:37:15 PM PDT 24
Peak memory 199412 kb
Host smart-9ce41a4a-7357-4d94-b3df-aa0ee681d665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290081158 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.290081158
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.2263490535
Short name T12
Test name
Test status
Simulation time 170439709186 ps
CPU time 234.76 seconds
Started Aug 02 05:36:56 PM PDT 24
Finished Aug 02 05:40:51 PM PDT 24
Peak memory 197208 kb
Host smart-1781a997-0467-4d1b-94a3-427cebe2b9c3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263490535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.2263490535
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.2538132920
Short name T1178
Test name
Test status
Simulation time 68798714607 ps
CPU time 75.17 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:38:18 PM PDT 24
Peak memory 199988 kb
Host smart-2f974f0c-6209-4cb6-b3f6-c2522bfb70fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2538132920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.2538132920
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.4218561798
Short name T653
Test name
Test status
Simulation time 1719144895 ps
CPU time 2.87 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 197392 kb
Host smart-4a5382ce-97aa-4ed0-ab40-88d51ad7c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218561798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.4218561798
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.1609332019
Short name T515
Test name
Test status
Simulation time 77323446060 ps
CPU time 149.27 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:39:26 PM PDT 24
Peak memory 200084 kb
Host smart-64b68d46-c3e2-46f7-82ee-13f0dce6c64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609332019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.1609332019
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.4144637513
Short name T555
Test name
Test status
Simulation time 12956417157 ps
CPU time 349.35 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:42:46 PM PDT 24
Peak memory 199972 kb
Host smart-608a8e62-a18e-444b-98fc-b6815eefe354
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144637513 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.4144637513
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.2666680684
Short name T601
Test name
Test status
Simulation time 5148161300 ps
CPU time 20.88 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 199148 kb
Host smart-bb51acf9-9a52-4909-908d-e40d8d6452e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2666680684 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.2666680684
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.1200625205
Short name T872
Test name
Test status
Simulation time 512738417 ps
CPU time 1.53 seconds
Started Aug 02 05:36:55 PM PDT 24
Finished Aug 02 05:36:57 PM PDT 24
Peak memory 195492 kb
Host smart-27f79f34-e663-4a27-9405-fa123e6832d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200625205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.1200625205
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.1582928543
Short name T546
Test name
Test status
Simulation time 898859169 ps
CPU time 1.51 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 198612 kb
Host smart-32cc45de-1f59-4616-9180-22cab0c53c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582928543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.1582928543
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.86729131
Short name T664
Test name
Test status
Simulation time 238048450293 ps
CPU time 526.36 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:45:52 PM PDT 24
Peak memory 216608 kb
Host smart-39f499c7-5b46-430a-8278-5959999a5746
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86729131 -assert nopostpro
c +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd
b -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.86729131
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.410341291
Short name T422
Test name
Test status
Simulation time 6445398766 ps
CPU time 18.36 seconds
Started Aug 02 05:37:08 PM PDT 24
Finished Aug 02 05:37:27 PM PDT 24
Peak memory 199876 kb
Host smart-97bb07fd-0ffe-4481-a539-5265094e2cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410341291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.410341291
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.3247332922
Short name T629
Test name
Test status
Simulation time 49372999160 ps
CPU time 15.71 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 199764 kb
Host smart-649ed889-8936-4e22-afb8-b8bb5fe95668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247332922 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.3247332922
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.3835229634
Short name T582
Test name
Test status
Simulation time 27696380 ps
CPU time 0.54 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:06 PM PDT 24
Peak memory 194872 kb
Host smart-512aeba7-d186-4f32-b21d-4240c0b38a77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835229634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.3835229634
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.134248596
Short name T300
Test name
Test status
Simulation time 64715115992 ps
CPU time 25.4 seconds
Started Aug 02 05:36:58 PM PDT 24
Finished Aug 02 05:37:23 PM PDT 24
Peak memory 199980 kb
Host smart-63f33043-f62e-4fb4-b6e6-b5977c58316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134248596 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.134248596
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.918525112
Short name T139
Test name
Test status
Simulation time 11018392675 ps
CPU time 17.69 seconds
Started Aug 02 05:37:06 PM PDT 24
Finished Aug 02 05:37:24 PM PDT 24
Peak memory 199916 kb
Host smart-ed2edb4c-66a9-4b8a-b58a-a136e55cdf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918525112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.918525112
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.3537173542
Short name T35
Test name
Test status
Simulation time 96072317619 ps
CPU time 296.36 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:42:01 PM PDT 24
Peak memory 199952 kb
Host smart-fb63732e-1e35-4664-bc79-98bb6fa6a9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537173542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.3537173542
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.3957592282
Short name T942
Test name
Test status
Simulation time 29290533302 ps
CPU time 52.85 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:37:57 PM PDT 24
Peak memory 199988 kb
Host smart-83fc4359-8c7b-40cd-8a0b-5b8d4196d98b
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957592282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.3957592282
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.2845001459
Short name T1056
Test name
Test status
Simulation time 141978371340 ps
CPU time 513.07 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:45:36 PM PDT 24
Peak memory 199740 kb
Host smart-984d67e8-b9bc-49e3-81a3-d9e2bd2847fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2845001459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.2845001459
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.608396820
Short name T1055
Test name
Test status
Simulation time 5484810008 ps
CPU time 5.82 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:11 PM PDT 24
Peak memory 199948 kb
Host smart-afb4db97-b1a6-461f-a073-da05a36e4f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608396820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.608396820
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.3497404396
Short name T821
Test name
Test status
Simulation time 98156054497 ps
CPU time 43.76 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:51 PM PDT 24
Peak memory 208324 kb
Host smart-a29630f0-913f-468f-bd97-593b6066f05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497404396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.3497404396
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1296701025
Short name T362
Test name
Test status
Simulation time 12243501999 ps
CPU time 126.39 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:39:08 PM PDT 24
Peak memory 199956 kb
Host smart-e5e10d5b-2b1d-4e28-9aec-ac901900b7d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1296701025 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1296701025
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.2006870306
Short name T611
Test name
Test status
Simulation time 4220273774 ps
CPU time 38.48 seconds
Started Aug 02 05:37:14 PM PDT 24
Finished Aug 02 05:37:52 PM PDT 24
Peak memory 198180 kb
Host smart-9a3db7e8-cba8-4ab4-aa33-2b8ba7b0c929
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006870306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.2006870306
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.1980827174
Short name T394
Test name
Test status
Simulation time 123084632539 ps
CPU time 84.4 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:38:34 PM PDT 24
Peak memory 199920 kb
Host smart-8c03eea1-e041-458a-a976-1c15c822bf98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980827174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.1980827174
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.405142455
Short name T996
Test name
Test status
Simulation time 5285045291 ps
CPU time 2.24 seconds
Started Aug 02 05:37:02 PM PDT 24
Finished Aug 02 05:37:04 PM PDT 24
Peak memory 196180 kb
Host smart-27801a48-e9b9-4ad8-b7a7-ae64d7e61af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405142455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.405142455
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.4246886970
Short name T512
Test name
Test status
Simulation time 123308068 ps
CPU time 1 seconds
Started Aug 02 05:36:57 PM PDT 24
Finished Aug 02 05:36:58 PM PDT 24
Peak memory 197844 kb
Host smart-3fe7d461-9500-4534-b481-c131b70e4f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246886970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.4246886970
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.2302658004
Short name T1138
Test name
Test status
Simulation time 412310406131 ps
CPU time 218.67 seconds
Started Aug 02 05:37:01 PM PDT 24
Finished Aug 02 05:40:40 PM PDT 24
Peak memory 199916 kb
Host smart-ac804644-3fef-41b1-9c41-bd94a70b2168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302658004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.2302658004
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.632513755
Short name T793
Test name
Test status
Simulation time 152267899142 ps
CPU time 201.14 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:40:28 PM PDT 24
Peak memory 213956 kb
Host smart-aa01ebe9-82cb-414d-8845-962c705798d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632513755 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.632513755
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2699073616
Short name T301
Test name
Test status
Simulation time 7510955682 ps
CPU time 8.84 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 199992 kb
Host smart-cf0c5427-069d-4995-89a5-a58d2ffc1e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699073616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2699073616
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1436280841
Short name T560
Test name
Test status
Simulation time 79119842781 ps
CPU time 78 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:38:22 PM PDT 24
Peak memory 199976 kb
Host smart-f2bd7586-f954-4291-a7e9-f58ee389cd29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436280841 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1436280841
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.1654680664
Short name T399
Test name
Test status
Simulation time 13408362 ps
CPU time 0.56 seconds
Started Aug 02 05:37:08 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 195740 kb
Host smart-1e2bbb5d-3cb6-461c-9700-074523bedf6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654680664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.1654680664
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2089167820
Short name T752
Test name
Test status
Simulation time 135169404390 ps
CPU time 182.44 seconds
Started Aug 02 05:37:06 PM PDT 24
Finished Aug 02 05:40:08 PM PDT 24
Peak memory 199964 kb
Host smart-2eed8a48-ba8b-4c96-8e20-76b2a793ed8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089167820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2089167820
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.1484359112
Short name T672
Test name
Test status
Simulation time 19746261182 ps
CPU time 19.83 seconds
Started Aug 02 05:37:06 PM PDT 24
Finished Aug 02 05:37:26 PM PDT 24
Peak memory 199880 kb
Host smart-c00a2722-ac08-4c7b-b08b-e942bd5ef970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484359112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.1484359112
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2477936314
Short name T34
Test name
Test status
Simulation time 45846601272 ps
CPU time 26.25 seconds
Started Aug 02 05:37:20 PM PDT 24
Finished Aug 02 05:37:47 PM PDT 24
Peak memory 199896 kb
Host smart-429d3fa5-3de2-407e-ac43-5a9b19a6679f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477936314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2477936314
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.4128774257
Short name T585
Test name
Test status
Simulation time 43178261979 ps
CPU time 76.45 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:38:23 PM PDT 24
Peak memory 200012 kb
Host smart-f10302f1-76eb-46ff-b48b-5d70e88681c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128774257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.4128774257
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.2371408796
Short name T465
Test name
Test status
Simulation time 246483564620 ps
CPU time 516.93 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:45:44 PM PDT 24
Peak memory 199916 kb
Host smart-bf53146e-a449-4162-b4e5-171166c14fdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2371408796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.2371408796
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2619083370
Short name T365
Test name
Test status
Simulation time 1160373909 ps
CPU time 0.81 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 195468 kb
Host smart-9882608f-5caf-4bd2-9003-99c5c040466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619083370 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2619083370
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.3924572477
Short name T733
Test name
Test status
Simulation time 143297530137 ps
CPU time 92.23 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 200120 kb
Host smart-68e2a836-241b-46af-9647-a1af7d0a9249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924572477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.3924572477
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.2437303374
Short name T455
Test name
Test status
Simulation time 15262434907 ps
CPU time 853.26 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:51:21 PM PDT 24
Peak memory 199972 kb
Host smart-7122d7b1-0646-4616-b3d0-d8382480c098
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437303374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.2437303374
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3578459895
Short name T1142
Test name
Test status
Simulation time 2225289267 ps
CPU time 3.76 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 198304 kb
Host smart-8fbabc4c-d4bb-4bad-910a-fd406478b74b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3578459895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3578459895
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.2039130220
Short name T1045
Test name
Test status
Simulation time 243672220498 ps
CPU time 20.99 seconds
Started Aug 02 05:37:02 PM PDT 24
Finished Aug 02 05:37:23 PM PDT 24
Peak memory 199064 kb
Host smart-5249c340-aa30-4785-b931-c49d4e09f722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039130220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.2039130220
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.1058927429
Short name T450
Test name
Test status
Simulation time 4114831528 ps
CPU time 7.02 seconds
Started Aug 02 05:37:02 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 196352 kb
Host smart-e6c4e200-7d70-4cda-a91f-bd8a3dd7b871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058927429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.1058927429
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.2232484798
Short name T1052
Test name
Test status
Simulation time 932804116 ps
CPU time 4.23 seconds
Started Aug 02 05:37:08 PM PDT 24
Finished Aug 02 05:37:13 PM PDT 24
Peak memory 198316 kb
Host smart-1be293a7-cd50-4e9c-b046-a57b20298c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232484798 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.2232484798
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2781807925
Short name T1134
Test name
Test status
Simulation time 308785756116 ps
CPU time 472.63 seconds
Started Aug 02 05:37:08 PM PDT 24
Finished Aug 02 05:45:00 PM PDT 24
Peak memory 200076 kb
Host smart-9177ddd6-418a-40ee-85c7-6a251c269d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781807925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2781807925
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.957037414
Short name T625
Test name
Test status
Simulation time 1246029875 ps
CPU time 1.97 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 198776 kb
Host smart-8aea0da7-5641-4265-9090-b4100adc1dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957037414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.957037414
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.1109827747
Short name T705
Test name
Test status
Simulation time 31884292296 ps
CPU time 80.34 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:38:24 PM PDT 24
Peak memory 199948 kb
Host smart-0fb2db0b-2b57-4b92-b8f3-e7a690c1955f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109827747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.1109827747
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.962039189
Short name T1103
Test name
Test status
Simulation time 36048754 ps
CPU time 0.56 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:37:10 PM PDT 24
Peak memory 195324 kb
Host smart-40d2f919-d9d0-4d50-8d1f-8e317581c58e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962039189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.962039189
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.3192940403
Short name T1114
Test name
Test status
Simulation time 205163463223 ps
CPU time 164.41 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:39:48 PM PDT 24
Peak memory 199876 kb
Host smart-44d5a423-8bd7-470a-b540-0dd3b680f7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192940403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.3192940403
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.1471652582
Short name T182
Test name
Test status
Simulation time 62167108778 ps
CPU time 99.99 seconds
Started Aug 02 05:37:04 PM PDT 24
Finished Aug 02 05:38:44 PM PDT 24
Peak memory 199872 kb
Host smart-b88b12d1-3ffc-4834-b2a4-ae3a92c665c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471652582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.1471652582
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.4168081177
Short name T1118
Test name
Test status
Simulation time 36065574941 ps
CPU time 15.54 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:22 PM PDT 24
Peak memory 199036 kb
Host smart-9413b150-73b1-4215-983b-652562b4ade2
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168081177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.4168081177
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.512062145
Short name T1102
Test name
Test status
Simulation time 83011730646 ps
CPU time 547.87 seconds
Started Aug 02 05:37:13 PM PDT 24
Finished Aug 02 05:46:22 PM PDT 24
Peak memory 199924 kb
Host smart-600e6366-e3cd-426a-9951-925d32d40836
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512062145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.512062145
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.3420925890
Short name T704
Test name
Test status
Simulation time 11144076801 ps
CPU time 11.12 seconds
Started Aug 02 05:37:09 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 200052 kb
Host smart-0695ef34-4ab7-4b2b-96f4-122fbb976258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420925890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.3420925890
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.67460809
Short name T764
Test name
Test status
Simulation time 105082780450 ps
CPU time 62.61 seconds
Started Aug 02 05:37:02 PM PDT 24
Finished Aug 02 05:38:05 PM PDT 24
Peak memory 200128 kb
Host smart-33fdfc42-5267-4458-8671-3ad96fdd208a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67460809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.67460809
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.1791648507
Short name T649
Test name
Test status
Simulation time 8721221010 ps
CPU time 507.65 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:45:42 PM PDT 24
Peak memory 200060 kb
Host smart-d5fee1cd-9e7c-4181-a35b-863d3d59be0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1791648507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.1791648507
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.1082035793
Short name T1124
Test name
Test status
Simulation time 4904926841 ps
CPU time 10.33 seconds
Started Aug 02 05:37:03 PM PDT 24
Finished Aug 02 05:37:13 PM PDT 24
Peak memory 198232 kb
Host smart-96c930f3-ce11-4812-b436-1f824fe67eb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082035793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.1082035793
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.3406732287
Short name T912
Test name
Test status
Simulation time 36586347710 ps
CPU time 41.25 seconds
Started Aug 02 05:37:13 PM PDT 24
Finished Aug 02 05:37:54 PM PDT 24
Peak memory 199944 kb
Host smart-2a639835-a196-49f2-be65-d627ec3919fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406732287 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.3406732287
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.2930604341
Short name T350
Test name
Test status
Simulation time 4071853821 ps
CPU time 0.94 seconds
Started Aug 02 05:37:07 PM PDT 24
Finished Aug 02 05:37:08 PM PDT 24
Peak memory 196848 kb
Host smart-0bda8a50-2498-4594-8a22-20e0357215de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930604341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.2930604341
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.2441708795
Short name T377
Test name
Test status
Simulation time 676868959 ps
CPU time 2.03 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:07 PM PDT 24
Peak memory 199040 kb
Host smart-edbd58f9-32c1-4be8-b18e-32a4754fa88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441708795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.2441708795
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.3073263630
Short name T895
Test name
Test status
Simulation time 169484080629 ps
CPU time 226.94 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:40:57 PM PDT 24
Peak memory 199828 kb
Host smart-f448995d-0751-4227-b6e5-fdb6035af94a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073263630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.3073263630
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.3147456172
Short name T1143
Test name
Test status
Simulation time 1029697746869 ps
CPU time 966.62 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:53:17 PM PDT 24
Peak memory 231292 kb
Host smart-3c7613ce-f4c6-4938-9493-090212b4d75a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147456172 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.3147456172
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.1038308281
Short name T755
Test name
Test status
Simulation time 598355004 ps
CPU time 2.43 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:37:14 PM PDT 24
Peak memory 198412 kb
Host smart-903a53b2-11ec-4c3e-9bf7-8e4cbf9695d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038308281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.1038308281
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.2965100518
Short name T354
Test name
Test status
Simulation time 39627323288 ps
CPU time 23.35 seconds
Started Aug 02 05:37:05 PM PDT 24
Finished Aug 02 05:37:28 PM PDT 24
Peak memory 199936 kb
Host smart-2b79b6ef-4c2a-4e4a-b552-6625b0df721b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965100518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.2965100518
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.762642687
Short name T561
Test name
Test status
Simulation time 61561610 ps
CPU time 0.54 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:16 PM PDT 24
Peak memory 195072 kb
Host smart-e93d6f59-928e-4185-9736-0aebac6d369c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762642687 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.762642687
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.857058205
Short name T824
Test name
Test status
Simulation time 160778656312 ps
CPU time 262.66 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:41:32 PM PDT 24
Peak memory 200012 kb
Host smart-698012de-6e52-4e9e-9709-e499edbf440f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857058205 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.857058205
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.1299077584
Short name T600
Test name
Test status
Simulation time 64113553528 ps
CPU time 29.99 seconds
Started Aug 02 05:37:08 PM PDT 24
Finished Aug 02 05:37:38 PM PDT 24
Peak memory 199884 kb
Host smart-fd9840a3-6141-485c-8e57-b8ed72767ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299077584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.1299077584
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3638910268
Short name T177
Test name
Test status
Simulation time 132669817455 ps
CPU time 154.94 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:39:46 PM PDT 24
Peak memory 199924 kb
Host smart-45fccd7e-1541-49ff-b094-bb290f07b01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638910268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3638910268
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.726022360
Short name T1033
Test name
Test status
Simulation time 135889759905 ps
CPU time 51.64 seconds
Started Aug 02 05:37:19 PM PDT 24
Finished Aug 02 05:38:11 PM PDT 24
Peak memory 196780 kb
Host smart-69409fd4-f103-43ec-9061-5de7201474b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726022360 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.726022360
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.3738525897
Short name T1135
Test name
Test status
Simulation time 115069044636 ps
CPU time 665.13 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:48:15 PM PDT 24
Peak memory 199900 kb
Host smart-75776495-9289-407c-94eb-294935694304
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3738525897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.3738525897
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1137268717
Short name T368
Test name
Test status
Simulation time 77728148 ps
CPU time 0.57 seconds
Started Aug 02 05:37:20 PM PDT 24
Finished Aug 02 05:37:20 PM PDT 24
Peak memory 195876 kb
Host smart-2821ea1b-3ab0-42ba-a581-f6d2b1a712d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137268717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1137268717
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.1925200793
Short name T838
Test name
Test status
Simulation time 70450469651 ps
CPU time 58.78 seconds
Started Aug 02 05:37:12 PM PDT 24
Finished Aug 02 05:38:10 PM PDT 24
Peak memory 199544 kb
Host smart-20c658d2-fdf3-4581-864b-94619207219e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925200793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.1925200793
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.3413134598
Short name T616
Test name
Test status
Simulation time 8455078706 ps
CPU time 124.87 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:39:15 PM PDT 24
Peak memory 199980 kb
Host smart-b0ef1e26-1b3f-4b1f-acd8-46bb763fd36a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3413134598 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.3413134598
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.1173201975
Short name T689
Test name
Test status
Simulation time 3658025519 ps
CPU time 3.15 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:37:13 PM PDT 24
Peak memory 198472 kb
Host smart-5a3c2577-a143-4347-8613-f4168ee6b593
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1173201975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.1173201975
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.4209355328
Short name T1105
Test name
Test status
Simulation time 78197535366 ps
CPU time 101.41 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:38:57 PM PDT 24
Peak memory 199972 kb
Host smart-6486a1c6-3e82-427a-bb70-2f3c7d7b8b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209355328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.4209355328
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.1979154253
Short name T1039
Test name
Test status
Simulation time 826986989 ps
CPU time 0.99 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:37:17 PM PDT 24
Peak memory 195444 kb
Host smart-c15dbfd4-cb70-4219-8a79-f6cc5b19dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979154253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.1979154253
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.3464295528
Short name T507
Test name
Test status
Simulation time 709891953 ps
CPU time 1.52 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:37:12 PM PDT 24
Peak memory 199876 kb
Host smart-08f71844-487c-4fb6-b48d-b5d23264cf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464295528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.3464295528
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all.2282183042
Short name T612
Test name
Test status
Simulation time 404045361520 ps
CPU time 420.85 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:44:17 PM PDT 24
Peak memory 208304 kb
Host smart-e613100c-de50-4435-bde7-5c3fc34571e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282183042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2282183042
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.1503678718
Short name T569
Test name
Test status
Simulation time 125274477548 ps
CPU time 1097.76 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:55:29 PM PDT 24
Peak memory 224788 kb
Host smart-60f825a1-0ef9-48ed-8409-3e080f97dfa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503678718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.1503678718
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.3632197543
Short name T373
Test name
Test status
Simulation time 6382960601 ps
CPU time 30.98 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 199740 kb
Host smart-f4073558-76da-41f1-964e-8ee98b5f8111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632197543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.3632197543
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.3018383834
Short name T692
Test name
Test status
Simulation time 97155813318 ps
CPU time 151.35 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 200008 kb
Host smart-11a4d0cd-b760-4171-a867-01063012f259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018383834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.3018383834
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.3752404479
Short name T566
Test name
Test status
Simulation time 50716777 ps
CPU time 0.53 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:16 PM PDT 24
Peak memory 195080 kb
Host smart-10ae1345-38ed-4fc5-bebc-37497e4da274
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752404479 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.3752404479
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.1291854237
Short name T968
Test name
Test status
Simulation time 116079304294 ps
CPU time 57.89 seconds
Started Aug 02 05:37:10 PM PDT 24
Finished Aug 02 05:38:08 PM PDT 24
Peak memory 200032 kb
Host smart-14235b25-482a-4dc5-bb77-4d2d95532fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291854237 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.1291854237
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.1388148871
Short name T156
Test name
Test status
Simulation time 14728404871 ps
CPU time 23.6 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:39 PM PDT 24
Peak memory 199972 kb
Host smart-81494b9b-30a5-4a84-872b-4b0dc22744d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388148871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.1388148871
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.541629177
Short name T201
Test name
Test status
Simulation time 23140169238 ps
CPU time 17.28 seconds
Started Aug 02 05:37:19 PM PDT 24
Finished Aug 02 05:37:37 PM PDT 24
Peak memory 199980 kb
Host smart-8d27cf77-cbeb-4915-aadf-05ad3fe94aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541629177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.541629177
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.4097991034
Short name T115
Test name
Test status
Simulation time 55618451713 ps
CPU time 29.94 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:45 PM PDT 24
Peak memory 199988 kb
Host smart-69a9bf4b-b201-4685-a927-05c8a11a1e2e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097991034 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.4097991034
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.2304258420
Short name T1095
Test name
Test status
Simulation time 77368427262 ps
CPU time 300.09 seconds
Started Aug 02 05:37:13 PM PDT 24
Finished Aug 02 05:42:13 PM PDT 24
Peak memory 199908 kb
Host smart-8b036a7f-0dd5-41db-9098-f2941e761416
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2304258420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.2304258420
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.2313593856
Short name T1010
Test name
Test status
Simulation time 6039343065 ps
CPU time 6.82 seconds
Started Aug 02 05:37:12 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 198900 kb
Host smart-979a5599-e3cc-45ff-bf55-d0287c4a7ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313593856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.2313593856
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.1231031357
Short name T658
Test name
Test status
Simulation time 61562833460 ps
CPU time 34.62 seconds
Started Aug 02 05:37:12 PM PDT 24
Finished Aug 02 05:37:46 PM PDT 24
Peak memory 200148 kb
Host smart-f4ac2b37-9798-4f28-a37f-92fee45c154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231031357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.1231031357
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.1903832616
Short name T438
Test name
Test status
Simulation time 15918078364 ps
CPU time 138.22 seconds
Started Aug 02 05:37:09 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 199940 kb
Host smart-8f230997-beb7-4aa8-bf72-2ed25916698b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1903832616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.1903832616
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.1521466242
Short name T1042
Test name
Test status
Simulation time 7079532945 ps
CPU time 4.89 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 197896 kb
Host smart-67b46b2b-0e39-4a78-9b7f-b143c924cac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1521466242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.1521466242
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2336975019
Short name T478
Test name
Test status
Simulation time 127208774758 ps
CPU time 21.04 seconds
Started Aug 02 05:37:11 PM PDT 24
Finished Aug 02 05:37:32 PM PDT 24
Peak memory 199980 kb
Host smart-9187323e-d8a5-4772-a16e-4972c238281e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336975019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2336975019
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.2946303270
Short name T761
Test name
Test status
Simulation time 5169011939 ps
CPU time 4.49 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:37:21 PM PDT 24
Peak memory 196320 kb
Host smart-dde0ab14-1fd4-41fb-83a2-c9b7ee116cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946303270 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.2946303270
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.990484051
Short name T548
Test name
Test status
Simulation time 103882849 ps
CPU time 0.97 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:37:16 PM PDT 24
Peak memory 198052 kb
Host smart-f3ae9628-5fef-42ba-a185-8f835e79ebff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990484051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.990484051
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.1259002988
Short name T703
Test name
Test status
Simulation time 212171518563 ps
CPU time 203.75 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:40:39 PM PDT 24
Peak memory 199872 kb
Host smart-4071de4a-cda3-4b96-a115-dbd2a987d6c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259002988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.1259002988
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.1125828986
Short name T100
Test name
Test status
Simulation time 91518365628 ps
CPU time 989.4 seconds
Started Aug 02 05:37:15 PM PDT 24
Finished Aug 02 05:53:45 PM PDT 24
Peak memory 216188 kb
Host smart-b3660e31-5fe1-4691-859e-a0bf1212e23a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125828986 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.1125828986
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.1834517518
Short name T787
Test name
Test status
Simulation time 1739004535 ps
CPU time 2.96 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 198796 kb
Host smart-ab3948b4-4c3c-4715-974d-fd8e0e3ab918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834517518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.1834517518
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.460989487
Short name T987
Test name
Test status
Simulation time 41472677266 ps
CPU time 69.68 seconds
Started Aug 02 05:37:09 PM PDT 24
Finished Aug 02 05:38:19 PM PDT 24
Peak memory 199984 kb
Host smart-7b9eeb88-53c7-4a73-bbb0-c4e15cf6fa03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460989487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.460989487
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.2316760241
Short name T757
Test name
Test status
Simulation time 30956863 ps
CPU time 0.62 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:35:34 PM PDT 24
Peak memory 195316 kb
Host smart-2bb6fe9d-ad46-4742-b0ae-cad71b2faa77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316760241 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.2316760241
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3898689215
Short name T1054
Test name
Test status
Simulation time 152564290801 ps
CPU time 130.4 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:37:44 PM PDT 24
Peak memory 199904 kb
Host smart-f6c2ab49-24b8-4d90-a534-121255cc1fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898689215 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3898689215
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.2113250768
Short name T545
Test name
Test status
Simulation time 36447341177 ps
CPU time 14.5 seconds
Started Aug 02 05:35:32 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 200004 kb
Host smart-e288eed6-2df8-47f6-99ca-e321d004897c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113250768 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.2113250768
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.176386824
Short name T962
Test name
Test status
Simulation time 7621959949 ps
CPU time 10 seconds
Started Aug 02 05:35:24 PM PDT 24
Finished Aug 02 05:35:35 PM PDT 24
Peak memory 199988 kb
Host smart-1e0ca392-7b50-4d2a-bbf2-080ba2accf5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176386824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.176386824
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.638369049
Short name T114
Test name
Test status
Simulation time 79141524157 ps
CPU time 63.13 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:36:25 PM PDT 24
Peak memory 199852 kb
Host smart-66188cad-053a-4bad-bdd2-172591fcb578
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638369049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.638369049
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.3559010028
Short name T969
Test name
Test status
Simulation time 165438318197 ps
CPU time 412.08 seconds
Started Aug 02 05:35:16 PM PDT 24
Finished Aug 02 05:42:09 PM PDT 24
Peak memory 200000 kb
Host smart-fb2a3143-adc9-4286-8059-5df9705987b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559010028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.3559010028
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.2403774120
Short name T433
Test name
Test status
Simulation time 6637995634 ps
CPU time 11.19 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:36 PM PDT 24
Peak memory 198712 kb
Host smart-74c264ac-2eb4-4299-86ba-823555386562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403774120 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.2403774120
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2525482291
Short name T514
Test name
Test status
Simulation time 6296567239 ps
CPU time 10.99 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 196264 kb
Host smart-09bf5143-7a90-4c6f-bf76-68dc82b50fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525482291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2525482291
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2198653578
Short name T558
Test name
Test status
Simulation time 24375440906 ps
CPU time 325.72 seconds
Started Aug 02 05:35:29 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 199932 kb
Host smart-9454d18c-ac7d-426a-bdd9-2f03116879c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2198653578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2198653578
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.2832867377
Short name T876
Test name
Test status
Simulation time 4604305032 ps
CPU time 9.43 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 198088 kb
Host smart-18737120-1bd9-4955-badc-08f1218fee4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2832867377 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.2832867377
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.2657426728
Short name T963
Test name
Test status
Simulation time 249136512616 ps
CPU time 76.04 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:36:52 PM PDT 24
Peak memory 199876 kb
Host smart-9199b015-73fb-44d5-82f9-8caf4a7842f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657426728 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.2657426728
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.2179041509
Short name T806
Test name
Test status
Simulation time 37182145094 ps
CPU time 51.67 seconds
Started Aug 02 05:35:23 PM PDT 24
Finished Aug 02 05:36:15 PM PDT 24
Peak memory 196128 kb
Host smart-9924165d-fbee-419d-8cc0-3ed89693c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179041509 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.2179041509
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.4124449905
Short name T797
Test name
Test status
Simulation time 274811251 ps
CPU time 1.38 seconds
Started Aug 02 05:35:24 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 198860 kb
Host smart-1fcfb70d-ff1b-48ea-b52a-4440c6779cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124449905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.4124449905
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.2531681350
Short name T1057
Test name
Test status
Simulation time 343721994685 ps
CPU time 91.24 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:37:09 PM PDT 24
Peak memory 199880 kb
Host smart-595c1b27-ba53-4f78-9392-13f9e255dd3b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531681350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.2531681350
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2163052268
Short name T295
Test name
Test status
Simulation time 550578568 ps
CPU time 2.21 seconds
Started Aug 02 05:35:22 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 199120 kb
Host smart-8749113c-3d72-49b6-acd9-8f5a5cd7b1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163052268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2163052268
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2106780128
Short name T251
Test name
Test status
Simulation time 117826026456 ps
CPU time 158.01 seconds
Started Aug 02 05:35:25 PM PDT 24
Finished Aug 02 05:38:03 PM PDT 24
Peak memory 200004 kb
Host smart-cd2512e8-26c8-4805-8c85-18b22f74b7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106780128 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2106780128
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2152674042
Short name T173
Test name
Test status
Simulation time 29177459437 ps
CPU time 47.63 seconds
Started Aug 02 05:37:12 PM PDT 24
Finished Aug 02 05:37:59 PM PDT 24
Peak memory 199904 kb
Host smart-174a4023-6dc8-4404-8099-ebf70e771821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152674042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2152674042
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1692480302
Short name T568
Test name
Test status
Simulation time 27028198309 ps
CPU time 207.27 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 208260 kb
Host smart-d9f7cfcb-c1c5-4d34-a4ef-0fcf65211f03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692480302 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1692480302
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.2829434327
Short name T169
Test name
Test status
Simulation time 20220691488 ps
CPU time 36.37 seconds
Started Aug 02 05:37:13 PM PDT 24
Finished Aug 02 05:37:49 PM PDT 24
Peak memory 199940 kb
Host smart-bbe167c0-c7aa-435b-8d82-89ba6c795de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829434327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.2829434327
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.4052165181
Short name T43
Test name
Test status
Simulation time 319305410509 ps
CPU time 905.01 seconds
Started Aug 02 05:37:13 PM PDT 24
Finished Aug 02 05:52:18 PM PDT 24
Peak memory 216496 kb
Host smart-b1c9c8c1-d997-43ec-8399-137e9fca6fc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052165181 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.4052165181
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2606900900
Short name T641
Test name
Test status
Simulation time 49957600612 ps
CPU time 155.88 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:39:52 PM PDT 24
Peak memory 200012 kb
Host smart-7604b0aa-b311-4a9d-a79b-00e122636ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606900900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2606900900
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.323791869
Short name T5
Test name
Test status
Simulation time 49331541770 ps
CPU time 360.59 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:43:18 PM PDT 24
Peak memory 208368 kb
Host smart-61e93cc2-f383-4f69-bbbb-ae5407c8fba3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323791869 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.323791869
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1040724972
Short name T1119
Test name
Test status
Simulation time 12084177395 ps
CPU time 18.69 seconds
Started Aug 02 05:37:18 PM PDT 24
Finished Aug 02 05:37:37 PM PDT 24
Peak memory 199740 kb
Host smart-06c72200-b35f-4491-8832-1f6c8df924e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040724972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1040724972
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.178643238
Short name T669
Test name
Test status
Simulation time 258120547149 ps
CPU time 237.21 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:41:19 PM PDT 24
Peak memory 199920 kb
Host smart-fbcbe1ed-467d-4cf3-966e-61bdc86a741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178643238 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.178643238
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.2381826577
Short name T550
Test name
Test status
Simulation time 71981414040 ps
CPU time 186.36 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:40:28 PM PDT 24
Peak memory 208240 kb
Host smart-5027bebe-ef95-4ad1-9d9f-3904fdb91b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381826577 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.2381826577
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.2470949097
Short name T776
Test name
Test status
Simulation time 8436484049 ps
CPU time 14.65 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:37:31 PM PDT 24
Peak memory 199888 kb
Host smart-db449327-33fc-49fe-be10-5ec9b3c0b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470949097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.2470949097
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.1293748418
Short name T633
Test name
Test status
Simulation time 914871344248 ps
CPU time 715.31 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:49:12 PM PDT 24
Peak memory 224880 kb
Host smart-c973bc43-2679-4bad-ab15-05ec310ba48f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293748418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.1293748418
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.3669887597
Short name T477
Test name
Test status
Simulation time 205180704213 ps
CPU time 84 seconds
Started Aug 02 05:37:19 PM PDT 24
Finished Aug 02 05:38:43 PM PDT 24
Peak memory 199916 kb
Host smart-dcb6544c-9456-43d4-b315-daf971b444a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669887597 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.3669887597
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.2213906128
Short name T1180
Test name
Test status
Simulation time 24616892604 ps
CPU time 296.26 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:42:13 PM PDT 24
Peak memory 216452 kb
Host smart-ac830f4e-9ddf-441d-a547-1af45e6c67e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213906128 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.2213906128
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.2008640094
Short name T270
Test name
Test status
Simulation time 202768699723 ps
CPU time 342.57 seconds
Started Aug 02 05:37:20 PM PDT 24
Finished Aug 02 05:43:03 PM PDT 24
Peak memory 199696 kb
Host smart-f3340bad-f0eb-47b8-8c66-99d00a8eec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008640094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.2008640094
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.2506520719
Short name T856
Test name
Test status
Simulation time 204510405767 ps
CPU time 856.49 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:51:34 PM PDT 24
Peak memory 224840 kb
Host smart-1e6f49a7-fb8a-49cc-aced-b655705cfbcb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506520719 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.2506520719
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.3445116944
Short name T131
Test name
Test status
Simulation time 27071636717 ps
CPU time 18.75 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:37:36 PM PDT 24
Peak memory 199804 kb
Host smart-2e7e0ad7-149d-4b54-bdb7-16493c3ba761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445116944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.3445116944
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.2579289740
Short name T972
Test name
Test status
Simulation time 63848085668 ps
CPU time 1140.31 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:56:23 PM PDT 24
Peak memory 216504 kb
Host smart-54e88160-babf-439c-9925-206611d29594
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579289740 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.2579289740
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.1886870328
Short name T96
Test name
Test status
Simulation time 60418625227 ps
CPU time 612.06 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:47:34 PM PDT 24
Peak memory 216416 kb
Host smart-9d9c94b6-812c-4ac6-8ada-0ca0f0d2b165
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886870328 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.1886870328
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.3621316042
Short name T845
Test name
Test status
Simulation time 10472577 ps
CPU time 0.56 seconds
Started Aug 02 05:35:38 PM PDT 24
Finished Aug 02 05:35:38 PM PDT 24
Peak memory 194168 kb
Host smart-c00aece7-2dda-4c2a-a689-d79defa18943
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621316042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.3621316042
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2317550654
Short name T1082
Test name
Test status
Simulation time 291210782352 ps
CPU time 112.7 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:37:19 PM PDT 24
Peak memory 199604 kb
Host smart-91f1607a-c459-4ba5-8709-da3735489ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317550654 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2317550654
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.3523543316
Short name T456
Test name
Test status
Simulation time 27420483512 ps
CPU time 12.54 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 199964 kb
Host smart-d8fc76bf-1c26-4b1a-8997-43e72d45e7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523543316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.3523543316
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_intr.3146968500
Short name T381
Test name
Test status
Simulation time 5761993248 ps
CPU time 2.38 seconds
Started Aug 02 05:35:20 PM PDT 24
Finished Aug 02 05:35:22 PM PDT 24
Peak memory 199496 kb
Host smart-45c1afeb-3087-409b-b34b-6cf5754e1ea5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146968500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.3146968500
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.3246605585
Short name T418
Test name
Test status
Simulation time 112908951522 ps
CPU time 408.74 seconds
Started Aug 02 05:35:28 PM PDT 24
Finished Aug 02 05:42:17 PM PDT 24
Peak memory 199984 kb
Host smart-7be7d272-410b-48c8-a775-81da4ac0b4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3246605585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.3246605585
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.102801707
Short name T1153
Test name
Test status
Simulation time 6244132264 ps
CPU time 7.89 seconds
Started Aug 02 05:35:29 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 199336 kb
Host smart-a88411d1-7bab-4df6-828f-cf6d00c36910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102801707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.102801707
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.1097181852
Short name T563
Test name
Test status
Simulation time 75572339184 ps
CPU time 70.69 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:36:31 PM PDT 24
Peak memory 200124 kb
Host smart-07d50164-5a6a-47fe-9d82-7928fa13397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097181852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.1097181852
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.2903952525
Short name T273
Test name
Test status
Simulation time 23285734333 ps
CPU time 245.29 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:39:39 PM PDT 24
Peak memory 199936 kb
Host smart-276e8bb9-b41e-4956-b104-7661f029d694
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903952525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.2903952525
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.277315245
Short name T909
Test name
Test status
Simulation time 6054078994 ps
CPU time 29.95 seconds
Started Aug 02 05:35:29 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 199032 kb
Host smart-1b0dd933-dd37-4266-8451-ea6438646bfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277315245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.277315245
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1414530177
Short name T1167
Test name
Test status
Simulation time 115623778178 ps
CPU time 110.72 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:37:27 PM PDT 24
Peak memory 200024 kb
Host smart-308396ee-b8b2-4586-a5ef-49c6c19f276c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414530177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1414530177
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.1301922052
Short name T955
Test name
Test status
Simulation time 2081909625 ps
CPU time 3.51 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:35:25 PM PDT 24
Peak memory 195488 kb
Host smart-4b57bd5c-076a-4fc2-8bbe-2c5f3cabe536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301922052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.1301922052
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3360825777
Short name T735
Test name
Test status
Simulation time 5883228534 ps
CPU time 17.67 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:59 PM PDT 24
Peak memory 199792 kb
Host smart-76fee540-c5b9-4944-a95a-d7855dc56774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360825777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3360825777
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.3312537005
Short name T609
Test name
Test status
Simulation time 29581612293 ps
CPU time 333.43 seconds
Started Aug 02 05:35:21 PM PDT 24
Finished Aug 02 05:40:55 PM PDT 24
Peak memory 216628 kb
Host smart-aeba905c-81e9-4c46-a875-04341f73f3f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312537005 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.3312537005
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.2810148125
Short name T1059
Test name
Test status
Simulation time 984950643 ps
CPU time 2.13 seconds
Started Aug 02 05:35:30 PM PDT 24
Finished Aug 02 05:35:32 PM PDT 24
Peak memory 198672 kb
Host smart-d34e83c8-2fb1-4453-b408-1580a085c7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810148125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.2810148125
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.630801762
Short name T699
Test name
Test status
Simulation time 40640328622 ps
CPU time 33.45 seconds
Started Aug 02 05:35:23 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 199988 kb
Host smart-fd4a1f6a-a838-4b69-86b8-b2e2ee008de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630801762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.630801762
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1140775521
Short name T199
Test name
Test status
Simulation time 18960240981 ps
CPU time 17.92 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:37:41 PM PDT 24
Peak memory 199928 kb
Host smart-6b3d98fd-41c5-4ce3-ae08-ebb8b24d499b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140775521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1140775521
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.3976089350
Short name T910
Test name
Test status
Simulation time 60281209452 ps
CPU time 942.16 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:53:04 PM PDT 24
Peak memory 216416 kb
Host smart-dffaf26d-038c-46db-a60b-3a5038ec9723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976089350 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.3976089350
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2660440346
Short name T441
Test name
Test status
Simulation time 65880000988 ps
CPU time 105.34 seconds
Started Aug 02 05:37:18 PM PDT 24
Finished Aug 02 05:39:03 PM PDT 24
Peak memory 199824 kb
Host smart-266b5d2e-143e-4a45-90a0-35801e9ff70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660440346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2660440346
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.2343984590
Short name T949
Test name
Test status
Simulation time 178000553530 ps
CPU time 267.71 seconds
Started Aug 02 05:37:18 PM PDT 24
Finished Aug 02 05:41:46 PM PDT 24
Peak memory 213100 kb
Host smart-787e3d25-142f-45e3-ba7e-3ad7711e2794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343984590 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.2343984590
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.2001011535
Short name T206
Test name
Test status
Simulation time 30558601692 ps
CPU time 47.68 seconds
Started Aug 02 05:37:19 PM PDT 24
Finished Aug 02 05:38:07 PM PDT 24
Peak memory 199772 kb
Host smart-5d4ae832-e7cd-4c61-97a7-49d901fd92ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001011535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.2001011535
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.1641861596
Short name T587
Test name
Test status
Simulation time 498246684125 ps
CPU time 708.37 seconds
Started Aug 02 05:37:16 PM PDT 24
Finished Aug 02 05:49:04 PM PDT 24
Peak memory 216424 kb
Host smart-aeb84fae-c080-4fdc-9c1f-6b2bf4b3571e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641861596 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.1641861596
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.3021174557
Short name T614
Test name
Test status
Simulation time 68923840435 ps
CPU time 30.35 seconds
Started Aug 02 05:37:17 PM PDT 24
Finished Aug 02 05:37:48 PM PDT 24
Peak memory 199884 kb
Host smart-ead286e5-e686-4425-830e-8968d1d52c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021174557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.3021174557
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.515627182
Short name T765
Test name
Test status
Simulation time 136014132127 ps
CPU time 421.71 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:44:24 PM PDT 24
Peak memory 215136 kb
Host smart-e5917fae-0774-4cd6-85e7-7a836133accc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515627182 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.515627182
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.2088842108
Short name T1159
Test name
Test status
Simulation time 144053295199 ps
CPU time 186.67 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:40:29 PM PDT 24
Peak memory 199976 kb
Host smart-bb3c0160-704e-4c5c-ba3f-948d114062f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088842108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.2088842108
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.599938652
Short name T840
Test name
Test status
Simulation time 31699330318 ps
CPU time 720.13 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:49:23 PM PDT 24
Peak memory 216544 kb
Host smart-9abf400e-4ae0-49f9-b6c7-e7f491a02051
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599938652 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.599938652
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.1955378736
Short name T33
Test name
Test status
Simulation time 67661444033 ps
CPU time 35.54 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:38:00 PM PDT 24
Peak memory 199924 kb
Host smart-0c031ce5-e81a-49d0-a6a0-e5dbff9146ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955378736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.1955378736
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.4243858718
Short name T921
Test name
Test status
Simulation time 106332467937 ps
CPU time 326.32 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:42:51 PM PDT 24
Peak memory 209424 kb
Host smart-1c4d3bf9-648a-4c38-8967-07c904344196
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243858718 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.4243858718
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.726880764
Short name T189
Test name
Test status
Simulation time 62739546511 ps
CPU time 26.67 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:37:52 PM PDT 24
Peak memory 199976 kb
Host smart-5fcb9d99-b699-41a1-ba59-925856f0235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726880764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.726880764
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.2012697238
Short name T1169
Test name
Test status
Simulation time 97368877456 ps
CPU time 847.32 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:51:31 PM PDT 24
Peak memory 216512 kb
Host smart-62cdc647-3c2c-4809-8162-04f4c1b2388f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012697238 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.2012697238
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.313325123
Short name T398
Test name
Test status
Simulation time 54643831857 ps
CPU time 109.05 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:39:13 PM PDT 24
Peak memory 199944 kb
Host smart-f54e5f2b-7d0c-40f8-b192-b4f9f5652578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313325123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.313325123
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.2441334189
Short name T538
Test name
Test status
Simulation time 143695936816 ps
CPU time 672.47 seconds
Started Aug 02 05:37:27 PM PDT 24
Finished Aug 02 05:48:40 PM PDT 24
Peak memory 216292 kb
Host smart-553195a0-9b3c-443d-8649-c1f7d07a4a3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441334189 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.2441334189
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.1946302233
Short name T986
Test name
Test status
Simulation time 230220836280 ps
CPU time 27.51 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:37:53 PM PDT 24
Peak memory 199940 kb
Host smart-0e5631c6-30c4-4636-a9c4-3cdce6a02169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946302233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.1946302233
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.209380179
Short name T710
Test name
Test status
Simulation time 49455069049 ps
CPU time 784.52 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:50:28 PM PDT 24
Peak memory 216532 kb
Host smart-c74a5432-c9dd-4e43-bb13-81f29192492b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209380179 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.209380179
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2516794155
Short name T341
Test name
Test status
Simulation time 16294162 ps
CPU time 0.54 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 195048 kb
Host smart-729af3f8-605d-4dc2-bd31-1a1ecc38e65b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516794155 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2516794155
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.3825928968
Short name T142
Test name
Test status
Simulation time 91087973979 ps
CPU time 68.77 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:36:44 PM PDT 24
Peak memory 199952 kb
Host smart-df506acb-91bb-47ec-b201-bc7426702b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825928968 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.3825928968
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.2833225199
Short name T1110
Test name
Test status
Simulation time 273209013480 ps
CPU time 332.88 seconds
Started Aug 02 05:35:49 PM PDT 24
Finished Aug 02 05:41:22 PM PDT 24
Peak memory 199780 kb
Host smart-8c4b89d4-89b0-49c5-9d67-0df730909b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833225199 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.2833225199
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.1253189797
Short name T505
Test name
Test status
Simulation time 129336609083 ps
CPU time 246.75 seconds
Started Aug 02 05:35:27 PM PDT 24
Finished Aug 02 05:39:34 PM PDT 24
Peak memory 199988 kb
Host smart-99a7a512-99bb-4481-ac8e-7ca54ace3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253189797 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.1253189797
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.713899938
Short name T1027
Test name
Test status
Simulation time 265797839307 ps
CPU time 110.42 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:37:30 PM PDT 24
Peak memory 199980 kb
Host smart-d8ec0f61-ecf0-40f1-934c-d344ec2cd209
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713899938 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.713899938
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.1178174042
Short name T389
Test name
Test status
Simulation time 274524021668 ps
CPU time 300.92 seconds
Started Aug 02 05:35:45 PM PDT 24
Finished Aug 02 05:40:46 PM PDT 24
Peak memory 199920 kb
Host smart-eb240001-5b69-4b84-8875-def717e90ba4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178174042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.1178174042
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2635072150
Short name T364
Test name
Test status
Simulation time 4211734332 ps
CPU time 4.81 seconds
Started Aug 02 05:35:38 PM PDT 24
Finished Aug 02 05:35:43 PM PDT 24
Peak memory 199440 kb
Host smart-e82750b1-f7dc-4e9f-8a25-661ebc757e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635072150 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2635072150
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.993625542
Short name T479
Test name
Test status
Simulation time 11419581735 ps
CPU time 11.78 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:35:56 PM PDT 24
Peak memory 199912 kb
Host smart-7b917b6d-25eb-49c4-b18d-ddae042a06f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993625542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.993625542
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.4237364281
Short name T767
Test name
Test status
Simulation time 10239872974 ps
CPU time 306.33 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:40:43 PM PDT 24
Peak memory 199864 kb
Host smart-a6352271-3096-4749-a8d4-3875af5b8baa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4237364281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.4237364281
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.568710160
Short name T1162
Test name
Test status
Simulation time 7125328911 ps
CPU time 32.33 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:36:07 PM PDT 24
Peak memory 199072 kb
Host smart-3e7f0208-6285-4401-9d04-9da8d06c47ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=568710160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.568710160
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.1877740153
Short name T244
Test name
Test status
Simulation time 106161789887 ps
CPU time 35.7 seconds
Started Aug 02 05:35:28 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 199968 kb
Host smart-45effd5d-6e13-4a51-9f04-5b0ffec2a34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877740153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.1877740153
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.3506323228
Short name T250
Test name
Test status
Simulation time 1988206252 ps
CPU time 3.32 seconds
Started Aug 02 05:35:58 PM PDT 24
Finished Aug 02 05:36:02 PM PDT 24
Peak memory 195460 kb
Host smart-6c9fe007-6b1d-4aab-af0e-ff7b29983c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506323228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.3506323228
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.2251020732
Short name T528
Test name
Test status
Simulation time 454585495 ps
CPU time 1.8 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 198208 kb
Host smart-840e568f-0ed9-44da-9f04-8c06cb7b893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251020732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.2251020732
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.2458684724
Short name T559
Test name
Test status
Simulation time 113499354652 ps
CPU time 44.98 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:36:16 PM PDT 24
Peak memory 199808 kb
Host smart-2e281b2e-3c26-4cb0-8fad-ad798b20b0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458684724 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.2458684724
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2170860418
Short name T648
Test name
Test status
Simulation time 82846221585 ps
CPU time 1487.99 seconds
Started Aug 02 05:35:29 PM PDT 24
Finished Aug 02 06:00:18 PM PDT 24
Peak memory 216528 kb
Host smart-74d959c9-dcbc-47aa-b938-95e2873d05e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170860418 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2170860418
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.782944168
Short name T682
Test name
Test status
Simulation time 1347208694 ps
CPU time 2.33 seconds
Started Aug 02 05:35:40 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 198960 kb
Host smart-9b3c2329-de27-466a-bff7-86cb8c7ffee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782944168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.782944168
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3835570277
Short name T661
Test name
Test status
Simulation time 26854666734 ps
CPU time 10.63 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:35:45 PM PDT 24
Peak memory 199600 kb
Host smart-251d0b62-8952-4c2c-9f1d-305d042e10d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835570277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3835570277
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.799904454
Short name T782
Test name
Test status
Simulation time 51861441108 ps
CPU time 26.25 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:37:50 PM PDT 24
Peak memory 199728 kb
Host smart-6a8d4930-3f44-41bd-8151-60ba807c5880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799904454 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.799904454
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.430445210
Short name T854
Test name
Test status
Simulation time 56630324116 ps
CPU time 189.95 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:40:33 PM PDT 24
Peak memory 215956 kb
Host smart-4619b9d0-1a89-4503-93de-4c83c943c1c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430445210 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.430445210
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.4211266811
Short name T404
Test name
Test status
Simulation time 49393823251 ps
CPU time 217.92 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:41:10 PM PDT 24
Peak memory 199980 kb
Host smart-7a2f07ac-0ac9-4e72-8614-97d356f2a510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211266811 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.4211266811
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3602594531
Short name T814
Test name
Test status
Simulation time 18508096678 ps
CPU time 179.19 seconds
Started Aug 02 05:37:23 PM PDT 24
Finished Aug 02 05:40:23 PM PDT 24
Peak memory 215524 kb
Host smart-ba714508-ce44-43ab-9185-c998edae36de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602594531 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3602594531
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.667479701
Short name T172
Test name
Test status
Simulation time 22390846144 ps
CPU time 47.03 seconds
Started Aug 02 05:37:27 PM PDT 24
Finished Aug 02 05:38:14 PM PDT 24
Peak memory 199892 kb
Host smart-9d4d49d5-e24a-4070-9845-b333537fe8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667479701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.667479701
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.384270813
Short name T931
Test name
Test status
Simulation time 132053559926 ps
CPU time 562.14 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:46:46 PM PDT 24
Peak memory 213812 kb
Host smart-f574ceba-a1ea-4b1c-a0a2-4c52369fbd56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384270813 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.384270813
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.2972097028
Short name T727
Test name
Test status
Simulation time 115190717998 ps
CPU time 202.41 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:40:48 PM PDT 24
Peak memory 199984 kb
Host smart-bd101686-4d0f-454b-a1a4-1af4c4abc798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972097028 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.2972097028
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.721792167
Short name T155
Test name
Test status
Simulation time 99452308072 ps
CPU time 623.23 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:47:49 PM PDT 24
Peak memory 216652 kb
Host smart-eb66d285-5b37-457f-9918-76223b6c26e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721792167 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.721792167
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.3405586717
Short name T1077
Test name
Test status
Simulation time 136423334375 ps
CPU time 228.02 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:41:14 PM PDT 24
Peak memory 199956 kb
Host smart-f010519b-60d9-4741-a40c-b35cf7967491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405586717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.3405586717
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.1577841069
Short name T914
Test name
Test status
Simulation time 81458906282 ps
CPU time 1206.92 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:57:31 PM PDT 24
Peak memory 216636 kb
Host smart-ad1e01f3-c904-4b54-9f55-747ae7e7733d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577841069 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.1577841069
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.3290264305
Short name T198
Test name
Test status
Simulation time 25007120062 ps
CPU time 48.7 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:38:14 PM PDT 24
Peak memory 200008 kb
Host smart-c14cda60-4af9-42a8-9af2-8bd72b9266f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290264305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.3290264305
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.2507146135
Short name T529
Test name
Test status
Simulation time 25708194482 ps
CPU time 289.07 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:42:14 PM PDT 24
Peak memory 215740 kb
Host smart-3fe0647f-de06-4765-bb31-67ebd789ce1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507146135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.2507146135
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.161476788
Short name T837
Test name
Test status
Simulation time 114688285104 ps
CPU time 40.92 seconds
Started Aug 02 05:37:22 PM PDT 24
Finished Aug 02 05:38:03 PM PDT 24
Peak memory 200024 kb
Host smart-709f168c-6525-46ab-984e-ed256aacfa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161476788 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.161476788
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3778212158
Short name T60
Test name
Test status
Simulation time 65386647437 ps
CPU time 260.88 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:41:45 PM PDT 24
Peak memory 210896 kb
Host smart-9b5851ab-e054-482b-90ec-ec53cd415931
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778212158 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3778212158
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.1790161437
Short name T462
Test name
Test status
Simulation time 11026001019 ps
CPU time 7.55 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:37:33 PM PDT 24
Peak memory 199964 kb
Host smart-2fc2971c-47de-4640-af36-d49671183895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790161437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.1790161437
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.3184539731
Short name T724
Test name
Test status
Simulation time 64148453420 ps
CPU time 414.62 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:44:21 PM PDT 24
Peak memory 216304 kb
Host smart-c4c37bd9-ce34-44d6-9bf3-be87587b82d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184539731 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.3184539731
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.1612147949
Short name T216
Test name
Test status
Simulation time 150884210266 ps
CPU time 333.98 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:43:00 PM PDT 24
Peak memory 200008 kb
Host smart-a007a85d-f380-45d8-b88e-332739f30a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612147949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.1612147949
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.2432948280
Short name T593
Test name
Test status
Simulation time 88672028974 ps
CPU time 293.26 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:42:19 PM PDT 24
Peak memory 216452 kb
Host smart-592a626a-9c23-4fc3-9aea-8a43826b9656
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432948280 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.2432948280
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.771963114
Short name T1003
Test name
Test status
Simulation time 33113180714 ps
CPU time 53.47 seconds
Started Aug 02 05:37:27 PM PDT 24
Finished Aug 02 05:38:21 PM PDT 24
Peak memory 199984 kb
Host smart-f45a3f90-dcae-4d19-baeb-63101c3e78ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771963114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.771963114
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2700162663
Short name T952
Test name
Test status
Simulation time 43242992228 ps
CPU time 363.49 seconds
Started Aug 02 05:37:26 PM PDT 24
Finished Aug 02 05:43:30 PM PDT 24
Peak memory 215608 kb
Host smart-3ee6c6e4-f405-4c6b-87e7-01f6d5f6aca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700162663 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2700162663
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.3040732607
Short name T23
Test name
Test status
Simulation time 32428332 ps
CPU time 0.54 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 195396 kb
Host smart-8d62debd-6491-4a83-99f9-d7907e8d0492
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040732607 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.3040732607
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.2942400543
Short name T675
Test name
Test status
Simulation time 185909896057 ps
CPU time 319.87 seconds
Started Aug 02 05:35:43 PM PDT 24
Finished Aug 02 05:41:03 PM PDT 24
Peak memory 199916 kb
Host smart-2d7956ea-b1eb-47d5-bd2b-ac0367660012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942400543 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.2942400543
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.3679522575
Short name T249
Test name
Test status
Simulation time 17419656907 ps
CPU time 7.31 seconds
Started Aug 02 05:35:38 PM PDT 24
Finished Aug 02 05:35:45 PM PDT 24
Peak memory 198440 kb
Host smart-00038541-7e3a-431a-8b36-c5885aa775a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679522575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.3679522575
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.4086085226
Short name T536
Test name
Test status
Simulation time 41575982865 ps
CPU time 65.61 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:36:53 PM PDT 24
Peak memory 199912 kb
Host smart-a978a6d1-93e0-45e3-af57-3dc519181564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086085226 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.4086085226
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.2369588936
Short name T89
Test name
Test status
Simulation time 28625564699 ps
CPU time 7.63 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 200024 kb
Host smart-6dadf921-5539-45e7-888c-d9b8c00825b3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369588936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.2369588936
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2902825701
Short name T697
Test name
Test status
Simulation time 75490458416 ps
CPU time 453.17 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:43:08 PM PDT 24
Peak memory 199960 kb
Host smart-d1dd474e-1055-4e4e-a53e-76f31faea38e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902825701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2902825701
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.1243928439
Short name T615
Test name
Test status
Simulation time 3432676615 ps
CPU time 2.86 seconds
Started Aug 02 05:35:41 PM PDT 24
Finished Aug 02 05:35:45 PM PDT 24
Peak memory 199940 kb
Host smart-3c6fed72-4841-435c-994f-ff1d52fdb11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243928439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.1243928439
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.1159947290
Short name T280
Test name
Test status
Simulation time 46857819148 ps
CPU time 70.67 seconds
Started Aug 02 05:35:46 PM PDT 24
Finished Aug 02 05:36:57 PM PDT 24
Peak memory 199972 kb
Host smart-4883c634-559f-40a3-b451-29f868395ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159947290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.1159947290
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.2977970888
Short name T372
Test name
Test status
Simulation time 10844619862 ps
CPU time 158.91 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:38:16 PM PDT 24
Peak memory 199964 kb
Host smart-ba7fdd05-c55f-4aac-a771-28505957f968
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2977970888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.2977970888
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2707695021
Short name T504
Test name
Test status
Simulation time 2069474553 ps
CPU time 8.03 seconds
Started Aug 02 05:36:01 PM PDT 24
Finished Aug 02 05:36:09 PM PDT 24
Peak memory 198084 kb
Host smart-12535a38-a2ca-40e7-b10d-970db2beb456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707695021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2707695021
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2753869058
Short name T820
Test name
Test status
Simulation time 142326294120 ps
CPU time 53.33 seconds
Started Aug 02 05:35:59 PM PDT 24
Finished Aug 02 05:36:52 PM PDT 24
Peak memory 199748 kb
Host smart-34c94005-395a-4917-8b5d-a02f57e57a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753869058 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2753869058
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.222575632
Short name T975
Test name
Test status
Simulation time 5704422243 ps
CPU time 2.89 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:35:40 PM PDT 24
Peak memory 196284 kb
Host smart-1ae1111e-9627-4188-aa6c-7c502365fbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222575632 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.222575632
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.728830739
Short name T1022
Test name
Test status
Simulation time 737163647 ps
CPU time 2.52 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 199836 kb
Host smart-008b2489-daa5-4710-b027-dcad59765433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728830739 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.728830739
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3549764950
Short name T1073
Test name
Test status
Simulation time 144659094812 ps
CPU time 934.66 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:51:14 PM PDT 24
Peak memory 200020 kb
Host smart-aeb49343-191e-4ca4-9e78-33c12bfc9917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549764950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3549764950
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3779440956
Short name T414
Test name
Test status
Simulation time 924953076 ps
CPU time 2.52 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:35:37 PM PDT 24
Peak memory 199836 kb
Host smart-18d6699a-3a0a-4eea-8eca-370ccc1bb59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779440956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3779440956
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3444072363
Short name T283
Test name
Test status
Simulation time 73147483588 ps
CPU time 44.49 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:36:29 PM PDT 24
Peak memory 200008 kb
Host smart-1d28fb97-8cd6-4678-aec6-b249dbfb86b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444072363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3444072363
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.4112921379
Short name T849
Test name
Test status
Simulation time 307205552191 ps
CPU time 34.07 seconds
Started Aug 02 05:37:24 PM PDT 24
Finished Aug 02 05:37:58 PM PDT 24
Peak memory 199988 kb
Host smart-65362a07-ebfe-4335-b64d-139661abedf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112921379 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.4112921379
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.1223241338
Short name T688
Test name
Test status
Simulation time 300938339263 ps
CPU time 406.89 seconds
Started Aug 02 05:37:25 PM PDT 24
Finished Aug 02 05:44:12 PM PDT 24
Peak memory 216680 kb
Host smart-d7847af9-ff7f-43ac-8c06-98da89eac0c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223241338 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.1223241338
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.468861585
Short name T409
Test name
Test status
Simulation time 9749633993 ps
CPU time 16.84 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:37:52 PM PDT 24
Peak memory 199952 kb
Host smart-6b8332c0-29af-4c43-88dd-7e348500273f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468861585 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.468861585
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.2548929821
Short name T922
Test name
Test status
Simulation time 168421195125 ps
CPU time 875.06 seconds
Started Aug 02 05:37:37 PM PDT 24
Finished Aug 02 05:52:12 PM PDT 24
Peak memory 216648 kb
Host smart-aeebf867-549c-4b30-8796-8031e4f712de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548929821 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.2548929821
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.148181398
Short name T279
Test name
Test status
Simulation time 15417523592 ps
CPU time 25.72 seconds
Started Aug 02 05:37:36 PM PDT 24
Finished Aug 02 05:38:01 PM PDT 24
Peak memory 199960 kb
Host smart-aac7f35c-355c-4dd2-bc0f-e1eb5e83d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148181398 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.148181398
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.2485242824
Short name T313
Test name
Test status
Simulation time 114783546517 ps
CPU time 657.79 seconds
Started Aug 02 05:37:34 PM PDT 24
Finished Aug 02 05:48:32 PM PDT 24
Peak memory 216484 kb
Host smart-20cb2c44-4b27-41a6-a55e-01c1ecc45881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485242824 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.2485242824
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.1467840193
Short name T168
Test name
Test status
Simulation time 27703028855 ps
CPU time 21.34 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:37:54 PM PDT 24
Peak memory 198740 kb
Host smart-8bd2c646-7cb7-4351-bdd6-a48cc517e1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467840193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.1467840193
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.597393009
Short name T918
Test name
Test status
Simulation time 55538839760 ps
CPU time 910.05 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:52:43 PM PDT 24
Peak memory 216644 kb
Host smart-5ecbf5ab-aa06-47b7-81e3-76792168f947
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597393009 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.597393009
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.3687677881
Short name T811
Test name
Test status
Simulation time 91861798064 ps
CPU time 17.58 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:37:53 PM PDT 24
Peak memory 199988 kb
Host smart-0d17488c-0574-4433-8696-c2f9b952499d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687677881 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.3687677881
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.972059335
Short name T771
Test name
Test status
Simulation time 70384904113 ps
CPU time 835.18 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:51:30 PM PDT 24
Peak memory 230288 kb
Host smart-3d3984d8-a034-461b-bd4c-e5758b0845fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972059335 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.972059335
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.1048855953
Short name T1163
Test name
Test status
Simulation time 116297620171 ps
CPU time 155.62 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:40:11 PM PDT 24
Peak memory 199916 kb
Host smart-bda5762a-d9df-4a75-9145-4071e216a61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048855953 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.1048855953
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3908305191
Short name T741
Test name
Test status
Simulation time 16612910585 ps
CPU time 163.28 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:40:18 PM PDT 24
Peak memory 216508 kb
Host smart-8cf66e69-5504-4ac4-bbd9-e8b5ad56b1d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908305191 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3908305191
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.215341024
Short name T680
Test name
Test status
Simulation time 115243035825 ps
CPU time 44.03 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 199980 kb
Host smart-7a502f02-9828-4fd8-b3cf-889ed64b9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215341024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.215341024
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2703329889
Short name T37
Test name
Test status
Simulation time 133956397356 ps
CPU time 1328.06 seconds
Started Aug 02 05:37:37 PM PDT 24
Finished Aug 02 05:59:45 PM PDT 24
Peak memory 224648 kb
Host smart-eb4c609f-d04a-4144-bf77-7d595e6bc917
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703329889 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2703329889
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2017125694
Short name T893
Test name
Test status
Simulation time 51213983128 ps
CPU time 23.05 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:37:58 PM PDT 24
Peak memory 199928 kb
Host smart-1d8cc4d4-bc2a-484d-84d9-a0ce5ed727bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017125694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2017125694
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1838714303
Short name T573
Test name
Test status
Simulation time 75843488626 ps
CPU time 473.74 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:45:26 PM PDT 24
Peak memory 216604 kb
Host smart-02d731ad-f00f-49de-bd4b-0d667cd2cd9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838714303 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1838714303
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.3577986004
Short name T938
Test name
Test status
Simulation time 113145996344 ps
CPU time 44.67 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:38:20 PM PDT 24
Peak memory 200008 kb
Host smart-497a1120-4dcc-476a-bb01-8fcb36052f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577986004 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.3577986004
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.483687037
Short name T991
Test name
Test status
Simulation time 96853939541 ps
CPU time 129.16 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:39:42 PM PDT 24
Peak memory 216244 kb
Host smart-b09e1197-6cbd-4432-87ee-754bcd73075b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483687037 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.483687037
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.3888223417
Short name T218
Test name
Test status
Simulation time 185455251657 ps
CPU time 18.13 seconds
Started Aug 02 05:37:36 PM PDT 24
Finished Aug 02 05:37:54 PM PDT 24
Peak memory 199908 kb
Host smart-842cd97d-aa1f-483a-86b0-5dd6cb880f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888223417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.3888223417
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.494786094
Short name T1007
Test name
Test status
Simulation time 908252400525 ps
CPU time 775.7 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:50:29 PM PDT 24
Peak memory 230240 kb
Host smart-2c3e831e-3c28-48f0-9c8e-cccb1e5bf47b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494786094 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.494786094
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_fifo_full.3331985363
Short name T459
Test name
Test status
Simulation time 129606958990 ps
CPU time 294.25 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:40:26 PM PDT 24
Peak memory 199932 kb
Host smart-2b693bd6-c68d-4e6b-be3a-36056d5cb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331985363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.3331985363
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3954620047
Short name T420
Test name
Test status
Simulation time 24791669654 ps
CPU time 26.89 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:36:06 PM PDT 24
Peak memory 199956 kb
Host smart-5c7b2fab-b80a-407a-bca7-8098727a742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954620047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3954620047
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.464565869
Short name T391
Test name
Test status
Simulation time 15321239601 ps
CPU time 24.75 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:36:01 PM PDT 24
Peak memory 200012 kb
Host smart-f334fb9a-e2d7-4a08-9f06-8169d9fd87e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464565869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.464565869
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.3489265071
Short name T292
Test name
Test status
Simulation time 30058555422 ps
CPU time 14.92 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:35:46 PM PDT 24
Peak memory 199964 kb
Host smart-4abf6d03-677b-4e03-8110-74ad20b6ae11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489265071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.3489265071
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2457542206
Short name T781
Test name
Test status
Simulation time 354683627209 ps
CPU time 650.87 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:46:25 PM PDT 24
Peak memory 199912 kb
Host smart-224c7f32-61ed-4fa0-8118-8aaf10193ce2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457542206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2457542206
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.2155848619
Short name T799
Test name
Test status
Simulation time 10900878361 ps
CPU time 19.17 seconds
Started Aug 02 05:35:34 PM PDT 24
Finished Aug 02 05:35:53 PM PDT 24
Peak memory 200036 kb
Host smart-0089b59e-ec44-4c23-9403-32594ba1d103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155848619 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.2155848619
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.754377563
Short name T647
Test name
Test status
Simulation time 36376349689 ps
CPU time 13.71 seconds
Started Aug 02 05:35:39 PM PDT 24
Finished Aug 02 05:35:53 PM PDT 24
Peak memory 199928 kb
Host smart-33dd6000-6021-44cb-82d0-e3b9a89dc5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754377563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.754377563
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.751710835
Short name T537
Test name
Test status
Simulation time 17282527998 ps
CPU time 752.02 seconds
Started Aug 02 05:35:33 PM PDT 24
Finished Aug 02 05:48:05 PM PDT 24
Peak memory 199924 kb
Host smart-32237f4e-8997-40a0-af1f-ac9663bc430b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=751710835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.751710835
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.2446918518
Short name T17
Test name
Test status
Simulation time 3107954558 ps
CPU time 3.59 seconds
Started Aug 02 05:36:02 PM PDT 24
Finished Aug 02 05:36:05 PM PDT 24
Peak memory 198848 kb
Host smart-ddf3fae6-c01c-44bb-9e61-cdc99da41c07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446918518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.2446918518
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.469401012
Short name T900
Test name
Test status
Simulation time 19001126574 ps
CPU time 25.21 seconds
Started Aug 02 05:35:35 PM PDT 24
Finished Aug 02 05:36:00 PM PDT 24
Peak memory 200000 kb
Host smart-f50ae9e0-c5f3-4a51-93ad-456d14df72e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469401012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.469401012
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.1255814259
Short name T416
Test name
Test status
Simulation time 2542229758 ps
CPU time 1.56 seconds
Started Aug 02 05:35:36 PM PDT 24
Finished Aug 02 05:35:42 PM PDT 24
Peak memory 196524 kb
Host smart-ec968f6b-baf2-43bd-afca-779887635ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255814259 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.1255814259
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.3208674236
Short name T632
Test name
Test status
Simulation time 931603866 ps
CPU time 3.91 seconds
Started Aug 02 05:35:44 PM PDT 24
Finished Aug 02 05:35:48 PM PDT 24
Peak memory 198916 kb
Host smart-703ac554-1500-448d-8d00-1885c335ab90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208674236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.3208674236
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.2326440438
Short name T258
Test name
Test status
Simulation time 47706601581 ps
CPU time 197.9 seconds
Started Aug 02 05:35:31 PM PDT 24
Finished Aug 02 05:38:50 PM PDT 24
Peak memory 200012 kb
Host smart-92c09330-3f60-43a9-b49f-6438c450a172
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326440438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.2326440438
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2025840248
Short name T974
Test name
Test status
Simulation time 65492400452 ps
CPU time 1011.53 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:52:28 PM PDT 24
Peak memory 216424 kb
Host smart-d8090e86-8d7a-4517-a2b1-1b6b31ca6566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025840248 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2025840248
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.35784341
Short name T886
Test name
Test status
Simulation time 1118441888 ps
CPU time 2.69 seconds
Started Aug 02 05:35:47 PM PDT 24
Finished Aug 02 05:35:50 PM PDT 24
Peak memory 198400 kb
Host smart-0d1436c8-ee7b-493c-bfb7-fbbaf8686a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35784341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.35784341
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.2303973662
Short name T731
Test name
Test status
Simulation time 35573103195 ps
CPU time 13.91 seconds
Started Aug 02 05:35:37 PM PDT 24
Finished Aug 02 05:35:51 PM PDT 24
Peak memory 199776 kb
Host smart-2e31a289-ea0c-4c27-a363-adc827066bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303973662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.2303973662
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.2650286712
Short name T240
Test name
Test status
Simulation time 39219920487 ps
CPU time 60.26 seconds
Started Aug 02 05:37:37 PM PDT 24
Finished Aug 02 05:38:37 PM PDT 24
Peak memory 199924 kb
Host smart-6aa7a3e9-e8e0-4a6f-9279-1213f283196b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650286712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.2650286712
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.246411447
Short name T305
Test name
Test status
Simulation time 192904109077 ps
CPU time 51.19 seconds
Started Aug 02 05:37:37 PM PDT 24
Finished Aug 02 05:38:28 PM PDT 24
Peak memory 199916 kb
Host smart-8f235da8-b312-4421-ad93-132264fe3553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246411447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.246411447
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1942711904
Short name T961
Test name
Test status
Simulation time 152079488714 ps
CPU time 1351.58 seconds
Started Aug 02 05:37:34 PM PDT 24
Finished Aug 02 06:00:06 PM PDT 24
Peak memory 216560 kb
Host smart-2a02093c-61f4-45c0-9cb9-c968e4ccd517
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942711904 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1942711904
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.1462405442
Short name T214
Test name
Test status
Simulation time 76246771529 ps
CPU time 104.25 seconds
Started Aug 02 05:37:34 PM PDT 24
Finished Aug 02 05:39:19 PM PDT 24
Peak memory 199892 kb
Host smart-fbfb05af-ddd1-44e1-a866-859278aefa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462405442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.1462405442
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.3787557553
Short name T997
Test name
Test status
Simulation time 53466692186 ps
CPU time 247.92 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:41:40 PM PDT 24
Peak memory 216264 kb
Host smart-c38e2afd-0ab1-4c4a-a66e-9f7df15bf606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787557553 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.3787557553
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.2096310280
Short name T1117
Test name
Test status
Simulation time 65900878512 ps
CPU time 111.43 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:39:27 PM PDT 24
Peak memory 199968 kb
Host smart-a1b4c355-a9e2-46a8-8441-70e62650267f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096310280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.2096310280
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1789449077
Short name T99
Test name
Test status
Simulation time 44990945256 ps
CPU time 223.78 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:41:16 PM PDT 24
Peak memory 216592 kb
Host smart-15060714-607e-4238-9a91-ba986c3bc465
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789449077 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1789449077
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.1417120626
Short name T1023
Test name
Test status
Simulation time 26009299559 ps
CPU time 22.17 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:37:55 PM PDT 24
Peak memory 199788 kb
Host smart-97ad7858-3157-4837-a688-e561cc6ddab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417120626 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.1417120626
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.2377091802
Short name T846
Test name
Test status
Simulation time 11570942560 ps
CPU time 132.47 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:39:48 PM PDT 24
Peak memory 208388 kb
Host smart-a62f1f16-5b01-4321-b32d-65ab2d14528b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377091802 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.2377091802
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.177443551
Short name T187
Test name
Test status
Simulation time 122857902817 ps
CPU time 191.43 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:40:44 PM PDT 24
Peak memory 199912 kb
Host smart-d3a036e3-bf16-4039-8e3c-670435f40182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177443551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.177443551
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.2353889096
Short name T95
Test name
Test status
Simulation time 57974400805 ps
CPU time 111.81 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:39:25 PM PDT 24
Peak memory 212488 kb
Host smart-55112df5-4feb-478b-a316-8725957ee218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353889096 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.2353889096
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3790851157
Short name T1041
Test name
Test status
Simulation time 20009369452 ps
CPU time 35.87 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:38:08 PM PDT 24
Peak memory 199760 kb
Host smart-4f95c847-4930-4706-90c9-186669b11d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790851157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3790851157
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.4183040429
Short name T517
Test name
Test status
Simulation time 54866145513 ps
CPU time 650.57 seconds
Started Aug 02 05:37:32 PM PDT 24
Finished Aug 02 05:48:23 PM PDT 24
Peak memory 216508 kb
Host smart-3d80cf92-2839-4697-aaae-935a55597ea9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183040429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.4183040429
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.106912948
Short name T960
Test name
Test status
Simulation time 142339694914 ps
CPU time 42.2 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:38:17 PM PDT 24
Peak memory 200012 kb
Host smart-e4e8ce1e-fa88-4b9d-b667-13d99baa5ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106912948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.106912948
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.2393683297
Short name T736
Test name
Test status
Simulation time 181150171445 ps
CPU time 1200.99 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:57:34 PM PDT 24
Peak memory 216532 kb
Host smart-65dc0630-2cc3-4c62-aca1-3a0e9c582161
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393683297 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.2393683297
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.60921996
Short name T557
Test name
Test status
Simulation time 75975562334 ps
CPU time 32.08 seconds
Started Aug 02 05:37:33 PM PDT 24
Finished Aug 02 05:38:05 PM PDT 24
Peak memory 200032 kb
Host smart-faba20bc-42bd-475f-ae54-baf7c958773c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60921996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.60921996
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/98.uart_stress_all_with_rand_reset.3646577774
Short name T94
Test name
Test status
Simulation time 118843774422 ps
CPU time 270.02 seconds
Started Aug 02 05:37:34 PM PDT 24
Finished Aug 02 05:42:04 PM PDT 24
Peak memory 214428 kb
Host smart-c52660c1-5bea-4352-bf22-c9e8175c6490
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646577774 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 98.uart_stress_all_with_rand_reset.3646577774
Directory /workspace/98.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1484306430
Short name T1081
Test name
Test status
Simulation time 32082937362 ps
CPU time 43.87 seconds
Started Aug 02 05:37:35 PM PDT 24
Finished Aug 02 05:38:19 PM PDT 24
Peak memory 199980 kb
Host smart-9a6e2513-13be-47b1-b403-f016f0684839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484306430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1484306430
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.3111615690
Short name T1037
Test name
Test status
Simulation time 384723868909 ps
CPU time 542.55 seconds
Started Aug 02 05:37:36 PM PDT 24
Finished Aug 02 05:46:39 PM PDT 24
Peak memory 216576 kb
Host smart-1e99092f-7592-4e50-95e1-68277f69dc13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111615690 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.3111615690
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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