Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	108071	1			T1	174		T2	40		T3	36
all_values[1]	108071	1			T1	174		T2	40		T3	36
all_values[2]	108071	1			T1	174		T2	40		T3	36
all_values[3]	108071	1			T1	174		T2	40		T3	36
all_values[4]	108071	1			T1	174		T2	40		T3	36
all_values[5]	108071	1			T1	174		T2	40		T3	36
all_values[6]	108071	1			T1	174		T2	40		T3	36
all_values[7]	108071	1			T1	174		T2	40		T3	36
all_values[8]	108071	1			T1	174		T2	40		T3	36

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

489177

1

T1

856

T2

193

T3

182

auto[1]

483462

1

T1

710

T2

167

T3

142

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

879667

1

T1

1489

T2

275

T3

278

auto[1]

92972

1

T1

77

T2

85

T3

46

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	30359	1			T1	143		T6	7		T12	2
all_values[0]	auto[0]	auto[1]	23702	1			T1	2		T2	17		T3	4
all_values[0]	auto[1]	auto[0]	32209	1			T2	13		T3	11		T6	11
all_values[0]	auto[1]	auto[1]	21801	1			T1	29		T2	10		T3	21
all_values[1]	auto[0]	auto[0]	54587	1			T1	45		T2	17		T3	2
all_values[1]	auto[0]	auto[1]	1564	1			T1	12		T2	15		T13	10
all_values[1]	auto[1]	auto[0]	50209	1			T1	117		T2	8		T3	34
all_values[1]	auto[1]	auto[1]	1711	1			T13	10		T107	5		T18	1
all_values[2]	auto[0]	auto[0]	52484	1			T1	130		T2	18		T3	30
all_values[2]	auto[0]	auto[1]	2896	1			T1	1		T2	6		T3	2
all_values[2]	auto[1]	auto[0]	50191	1			T1	41		T2	11		T3	3
all_values[2]	auto[1]	auto[1]	2500	1			T1	2		T2	5		T3	1
all_values[3]	auto[0]	auto[0]	54961	1			T1	148		T2	23		T3	4
all_values[3]	auto[0]	auto[1]	315	1			T16	1		T18	1		T36	6
all_values[3]	auto[1]	auto[0]	52521	1			T1	26		T2	17		T3	32
all_values[3]	auto[1]	auto[1]	274	1			T15	2		T16	2		T18	3
all_values[4]	auto[0]	auto[0]	52515	1			T1	132		T2	24		T3	34
all_values[4]	auto[0]	auto[1]	433	1			T240	1		T20	8		T21	14
all_values[4]	auto[1]	auto[0]	54675	1			T1	42		T2	16		T3	2
all_values[4]	auto[1]	auto[1]	448	1			T18	1		T20	1		T21	12
all_values[5]	auto[0]	auto[0]	52064	1			T1	69		T2	32		T3	6
all_values[5]	auto[0]	auto[1]	186	1			T18	2		T20	3		T29	1
all_values[5]	auto[1]	auto[0]	55643	1			T1	105		T2	8		T3	30
all_values[5]	auto[1]	auto[1]	178	1			T18	1		T36	4		T38	2
all_values[6]	auto[0]	auto[0]	54542	1			T1	64		T3	32		T4	22
all_values[6]	auto[0]	auto[1]	162	1			T20	2		T36	3		T38	3
all_values[6]	auto[1]	auto[0]	53221	1			T1	110		T2	40		T3	4
all_values[6]	auto[1]	auto[1]	146	1			T20	2		T29	1		T36	3
all_values[7]	auto[0]	auto[0]	52361	1			T1	43		T2	35		T3	34
all_values[7]	auto[0]	auto[1]	339	1			T2	5		T16	2		T18	3
all_values[7]	auto[1]	auto[0]	54974	1			T1	131		T3	2		T6	8
all_values[7]	auto[1]	auto[1]	397	1			T15	2		T18	1		T85	3
all_values[8]	auto[0]	auto[0]	38249	1			T1	52		T3	18		T6	3
all_values[8]	auto[0]	auto[1]	17458	1			T1	15		T2	1		T3	16
all_values[8]	auto[1]	auto[0]	33902	1			T1	91		T2	13		T6	18
all_values[8]	auto[1]	auto[1]	18462	1			T1	16		T2	26		T3	2