Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2299	1			T1	2		T3	1		T6	3
auto[BaudRate115200]	1813	1			T1	1		T2	1		T3	1
auto[BaudRate230400]	2005	1			T4	1		T6	2		T8	5
auto[BaudRate128Kbps]	1839	1			T1	5		T2	1		T3	1
auto[BaudRate256Kbps]	2082	1			T1	3		T2	3		T3	1
auto[BaudRate1Mbps]	1820	1			T1	1		T2	2		T3	3
auto[BaudRate1p5Mbps]	1351	1			T1	1		T3	1		T6	2

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	925	1			T4	1		T13	10		T89	5
freqs[25]	1186	1			T22	9		T24	2		T169	9
freqs[48]	464	1			T287	2		T286	2		T118	3
freqs[50]	542	1			T14	9		T285	5		T180	8
freqs[100]	1157	1			T1	13		T315	3		T248	5

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	143	1			T13	4		T89	1		T124	1
auto[BaudRate9600]	freqs[25]	224	1			T22	2		T24	1		T169	2
auto[BaudRate9600]	freqs[48]	72	1			T39	6		T205	1		T114	4
auto[BaudRate9600]	freqs[50]	85	1			T180	1		T103	1		T109	3
auto[BaudRate9600]	freqs[100]	179	1			T1	2		T315	1		T248	1
auto[BaudRate115200]	freqs[24]	129	1			T42	1		T43	3		T124	2
auto[BaudRate115200]	freqs[25]	160	1			T22	1		T169	1		T129	2
auto[BaudRate115200]	freqs[48]	53	1			T287	1		T39	6		T205	1
auto[BaudRate115200]	freqs[50]	58	1			T285	1		T180	1		T256	2
auto[BaudRate115200]	freqs[100]	161	1			T1	1		T262	1		T20	4
auto[BaudRate230400]	freqs[24]	149	1			T4	1		T89	1		T43	1
auto[BaudRate230400]	freqs[25]	177	1			T169	2		T138	3		T322	15
auto[BaudRate230400]	freqs[48]	67	1			T286	1		T118	2		T39	3
auto[BaudRate230400]	freqs[50]	71	1			T285	1		T103	1		T256	1
auto[BaudRate230400]	freqs[100]	158	1			T144	1		T20	11		T116	1
auto[BaudRate128Kbps]	freqs[24]	146	1			T13	5		T89	1		T42	4
auto[BaudRate128Kbps]	freqs[25]	158	1			T22	2		T24	1		T323	3
auto[BaudRate128Kbps]	freqs[48]	58	1			T287	1		T118	1		T39	6
auto[BaudRate128Kbps]	freqs[50]	77	1			T285	1		T180	2		T103	2
auto[BaudRate128Kbps]	freqs[100]	155	1			T1	5		T315	1		T248	1
auto[BaudRate256Kbps]	freqs[24]	130	1			T42	1		T43	2		T150	1
auto[BaudRate256Kbps]	freqs[25]	188	1			T323	3		T129	2		T251	3
auto[BaudRate256Kbps]	freqs[48]	64	1			T286	1		T39	8		T324	4
auto[BaudRate256Kbps]	freqs[50]	71	1			T14	2		T103	1		T256	1
auto[BaudRate256Kbps]	freqs[100]	173	1			T1	3		T315	1		T248	2
auto[BaudRate1Mbps]	freqs[24]	142	1			T13	1		T89	1		T42	1
auto[BaudRate1Mbps]	freqs[25]	191	1			T22	3		T169	3		T245	1
auto[BaudRate1Mbps]	freqs[48]	76	1			T39	6		T324	3		T325	2
auto[BaudRate1Mbps]	freqs[50]	81	1			T14	4		T180	1		T256	1
auto[BaudRate1Mbps]	freqs[100]	147	1			T1	1		T144	1		T20	5
auto[BaudRate1p5Mbps]	freqs[25]	88	1			T22	1		T169	1		T138	1
auto[BaudRate1p5Mbps]	freqs[48]	74	1			T39	8		T325	2		T326	1
auto[BaudRate1p5Mbps]	freqs[50]	99	1			T14	3		T285	2		T180	3
auto[BaudRate1p5Mbps]	freqs[100]	184	1			T1	1		T248	1		T144	2

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded