Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::rx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::rx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	67	0	67	100.00
Crosses	130	10	120	92.31

Variables for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	65	0	65	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::rx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
rx_fifo_level_cg_cc	130	10	120	92.31	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	29718560	1			T1	87259		T2	40		T3	116
all_levels[1]	200983	1			T1	296		T2	2		T6	6
all_levels[2]	2502	1			T1	5		T2	3		T6	6
all_levels[3]	1076	1			T1	3		T2	3		T6	1
all_levels[4]	744	1			T1	1		T2	4		T3	1
all_levels[5]	519	1			T1	1		T6	1		T8	1
all_levels[6]	439	1			T1	2		T2	1		T13	1
all_levels[7]	352	1			T1	1		T2	3		T3	1
all_levels[8]	307	1			T2	2		T10	1		T41	1
all_levels[9]	252	1			T2	3		T107	1		T18	1
all_levels[10]	215	1			T1	1		T90	1		T43	1
all_levels[11]	218	1			T2	3		T13	1		T22	1
all_levels[12]	159	1			T1	1		T2	1		T8	1
all_levels[13]	189	1			T2	3		T85	1		T17	1
all_levels[14]	140	1			T1	1		T2	1		T41	1
all_levels[15]	131	1			T2	1		T85	2		T124	1
all_levels[16]	107	1			T18	2		T125	1		T105	2
all_levels[17]	96	1			T8	1		T90	2		T44	1
all_levels[18]	88	1			T1	1		T8	1		T12	4
all_levels[19]	95	1			T2	1		T89	1		T90	1
all_levels[20]	78	1			T44	1		T27	1		T126	1
all_levels[21]	76	1			T22	1		T16	1		T85	1
all_levels[22]	71	1			T2	1		T85	1		T125	1
all_levels[23]	54	1			T2	2		T8	1		T89	2
all_levels[24]	52	1			T127	1		T128	1		T129	1
all_levels[25]	60	1			T2	1		T13	1		T90	1
all_levels[26]	47	1			T103	2		T130	1		T131	2
all_levels[27]	52	1			T22	6		T105	2		T29	1
all_levels[28]	49	1			T2	1		T16	1		T132	6
all_levels[29]	43	1			T16	1		T27	1		T129	1
all_levels[30]	25	1			T111	1		T133	1		T91	1
all_levels[31]	26	1			T134	1		T135	2		T136	1
all_levels[32]	23	1			T86	1		T137	1		T138	1
all_levels[33]	18	1			T45	1		T139	1		T46	2
all_levels[34]	26	1			T108	1		T137	1		T38	1
all_levels[35]	29	1			T138	1		T130	1		T140	1
all_levels[36]	21	1			T141	1		T142	1		T143	1
all_levels[37]	18	1			T2	1		T144	1		T109	1
all_levels[38]	26	1			T144	1		T108	1		T137	1
all_levels[39]	21	1			T29	1		T133	1		T38	2
all_levels[40]	18	1			T27	1		T109	1		T127	1
all_levels[41]	17	1			T2	1		T89	1		T110	2
all_levels[42]	19	1			T86	1		T27	1		T144	1
all_levels[43]	18	1			T145	1		T141	1		T146	1
all_levels[44]	23	1			T147	1		T148	1		T134	1
all_levels[45]	13	1			T29	1		T149	1		T142	1
all_levels[46]	19	1			T150	1		T110	1		T133	1
all_levels[47]	14	1			T151	2		T152	3		T153	1
all_levels[48]	7	1			T105	1		T154	1		T155	1
all_levels[49]	16	1			T151	1		T155	2		T156	1
all_levels[50]	7	1			T154	1		T157	2		T158	1
all_levels[51]	16	1			T112	2		T142	2		T153	1
all_levels[52]	11	1			T12	1		T29	1		T159	2
all_levels[53]	5	1			T160	2		T161	1		T162	1
all_levels[54]	5	1			T163	1		T164	1		T165	1
all_levels[55]	6	1			T110	1		T112	1		T166	1
all_levels[56]	10	1			T27	1		T38	1		T167	2
all_levels[57]	10	1			T129	1		T168	1		T163	1
all_levels[58]	17	1			T169	3		T170	1		T171	1
all_levels[59]	8	1			T172	2		T115	1		T173	1
all_levels[60]	7	1			T89	1		T174	3		T175	1
all_levels[61]	5	1			T113	1		T174	1		T176	1
all_levels[62]	11	1			T172	1		T135	1		T177	1
all_levels[63]	15	1			T154	1		T178	2		T179	1
all_levels[64]	92	1			T15	1		T16	1		T17	1

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29923682

1

T1

87565

T2

78

T3

112

auto[1]

4694

1

T1

7

T3

6

T4

11

---

Summary for Cross rx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	10	120	92.31	10

Automatically Generated Cross Bins for rx_fifo_level_cg_cc

Uncovered bins

cp_lvl	cp_rst	COUNT	AT LEAST	NUMBER	STATUS
[all_levels[30]]	[auto[1]]	0	1	1
[all_levels[36]]	[auto[1]]	0	1	1
[all_levels[40]]	[auto[1]]	0	1	1
[all_levels[42]]	[auto[1]]	0	1	1
[all_levels[45]]	[auto[1]]	0	1	1
[all_levels[48]]	[auto[1]]	0	1	1
[all_levels[54] , all_levels[55]]	[auto[1]]	--	--	2
[all_levels[57]]	[auto[1]]	0	1	1
[all_levels[62]]	[auto[1]]	0	1	1

Covered bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	29714314	1			T1	87252		T2	40		T3	110
all_levels[0]	auto[1]	4246	1			T1	7		T3	6		T4	11
all_levels[1]	auto[0]	200920	1			T1	296		T2	2		T6	6
all_levels[1]	auto[1]	63	1			T107	1		T90	1		T44	1
all_levels[2]	auto[0]	2478	1			T1	5		T2	3		T6	6
all_levels[2]	auto[1]	24	1			T180	1		T101	3		T181	2
all_levels[3]	auto[0]	1057	1			T1	3		T2	3		T6	1
all_levels[3]	auto[1]	19	1			T145	2		T182	1		T183	2
all_levels[4]	auto[0]	723	1			T1	1		T2	4		T3	1
all_levels[4]	auto[1]	21	1			T169	1		T108	1		T157	1
all_levels[5]	auto[0]	503	1			T1	1		T6	1		T8	1
all_levels[5]	auto[1]	16	1			T13	2		T128	2		T170	1
all_levels[6]	auto[0]	422	1			T1	2		T2	1		T13	1
all_levels[6]	auto[1]	17	1			T105	1		T141	2		T167	2
all_levels[7]	auto[0]	334	1			T1	1		T2	3		T3	1
all_levels[7]	auto[1]	18	1			T12	3		T107	1		T102	3
all_levels[8]	auto[0]	288	1			T2	2		T10	1		T41	1
all_levels[8]	auto[1]	19	1			T27	2		T128	1		T184	2
all_levels[9]	auto[0]	237	1			T2	3		T107	1		T18	1
all_levels[9]	auto[1]	15	1			T109	1		T183	3		T185	1
all_levels[10]	auto[0]	208	1			T1	1		T90	1		T43	1
all_levels[10]	auto[1]	7	1			T140	2		T186	1		T187	2
all_levels[11]	auto[0]	200	1			T2	3		T13	1		T22	1
all_levels[11]	auto[1]	18	1			T102	2		T152	1		T188	1
all_levels[12]	auto[0]	149	1			T1	1		T2	1		T8	1
all_levels[12]	auto[1]	10	1			T189	1		T190	1		T191	1
all_levels[13]	auto[0]	174	1			T2	3		T85	1		T17	1
all_levels[13]	auto[1]	15	1			T91	3		T159	1		T134	1
all_levels[14]	auto[0]	132	1			T1	1		T2	1		T41	1
all_levels[14]	auto[1]	8	1			T90	1		T192	2		T193	2
all_levels[15]	auto[0]	118	1			T2	1		T85	2		T124	1
all_levels[15]	auto[1]	13	1			T151	2		T135	1		T194	2
all_levels[16]	auto[0]	99	1			T18	1		T125	1		T105	1
all_levels[16]	auto[1]	8	1			T18	1		T105	1		T195	2
all_levels[17]	auto[0]	88	1			T8	1		T90	2		T44	1
all_levels[17]	auto[1]	8	1			T196	2		T119	2		T197	2
all_levels[18]	auto[0]	79	1			T1	1		T8	1		T12	2
all_levels[18]	auto[1]	9	1			T12	2		T18	3		T198	1
all_levels[19]	auto[0]	85	1			T2	1		T89	1		T90	1
all_levels[19]	auto[1]	10	1			T199	1		T200	2		T201	1
all_levels[20]	auto[0]	71	1			T44	1		T27	1		T126	1
all_levels[20]	auto[1]	7	1			T117	1		T155	1		T202	1
all_levels[21]	auto[0]	71	1			T22	1		T16	1		T85	1
all_levels[21]	auto[1]	5	1			T156	1		T203	1		T204	3
all_levels[22]	auto[0]	66	1			T2	1		T85	1		T125	1
all_levels[22]	auto[1]	5	1			T205	4		T206	1		-	-
all_levels[23]	auto[0]	51	1			T2	2		T8	1		T89	1
all_levels[23]	auto[1]	3	1			T89	1		T207	2		-	-
all_levels[24]	auto[0]	45	1			T127	1		T128	1		T129	1
all_levels[24]	auto[1]	7	1			T208	2		T93	1		T209	3
all_levels[25]	auto[0]	55	1			T2	1		T13	1		T90	1
all_levels[25]	auto[1]	5	1			T135	3		T210	1		T211	1
all_levels[26]	auto[0]	41	1			T103	2		T130	1		T131	2
all_levels[26]	auto[1]	6	1			T212	2		T213	1		T214	3
all_levels[27]	auto[0]	44	1			T22	1		T105	2		T29	1
all_levels[27]	auto[1]	8	1			T22	5		T215	1		T216	2
all_levels[28]	auto[0]	42	1			T2	1		T16	1		T132	1
all_levels[28]	auto[1]	7	1			T132	5		T105	1		T217	1
all_levels[29]	auto[0]	35	1			T16	1		T27	1		T129	1
all_levels[29]	auto[1]	8	1			T218	4		T204	1		T190	1
all_levels[30]	auto[0]	25	1			T111	1		T133	1		T91	1
all_levels[31]	auto[0]	25	1			T134	1		T135	2		T136	1
all_levels[31]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[32]	auto[0]	22	1			T86	1		T137	1		T138	1
all_levels[32]	auto[1]	1	1			T219	1		-	-		-	-
all_levels[33]	auto[0]	15	1			T45	1		T139	1		T46	1
all_levels[33]	auto[1]	3	1			T46	1		T220	1		T221	1
all_levels[34]	auto[0]	21	1			T108	1		T137	1		T38	1
all_levels[34]	auto[1]	5	1			T222	4		T223	1		-	-
all_levels[35]	auto[0]	27	1			T138	1		T130	1		T140	1
all_levels[35]	auto[1]	2	1			T224	2		-	-		-	-
all_levels[36]	auto[0]	21	1			T141	1		T142	1		T143	1
all_levels[37]	auto[0]	17	1			T2	1		T144	1		T109	1
all_levels[37]	auto[1]	1	1			T225	1		-	-		-	-
all_levels[38]	auto[0]	23	1			T144	1		T108	1		T137	1
all_levels[38]	auto[1]	3	1			T134	1		T226	1		T50	1
all_levels[39]	auto[0]	18	1			T29	1		T133	1		T38	2
all_levels[39]	auto[1]	3	1			T226	2		T227	1		-	-
all_levels[40]	auto[0]	18	1			T27	1		T109	1		T127	1
all_levels[41]	auto[0]	15	1			T2	1		T89	1		T110	2
all_levels[41]	auto[1]	2	1			T228	1		T229	1		-	-
all_levels[42]	auto[0]	19	1			T86	1		T27	1		T144	1
all_levels[43]	auto[0]	16	1			T145	1		T141	1		T146	1
all_levels[43]	auto[1]	2	1			T230	1		T231	1		-	-
all_levels[44]	auto[0]	21	1			T147	1		T148	1		T134	1
all_levels[44]	auto[1]	2	1			T232	1		T233	1		-	-
all_levels[45]	auto[0]	13	1			T29	1		T149	1		T142	1
all_levels[46]	auto[0]	16	1			T150	1		T110	1		T133	1
all_levels[46]	auto[1]	3	1			T141	1		T234	1		T219	1
all_levels[47]	auto[0]	11	1			T151	1		T152	1		T153	1
all_levels[47]	auto[1]	3	1			T151	1		T152	2		-	-
all_levels[48]	auto[0]	7	1			T105	1		T154	1		T155	1
all_levels[49]	auto[0]	15	1			T151	1		T155	1		T156	1
all_levels[49]	auto[1]	1	1			T155	1		-	-		-	-
all_levels[50]	auto[0]	6	1			T154	1		T157	1		T158	1
all_levels[50]	auto[1]	1	1			T157	1		-	-		-	-
all_levels[51]	auto[0]	12	1			T112	1		T142	1		T153	1
all_levels[51]	auto[1]	4	1			T112	1		T142	1		T190	1
all_levels[52]	auto[0]	10	1			T12	1		T29	1		T159	2
all_levels[52]	auto[1]	1	1			T162	1		-	-		-	-
all_levels[53]	auto[0]	4	1			T160	1		T161	1		T162	1
all_levels[53]	auto[1]	1	1			T160	1		-	-		-	-
all_levels[54]	auto[0]	5	1			T163	1		T164	1		T165	1
all_levels[55]	auto[0]	6	1			T110	1		T112	1		T166	1
all_levels[56]	auto[0]	7	1			T27	1		T38	1		T167	1
all_levels[56]	auto[1]	3	1			T167	1		T235	2		-	-
all_levels[57]	auto[0]	10	1			T129	1		T168	1		T163	1
all_levels[58]	auto[0]	12	1			T169	1		T170	1		T171	1
all_levels[58]	auto[1]	5	1			T169	2		T236	3		-	-
all_levels[59]	auto[0]	5	1			T172	1		T115	1		T173	1
all_levels[59]	auto[1]	3	1			T172	1		T237	2		-	-
all_levels[60]	auto[0]	5	1			T89	1		T174	1		T175	1
all_levels[60]	auto[1]	2	1			T174	2		-	-		-	-
all_levels[61]	auto[0]	4	1			T113	1		T174	1		T176	1
all_levels[61]	auto[1]	1	1			T238	1		-	-		-	-
all_levels[62]	auto[0]	11	1			T172	1		T135	1		T177	1
all_levels[63]	auto[0]	11	1			T154	1		T178	1		T179	1
all_levels[63]	auto[1]	4	1			T178	1		T239	3		-	-
all_levels[64]	auto[0]	80	1			T15	1		T16	1		T17	1
all_levels[64]	auto[1]	12	1			T141	1		T142	3		T134	1