Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	9	0	9	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	108071	1			T1	174		T2	40		T3	36
all_pins[1]	108071	1			T1	174		T2	40		T3	36
all_pins[2]	108071	1			T1	174		T2	40		T3	36
all_pins[3]	108071	1			T1	174		T2	40		T3	36
all_pins[4]	108071	1			T1	174		T2	40		T3	36
all_pins[5]	108071	1			T1	174		T2	40		T3	36
all_pins[6]	108071	1			T1	174		T2	40		T3	36
all_pins[7]	108071	1			T1	174		T2	40		T3	36
all_pins[8]	108071	1			T1	174		T2	40		T3	36

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	925796	1			T1	1519		T2	319		T3	300
values[0x1]	46843	1			T1	47		T2	41		T3	24
transitions[0x0=>0x1]	36228	1			T1	32		T2	31		T3	22
transitions[0x1=>0x0]	36040	1			T1	32		T2	31		T3	22

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	86191	1			T1	145		T2	30		T3	15
all_pins[0]	values[0x1]	21880	1			T1	29		T2	10		T3	21
all_pins[0]	transitions[0x0=>0x1]	21321	1			T1	29		T2	10		T3	21
all_pins[0]	transitions[0x1=>0x0]	1148	1			T13	10		T107	5		T18	1
all_pins[1]	values[0x0]	106364	1			T1	174		T2	40		T3	36
all_pins[1]	values[0x1]	1707	1			T13	10		T107	5		T18	1
all_pins[1]	transitions[0x0=>0x1]	1606	1			T13	10		T107	5		T18	1
all_pins[1]	transitions[0x1=>0x0]	2459	1			T1	2		T2	5		T3	1
all_pins[2]	values[0x0]	105511	1			T1	172		T2	35		T3	35
all_pins[2]	values[0x1]	2560	1			T1	2		T2	5		T3	1
all_pins[2]	transitions[0x0=>0x1]	2484	1			T1	2		T2	5		T3	1
all_pins[2]	transitions[0x1=>0x0]	198	1			T15	2		T16	2		T18	2
all_pins[3]	values[0x0]	107797	1			T1	174		T2	40		T3	36
all_pins[3]	values[0x1]	274	1			T15	2		T16	2		T18	3
all_pins[3]	transitions[0x0=>0x1]	222	1			T15	2		T16	2		T18	2
all_pins[3]	transitions[0x1=>0x0]	396	1			T20	1		T21	12		T29	2
all_pins[4]	values[0x0]	107623	1			T1	174		T2	40		T3	36
all_pins[4]	values[0x1]	448	1			T18	1		T20	1		T21	12
all_pins[4]	transitions[0x0=>0x1]	382	1			T18	1		T20	1		T21	12
all_pins[4]	transitions[0x1=>0x0]	175	1			T18	1		T36	4		T25	1
all_pins[5]	values[0x0]	107830	1			T1	174		T2	40		T3	36
all_pins[5]	values[0x1]	241	1			T18	1		T36	4		T25	1
all_pins[5]	transitions[0x0=>0x1]	207	1			T18	1		T36	4		T25	1
all_pins[5]	transitions[0x1=>0x0]	776	1			T12	2		T41	7		T107	2
all_pins[6]	values[0x0]	107261	1			T1	174		T2	40		T3	36
all_pins[6]	values[0x1]	810	1			T12	2		T41	7		T107	2
all_pins[6]	transitions[0x0=>0x1]	760	1			T12	2		T41	7		T107	2
all_pins[6]	transitions[0x1=>0x0]	347	1			T15	1		T18	1		T85	3
all_pins[7]	values[0x0]	107674	1			T1	174		T2	40		T3	36
all_pins[7]	values[0x1]	397	1			T15	2		T18	1		T85	3
all_pins[7]	transitions[0x0=>0x1]	195	1			T15	2		T18	1		T85	1
all_pins[7]	transitions[0x1=>0x0]	18324	1			T1	16		T2	26		T3	2
all_pins[8]	values[0x0]	89545	1			T1	158		T2	14		T3	34
all_pins[8]	values[0x1]	18526	1			T1	16		T2	26		T3	2
all_pins[8]	transitions[0x0=>0x1]	9051	1			T1	1		T2	16		T6	3
all_pins[8]	transitions[0x1=>0x0]	12217	1			T1	14		T3	19		T4	21