Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::tx_fifo_level_cg

Group : uart_env_pkg::uart_env_cov::tx_fifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

---

Summary for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	35	0	35	100.00
Crosses	66	0	66	100.00

Variables for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_lvl	33	0	33	100.00	100	1	1	0
cp_rst	2	0	2	100.00	100	1	1	2

Crosses for Group uart_env_pkg::uart_env_cov::tx_fifo_level_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tx_fifo_level_cg_cc	66	0	66	100.00	100	1	1	0

Summary for Variable cp_lvl

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_lvl

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	7908938	1			T1	7103		T2	69		T3	43
all_levels[1]	951432	1			T1	78		T3	8		T6	39
all_levels[2]	437455	1			T1	80		T3	4		T6	18
all_levels[3]	276728	1			T1	68		T3	1		T6	9
all_levels[4]	231793	1			T1	76		T3	1		T6	6
all_levels[5]	209828	1			T1	77		T3	5		T6	17
all_levels[6]	222667	1			T1	78		T3	3		T6	11
all_levels[7]	200962	1			T1	73		T3	2		T6	8
all_levels[8]	213454	1			T1	81		T3	1		T6	13
all_levels[9]	196691	1			T1	72		T3	1		T6	24
all_levels[10]	326172	1			T1	68		T3	4		T6	21
all_levels[11]	322491	1			T1	86		T3	1		T6	22
all_levels[12]	224428	1			T1	85		T3	7		T6	7
all_levels[13]	190893	1			T1	60		T6	13		T10	3
all_levels[14]	194887	1			T1	70		T2	1		T3	2
all_levels[15]	221205	1			T1	76		T3	3		T6	41
all_levels[16]	717147	1			T1	78		T3	4		T6	13
all_levels[17]	469862	1			T1	208		T3	3		T6	31
all_levels[18]	209642	1			T1	85		T2	1		T3	3
all_levels[19]	216581	1			T1	61		T3	5		T6	8
all_levels[20]	329525	1			T1	77		T3	2		T6	5
all_levels[21]	187269	1			T1	67		T3	1		T12	1
all_levels[22]	238496	1			T1	84		T3	4		T6	1
all_levels[23]	557477	1			T1	62		T10	2		T12	1
all_levels[24]	325030	1			T1	82		T6	2		T12	1
all_levels[25]	222270	1			T1	61		T12	1		T13	2
all_levels[26]	606068	1			T1	71		T6	1		T13	1
all_levels[27]	274982	1			T1	82		T2	1		T12	1
all_levels[28]	178262	1			T1	81		T2	1		T6	5
all_levels[29]	177328	1			T1	64		T2	1		T6	3
all_levels[30]	209407	1			T1	57		T6	1		T10	1
all_levels[31]	498065	1			T1	885		T6	2		T14	3524
all_levels[32]	12180587	1			T1	77235		T2	4		T3	10

---

Summary for Variable cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rst

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29923682

1

T1

87565

T2

78

T3

112

auto[1]

4340

1

T1

6

T3

6

T4

9

---

Summary for Cross tx_fifo_level_cg_cc

Samples crossed: cp_lvl cp_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	66	0	66	100.00

Automatically Generated Cross Bins for tx_fifo_level_cg_cc

Bins

cp_lvl	cp_rst	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_levels[0]	auto[0]	7906429	1			T1	7097		T2	69		T3	40
all_levels[0]	auto[1]	2509	1			T1	6		T3	3		T4	9
all_levels[1]	auto[0]	951120	1			T1	78		T3	7		T6	39
all_levels[1]	auto[1]	312	1			T3	1		T12	2		T89	1
all_levels[2]	auto[0]	437415	1			T1	80		T3	4		T6	18
all_levels[2]	auto[1]	40	1			T8	4		T18	1		T285	4
all_levels[3]	auto[0]	276592	1			T1	68		T3	1		T6	9
all_levels[3]	auto[1]	136	1			T125	1		T27	2		T104	1
all_levels[4]	auto[0]	231773	1			T1	76		T3	1		T6	6
all_levels[4]	auto[1]	20	1			T18	1		T242	1		T167	1
all_levels[5]	auto[0]	209807	1			T1	77		T3	5		T6	17
all_levels[5]	auto[1]	21	1			T169	2		T113	2		T254	1
all_levels[6]	auto[0]	222626	1			T1	78		T3	3		T6	11
all_levels[6]	auto[1]	41	1			T272	1		T138	1		T170	2
all_levels[7]	auto[0]	200842	1			T1	73		T3	2		T6	8
all_levels[7]	auto[1]	120	1			T21	11		T118	5		T246	7
all_levels[8]	auto[0]	213427	1			T1	81		T3	1		T6	13
all_levels[8]	auto[1]	27	1			T132	5		T124	1		T170	1
all_levels[9]	auto[0]	196662	1			T1	72		T3	1		T6	24
all_levels[9]	auto[1]	29	1			T22	2		T140	1		T300	2
all_levels[10]	auto[0]	326150	1			T1	68		T3	4		T6	21
all_levels[10]	auto[1]	22	1			T12	1		T327	1		T328	3
all_levels[11]	auto[0]	322464	1			T1	86		T3	1		T6	22
all_levels[11]	auto[1]	27	1			T44	1		T248	1		T108	1
all_levels[12]	auto[0]	224405	1			T1	85		T3	7		T6	7
all_levels[12]	auto[1]	23	1			T308	1		T133	1		T131	1
all_levels[13]	auto[0]	190857	1			T1	60		T6	13		T10	2
all_levels[13]	auto[1]	36	1			T10	1		T44	1		T117	1
all_levels[14]	auto[0]	194863	1			T1	70		T2	1		T3	2
all_levels[14]	auto[1]	24	1			T315	1		T102	1		T281	1
all_levels[15]	auto[0]	221113	1			T1	76		T3	3		T6	41
all_levels[15]	auto[1]	92	1			T105	1		T267	1		T145	2
all_levels[16]	auto[0]	717129	1			T1	78		T3	4		T6	13
all_levels[16]	auto[1]	18	1			T12	1		T146	1		T185	2
all_levels[17]	auto[0]	469837	1			T1	208		T3	3		T6	31
all_levels[17]	auto[1]	25	1			T108	1		T170	1		T329	1
all_levels[18]	auto[0]	209623	1			T1	85		T2	1		T3	3
all_levels[18]	auto[1]	19	1			T212	1		T330	1		T185	1
all_levels[19]	auto[0]	216562	1			T1	61		T3	5		T6	8
all_levels[19]	auto[1]	19	1			T8	1		T142	4		T166	1
all_levels[20]	auto[0]	329505	1			T1	77		T3	2		T6	5
all_levels[20]	auto[1]	20	1			T182	1		T183	2		T293	1
all_levels[21]	auto[0]	187248	1			T1	67		T3	1		T12	1
all_levels[21]	auto[1]	21	1			T18	1		T159	1		T312	1
all_levels[22]	auto[0]	238471	1			T1	84		T3	4		T6	1
all_levels[22]	auto[1]	25	1			T10	1		T107	2		T86	2
all_levels[23]	auto[0]	557457	1			T1	62		T10	2		T12	1
all_levels[23]	auto[1]	20	1			T42	1		T182	1		T38	2
all_levels[24]	auto[0]	325011	1			T1	82		T6	2		T12	1
all_levels[24]	auto[1]	19	1			T18	3		T102	2		T105	1
all_levels[25]	auto[0]	222256	1			T1	61		T12	1		T13	2
all_levels[25]	auto[1]	14	1			T90	1		T181	2		T331	1
all_levels[26]	auto[0]	606042	1			T1	71		T6	1		T13	1
all_levels[26]	auto[1]	26	1			T22	1		T308	3		T112	1
all_levels[27]	auto[0]	274969	1			T1	82		T2	1		T12	1
all_levels[27]	auto[1]	13	1			T151	1		T117	3		T175	1
all_levels[28]	auto[0]	178241	1			T1	81		T2	1		T6	5
all_levels[28]	auto[1]	21	1			T125	1		T246	4		T332	1
all_levels[29]	auto[0]	177312	1			T1	64		T2	1		T6	3
all_levels[29]	auto[1]	16	1			T8	1		T98	1		T111	1
all_levels[30]	auto[0]	209391	1			T1	57		T6	1		T10	1
all_levels[30]	auto[1]	16	1			T38	2		T186	1		T333	2
all_levels[31]	auto[0]	498044	1			T1	885		T6	2		T14	3524
all_levels[31]	auto[1]	21	1			T38	2		T113	1		T119	2
all_levels[32]	auto[0]	12180039	1			T1	77235		T2	4		T3	8
all_levels[32]	auto[1]	548	1			T3	2		T10	2		T13	4