Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	54	6	48	88.89

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	54	6	48	88.89	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	762	1			T18	7		T20	7		T29	4
all_values[1]	762	1			T18	7		T20	7		T29	4
all_values[2]	762	1			T18	7		T20	7		T29	4
all_values[3]	762	1			T18	7		T20	7		T29	4
all_values[4]	762	1			T18	7		T20	7		T29	4
all_values[5]	762	1			T18	7		T20	7		T29	4
all_values[6]	762	1			T18	7		T20	7		T29	4
all_values[7]	762	1			T18	7		T20	7		T29	4
all_values[8]	762	1			T18	7		T20	7		T29	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3692

1

T18

30

T20

41

T29

22

auto[1]

3166

1

T18

33

T20

22

T29

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2228

1

T18

22

T20

22

T29

15

auto[1]

4630

1

T18

41

T20

41

T29

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3977

1

T18

37

T20

38

T29

23

auto[1]

2881

1

T18

26

T20

25

T29

13

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	54	6	48	88.89	6
Automatically Generated Cross Bins	54	6	48	88.89	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0]]	[auto[0]]	*	[auto[0]]	--	--	2
[all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[all_values[8]]	[auto[0]]	*	[auto[0]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	243	1			T18	1		T20	5		T29	2
all_values[0]	auto[0]	auto[1]	auto[1]	193	1			T18	3		T36	3		T108	1
all_values[0]	auto[1]	auto[0]	auto[1]	183	1			T18	2		T20	2		T29	2
all_values[0]	auto[1]	auto[1]	auto[1]	143	1			T18	1		T36	1		T108	2
all_values[1]	auto[0]	auto[0]	auto[0]	218	1			T18	2		T20	1		T29	1
all_values[1]	auto[0]	auto[1]	auto[0]	207	1			T18	1		T20	4		T29	2
all_values[1]	auto[1]	auto[0]	auto[1]	180	1			T18	4		T20	1		T29	1
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T20	1		T36	3		T108	2
all_values[2]	auto[0]	auto[0]	auto[0]	144	1			T20	1		T36	2		T108	2
all_values[2]	auto[0]	auto[0]	auto[1]	82	1			T18	1		T20	1		T29	2
all_values[2]	auto[0]	auto[1]	auto[0]	116	1			T20	1		T36	1		T38	2
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T18	2		T36	1		T39	1
all_values[2]	auto[1]	auto[0]	auto[1]	175	1			T18	3		T36	3		T108	1
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T18	1		T20	4		T29	2
all_values[3]	auto[0]	auto[0]	auto[0]	164	1			T18	2		T20	1		T39	1
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T20	1		T36	3		T108	1
all_values[3]	auto[0]	auto[1]	auto[0]	128	1			T20	3		T29	4		T36	1
all_values[3]	auto[0]	auto[1]	auto[1]	75	1			T18	1		T36	1		T38	1
all_values[3]	auto[1]	auto[0]	auto[1]	170	1			T18	2		T36	3		T108	1
all_values[3]	auto[1]	auto[1]	auto[1]	147	1			T18	2		T20	2		T36	3
all_values[4]	auto[0]	auto[0]	auto[0]	160	1			T18	2		T20	3		T29	1
all_values[4]	auto[0]	auto[0]	auto[1]	57	1			T20	2		T36	1		T121	1
all_values[4]	auto[0]	auto[1]	auto[0]	166	1			T18	2		T36	2		T38	1
all_values[4]	auto[0]	auto[1]	auto[1]	73	1			T29	1		T36	2		T108	1
all_values[4]	auto[1]	auto[0]	auto[1]	166	1			T20	2		T29	1		T36	5
all_values[4]	auto[1]	auto[1]	auto[1]	140	1			T18	3		T29	1		T36	1
all_values[5]	auto[0]	auto[0]	auto[0]	162	1			T18	1		T20	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[1]	86	1			T18	1		T108	1		T39	1
all_values[5]	auto[0]	auto[1]	auto[0]	133	1			T18	2		T20	2		T29	2
all_values[5]	auto[0]	auto[1]	auto[1]	70	1			T18	1		T36	2		T38	1
all_values[5]	auto[1]	auto[0]	auto[1]	171	1			T18	1		T20	3		T29	1
all_values[5]	auto[1]	auto[1]	auto[1]	140	1			T18	1		T20	1		T36	1
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T18	2		T20	1		T29	3
all_values[6]	auto[0]	auto[0]	auto[1]	64	1			T20	2		T36	1		T38	1
all_values[6]	auto[0]	auto[1]	auto[0]	155	1			T18	5		T20	1		T36	2
all_values[6]	auto[0]	auto[1]	auto[1]	63	1			T36	1		T108	1		T39	1
all_values[6]	auto[1]	auto[0]	auto[1]	177	1			T20	2		T29	1		T36	1
all_values[6]	auto[1]	auto[1]	auto[1]	119	1			T20	1		T36	4		T108	1
all_values[7]	auto[0]	auto[0]	auto[0]	156	1			T20	1		T29	1		T36	2
all_values[7]	auto[0]	auto[0]	auto[1]	74	1			T18	1		T20	1		T29	1
all_values[7]	auto[0]	auto[1]	auto[0]	135	1			T18	3		T20	2		T36	1
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T36	2		T121	2		T92	1
all_values[7]	auto[1]	auto[0]	auto[1]	173	1			T18	1		T20	3		T29	2
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T18	2		T36	1		T38	3
all_values[8]	auto[0]	auto[0]	auto[1]	233	1			T18	3		T20	4		T29	2
all_values[8]	auto[0]	auto[1]	auto[1]	201	1			T18	1		T36	4		T108	1
all_values[8]	auto[1]	auto[0]	auto[1]	192	1			T18	1		T20	3		T36	2
all_values[8]	auto[1]	auto[1]	auto[1]	136	1			T18	2		T29	2		T36	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal