Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.11 99.10 97.65 100.00 98.38 100.00 99.55


Total test records in report: 1317
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T1257 /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.593019852 Aug 03 04:16:34 PM PDT 24 Aug 03 04:16:35 PM PDT 24 100191921 ps
T1258 /workspace/coverage/cover_reg_top/45.uart_intr_test.2133722099 Aug 03 04:21:08 PM PDT 24 Aug 03 04:21:09 PM PDT 24 89138418 ps
T1259 /workspace/coverage/cover_reg_top/34.uart_intr_test.96871843 Aug 03 04:19:21 PM PDT 24 Aug 03 04:19:22 PM PDT 24 14741707 ps
T1260 /workspace/coverage/cover_reg_top/24.uart_intr_test.2435654859 Aug 03 04:18:37 PM PDT 24 Aug 03 04:18:38 PM PDT 24 40164426 ps
T1261 /workspace/coverage/cover_reg_top/9.uart_intr_test.816008425 Aug 03 04:17:01 PM PDT 24 Aug 03 04:17:02 PM PDT 24 69180021 ps
T1262 /workspace/coverage/cover_reg_top/27.uart_intr_test.1006872884 Aug 03 04:17:53 PM PDT 24 Aug 03 04:17:54 PM PDT 24 52874182 ps
T1263 /workspace/coverage/cover_reg_top/26.uart_intr_test.4138201616 Aug 03 04:17:53 PM PDT 24 Aug 03 04:17:53 PM PDT 24 13235000 ps
T1264 /workspace/coverage/cover_reg_top/8.uart_tl_errors.2465497506 Aug 03 04:21:25 PM PDT 24 Aug 03 04:21:27 PM PDT 24 190166153 ps
T1265 /workspace/coverage/cover_reg_top/1.uart_csr_rw.2137359022 Aug 03 04:19:45 PM PDT 24 Aug 03 04:19:45 PM PDT 24 23800755 ps
T1266 /workspace/coverage/cover_reg_top/1.uart_intr_test.4246864314 Aug 03 04:16:37 PM PDT 24 Aug 03 04:16:38 PM PDT 24 29034995 ps
T1267 /workspace/coverage/cover_reg_top/4.uart_csr_rw.896019282 Aug 03 04:16:15 PM PDT 24 Aug 03 04:16:16 PM PDT 24 64165552 ps
T122 /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3813500847 Aug 03 04:18:05 PM PDT 24 Aug 03 04:18:07 PM PDT 24 70919481 ps
T1268 /workspace/coverage/cover_reg_top/5.uart_tl_errors.1969560528 Aug 03 04:18:24 PM PDT 24 Aug 03 04:18:26 PM PDT 24 99175223 ps
T1269 /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.423549630 Aug 03 04:16:15 PM PDT 24 Aug 03 04:16:16 PM PDT 24 139761651 ps
T1270 /workspace/coverage/cover_reg_top/13.uart_tl_errors.1874710710 Aug 03 04:17:37 PM PDT 24 Aug 03 04:17:38 PM PDT 24 74115825 ps
T1271 /workspace/coverage/cover_reg_top/12.uart_tl_errors.1193165400 Aug 03 04:16:15 PM PDT 24 Aug 03 04:16:16 PM PDT 24 154108507 ps
T1272 /workspace/coverage/cover_reg_top/11.uart_intr_test.2886738578 Aug 03 04:16:15 PM PDT 24 Aug 03 04:16:16 PM PDT 24 38854844 ps
T1273 /workspace/coverage/cover_reg_top/44.uart_intr_test.3348290583 Aug 03 04:18:40 PM PDT 24 Aug 03 04:18:40 PM PDT 24 51996994 ps
T1274 /workspace/coverage/cover_reg_top/18.uart_intr_test.963038859 Aug 03 04:17:17 PM PDT 24 Aug 03 04:17:18 PM PDT 24 77275849 ps
T1275 /workspace/coverage/cover_reg_top/43.uart_intr_test.1876494447 Aug 03 04:21:33 PM PDT 24 Aug 03 04:21:34 PM PDT 24 13087633 ps
T1276 /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3117165104 Aug 03 04:18:38 PM PDT 24 Aug 03 04:18:39 PM PDT 24 47797095 ps
T1277 /workspace/coverage/cover_reg_top/6.uart_csr_rw.2044966086 Aug 03 04:17:01 PM PDT 24 Aug 03 04:17:02 PM PDT 24 22968220 ps
T123 /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3152746686 Aug 03 04:18:16 PM PDT 24 Aug 03 04:18:17 PM PDT 24 320284113 ps
T1278 /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2378373803 Aug 03 04:24:00 PM PDT 24 Aug 03 04:24:01 PM PDT 24 118183886 ps
T1279 /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3868985628 Aug 03 04:16:19 PM PDT 24 Aug 03 04:16:20 PM PDT 24 22713781 ps
T1280 /workspace/coverage/cover_reg_top/28.uart_intr_test.1789338795 Aug 03 04:17:53 PM PDT 24 Aug 03 04:17:53 PM PDT 24 92041772 ps
T1281 /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4095389336 Aug 03 04:16:58 PM PDT 24 Aug 03 04:16:59 PM PDT 24 46081691 ps
T1282 /workspace/coverage/cover_reg_top/39.uart_intr_test.3854619840 Aug 03 04:20:42 PM PDT 24 Aug 03 04:20:44 PM PDT 24 194591451 ps
T1283 /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1637061209 Aug 03 04:16:15 PM PDT 24 Aug 03 04:16:16 PM PDT 24 90200144 ps
T1284 /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1398780372 Aug 03 04:18:51 PM PDT 24 Aug 03 04:18:52 PM PDT 24 126928214 ps
T81 /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3763220303 Aug 03 04:17:23 PM PDT 24 Aug 03 04:17:24 PM PDT 24 52708646 ps
T1285 /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1395182583 Aug 03 04:17:40 PM PDT 24 Aug 03 04:17:40 PM PDT 24 21485671 ps
T1286 /workspace/coverage/cover_reg_top/0.uart_csr_rw.653714591 Aug 03 04:18:21 PM PDT 24 Aug 03 04:18:22 PM PDT 24 12405887 ps
T1287 /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2351658244 Aug 03 04:23:09 PM PDT 24 Aug 03 04:23:11 PM PDT 24 270677364 ps
T77 /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3673127988 Aug 03 04:18:16 PM PDT 24 Aug 03 04:18:17 PM PDT 24 322477030 ps
T1288 /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.815236241 Aug 03 04:16:19 PM PDT 24 Aug 03 04:16:20 PM PDT 24 28852978 ps
T1289 /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3951589977 Aug 03 04:17:01 PM PDT 24 Aug 03 04:17:02 PM PDT 24 342630761 ps
T82 /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2611509231 Aug 03 04:16:24 PM PDT 24 Aug 03 04:16:25 PM PDT 24 188968581 ps
T1290 /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2637817108 Aug 03 04:17:24 PM PDT 24 Aug 03 04:17:25 PM PDT 24 54657695 ps
T1291 /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3293445185 Aug 03 04:18:04 PM PDT 24 Aug 03 04:18:06 PM PDT 24 261132803 ps
T1292 /workspace/coverage/cover_reg_top/15.uart_intr_test.2160166741 Aug 03 04:17:39 PM PDT 24 Aug 03 04:17:40 PM PDT 24 36735822 ps
T1293 /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2892658255 Aug 03 04:17:44 PM PDT 24 Aug 03 04:17:45 PM PDT 24 410257567 ps
T1294 /workspace/coverage/cover_reg_top/18.uart_tl_errors.1357503832 Aug 03 04:17:29 PM PDT 24 Aug 03 04:17:31 PM PDT 24 47952353 ps
T1295 /workspace/coverage/cover_reg_top/46.uart_intr_test.1618535941 Aug 03 04:17:04 PM PDT 24 Aug 03 04:17:05 PM PDT 24 30890404 ps
T1296 /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.348563042 Aug 03 04:17:35 PM PDT 24 Aug 03 04:17:36 PM PDT 24 36335142 ps
T1297 /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1430857414 Aug 03 04:17:09 PM PDT 24 Aug 03 04:17:10 PM PDT 24 33048689 ps
T1298 /workspace/coverage/cover_reg_top/19.uart_tl_errors.2743866307 Aug 03 04:17:48 PM PDT 24 Aug 03 04:17:50 PM PDT 24 173954922 ps
T1299 /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2164598051 Aug 03 04:16:56 PM PDT 24 Aug 03 04:16:57 PM PDT 24 64638832 ps
T1300 /workspace/coverage/cover_reg_top/21.uart_intr_test.1327339965 Aug 03 04:18:28 PM PDT 24 Aug 03 04:18:29 PM PDT 24 14951490 ps
T1301 /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2942263006 Aug 03 04:16:09 PM PDT 24 Aug 03 04:16:10 PM PDT 24 16511610 ps
T1302 /workspace/coverage/cover_reg_top/3.uart_intr_test.1902152678 Aug 03 04:16:43 PM PDT 24 Aug 03 04:16:44 PM PDT 24 41558894 ps
T1303 /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1742781312 Aug 03 04:20:26 PM PDT 24 Aug 03 04:20:27 PM PDT 24 100074036 ps
T1304 /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2962310879 Aug 03 04:18:52 PM PDT 24 Aug 03 04:18:53 PM PDT 24 117130315 ps
T78 /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.830693383 Aug 03 04:18:38 PM PDT 24 Aug 03 04:18:39 PM PDT 24 68080337 ps
T1305 /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3951785703 Aug 03 04:18:08 PM PDT 24 Aug 03 04:18:09 PM PDT 24 46777657 ps
T1306 /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2652764187 Aug 03 04:21:15 PM PDT 24 Aug 03 04:21:16 PM PDT 24 47302633 ps
T1307 /workspace/coverage/cover_reg_top/40.uart_intr_test.2461894071 Aug 03 04:20:57 PM PDT 24 Aug 03 04:20:58 PM PDT 24 163915092 ps
T1308 /workspace/coverage/cover_reg_top/15.uart_tl_errors.2196728090 Aug 03 04:17:52 PM PDT 24 Aug 03 04:17:53 PM PDT 24 23104000 ps
T1309 /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.409037167 Aug 03 04:17:04 PM PDT 24 Aug 03 04:17:05 PM PDT 24 75587674 ps
T1310 /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3459136122 Aug 03 04:18:38 PM PDT 24 Aug 03 04:18:39 PM PDT 24 22965169 ps
T1311 /workspace/coverage/cover_reg_top/7.uart_intr_test.1994648571 Aug 03 04:16:28 PM PDT 24 Aug 03 04:16:29 PM PDT 24 53844082 ps
T1312 /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.824470018 Aug 03 04:18:26 PM PDT 24 Aug 03 04:18:27 PM PDT 24 753278770 ps
T1313 /workspace/coverage/cover_reg_top/23.uart_intr_test.2774155147 Aug 03 04:17:57 PM PDT 24 Aug 03 04:17:57 PM PDT 24 29589852 ps
T1314 /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1398187820 Aug 03 04:17:10 PM PDT 24 Aug 03 04:17:10 PM PDT 24 16551925 ps
T1315 /workspace/coverage/cover_reg_top/35.uart_intr_test.1530947593 Aug 03 04:18:30 PM PDT 24 Aug 03 04:18:32 PM PDT 24 11607946 ps
T1316 /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.739295233 Aug 03 04:18:03 PM PDT 24 Aug 03 04:18:04 PM PDT 24 32988881 ps
T1317 /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3376510443 Aug 03 04:17:07 PM PDT 24 Aug 03 04:17:08 PM PDT 24 15500081 ps

Test location /workspace/coverage/default/4.uart_stress_all_with_rand_reset.3614631846
Short name T1
Test name
Test status
Simulation time 117063012055 ps
CPU time 1147.04 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 05:11:08 PM PDT 24
Peak memory 216452 kb
Host smart-014dd253-961f-4803-b665-7cc54b362548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614631846 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 4.uart_stress_all_with_rand_reset.3614631846
Directory /workspace/4.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_stress_all.2254808302
Short name T18
Test name
Test status
Simulation time 245706094727 ps
CPU time 442 seconds
Started Aug 03 04:54:58 PM PDT 24
Finished Aug 03 05:02:20 PM PDT 24
Peak memory 199784 kb
Host smart-23438a6b-d7a0-4088-9c7f-6321da200aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254808302 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_stress_all.2254808302
Directory /workspace/48.uart_stress_all/latest

Test location /workspace/coverage/default/34.uart_stress_all.4096284721
Short name T110
Test name
Test status
Simulation time 403668182186 ps
CPU time 797.74 seconds
Started Aug 03 04:53:41 PM PDT 24
Finished Aug 03 05:06:59 PM PDT 24
Peak memory 208172 kb
Host smart-64eb82df-2744-4360-88e1-446797980867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096284721 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_stress_all.4096284721
Directory /workspace/34.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_stress_all_with_rand_reset.453192313
Short name T38
Test name
Test status
Simulation time 271662518868 ps
CPU time 663.27 seconds
Started Aug 03 04:54:10 PM PDT 24
Finished Aug 03 05:05:14 PM PDT 24
Peak memory 216400 kb
Host smart-798a6922-d9d4-4bd9-adc5-74421736493f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453192313 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 41.uart_stress_all_with_rand_reset.453192313
Directory /workspace/41.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_rx_parity_err.3444180698
Short name T85
Test name
Test status
Simulation time 272678489997 ps
CPU time 118.56 seconds
Started Aug 03 04:54:57 PM PDT 24
Finished Aug 03 04:56:56 PM PDT 24
Peak memory 199832 kb
Host smart-d4b7dbf4-d96d-4575-a849-0484f645a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444180698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_parity_err.3444180698
Directory /workspace/48.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_stress_all_with_rand_reset.1527426142
Short name T20
Test name
Test status
Simulation time 30063776297 ps
CPU time 719.51 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 05:04:24 PM PDT 24
Peak memory 216304 kb
Host smart-353a791e-df6e-4943-be27-e59eceedfc6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527426142 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 16.uart_stress_all_with_rand_reset.1527426142
Directory /workspace/16.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_long_xfer_wo_dly.2377767343
Short name T251
Test name
Test status
Simulation time 120270760108 ps
CPU time 324.27 seconds
Started Aug 03 04:54:02 PM PDT 24
Finished Aug 03 04:59:27 PM PDT 24
Peak memory 199924 kb
Host smart-42500957-8ab1-44f3-b2d2-4ff787f08a7e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2377767343 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_long_xfer_wo_dly.2377767343
Directory /workspace/39.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_sec_cm.2284984942
Short name T31
Test name
Test status
Simulation time 32310824 ps
CPU time 0.76 seconds
Started Aug 03 04:51:56 PM PDT 24
Finished Aug 03 04:51:57 PM PDT 24
Peak memory 218176 kb
Host smart-ed38a24c-a1ef-46c7-b491-f903d0bb9084
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284984942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_sec_cm.2284984942
Directory /workspace/4.uart_sec_cm/latest

Test location /workspace/coverage/default/12.uart_fifo_reset.2820792916
Short name T12
Test name
Test status
Simulation time 78967196076 ps
CPU time 65.36 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 199916 kb
Host smart-f4fe0b99-35c8-42e4-bc19-7f8d09a828d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820792916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_reset.2820792916
Directory /workspace/12.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_fifo_overflow.4121481304
Short name T154
Test name
Test status
Simulation time 241410356204 ps
CPU time 109.72 seconds
Started Aug 03 04:54:28 PM PDT 24
Finished Aug 03 04:56:18 PM PDT 24
Peak memory 199892 kb
Host smart-390f3cb5-41b2-4239-b786-a22674506c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121481304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_overflow.4121481304
Directory /workspace/45.uart_fifo_overflow/latest

Test location /workspace/coverage/default/58.uart_stress_all_with_rand_reset.735208530
Short name T92
Test name
Test status
Simulation time 24339598488 ps
CPU time 431.36 seconds
Started Aug 03 04:55:23 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 208224 kb
Host smart-90b9407a-8bfa-4af0-9c58-b725485bcd63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735208530 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 58.uart_stress_all_with_rand_reset.735208530
Directory /workspace/58.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/248.uart_fifo_reset.3303999240
Short name T133
Test name
Test status
Simulation time 113369383630 ps
CPU time 32.35 seconds
Started Aug 03 04:57:49 PM PDT 24
Finished Aug 03 04:58:21 PM PDT 24
Peak memory 199824 kb
Host smart-e67db88d-68b9-467d-a0f9-3446d5790a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303999240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 248.uart_fifo_reset.3303999240
Directory /workspace/248.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_stress_all.101024109
Short name T121
Test name
Test status
Simulation time 304101639915 ps
CPU time 181.21 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:55:10 PM PDT 24
Peak memory 208364 kb
Host smart-8dad9d79-7e9d-49a4-afbe-80efc23604c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101024109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_stress_all.101024109
Directory /workspace/11.uart_stress_all/latest

Test location /workspace/coverage/default/81.uart_stress_all_with_rand_reset.1830801676
Short name T307
Test name
Test status
Simulation time 288256315511 ps
CPU time 852.79 seconds
Started Aug 03 04:56:00 PM PDT 24
Finished Aug 03 05:10:13 PM PDT 24
Peak memory 216408 kb
Host smart-f6adf0dd-1aff-4c4d-9d5e-7439c884aa55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830801676 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 81.uart_stress_all_with_rand_reset.1830801676
Directory /workspace/81.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_stress_all.1594564408
Short name T108
Test name
Test status
Simulation time 73915783135 ps
CPU time 126.17 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:53:53 PM PDT 24
Peak memory 199828 kb
Host smart-ce0a7c05-4df5-4ecb-b9ea-954f5255b1e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594564408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_stress_all.1594564408
Directory /workspace/1.uart_stress_all/latest

Test location /workspace/coverage/default/140.uart_fifo_reset.101075339
Short name T141
Test name
Test status
Simulation time 20028877414 ps
CPU time 25.27 seconds
Started Aug 03 04:56:51 PM PDT 24
Finished Aug 03 04:57:17 PM PDT 24
Peak memory 199888 kb
Host smart-fdee65ce-937d-449f-af09-c6ceabd55e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101075339 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 140.uart_fifo_reset.101075339
Directory /workspace/140.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_intg_err.2408263097
Short name T76
Test name
Test status
Simulation time 86172098 ps
CPU time 1.31 seconds
Started Aug 03 04:17:27 PM PDT 24
Finished Aug 03 04:17:28 PM PDT 24
Peak memory 199492 kb
Host smart-45a6632c-98d0-4dbe-b1d2-410bbdcb9c5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408263097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_intg_err.2408263097
Directory /workspace/10.uart_tl_intg_err/latest

Test location /workspace/coverage/default/29.uart_tx_rx.1050030944
Short name T274
Test name
Test status
Simulation time 159305874000 ps
CPU time 116.3 seconds
Started Aug 03 04:53:10 PM PDT 24
Finished Aug 03 04:55:06 PM PDT 24
Peak memory 199832 kb
Host smart-50015016-2d90-46a4-bb23-c42efa228d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050030944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_rx.1050030944
Directory /workspace/29.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_stress_all_with_rand_reset.830939607
Short name T28
Test name
Test status
Simulation time 42769897045 ps
CPU time 259.27 seconds
Started Aug 03 04:53:46 PM PDT 24
Finished Aug 03 04:58:06 PM PDT 24
Peak memory 216560 kb
Host smart-c5c41e2d-cb97-49bc-b320-ab2faea05e85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830939607 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 36.uart_stress_all_with_rand_reset.830939607
Directory /workspace/36.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_fifo_overflow.3850944895
Short name T129
Test name
Test status
Simulation time 76980032678 ps
CPU time 30.46 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 199876 kb
Host smart-fbed48d1-2772-4d62-a568-6f69fab37f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850944895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_overflow.3850944895
Directory /workspace/14.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_stress_all_with_rand_reset.2293980216
Short name T39
Test name
Test status
Simulation time 88714577213 ps
CPU time 533.67 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 05:01:27 PM PDT 24
Peak memory 224776 kb
Host smart-c13cdd57-dbe5-439b-9473-89602a52493b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293980216 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 18.uart_stress_all_with_rand_reset.2293980216
Directory /workspace/18.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.uart_alert_test.899671796
Short name T376
Test name
Test status
Simulation time 13333119 ps
CPU time 0.55 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:09 PM PDT 24
Peak memory 195224 kb
Host smart-78041ee6-4009-403e-983c-bcc692951544
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899671796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_alert_test.899671796
Directory /workspace/10.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_perf.1619181079
Short name T42
Test name
Test status
Simulation time 18900680731 ps
CPU time 255.64 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 199916 kb
Host smart-ecf1b451-b4f7-46b4-8e3c-8bf97443829a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1619181079 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_perf.1619181079
Directory /workspace/42.uart_perf/latest

Test location /workspace/coverage/default/185.uart_fifo_reset.1161631429
Short name T13
Test name
Test status
Simulation time 211975233820 ps
CPU time 170.9 seconds
Started Aug 03 04:57:12 PM PDT 24
Finished Aug 03 05:00:03 PM PDT 24
Peak memory 199876 kb
Host smart-114e1ef2-d2ea-4874-aa68-64adc271866b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161631429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 185.uart_fifo_reset.1161631429
Directory /workspace/185.uart_fifo_reset/latest

Test location /workspace/coverage/default/117.uart_fifo_reset.4238257575
Short name T208
Test name
Test status
Simulation time 120096976698 ps
CPU time 129.1 seconds
Started Aug 03 04:56:30 PM PDT 24
Finished Aug 03 04:58:40 PM PDT 24
Peak memory 199860 kb
Host smart-1702afe5-b0b2-457d-9788-eaa1af6f86d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238257575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 117.uart_fifo_reset.4238257575
Directory /workspace/117.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_tx_rx.3965582583
Short name T261
Test name
Test status
Simulation time 132369798289 ps
CPU time 64.92 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 199756 kb
Host smart-dc78388b-2aa8-4694-9595-4e495558fb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965582583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_rx.3965582583
Directory /workspace/24.uart_tx_rx/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_rw.783197418
Short name T54
Test name
Test status
Simulation time 25367421 ps
CPU time 0.64 seconds
Started Aug 03 04:16:21 PM PDT 24
Finished Aug 03 04:16:21 PM PDT 24
Peak memory 195752 kb
Host smart-90b346b6-e411-44a0-b9dc-bfecc2e7c217
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783197418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_csr_rw.783197418
Directory /workspace/10.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_same_csr_outstanding.2161457507
Short name T69
Test name
Test status
Simulation time 72624108 ps
CPU time 0.65 seconds
Started Aug 03 04:17:19 PM PDT 24
Finished Aug 03 04:17:19 PM PDT 24
Peak memory 196428 kb
Host smart-6e634c44-82de-4498-8aa3-15e2456b8fa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161457507 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_same_cs
r_outstanding.2161457507
Directory /workspace/11.uart_same_csr_outstanding/latest

Test location /workspace/coverage/default/33.uart_stress_all.1795829293
Short name T246
Test name
Test status
Simulation time 876205125983 ps
CPU time 97.99 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:55:22 PM PDT 24
Peak memory 216436 kb
Host smart-b6665415-a7a6-47bb-91c1-a2298565fa54
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795829293 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_stress_all.1795829293
Directory /workspace/33.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_perf.433127736
Short name T256
Test name
Test status
Simulation time 24123120424 ps
CPU time 522.29 seconds
Started Aug 03 04:53:52 PM PDT 24
Finished Aug 03 05:02:35 PM PDT 24
Peak memory 199808 kb
Host smart-eca304c7-ea3b-4bd1-b441-f10293e8f3db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=433127736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_perf.433127736
Directory /workspace/37.uart_perf/latest

Test location /workspace/coverage/default/282.uart_fifo_reset.2391295305
Short name T186
Test name
Test status
Simulation time 194280111494 ps
CPU time 88.01 seconds
Started Aug 03 04:58:11 PM PDT 24
Finished Aug 03 04:59:39 PM PDT 24
Peak memory 199860 kb
Host smart-4338c879-18f2-451f-8c19-7ffdbf7b943f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391295305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 282.uart_fifo_reset.2391295305
Directory /workspace/282.uart_fifo_reset/latest

Test location /workspace/coverage/default/34.uart_fifo_reset.1851530298
Short name T142
Test name
Test status
Simulation time 50906021543 ps
CPU time 16.81 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:55 PM PDT 24
Peak memory 199800 kb
Host smart-94de7b49-fe5c-445f-8e83-19939da45517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851530298 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_reset.1851530298
Directory /workspace/34.uart_fifo_reset/latest

Test location /workspace/coverage/default/124.uart_fifo_reset.917955105
Short name T134
Test name
Test status
Simulation time 158638193699 ps
CPU time 293.61 seconds
Started Aug 03 04:56:29 PM PDT 24
Finished Aug 03 05:01:23 PM PDT 24
Peak memory 199828 kb
Host smart-8c476340-3b88-426a-962f-22015a335e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917955105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 124.uart_fifo_reset.917955105
Directory /workspace/124.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_stress_all.1084050480
Short name T117
Test name
Test status
Simulation time 353370583981 ps
CPU time 645.6 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 05:03:26 PM PDT 24
Peak memory 199864 kb
Host smart-b34b1766-c207-4713-a4a7-585e9c91ebc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084050480 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_stress_all.1084050480
Directory /workspace/19.uart_stress_all/latest

Test location /workspace/coverage/default/184.uart_fifo_reset.501751487
Short name T162
Test name
Test status
Simulation time 21404560649 ps
CPU time 30.67 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 04:57:44 PM PDT 24
Peak memory 199888 kb
Host smart-9cf1778d-ad40-408b-acde-678c7793dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501751487 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 184.uart_fifo_reset.501751487
Directory /workspace/184.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_stress_all_with_rand_reset.3143207255
Short name T46
Test name
Test status
Simulation time 169957266069 ps
CPU time 433.49 seconds
Started Aug 03 04:52:53 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 216440 kb
Host smart-f0ee4406-0d07-4ebe-97e5-c13ebc107d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143207255 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 23.uart_stress_all_with_rand_reset.3143207255
Directory /workspace/23.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_rx.2315865153
Short name T259
Test name
Test status
Simulation time 160258974954 ps
CPU time 96.66 seconds
Started Aug 03 04:54:09 PM PDT 24
Finished Aug 03 04:55:46 PM PDT 24
Peak memory 199924 kb
Host smart-62375859-d827-4562-9d4a-04ce50740ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315865153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_rx.2315865153
Directory /workspace/42.uart_tx_rx/latest

Test location /workspace/coverage/default/267.uart_fifo_reset.3421230559
Short name T174
Test name
Test status
Simulation time 45992531808 ps
CPU time 14.84 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:12 PM PDT 24
Peak memory 199836 kb
Host smart-5f038d89-5607-4a9f-8a1f-f61780cfa863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421230559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 267.uart_fifo_reset.3421230559
Directory /workspace/267.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_stress_all_with_rand_reset.4091805122
Short name T114
Test name
Test status
Simulation time 186637800115 ps
CPU time 1175.37 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 05:11:45 PM PDT 24
Peak memory 229384 kb
Host smart-1834773f-18f3-4abd-9ec3-98b4e6e4f3ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091805122 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 10.uart_stress_all_with_rand_reset.4091805122
Directory /workspace/10.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_intg_err.2611509231
Short name T82
Test name
Test status
Simulation time 188968581 ps
CPU time 0.92 seconds
Started Aug 03 04:16:24 PM PDT 24
Finished Aug 03 04:16:25 PM PDT 24
Peak memory 199096 kb
Host smart-40d5dac7-e9c2-4991-acf4-9405813acdab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611509231 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_intg_err.2611509231
Directory /workspace/1.uart_tl_intg_err/latest

Test location /workspace/coverage/default/13.uart_tx_rx.2303606273
Short name T298
Test name
Test status
Simulation time 100489169283 ps
CPU time 76.72 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:53:37 PM PDT 24
Peak memory 199924 kb
Host smart-e2b77ddb-a854-4580-adaf-3d1484e806ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303606273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_rx.2303606273
Directory /workspace/13.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_fifo_full.591144915
Short name T384
Test name
Test status
Simulation time 278908813425 ps
CPU time 67.09 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 199828 kb
Host smart-a9aa9b12-b31b-483f-8c87-8e4f70233ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591144915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_full.591144915
Directory /workspace/20.uart_fifo_full/latest

Test location /workspace/coverage/default/179.uart_fifo_reset.586043885
Short name T169
Test name
Test status
Simulation time 46188156260 ps
CPU time 24.98 seconds
Started Aug 03 04:57:07 PM PDT 24
Finished Aug 03 04:57:32 PM PDT 24
Peak memory 199880 kb
Host smart-1c46f117-94df-417d-a064-910410ce01c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586043885 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 179.uart_fifo_reset.586043885
Directory /workspace/179.uart_fifo_reset/latest

Test location /workspace/coverage/default/219.uart_fifo_reset.2352889173
Short name T172
Test name
Test status
Simulation time 116593589537 ps
CPU time 31.69 seconds
Started Aug 03 04:57:36 PM PDT 24
Finished Aug 03 04:58:08 PM PDT 24
Peak memory 199852 kb
Host smart-be37e7c6-6372-4a71-b66c-5d26f0b2e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352889173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 219.uart_fifo_reset.2352889173
Directory /workspace/219.uart_fifo_reset/latest

Test location /workspace/coverage/default/265.uart_fifo_reset.3654585059
Short name T968
Test name
Test status
Simulation time 17402193338 ps
CPU time 30.68 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 199860 kb
Host smart-d97c2f17-4b16-4de0-9a79-542e129622e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654585059 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 265.uart_fifo_reset.3654585059
Directory /workspace/265.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_stress_all.2948772490
Short name T302
Test name
Test status
Simulation time 157005936276 ps
CPU time 568.34 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 05:03:13 PM PDT 24
Peak memory 199896 kb
Host smart-a3d039bd-9baf-4c45-8257-69f0afde7b6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948772490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_stress_all.2948772490
Directory /workspace/35.uart_stress_all/latest

Test location /workspace/coverage/default/36.uart_stress_all.532233822
Short name T233
Test name
Test status
Simulation time 264808430001 ps
CPU time 646.74 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 05:04:35 PM PDT 24
Peak memory 199296 kb
Host smart-6c74c253-c59c-419f-8bed-fe6ef4d97461
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532233822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_stress_all.532233822
Directory /workspace/36.uart_stress_all/latest

Test location /workspace/coverage/default/112.uart_fifo_reset.28979465
Short name T183
Test name
Test status
Simulation time 78274162440 ps
CPU time 46.35 seconds
Started Aug 03 04:56:25 PM PDT 24
Finished Aug 03 04:57:12 PM PDT 24
Peak memory 199856 kb
Host smart-82dc324e-1156-4b2d-b85d-9971aa6855f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28979465 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 112.uart_fifo_reset.28979465
Directory /workspace/112.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_fifo_reset.1540906645
Short name T132
Test name
Test status
Simulation time 25824385928 ps
CPU time 14.04 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:52:47 PM PDT 24
Peak memory 199768 kb
Host smart-3684be13-42b1-4ad9-a91d-8bf9e66966f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540906645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_reset.1540906645
Directory /workspace/19.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_stress_all_with_rand_reset.1130417868
Short name T178
Test name
Test status
Simulation time 286725826273 ps
CPU time 993.34 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 224704 kb
Host smart-f6b97570-8ddd-4a44-a98f-cbacf58f3985
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130417868 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 26.uart_stress_all_with_rand_reset.1130417868
Directory /workspace/26.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_fifo_reset.2478946458
Short name T212
Test name
Test status
Simulation time 25724230974 ps
CPU time 24.24 seconds
Started Aug 03 04:53:59 PM PDT 24
Finished Aug 03 04:54:23 PM PDT 24
Peak memory 199812 kb
Host smart-1dfc963a-2923-4812-95fc-e5afd585c20e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478946458 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_reset.2478946458
Directory /workspace/39.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_fifo_overflow.255939257
Short name T292
Test name
Test status
Simulation time 93617447437 ps
CPU time 45.05 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:52:36 PM PDT 24
Peak memory 199864 kb
Host smart-7e656503-eddf-4a8f-83a9-04e25490dd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255939257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_overflow.255939257
Directory /workspace/1.uart_fifo_overflow/latest

Test location /workspace/coverage/default/115.uart_fifo_reset.842232068
Short name T511
Test name
Test status
Simulation time 117279034761 ps
CPU time 151.65 seconds
Started Aug 03 04:56:33 PM PDT 24
Finished Aug 03 04:59:05 PM PDT 24
Peak memory 199828 kb
Host smart-9bdf170b-5b4a-4535-a501-2204829044d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842232068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 115.uart_fifo_reset.842232068
Directory /workspace/115.uart_fifo_reset/latest

Test location /workspace/coverage/default/175.uart_fifo_reset.3271561243
Short name T204
Test name
Test status
Simulation time 27447238825 ps
CPU time 18.78 seconds
Started Aug 03 04:57:06 PM PDT 24
Finished Aug 03 04:57:25 PM PDT 24
Peak memory 199820 kb
Host smart-12a75336-54e5-473b-8b50-3ce22f3ee80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271561243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 175.uart_fifo_reset.3271561243
Directory /workspace/175.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_fifo_reset.3465276153
Short name T152
Test name
Test status
Simulation time 132356072560 ps
CPU time 84.33 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:54:24 PM PDT 24
Peak memory 199892 kb
Host smart-4c09146c-02ce-4132-8f9f-75fcf51bf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465276153 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_reset.3465276153
Directory /workspace/25.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_stress_all_with_rand_reset.1092175015
Short name T115
Test name
Test status
Simulation time 133144809676 ps
CPU time 1371.99 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 05:16:23 PM PDT 24
Peak memory 231140 kb
Host smart-46ce48c5-1f31-4c59-a1e7-9e13f0ece516
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092175015 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 32.uart_stress_all_with_rand_reset.1092175015
Directory /workspace/32.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_fifo_reset.2776028736
Short name T228
Test name
Test status
Simulation time 68955705796 ps
CPU time 61.04 seconds
Started Aug 03 04:55:15 PM PDT 24
Finished Aug 03 04:56:16 PM PDT 24
Peak memory 199760 kb
Host smart-153a34c7-2e90-4b4c-84d9-3ae9a2f8bbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776028736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.uart_fifo_reset.2776028736
Directory /workspace/54.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_intg_err.3152746686
Short name T123
Test name
Test status
Simulation time 320284113 ps
CPU time 1.28 seconds
Started Aug 03 04:18:16 PM PDT 24
Finished Aug 03 04:18:17 PM PDT 24
Peak memory 199512 kb
Host smart-16a97024-d3a3-4acc-9e7d-8d02e4646bea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152746686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_intg_err.3152746686
Directory /workspace/0.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_fifo_reset.3788685518
Short name T89
Test name
Test status
Simulation time 44239438919 ps
CPU time 17.73 seconds
Started Aug 03 04:51:45 PM PDT 24
Finished Aug 03 04:52:03 PM PDT 24
Peak memory 199892 kb
Host smart-1314fbad-5e36-4592-89d3-cabe74b935bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788685518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_reset.3788685518
Directory /workspace/0.uart_fifo_reset/latest

Test location /workspace/coverage/default/0.uart_noise_filter.2871227172
Short name T520
Test name
Test status
Simulation time 108048752251 ps
CPU time 49.13 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:52:30 PM PDT 24
Peak memory 208144 kb
Host smart-8f655521-4aac-44ad-9e7d-0eec4026aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871227172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_noise_filter.2871227172
Directory /workspace/0.uart_noise_filter/latest

Test location /workspace/coverage/default/101.uart_fifo_reset.3814306992
Short name T205
Test name
Test status
Simulation time 49006116511 ps
CPU time 42.07 seconds
Started Aug 03 04:56:17 PM PDT 24
Finished Aug 03 04:56:59 PM PDT 24
Peak memory 199824 kb
Host smart-94a3885c-8da1-4dd7-98ae-2eb94c7c6b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814306992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 101.uart_fifo_reset.3814306992
Directory /workspace/101.uart_fifo_reset/latest

Test location /workspace/coverage/default/118.uart_fifo_reset.2552450510
Short name T238
Test name
Test status
Simulation time 83088126279 ps
CPU time 68.16 seconds
Started Aug 03 04:56:30 PM PDT 24
Finished Aug 03 04:57:38 PM PDT 24
Peak memory 199888 kb
Host smart-2e211898-3d6b-494e-8110-82f253151914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552450510 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 118.uart_fifo_reset.2552450510
Directory /workspace/118.uart_fifo_reset/latest

Test location /workspace/coverage/default/119.uart_fifo_reset.626528586
Short name T167
Test name
Test status
Simulation time 81139679071 ps
CPU time 310.93 seconds
Started Aug 03 04:56:34 PM PDT 24
Finished Aug 03 05:01:45 PM PDT 24
Peak memory 199804 kb
Host smart-857340f7-9bc5-4dcc-b17f-b41c1a9f0056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626528586 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 119.uart_fifo_reset.626528586
Directory /workspace/119.uart_fifo_reset/latest

Test location /workspace/coverage/default/123.uart_fifo_reset.1647257414
Short name T1168
Test name
Test status
Simulation time 19302160516 ps
CPU time 34.2 seconds
Started Aug 03 04:56:30 PM PDT 24
Finished Aug 03 04:57:04 PM PDT 24
Peak memory 199936 kb
Host smart-94eeac70-3f77-4dd6-bb73-b8b654ec1217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647257414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 123.uart_fifo_reset.1647257414
Directory /workspace/123.uart_fifo_reset/latest

Test location /workspace/coverage/default/132.uart_fifo_reset.993717221
Short name T200
Test name
Test status
Simulation time 104877427626 ps
CPU time 175.64 seconds
Started Aug 03 04:56:39 PM PDT 24
Finished Aug 03 04:59:34 PM PDT 24
Peak memory 199832 kb
Host smart-34ae317c-c142-427a-a691-a22dcc115676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993717221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 132.uart_fifo_reset.993717221
Directory /workspace/132.uart_fifo_reset/latest

Test location /workspace/coverage/default/134.uart_fifo_reset.2785498188
Short name T230
Test name
Test status
Simulation time 25159732016 ps
CPU time 37.52 seconds
Started Aug 03 04:56:42 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 199908 kb
Host smart-b93a1137-3350-44e2-854b-ada50070c0ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785498188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 134.uart_fifo_reset.2785498188
Directory /workspace/134.uart_fifo_reset/latest

Test location /workspace/coverage/default/153.uart_fifo_reset.229649094
Short name T227
Test name
Test status
Simulation time 80359572458 ps
CPU time 45.51 seconds
Started Aug 03 04:56:51 PM PDT 24
Finished Aug 03 04:57:37 PM PDT 24
Peak memory 199848 kb
Host smart-73312762-832a-4eb2-b542-29b60f151a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229649094 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 153.uart_fifo_reset.229649094
Directory /workspace/153.uart_fifo_reset/latest

Test location /workspace/coverage/default/174.uart_fifo_reset.1709979389
Short name T155
Test name
Test status
Simulation time 122843343183 ps
CPU time 81.05 seconds
Started Aug 03 04:57:06 PM PDT 24
Finished Aug 03 04:58:27 PM PDT 24
Peak memory 199892 kb
Host smart-db972d58-82fe-4a4f-a5da-3305da206e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709979389 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 174.uart_fifo_reset.1709979389
Directory /workspace/174.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_intr.3325222665
Short name T959
Test name
Test status
Simulation time 137554590746 ps
CPU time 43.29 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:16 PM PDT 24
Peak memory 196548 kb
Host smart-1dbda494-2de8-4c23-a44b-73124892a8f3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325222665 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_intr.3325222665
Directory /workspace/19.uart_intr/latest

Test location /workspace/coverage/default/200.uart_fifo_reset.2314278473
Short name T225
Test name
Test status
Simulation time 77974518362 ps
CPU time 56.66 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:58:21 PM PDT 24
Peak memory 199788 kb
Host smart-036a1257-5829-413b-b003-b176d5031d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314278473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 200.uart_fifo_reset.2314278473
Directory /workspace/200.uart_fifo_reset/latest

Test location /workspace/coverage/default/202.uart_fifo_reset.3173716814
Short name T210
Test name
Test status
Simulation time 119293487234 ps
CPU time 51.29 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 199864 kb
Host smart-f5a6eccd-28e4-4f1b-a8d8-100eb50f5f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173716814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 202.uart_fifo_reset.3173716814
Directory /workspace/202.uart_fifo_reset/latest

Test location /workspace/coverage/default/211.uart_fifo_reset.3084102876
Short name T219
Test name
Test status
Simulation time 33154709173 ps
CPU time 15.43 seconds
Started Aug 03 04:57:32 PM PDT 24
Finished Aug 03 04:57:47 PM PDT 24
Peak memory 200028 kb
Host smart-69f3aa60-6dc6-42e9-bde9-23dc82f0201f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084102876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 211.uart_fifo_reset.3084102876
Directory /workspace/211.uart_fifo_reset/latest

Test location /workspace/coverage/default/269.uart_fifo_reset.1535454656
Short name T222
Test name
Test status
Simulation time 38076887696 ps
CPU time 19.84 seconds
Started Aug 03 04:57:56 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 199748 kb
Host smart-c7954772-4c4e-4444-b083-1de207deacca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535454656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 269.uart_fifo_reset.1535454656
Directory /workspace/269.uart_fifo_reset/latest

Test location /workspace/coverage/default/270.uart_fifo_reset.2296629514
Short name T160
Test name
Test status
Simulation time 64551276064 ps
CPU time 92.39 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:59:29 PM PDT 24
Peak memory 199816 kb
Host smart-ac456ebc-c153-4bc6-9c09-a3ac400fd5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296629514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 270.uart_fifo_reset.2296629514
Directory /workspace/270.uart_fifo_reset/latest

Test location /workspace/coverage/default/284.uart_fifo_reset.2598177560
Short name T157
Test name
Test status
Simulation time 119739942773 ps
CPU time 159.14 seconds
Started Aug 03 04:58:11 PM PDT 24
Finished Aug 03 05:00:51 PM PDT 24
Peak memory 199712 kb
Host smart-cd266825-d769-4c7d-a97a-a3417d3a125b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598177560 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 284.uart_fifo_reset.2598177560
Directory /workspace/284.uart_fifo_reset/latest

Test location /workspace/coverage/default/287.uart_fifo_reset.3999151961
Short name T215
Test name
Test status
Simulation time 42078257493 ps
CPU time 16.24 seconds
Started Aug 03 04:58:10 PM PDT 24
Finished Aug 03 04:58:26 PM PDT 24
Peak memory 199848 kb
Host smart-bfd761a7-3a6d-435c-a343-78a3cd527b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999151961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 287.uart_fifo_reset.3999151961
Directory /workspace/287.uart_fifo_reset/latest

Test location /workspace/coverage/default/56.uart_fifo_reset.4248905175
Short name T224
Test name
Test status
Simulation time 11097096737 ps
CPU time 21.59 seconds
Started Aug 03 04:55:22 PM PDT 24
Finished Aug 03 04:55:44 PM PDT 24
Peak memory 199928 kb
Host smart-27f61002-2ef2-4523-8d9c-d853ce27cf23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248905175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.uart_fifo_reset.4248905175
Directory /workspace/56.uart_fifo_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_aliasing.3318556683
Short name T1182
Test name
Test status
Simulation time 54656675 ps
CPU time 0.65 seconds
Started Aug 03 04:22:39 PM PDT 24
Finished Aug 03 04:22:40 PM PDT 24
Peak memory 194980 kb
Host smart-c90503e0-082c-44e2-8882-24953b5219b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318556683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_aliasing.3318556683
Directory /workspace/0.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_bit_bash.3420436700
Short name T1239
Test name
Test status
Simulation time 170113659 ps
CPU time 2.51 seconds
Started Aug 03 04:17:40 PM PDT 24
Finished Aug 03 04:17:42 PM PDT 24
Peak memory 197944 kb
Host smart-03401ff7-10a1-41c5-9a0a-6896d66524c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420436700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_bit_bash.3420436700
Directory /workspace/0.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_hw_reset.2942263006
Short name T1301
Test name
Test status
Simulation time 16511610 ps
CPU time 0.59 seconds
Started Aug 03 04:16:09 PM PDT 24
Finished Aug 03 04:16:10 PM PDT 24
Peak memory 195420 kb
Host smart-eefa043c-a7a4-4cac-95a1-c6869db16c2e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942263006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_hw_reset.2942263006
Directory /workspace/0.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1808878230
Short name T1230
Test name
Test status
Simulation time 45837617 ps
CPU time 0.73 seconds
Started Aug 03 04:16:36 PM PDT 24
Finished Aug 03 04:16:37 PM PDT 24
Peak memory 199072 kb
Host smart-31c35f75-8b19-4a5f-a149-0cef76d6601c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808878230 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.uart_csr_mem_rw_with_rand_reset.1808878230
Directory /workspace/0.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.uart_csr_rw.653714591
Short name T1286
Test name
Test status
Simulation time 12405887 ps
CPU time 0.61 seconds
Started Aug 03 04:18:21 PM PDT 24
Finished Aug 03 04:18:22 PM PDT 24
Peak memory 195600 kb
Host smart-0af6f016-b1e5-4706-b00d-cf02e47d8cc6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653714591 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_csr_rw.653714591
Directory /workspace/0.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.uart_intr_test.4025985746
Short name T1195
Test name
Test status
Simulation time 31461085 ps
CPU time 0.58 seconds
Started Aug 03 04:18:16 PM PDT 24
Finished Aug 03 04:18:17 PM PDT 24
Peak memory 194596 kb
Host smart-a73204de-27f6-49c9-b71b-1c32e5196e7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025985746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_intr_test.4025985746
Directory /workspace/0.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.uart_same_csr_outstanding.739295233
Short name T1316
Test name
Test status
Simulation time 32988881 ps
CPU time 0.79 seconds
Started Aug 03 04:18:03 PM PDT 24
Finished Aug 03 04:18:04 PM PDT 24
Peak memory 197200 kb
Host smart-8530a873-eb08-411c-ae35-e12f6da180c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739295233 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_same_csr_
outstanding.739295233
Directory /workspace/0.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.uart_tl_errors.907541645
Short name T1199
Test name
Test status
Simulation time 505459397 ps
CPU time 1.58 seconds
Started Aug 03 04:17:59 PM PDT 24
Finished Aug 03 04:18:01 PM PDT 24
Peak memory 200616 kb
Host smart-12af3b18-a4cc-40ce-aeb1-b3f59998ebaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907541645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.uart_tl_errors.907541645
Directory /workspace/0.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_aliasing.1398780372
Short name T1284
Test name
Test status
Simulation time 126928214 ps
CPU time 0.7 seconds
Started Aug 03 04:18:51 PM PDT 24
Finished Aug 03 04:18:52 PM PDT 24
Peak memory 195016 kb
Host smart-d3b0deda-8d46-4d96-9b5d-c47042fd4452
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398780372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_aliasing.1398780372
Directory /workspace/1.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_bit_bash.1625869957
Short name T1235
Test name
Test status
Simulation time 273611529 ps
CPU time 2.32 seconds
Started Aug 03 04:18:02 PM PDT 24
Finished Aug 03 04:18:05 PM PDT 24
Peak memory 198072 kb
Host smart-9cea1d92-77b6-4456-b28b-00b3af3273d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625869957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_bit_bash.1625869957
Directory /workspace/1.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_hw_reset.1163961950
Short name T1222
Test name
Test status
Simulation time 15296303 ps
CPU time 0.59 seconds
Started Aug 03 04:16:14 PM PDT 24
Finished Aug 03 04:16:14 PM PDT 24
Peak memory 195456 kb
Host smart-188b0fc3-a840-47d8-9e10-190225e11f5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163961950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_hw_reset.1163961950
Directory /workspace/1.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.423549630
Short name T1269
Test name
Test status
Simulation time 139761651 ps
CPU time 1.12 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 200236 kb
Host smart-e69fa6ca-a8f7-4401-98ec-12fef85271b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423549630 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.uart_csr_mem_rw_with_rand_reset.423549630
Directory /workspace/1.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.uart_csr_rw.2137359022
Short name T1265
Test name
Test status
Simulation time 23800755 ps
CPU time 0.67 seconds
Started Aug 03 04:19:45 PM PDT 24
Finished Aug 03 04:19:45 PM PDT 24
Peak memory 195728 kb
Host smart-e30d3b6e-c779-4ee1-bb7a-54dbe045b94e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137359022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_csr_rw.2137359022
Directory /workspace/1.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.uart_intr_test.4246864314
Short name T1266
Test name
Test status
Simulation time 29034995 ps
CPU time 0.56 seconds
Started Aug 03 04:16:37 PM PDT 24
Finished Aug 03 04:16:38 PM PDT 24
Peak memory 194596 kb
Host smart-b46d7b96-8791-4e19-aa59-de988bd19613
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246864314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_intr_test.4246864314
Directory /workspace/1.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.uart_same_csr_outstanding.1395182583
Short name T1285
Test name
Test status
Simulation time 21485671 ps
CPU time 0.66 seconds
Started Aug 03 04:17:40 PM PDT 24
Finished Aug 03 04:17:40 PM PDT 24
Peak memory 194760 kb
Host smart-287e8378-6eea-403c-b82b-6de0f653b833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395182583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_same_csr
_outstanding.1395182583
Directory /workspace/1.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.uart_tl_errors.2773725590
Short name T1181
Test name
Test status
Simulation time 98158847 ps
CPU time 1.19 seconds
Started Aug 03 04:18:22 PM PDT 24
Finished Aug 03 04:18:23 PM PDT 24
Peak memory 200232 kb
Host smart-876290a9-978f-4bec-be5f-96c0a05c6039
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773725590 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.uart_tl_errors.2773725590
Directory /workspace/1.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.uart_csr_mem_rw_with_rand_reset.1430857414
Short name T1297
Test name
Test status
Simulation time 33048689 ps
CPU time 1 seconds
Started Aug 03 04:17:09 PM PDT 24
Finished Aug 03 04:17:10 PM PDT 24
Peak memory 200024 kb
Host smart-b5468838-0097-480e-83db-b2be869c7cd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430857414 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.uart_csr_mem_rw_with_rand_reset.1430857414
Directory /workspace/10.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.uart_intr_test.37571040
Short name T1187
Test name
Test status
Simulation time 31592084 ps
CPU time 0.58 seconds
Started Aug 03 04:16:25 PM PDT 24
Finished Aug 03 04:16:26 PM PDT 24
Peak memory 194600 kb
Host smart-27c31096-8060-437c-bfab-7c681f60bc9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37571040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_intr_test.37571040
Directory /workspace/10.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.uart_same_csr_outstanding.3117165104
Short name T1276
Test name
Test status
Simulation time 47797095 ps
CPU time 0.61 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 195396 kb
Host smart-26a5c1c9-a9ca-4877-9756-97e0b9850031
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117165104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_same_cs
r_outstanding.3117165104
Directory /workspace/10.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.uart_tl_errors.3215452418
Short name T1201
Test name
Test status
Simulation time 82834183 ps
CPU time 1.41 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:03 PM PDT 24
Peak memory 200228 kb
Host smart-dba41768-a772-47f0-97a7-a01f0b18dff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215452418 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.uart_tl_errors.3215452418
Directory /workspace/10.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_mem_rw_with_rand_reset.2892658255
Short name T1293
Test name
Test status
Simulation time 410257567 ps
CPU time 1.23 seconds
Started Aug 03 04:17:44 PM PDT 24
Finished Aug 03 04:17:45 PM PDT 24
Peak memory 200260 kb
Host smart-f06b67ed-bd60-490c-8631-917543a51950
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892658255 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.uart_csr_mem_rw_with_rand_reset.2892658255
Directory /workspace/11.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.uart_csr_rw.3889242595
Short name T1204
Test name
Test status
Simulation time 20242186 ps
CPU time 0.67 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 194492 kb
Host smart-51aab5a5-bd21-434d-8da7-c0f1d2e86e6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889242595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_csr_rw.3889242595
Directory /workspace/11.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.uart_intr_test.2886738578
Short name T1272
Test name
Test status
Simulation time 38854844 ps
CPU time 0.57 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 194576 kb
Host smart-8163d1b4-2c11-4a46-8a97-913235ccc948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886738578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_intr_test.2886738578
Directory /workspace/11.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_errors.3187714474
Short name T1216
Test name
Test status
Simulation time 165784754 ps
CPU time 2.05 seconds
Started Aug 03 04:18:11 PM PDT 24
Finished Aug 03 04:18:13 PM PDT 24
Peak memory 200260 kb
Host smart-e29d266d-ef7a-47d7-9691-17796bea83b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187714474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_errors.3187714474
Directory /workspace/11.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.uart_tl_intg_err.1349560652
Short name T79
Test name
Test status
Simulation time 207362307 ps
CPU time 1.33 seconds
Started Aug 03 04:16:41 PM PDT 24
Finished Aug 03 04:16:42 PM PDT 24
Peak memory 199888 kb
Host smart-f97edce9-d8f7-466f-8b01-35f4ba820225
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349560652 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.uart_tl_intg_err.1349560652
Directory /workspace/11.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_mem_rw_with_rand_reset.3459136122
Short name T1310
Test name
Test status
Simulation time 22965169 ps
CPU time 0.84 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 197780 kb
Host smart-ab33f796-15e8-4a72-91f0-85608ec30deb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459136122 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.uart_csr_mem_rw_with_rand_reset.3459136122
Directory /workspace/12.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.uart_csr_rw.4096331784
Short name T67
Test name
Test status
Simulation time 16081985 ps
CPU time 0.65 seconds
Started Aug 03 04:17:09 PM PDT 24
Finished Aug 03 04:17:10 PM PDT 24
Peak memory 195876 kb
Host smart-793f5fb6-3e09-412a-b838-3c3f25589dab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096331784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_csr_rw.4096331784
Directory /workspace/12.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.uart_intr_test.3183409668
Short name T1240
Test name
Test status
Simulation time 57160713 ps
CPU time 0.59 seconds
Started Aug 03 04:17:28 PM PDT 24
Finished Aug 03 04:17:29 PM PDT 24
Peak memory 194604 kb
Host smart-848f26a9-73cb-4eb9-899c-0628133bcb55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183409668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_intr_test.3183409668
Directory /workspace/12.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.uart_same_csr_outstanding.3376510443
Short name T1317
Test name
Test status
Simulation time 15500081 ps
CPU time 0.78 seconds
Started Aug 03 04:17:07 PM PDT 24
Finished Aug 03 04:17:08 PM PDT 24
Peak memory 195908 kb
Host smart-50b55401-2482-4d0a-8543-8df8116320ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376510443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_same_cs
r_outstanding.3376510443
Directory /workspace/12.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_errors.1193165400
Short name T1271
Test name
Test status
Simulation time 154108507 ps
CPU time 1.13 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 199012 kb
Host smart-8c33e09e-d51b-4b46-b11e-197a7ca71edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193165400 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_errors.1193165400
Directory /workspace/12.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.uart_tl_intg_err.1321007315
Short name T80
Test name
Test status
Simulation time 61876598 ps
CPU time 0.97 seconds
Started Aug 03 04:17:51 PM PDT 24
Finished Aug 03 04:17:52 PM PDT 24
Peak memory 199276 kb
Host smart-ce975610-ea80-4e14-819c-03d27550dc2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321007315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.uart_tl_intg_err.1321007315
Directory /workspace/12.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_mem_rw_with_rand_reset.593019852
Short name T1257
Test name
Test status
Simulation time 100191921 ps
CPU time 0.87 seconds
Started Aug 03 04:16:34 PM PDT 24
Finished Aug 03 04:16:35 PM PDT 24
Peak memory 199348 kb
Host smart-a1431559-3941-4b76-a6d6-c3a7d1c25ee8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593019852 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.uart_csr_mem_rw_with_rand_reset.593019852
Directory /workspace/13.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.uart_csr_rw.4188151804
Short name T1252
Test name
Test status
Simulation time 164872968 ps
CPU time 0.62 seconds
Started Aug 03 04:16:48 PM PDT 24
Finished Aug 03 04:16:49 PM PDT 24
Peak memory 196108 kb
Host smart-b6a56bf9-197b-4518-adc2-6846a29e8f46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188151804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_csr_rw.4188151804
Directory /workspace/13.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.uart_intr_test.4286624979
Short name T1248
Test name
Test status
Simulation time 145803685 ps
CPU time 0.56 seconds
Started Aug 03 04:17:15 PM PDT 24
Finished Aug 03 04:17:15 PM PDT 24
Peak memory 194596 kb
Host smart-0477e4f4-3ea4-4b89-bf7c-aef53505b5dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286624979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_intr_test.4286624979
Directory /workspace/13.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.uart_same_csr_outstanding.325428000
Short name T64
Test name
Test status
Simulation time 39837039 ps
CPU time 0.69 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:02 PM PDT 24
Peak memory 195760 kb
Host smart-849e3a85-2960-4d19-8999-1c511c17a222
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325428000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_same_csr
_outstanding.325428000
Directory /workspace/13.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_errors.1874710710
Short name T1270
Test name
Test status
Simulation time 74115825 ps
CPU time 1.05 seconds
Started Aug 03 04:17:37 PM PDT 24
Finished Aug 03 04:17:38 PM PDT 24
Peak memory 200012 kb
Host smart-61277c70-6309-4f56-bccc-429c778c872f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874710710 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_errors.1874710710
Directory /workspace/13.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.uart_tl_intg_err.824470018
Short name T1312
Test name
Test status
Simulation time 753278770 ps
CPU time 1.33 seconds
Started Aug 03 04:18:26 PM PDT 24
Finished Aug 03 04:18:27 PM PDT 24
Peak memory 199612 kb
Host smart-fe8f6d2b-c641-4a4d-b78c-5c6b711a5718
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824470018 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.uart_tl_intg_err.824470018
Directory /workspace/13.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_mem_rw_with_rand_reset.3951589977
Short name T1289
Test name
Test status
Simulation time 342630761 ps
CPU time 0.94 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:02 PM PDT 24
Peak memory 199848 kb
Host smart-4d8a807d-a961-4308-a93f-953c4a3f2bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951589977 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.uart_csr_mem_rw_with_rand_reset.3951589977
Directory /workspace/14.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.uart_csr_rw.1853867950
Short name T1197
Test name
Test status
Simulation time 68507696 ps
CPU time 0.69 seconds
Started Aug 03 04:17:59 PM PDT 24
Finished Aug 03 04:18:00 PM PDT 24
Peak memory 195756 kb
Host smart-d731c914-d07d-4b8c-b911-c63b244a830c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853867950 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_csr_rw.1853867950
Directory /workspace/14.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.uart_intr_test.970213941
Short name T1251
Test name
Test status
Simulation time 41756545 ps
CPU time 0.56 seconds
Started Aug 03 04:17:16 PM PDT 24
Finished Aug 03 04:17:17 PM PDT 24
Peak memory 194592 kb
Host smart-052823a8-e0c5-41fe-a71c-d35d0acff9ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970213941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_intr_test.970213941
Directory /workspace/14.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.uart_same_csr_outstanding.2637817108
Short name T1290
Test name
Test status
Simulation time 54657695 ps
CPU time 0.75 seconds
Started Aug 03 04:17:24 PM PDT 24
Finished Aug 03 04:17:25 PM PDT 24
Peak memory 197284 kb
Host smart-88dbdd90-7231-49d8-8f05-6f71ba170288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637817108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_same_cs
r_outstanding.2637817108
Directory /workspace/14.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_errors.2588993305
Short name T1203
Test name
Test status
Simulation time 67264968 ps
CPU time 1.81 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:03 PM PDT 24
Peak memory 200228 kb
Host smart-85692d28-b761-497a-a53c-7a2ceb321193
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588993305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_errors.2588993305
Directory /workspace/14.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.uart_tl_intg_err.3763220303
Short name T81
Test name
Test status
Simulation time 52708646 ps
CPU time 1.05 seconds
Started Aug 03 04:17:23 PM PDT 24
Finished Aug 03 04:17:24 PM PDT 24
Peak memory 199204 kb
Host smart-8a282749-8fc4-46ea-9015-97c78509c3cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763220303 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.uart_tl_intg_err.3763220303
Directory /workspace/14.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_mem_rw_with_rand_reset.409037167
Short name T1309
Test name
Test status
Simulation time 75587674 ps
CPU time 0.8 seconds
Started Aug 03 04:17:04 PM PDT 24
Finished Aug 03 04:17:05 PM PDT 24
Peak memory 198744 kb
Host smart-733cf459-0498-4b0b-ad37-e77810fde42a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409037167 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.uart_csr_mem_rw_with_rand_reset.409037167
Directory /workspace/15.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.uart_csr_rw.2834413054
Short name T1225
Test name
Test status
Simulation time 14423899 ps
CPU time 0.73 seconds
Started Aug 03 04:16:54 PM PDT 24
Finished Aug 03 04:16:54 PM PDT 24
Peak memory 195664 kb
Host smart-fa19e595-63b8-4284-a05c-07c21eb67342
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834413054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_csr_rw.2834413054
Directory /workspace/15.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.uart_intr_test.2160166741
Short name T1292
Test name
Test status
Simulation time 36735822 ps
CPU time 0.56 seconds
Started Aug 03 04:17:39 PM PDT 24
Finished Aug 03 04:17:40 PM PDT 24
Peak memory 194568 kb
Host smart-8b1393db-0516-4b8e-9c73-0c376a3f68ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160166741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_intr_test.2160166741
Directory /workspace/15.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.uart_same_csr_outstanding.1547675916
Short name T1205
Test name
Test status
Simulation time 44030367 ps
CPU time 0.63 seconds
Started Aug 03 04:18:52 PM PDT 24
Finished Aug 03 04:18:53 PM PDT 24
Peak memory 195692 kb
Host smart-fecb0eb6-49eb-44be-bc1b-0e118c0b0406
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547675916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_same_cs
r_outstanding.1547675916
Directory /workspace/15.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_errors.2196728090
Short name T1308
Test name
Test status
Simulation time 23104000 ps
CPU time 1.12 seconds
Started Aug 03 04:17:52 PM PDT 24
Finished Aug 03 04:17:53 PM PDT 24
Peak memory 200264 kb
Host smart-14a23cc5-2a52-4e83-adf8-d6352821d23a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196728090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_errors.2196728090
Directory /workspace/15.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.uart_tl_intg_err.830693383
Short name T78
Test name
Test status
Simulation time 68080337 ps
CPU time 1.26 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 198080 kb
Host smart-38bd60da-c783-4e2f-8461-f15f6944546e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830693383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.uart_tl_intg_err.830693383
Directory /workspace/15.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_mem_rw_with_rand_reset.151904114
Short name T1247
Test name
Test status
Simulation time 24215354 ps
CPU time 0.76 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 199092 kb
Host smart-8d7dbd14-c8b0-48fb-9fe3-0edb1446dafd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151904114 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.uart_csr_mem_rw_with_rand_reset.151904114
Directory /workspace/16.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.uart_csr_rw.658276350
Short name T1228
Test name
Test status
Simulation time 25423781 ps
CPU time 0.59 seconds
Started Aug 03 04:17:37 PM PDT 24
Finished Aug 03 04:17:37 PM PDT 24
Peak memory 195608 kb
Host smart-d376d7d5-792f-493e-b923-0f00aa636287
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658276350 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_csr_rw.658276350
Directory /workspace/16.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.uart_intr_test.222686810
Short name T1256
Test name
Test status
Simulation time 16253977 ps
CPU time 0.66 seconds
Started Aug 03 04:16:45 PM PDT 24
Finished Aug 03 04:16:46 PM PDT 24
Peak memory 194600 kb
Host smart-3920ee1d-e3ab-4fdc-91e8-e2963c847bc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222686810 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_intr_test.222686810
Directory /workspace/16.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.uart_same_csr_outstanding.668554294
Short name T1198
Test name
Test status
Simulation time 88093554 ps
CPU time 0.66 seconds
Started Aug 03 04:18:51 PM PDT 24
Finished Aug 03 04:18:52 PM PDT 24
Peak memory 195844 kb
Host smart-fa31e884-2ded-428e-b037-12d689dd7ebb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668554294 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_same_csr
_outstanding.668554294
Directory /workspace/16.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_errors.980643934
Short name T1194
Test name
Test status
Simulation time 1180134397 ps
CPU time 2.16 seconds
Started Aug 03 04:17:04 PM PDT 24
Finished Aug 03 04:17:06 PM PDT 24
Peak memory 200272 kb
Host smart-70ac5788-81d2-46c4-8428-4ff42f20b0b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980643934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_errors.980643934
Directory /workspace/16.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.uart_tl_intg_err.3132190629
Short name T72
Test name
Test status
Simulation time 143147521 ps
CPU time 0.91 seconds
Started Aug 03 04:16:21 PM PDT 24
Finished Aug 03 04:16:22 PM PDT 24
Peak memory 198892 kb
Host smart-c5fa6024-9397-4d19-948b-987fcc31eb25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132190629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.uart_tl_intg_err.3132190629
Directory /workspace/16.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_mem_rw_with_rand_reset.3868985628
Short name T1279
Test name
Test status
Simulation time 22713781 ps
CPU time 0.66 seconds
Started Aug 03 04:16:19 PM PDT 24
Finished Aug 03 04:16:20 PM PDT 24
Peak memory 197996 kb
Host smart-14dcb070-bde9-4f24-b70b-10be751ad98d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868985628 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.uart_csr_mem_rw_with_rand_reset.3868985628
Directory /workspace/17.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.uart_csr_rw.564931416
Short name T70
Test name
Test status
Simulation time 18847619 ps
CPU time 0.63 seconds
Started Aug 03 04:17:57 PM PDT 24
Finished Aug 03 04:17:58 PM PDT 24
Peak memory 195616 kb
Host smart-f7cbfaa0-8f99-44c0-af3a-0eef3edbb7e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564931416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_csr_rw.564931416
Directory /workspace/17.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.uart_intr_test.3023294889
Short name T1213
Test name
Test status
Simulation time 21776658 ps
CPU time 0.59 seconds
Started Aug 03 04:16:56 PM PDT 24
Finished Aug 03 04:16:57 PM PDT 24
Peak memory 194576 kb
Host smart-00d931bf-e666-4a77-aeec-cec20c371737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023294889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_intr_test.3023294889
Directory /workspace/17.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.uart_same_csr_outstanding.2962310879
Short name T1304
Test name
Test status
Simulation time 117130315 ps
CPU time 0.82 seconds
Started Aug 03 04:18:52 PM PDT 24
Finished Aug 03 04:18:53 PM PDT 24
Peak memory 197108 kb
Host smart-311d6b6b-3b38-40a2-8892-32b14a105a19
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962310879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_same_cs
r_outstanding.2962310879
Directory /workspace/17.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_errors.2781275443
Short name T1218
Test name
Test status
Simulation time 64570372 ps
CPU time 1.67 seconds
Started Aug 03 04:17:08 PM PDT 24
Finished Aug 03 04:17:10 PM PDT 24
Peak memory 200264 kb
Host smart-385e4265-190a-4fca-9a78-d95c60794432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781275443 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_errors.2781275443
Directory /workspace/17.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.uart_tl_intg_err.637599452
Short name T1192
Test name
Test status
Simulation time 105716853 ps
CPU time 1.02 seconds
Started Aug 03 04:17:04 PM PDT 24
Finished Aug 03 04:17:05 PM PDT 24
Peak memory 199484 kb
Host smart-17eeec8b-480e-4042-af4c-9bf6a52dc675
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637599452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.uart_tl_intg_err.637599452
Directory /workspace/17.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_mem_rw_with_rand_reset.3182349592
Short name T1219
Test name
Test status
Simulation time 19159418 ps
CPU time 0.66 seconds
Started Aug 03 04:17:58 PM PDT 24
Finished Aug 03 04:17:59 PM PDT 24
Peak memory 197896 kb
Host smart-d4ddf9ad-cc4b-4b26-8269-af4eccf04380
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182349592 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.uart_csr_mem_rw_with_rand_reset.3182349592
Directory /workspace/18.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.uart_csr_rw.2803785065
Short name T71
Test name
Test status
Simulation time 15474700 ps
CPU time 0.65 seconds
Started Aug 03 04:16:49 PM PDT 24
Finished Aug 03 04:16:50 PM PDT 24
Peak memory 195844 kb
Host smart-35de83eb-a6f1-44c0-9f6e-528ad8f03e94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803785065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_csr_rw.2803785065
Directory /workspace/18.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.uart_intr_test.963038859
Short name T1274
Test name
Test status
Simulation time 77275849 ps
CPU time 0.61 seconds
Started Aug 03 04:17:17 PM PDT 24
Finished Aug 03 04:17:18 PM PDT 24
Peak memory 194560 kb
Host smart-9b658e17-9dcd-4dff-b48f-e3c533b75028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963038859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_intr_test.963038859
Directory /workspace/18.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.uart_same_csr_outstanding.244312664
Short name T1212
Test name
Test status
Simulation time 17019151 ps
CPU time 0.84 seconds
Started Aug 03 04:16:56 PM PDT 24
Finished Aug 03 04:16:57 PM PDT 24
Peak memory 197696 kb
Host smart-6a76710c-410b-4506-a09f-f6126847aa0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244312664 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_same_csr
_outstanding.244312664
Directory /workspace/18.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_errors.1357503832
Short name T1294
Test name
Test status
Simulation time 47952353 ps
CPU time 2.31 seconds
Started Aug 03 04:17:29 PM PDT 24
Finished Aug 03 04:17:31 PM PDT 24
Peak memory 200260 kb
Host smart-ee20bec4-1edb-4a55-9224-300838104b26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357503832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_errors.1357503832
Directory /workspace/18.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.uart_tl_intg_err.588331118
Short name T1207
Test name
Test status
Simulation time 419135477 ps
CPU time 1.25 seconds
Started Aug 03 04:17:04 PM PDT 24
Finished Aug 03 04:17:06 PM PDT 24
Peak memory 199316 kb
Host smart-223fbb44-1342-4da3-bf11-05ac9ef912e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588331118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.uart_tl_intg_err.588331118
Directory /workspace/18.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_mem_rw_with_rand_reset.668752016
Short name T1220
Test name
Test status
Simulation time 92169749 ps
CPU time 0.77 seconds
Started Aug 03 04:17:56 PM PDT 24
Finished Aug 03 04:17:57 PM PDT 24
Peak memory 198400 kb
Host smart-195f5d79-1d0f-4a8f-a89d-ae7691c9f299
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668752016 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.uart_csr_mem_rw_with_rand_reset.668752016
Directory /workspace/19.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.uart_csr_rw.362858151
Short name T1234
Test name
Test status
Simulation time 16366268 ps
CPU time 0.65 seconds
Started Aug 03 04:17:19 PM PDT 24
Finished Aug 03 04:17:19 PM PDT 24
Peak memory 195912 kb
Host smart-52649a17-7495-4597-be4e-427afe2e19e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362858151 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_csr_rw.362858151
Directory /workspace/19.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.uart_intr_test.3111363839
Short name T1255
Test name
Test status
Simulation time 25940453 ps
CPU time 0.58 seconds
Started Aug 03 04:18:08 PM PDT 24
Finished Aug 03 04:18:08 PM PDT 24
Peak memory 194592 kb
Host smart-1bedc69b-ca4f-4696-85bd-40e8d49c815a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111363839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_intr_test.3111363839
Directory /workspace/19.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.uart_same_csr_outstanding.2729181253
Short name T68
Test name
Test status
Simulation time 56490289 ps
CPU time 0.61 seconds
Started Aug 03 04:18:54 PM PDT 24
Finished Aug 03 04:18:55 PM PDT 24
Peak memory 195792 kb
Host smart-ba01ff4a-5547-407f-b5a6-35aebc468610
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729181253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_same_cs
r_outstanding.2729181253
Directory /workspace/19.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_errors.2743866307
Short name T1298
Test name
Test status
Simulation time 173954922 ps
CPU time 1.72 seconds
Started Aug 03 04:17:48 PM PDT 24
Finished Aug 03 04:17:50 PM PDT 24
Peak memory 200256 kb
Host smart-827d93ef-76c0-4ff6-9aa9-b37ca8c646d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743866307 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_errors.2743866307
Directory /workspace/19.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.uart_tl_intg_err.1369442291
Short name T73
Test name
Test status
Simulation time 128285979 ps
CPU time 1.29 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 197552 kb
Host smart-e217b7a3-c326-4564-88dc-fdbc9fddccc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369442291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.uart_tl_intg_err.1369442291
Directory /workspace/19.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_aliasing.3794574277
Short name T1241
Test name
Test status
Simulation time 47506225 ps
CPU time 0.74 seconds
Started Aug 03 04:16:27 PM PDT 24
Finished Aug 03 04:16:28 PM PDT 24
Peak memory 196568 kb
Host smart-112e5e18-5bb8-4d97-9714-82a17e1d84c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794574277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_aliasing.3794574277
Directory /workspace/2.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_bit_bash.736164183
Short name T1183
Test name
Test status
Simulation time 73298460 ps
CPU time 2.33 seconds
Started Aug 03 04:18:10 PM PDT 24
Finished Aug 03 04:18:12 PM PDT 24
Peak memory 197788 kb
Host smart-c7553769-4f93-41c4-aa66-a66a6666e475
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736164183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_bit_bash.736164183
Directory /workspace/2.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_hw_reset.3826868957
Short name T1208
Test name
Test status
Simulation time 11759928 ps
CPU time 0.6 seconds
Started Aug 03 04:22:32 PM PDT 24
Finished Aug 03 04:22:33 PM PDT 24
Peak memory 195600 kb
Host smart-a6fb0cd5-a85c-48c7-a65c-48897dbbb281
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826868957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_hw_reset.3826868957
Directory /workspace/2.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2635923184
Short name T1250
Test name
Test status
Simulation time 30364031 ps
CPU time 0.8 seconds
Started Aug 03 04:17:39 PM PDT 24
Finished Aug 03 04:17:40 PM PDT 24
Peak memory 200016 kb
Host smart-22497cd2-3ceb-4c1b-ab56-e65756020160
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635923184 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.uart_csr_mem_rw_with_rand_reset.2635923184
Directory /workspace/2.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.uart_csr_rw.4031920653
Short name T1190
Test name
Test status
Simulation time 34836881 ps
CPU time 0.65 seconds
Started Aug 03 04:17:09 PM PDT 24
Finished Aug 03 04:17:10 PM PDT 24
Peak memory 195848 kb
Host smart-cc3eb256-f4c8-4a15-8c15-d40138b4ccef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031920653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_csr_rw.4031920653
Directory /workspace/2.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.uart_intr_test.1818375297
Short name T1184
Test name
Test status
Simulation time 37635997 ps
CPU time 0.66 seconds
Started Aug 03 04:18:22 PM PDT 24
Finished Aug 03 04:18:23 PM PDT 24
Peak memory 194564 kb
Host smart-5e77cc8d-654c-44b1-b251-ad8994b760cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818375297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_intr_test.1818375297
Directory /workspace/2.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.uart_same_csr_outstanding.3951785703
Short name T1305
Test name
Test status
Simulation time 46777657 ps
CPU time 0.75 seconds
Started Aug 03 04:18:08 PM PDT 24
Finished Aug 03 04:18:09 PM PDT 24
Peak memory 197228 kb
Host smart-7b1d25c2-2122-4b39-8b9e-ab875bdcb673
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951785703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_same_csr
_outstanding.3951785703
Directory /workspace/2.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_errors.105053392
Short name T1244
Test name
Test status
Simulation time 57451581 ps
CPU time 0.95 seconds
Started Aug 03 04:22:27 PM PDT 24
Finished Aug 03 04:22:28 PM PDT 24
Peak memory 200008 kb
Host smart-f4376cbb-364b-400d-b01a-04ba768fbd97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105053392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_errors.105053392
Directory /workspace/2.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.uart_tl_intg_err.3813500847
Short name T122
Test name
Test status
Simulation time 70919481 ps
CPU time 1.39 seconds
Started Aug 03 04:18:05 PM PDT 24
Finished Aug 03 04:18:07 PM PDT 24
Peak memory 199428 kb
Host smart-c77b4727-c144-4f85-9978-f1f7a08df701
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813500847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.uart_tl_intg_err.3813500847
Directory /workspace/2.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.uart_intr_test.2274651546
Short name T1191
Test name
Test status
Simulation time 17791738 ps
CPU time 0.62 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 192572 kb
Host smart-fef58fd3-67f5-4653-81a3-c1f4df91db08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274651546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.uart_intr_test.2274651546
Directory /workspace/20.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.uart_intr_test.1327339965
Short name T1300
Test name
Test status
Simulation time 14951490 ps
CPU time 0.63 seconds
Started Aug 03 04:18:28 PM PDT 24
Finished Aug 03 04:18:29 PM PDT 24
Peak memory 194580 kb
Host smart-6ed0d487-45ab-48a4-93f7-8bcd3c4c5419
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327339965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.uart_intr_test.1327339965
Directory /workspace/21.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.uart_intr_test.421366090
Short name T1209
Test name
Test status
Simulation time 13870435 ps
CPU time 0.59 seconds
Started Aug 03 04:17:51 PM PDT 24
Finished Aug 03 04:17:52 PM PDT 24
Peak memory 194560 kb
Host smart-201a2325-2cec-473c-95b5-22b20fab6bb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421366090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.uart_intr_test.421366090
Directory /workspace/22.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.uart_intr_test.2774155147
Short name T1313
Test name
Test status
Simulation time 29589852 ps
CPU time 0.6 seconds
Started Aug 03 04:17:57 PM PDT 24
Finished Aug 03 04:17:57 PM PDT 24
Peak memory 194596 kb
Host smart-d92b3ea5-ae1c-48fc-9278-503452f12d85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774155147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.uart_intr_test.2774155147
Directory /workspace/23.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.uart_intr_test.2435654859
Short name T1260
Test name
Test status
Simulation time 40164426 ps
CPU time 0.57 seconds
Started Aug 03 04:18:37 PM PDT 24
Finished Aug 03 04:18:38 PM PDT 24
Peak memory 193792 kb
Host smart-f8a44b27-f1b3-44de-9cb8-5c895150302e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435654859 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.uart_intr_test.2435654859
Directory /workspace/24.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.uart_intr_test.2444138702
Short name T1217
Test name
Test status
Simulation time 15030928 ps
CPU time 0.57 seconds
Started Aug 03 04:17:53 PM PDT 24
Finished Aug 03 04:17:54 PM PDT 24
Peak memory 194564 kb
Host smart-f548f7c2-8dc1-4e21-b933-ad0be0afdd03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444138702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.uart_intr_test.2444138702
Directory /workspace/25.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.uart_intr_test.4138201616
Short name T1263
Test name
Test status
Simulation time 13235000 ps
CPU time 0.58 seconds
Started Aug 03 04:17:53 PM PDT 24
Finished Aug 03 04:17:53 PM PDT 24
Peak memory 194532 kb
Host smart-0ececbe1-587b-4b59-ad5d-3dfaaa9bbd8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138201616 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.uart_intr_test.4138201616
Directory /workspace/26.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.uart_intr_test.1006872884
Short name T1262
Test name
Test status
Simulation time 52874182 ps
CPU time 0.57 seconds
Started Aug 03 04:17:53 PM PDT 24
Finished Aug 03 04:17:54 PM PDT 24
Peak memory 194604 kb
Host smart-070e1919-2f31-440a-97d5-501b703257c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006872884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.uart_intr_test.1006872884
Directory /workspace/27.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.uart_intr_test.1789338795
Short name T1280
Test name
Test status
Simulation time 92041772 ps
CPU time 0.58 seconds
Started Aug 03 04:17:53 PM PDT 24
Finished Aug 03 04:17:53 PM PDT 24
Peak memory 193688 kb
Host smart-f8bde275-588a-4eb9-9892-27871a1b4217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789338795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.uart_intr_test.1789338795
Directory /workspace/28.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.uart_intr_test.1842088956
Short name T1231
Test name
Test status
Simulation time 43751234 ps
CPU time 0.58 seconds
Started Aug 03 04:18:27 PM PDT 24
Finished Aug 03 04:18:28 PM PDT 24
Peak memory 194572 kb
Host smart-9bdd1157-3f7d-47d9-8a1c-8e34339e090a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842088956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.uart_intr_test.1842088956
Directory /workspace/29.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_aliasing.1637061209
Short name T1283
Test name
Test status
Simulation time 90200144 ps
CPU time 0.77 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 196460 kb
Host smart-f9c3ed94-ded1-4788-b71a-68190c2171e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637061209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_aliasing.1637061209
Directory /workspace/3.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_bit_bash.348563042
Short name T1296
Test name
Test status
Simulation time 36335142 ps
CPU time 1.55 seconds
Started Aug 03 04:17:35 PM PDT 24
Finished Aug 03 04:17:36 PM PDT 24
Peak memory 198152 kb
Host smart-5a1f3b54-8f86-41f9-bd9a-92c24e825ded
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348563042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_bit_bash.348563042
Directory /workspace/3.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_hw_reset.2655569196
Short name T1186
Test name
Test status
Simulation time 15354212 ps
CPU time 0.57 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 195564 kb
Host smart-7d5da0da-ff9a-4dfd-9c55-4e07b63c95bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655569196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_hw_reset.2655569196
Directory /workspace/3.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3151360766
Short name T1223
Test name
Test status
Simulation time 33764458 ps
CPU time 0.91 seconds
Started Aug 03 04:18:12 PM PDT 24
Finished Aug 03 04:18:13 PM PDT 24
Peak memory 200008 kb
Host smart-69d23c4c-029e-483c-81e5-a04aa1663ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151360766 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.uart_csr_mem_rw_with_rand_reset.3151360766
Directory /workspace/3.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.uart_csr_rw.727549727
Short name T1253
Test name
Test status
Simulation time 25980902 ps
CPU time 0.63 seconds
Started Aug 03 04:22:51 PM PDT 24
Finished Aug 03 04:22:52 PM PDT 24
Peak memory 195740 kb
Host smart-5ceae816-c775-44d8-a920-4b4a7ec179ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727549727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_csr_rw.727549727
Directory /workspace/3.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.uart_intr_test.1902152678
Short name T1302
Test name
Test status
Simulation time 41558894 ps
CPU time 0.55 seconds
Started Aug 03 04:16:43 PM PDT 24
Finished Aug 03 04:16:44 PM PDT 24
Peak memory 194600 kb
Host smart-1bf184f0-d242-4f7e-9dde-f247c73b2ff0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902152678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_intr_test.1902152678
Directory /workspace/3.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.uart_same_csr_outstanding.1766456699
Short name T63
Test name
Test status
Simulation time 115694897 ps
CPU time 0.76 seconds
Started Aug 03 04:22:15 PM PDT 24
Finished Aug 03 04:22:16 PM PDT 24
Peak memory 197160 kb
Host smart-c051158f-8ee1-4e90-9cf7-0861bea36556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766456699 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_same_csr
_outstanding.1766456699
Directory /workspace/3.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_errors.387013916
Short name T1202
Test name
Test status
Simulation time 504789797 ps
CPU time 1.57 seconds
Started Aug 03 04:18:07 PM PDT 24
Finished Aug 03 04:18:08 PM PDT 24
Peak memory 200248 kb
Host smart-667425a6-3f21-4140-ad73-09ceb5085382
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387013916 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_errors.387013916
Directory /workspace/3.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.uart_tl_intg_err.3673127988
Short name T77
Test name
Test status
Simulation time 322477030 ps
CPU time 1.29 seconds
Started Aug 03 04:18:16 PM PDT 24
Finished Aug 03 04:18:17 PM PDT 24
Peak memory 199536 kb
Host smart-3e587e38-72de-43eb-9556-85f90b49f1d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673127988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.uart_tl_intg_err.3673127988
Directory /workspace/3.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.uart_intr_test.695937646
Short name T1196
Test name
Test status
Simulation time 39508996 ps
CPU time 0.59 seconds
Started Aug 03 04:21:06 PM PDT 24
Finished Aug 03 04:21:07 PM PDT 24
Peak memory 193812 kb
Host smart-056007b2-cc59-4203-98e1-8f08875f664a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695937646 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.uart_intr_test.695937646
Directory /workspace/30.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.uart_intr_test.3907917762
Short name T1189
Test name
Test status
Simulation time 13214860 ps
CPU time 0.54 seconds
Started Aug 03 04:21:24 PM PDT 24
Finished Aug 03 04:21:24 PM PDT 24
Peak memory 194536 kb
Host smart-207b0304-f3b3-4112-9ab4-8dcede208442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907917762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.uart_intr_test.3907917762
Directory /workspace/31.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.uart_intr_test.4283775771
Short name T1238
Test name
Test status
Simulation time 26556944 ps
CPU time 0.61 seconds
Started Aug 03 04:19:43 PM PDT 24
Finished Aug 03 04:19:44 PM PDT 24
Peak memory 194576 kb
Host smart-5d5bfffd-79dd-43af-b2be-f5894a7e5664
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283775771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.uart_intr_test.4283775771
Directory /workspace/32.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.uart_intr_test.4075165355
Short name T1200
Test name
Test status
Simulation time 37457192 ps
CPU time 0.58 seconds
Started Aug 03 04:18:30 PM PDT 24
Finished Aug 03 04:18:32 PM PDT 24
Peak memory 193380 kb
Host smart-f3cb711f-6b0e-4e45-830e-29ab94fce2dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075165355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.uart_intr_test.4075165355
Directory /workspace/33.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.uart_intr_test.96871843
Short name T1259
Test name
Test status
Simulation time 14741707 ps
CPU time 0.6 seconds
Started Aug 03 04:19:21 PM PDT 24
Finished Aug 03 04:19:22 PM PDT 24
Peak memory 194608 kb
Host smart-bca56abd-a224-4141-aacf-9aa31b0e95b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96871843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.uart_intr_test.96871843
Directory /workspace/34.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.uart_intr_test.1530947593
Short name T1315
Test name
Test status
Simulation time 11607946 ps
CPU time 0.62 seconds
Started Aug 03 04:18:30 PM PDT 24
Finished Aug 03 04:18:32 PM PDT 24
Peak memory 193468 kb
Host smart-0e942819-5018-4103-9a8a-5e4d400a0d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530947593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.uart_intr_test.1530947593
Directory /workspace/35.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.uart_intr_test.468016315
Short name T1229
Test name
Test status
Simulation time 14866700 ps
CPU time 0.6 seconds
Started Aug 03 04:19:03 PM PDT 24
Finished Aug 03 04:19:03 PM PDT 24
Peak memory 194600 kb
Host smart-bf1da0c1-d9bf-4977-8736-f3a38094c629
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468016315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.uart_intr_test.468016315
Directory /workspace/36.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.uart_intr_test.253910173
Short name T1180
Test name
Test status
Simulation time 59056363 ps
CPU time 0.56 seconds
Started Aug 03 04:18:46 PM PDT 24
Finished Aug 03 04:18:46 PM PDT 24
Peak memory 194556 kb
Host smart-98abf4d6-5a49-48d5-986a-b107a44c90fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253910173 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.uart_intr_test.253910173
Directory /workspace/37.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.uart_intr_test.3796000695
Short name T1221
Test name
Test status
Simulation time 15359859 ps
CPU time 0.6 seconds
Started Aug 03 04:17:44 PM PDT 24
Finished Aug 03 04:17:44 PM PDT 24
Peak memory 194572 kb
Host smart-88da3da4-1d6b-487a-a0c7-10e6c66a558b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796000695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.uart_intr_test.3796000695
Directory /workspace/38.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.uart_intr_test.3854619840
Short name T1282
Test name
Test status
Simulation time 194591451 ps
CPU time 0.68 seconds
Started Aug 03 04:20:42 PM PDT 24
Finished Aug 03 04:20:44 PM PDT 24
Peak memory 192776 kb
Host smart-2a029fd8-c869-4399-93d3-c99e9b2458aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854619840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.uart_intr_test.3854619840
Directory /workspace/39.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_aliasing.2652764187
Short name T1306
Test name
Test status
Simulation time 47302633 ps
CPU time 0.84 seconds
Started Aug 03 04:21:15 PM PDT 24
Finished Aug 03 04:21:16 PM PDT 24
Peak memory 196932 kb
Host smart-e6385d65-ef16-49c6-9b1b-99cf377c38cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652764187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_aliasing.2652764187
Directory /workspace/4.uart_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_bit_bash.3195145144
Short name T1242
Test name
Test status
Simulation time 123508513 ps
CPU time 1.54 seconds
Started Aug 03 04:17:11 PM PDT 24
Finished Aug 03 04:17:12 PM PDT 24
Peak memory 198180 kb
Host smart-31c73c82-64a1-426b-87a9-a5b229eb5b6b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195145144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_bit_bash.3195145144
Directory /workspace/4.uart_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_hw_reset.2181955777
Short name T55
Test name
Test status
Simulation time 49749267 ps
CPU time 0.59 seconds
Started Aug 03 04:18:40 PM PDT 24
Finished Aug 03 04:18:41 PM PDT 24
Peak memory 195616 kb
Host smart-8fb6d055-21d1-4475-a79b-d5228afc6afe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181955777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_hw_reset.2181955777
Directory /workspace/4.uart_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.1661981886
Short name T1246
Test name
Test status
Simulation time 81437351 ps
CPU time 1.09 seconds
Started Aug 03 04:17:08 PM PDT 24
Finished Aug 03 04:17:09 PM PDT 24
Peak memory 200212 kb
Host smart-ee2c3457-354a-40a1-8d23-cf6567740656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661981886 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.uart_csr_mem_rw_with_rand_reset.1661981886
Directory /workspace/4.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.uart_csr_rw.896019282
Short name T1267
Test name
Test status
Simulation time 64165552 ps
CPU time 0.58 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 195512 kb
Host smart-2da5b9b9-fb15-4c6d-910d-3dae7170b1b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896019282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_csr_rw.896019282
Directory /workspace/4.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.uart_intr_test.2822873653
Short name T1227
Test name
Test status
Simulation time 14582549 ps
CPU time 0.65 seconds
Started Aug 03 04:17:35 PM PDT 24
Finished Aug 03 04:17:36 PM PDT 24
Peak memory 194564 kb
Host smart-caa814e9-a638-4ef7-aa0d-ef011a8afb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822873653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_intr_test.2822873653
Directory /workspace/4.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.uart_same_csr_outstanding.3983302600
Short name T1193
Test name
Test status
Simulation time 26795333 ps
CPU time 0.69 seconds
Started Aug 03 04:21:45 PM PDT 24
Finished Aug 03 04:21:46 PM PDT 24
Peak memory 196196 kb
Host smart-abb56d5e-9270-4363-8060-5c2018b11ed8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983302600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_same_csr
_outstanding.3983302600
Directory /workspace/4.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_errors.2344377388
Short name T1237
Test name
Test status
Simulation time 130172999 ps
CPU time 2.84 seconds
Started Aug 03 04:18:07 PM PDT 24
Finished Aug 03 04:18:10 PM PDT 24
Peak memory 200208 kb
Host smart-e4b84715-90f8-4dbd-8bd8-b24eb48a447b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344377388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_errors.2344377388
Directory /workspace/4.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.uart_tl_intg_err.4095389336
Short name T1281
Test name
Test status
Simulation time 46081691 ps
CPU time 0.94 seconds
Started Aug 03 04:16:58 PM PDT 24
Finished Aug 03 04:16:59 PM PDT 24
Peak memory 199180 kb
Host smart-2adaad2e-eb3d-4371-abdb-2b5c0deed6ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095389336 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.uart_tl_intg_err.4095389336
Directory /workspace/4.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.uart_intr_test.2461894071
Short name T1307
Test name
Test status
Simulation time 163915092 ps
CPU time 0.57 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 194544 kb
Host smart-786492e1-1555-4f3c-b50d-49eaf4bc09b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461894071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.uart_intr_test.2461894071
Directory /workspace/40.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.uart_intr_test.790896749
Short name T1206
Test name
Test status
Simulation time 17183183 ps
CPU time 0.6 seconds
Started Aug 03 04:20:57 PM PDT 24
Finished Aug 03 04:20:58 PM PDT 24
Peak memory 194540 kb
Host smart-d32ba9b3-3389-46d4-a650-5bc8846cb80f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790896749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.uart_intr_test.790896749
Directory /workspace/41.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.uart_intr_test.313815771
Short name T1249
Test name
Test status
Simulation time 14072516 ps
CPU time 0.55 seconds
Started Aug 03 04:21:33 PM PDT 24
Finished Aug 03 04:21:34 PM PDT 24
Peak memory 194492 kb
Host smart-fd708624-313e-42a9-b2e8-892b6ca3e839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313815771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.uart_intr_test.313815771
Directory /workspace/42.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.uart_intr_test.1876494447
Short name T1275
Test name
Test status
Simulation time 13087633 ps
CPU time 0.56 seconds
Started Aug 03 04:21:33 PM PDT 24
Finished Aug 03 04:21:34 PM PDT 24
Peak memory 194216 kb
Host smart-4f9dd637-0c27-46db-8b7d-fffef5494e5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876494447 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.uart_intr_test.1876494447
Directory /workspace/43.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.uart_intr_test.3348290583
Short name T1273
Test name
Test status
Simulation time 51996994 ps
CPU time 0.59 seconds
Started Aug 03 04:18:40 PM PDT 24
Finished Aug 03 04:18:40 PM PDT 24
Peak memory 194600 kb
Host smart-2371c102-10dd-4099-903f-2616a017bd4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348290583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.uart_intr_test.3348290583
Directory /workspace/44.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.uart_intr_test.2133722099
Short name T1258
Test name
Test status
Simulation time 89138418 ps
CPU time 0.57 seconds
Started Aug 03 04:21:08 PM PDT 24
Finished Aug 03 04:21:09 PM PDT 24
Peak memory 193652 kb
Host smart-b3e791de-9835-4b90-ac88-2a68b45c31c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133722099 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.uart_intr_test.2133722099
Directory /workspace/45.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.uart_intr_test.1618535941
Short name T1295
Test name
Test status
Simulation time 30890404 ps
CPU time 0.58 seconds
Started Aug 03 04:17:04 PM PDT 24
Finished Aug 03 04:17:05 PM PDT 24
Peak memory 194596 kb
Host smart-fad4bd80-554d-487e-840f-2276836bd3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618535941 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.uart_intr_test.1618535941
Directory /workspace/46.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.uart_intr_test.64603316
Short name T1224
Test name
Test status
Simulation time 22587564 ps
CPU time 0.58 seconds
Started Aug 03 04:18:38 PM PDT 24
Finished Aug 03 04:18:39 PM PDT 24
Peak memory 194496 kb
Host smart-1d13b80b-2ecd-4364-92ec-204bbcf8420b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64603316 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.uart_intr_test.64603316
Directory /workspace/47.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.uart_intr_test.288190429
Short name T1185
Test name
Test status
Simulation time 23145770 ps
CPU time 0.6 seconds
Started Aug 03 04:19:59 PM PDT 24
Finished Aug 03 04:19:59 PM PDT 24
Peak memory 194576 kb
Host smart-6c245115-874e-464d-bed8-9e90015994f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288190429 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.uart_intr_test.288190429
Directory /workspace/48.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.uart_intr_test.3488726779
Short name T1188
Test name
Test status
Simulation time 47380550 ps
CPU time 0.6 seconds
Started Aug 03 04:21:47 PM PDT 24
Finished Aug 03 04:21:48 PM PDT 24
Peak memory 194636 kb
Host smart-faec97a6-4596-4c1b-962a-1edbc01e1dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488726779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.uart_intr_test.3488726779
Directory /workspace/49.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_mem_rw_with_rand_reset.955308709
Short name T1215
Test name
Test status
Simulation time 25363571 ps
CPU time 0.79 seconds
Started Aug 03 04:16:26 PM PDT 24
Finished Aug 03 04:16:27 PM PDT 24
Peak memory 198740 kb
Host smart-ac1b1d90-fb1b-477e-b6bd-655abbc9b2d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955308709 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.uart_csr_mem_rw_with_rand_reset.955308709
Directory /workspace/5.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.uart_csr_rw.684130017
Short name T65
Test name
Test status
Simulation time 29155810 ps
CPU time 0.59 seconds
Started Aug 03 04:21:52 PM PDT 24
Finished Aug 03 04:21:53 PM PDT 24
Peak memory 195636 kb
Host smart-28461a9f-33d1-471e-b06a-285ffd2ad6f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684130017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_csr_rw.684130017
Directory /workspace/5.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.uart_intr_test.4013435467
Short name T1236
Test name
Test status
Simulation time 46064532 ps
CPU time 0.63 seconds
Started Aug 03 04:18:22 PM PDT 24
Finished Aug 03 04:18:23 PM PDT 24
Peak memory 194564 kb
Host smart-95d31881-b4c5-42cd-af32-9bf9ea652142
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013435467 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_intr_test.4013435467
Directory /workspace/5.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.uart_same_csr_outstanding.4061510032
Short name T66
Test name
Test status
Simulation time 18544514 ps
CPU time 0.74 seconds
Started Aug 03 04:16:27 PM PDT 24
Finished Aug 03 04:16:28 PM PDT 24
Peak memory 197260 kb
Host smart-77798174-dda2-4da2-997d-a5758263e50b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061510032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_same_csr
_outstanding.4061510032
Directory /workspace/5.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_errors.1969560528
Short name T1268
Test name
Test status
Simulation time 99175223 ps
CPU time 1.38 seconds
Started Aug 03 04:18:24 PM PDT 24
Finished Aug 03 04:18:26 PM PDT 24
Peak memory 200264 kb
Host smart-3a1009cb-c842-478f-90e3-735b8ac16c33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969560528 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_errors.1969560528
Directory /workspace/5.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.uart_tl_intg_err.204453228
Short name T74
Test name
Test status
Simulation time 168173798 ps
CPU time 0.93 seconds
Started Aug 03 04:22:14 PM PDT 24
Finished Aug 03 04:22:15 PM PDT 24
Peak memory 199088 kb
Host smart-d8fd5d3d-fff6-47f1-97cf-1b0cec8605e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204453228 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.uart_tl_intg_err.204453228
Directory /workspace/5.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_mem_rw_with_rand_reset.4198857263
Short name T1214
Test name
Test status
Simulation time 30381736 ps
CPU time 0.9 seconds
Started Aug 03 04:17:52 PM PDT 24
Finished Aug 03 04:17:53 PM PDT 24
Peak memory 199976 kb
Host smart-76976d3f-bde6-435e-8b47-95a35513c093
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198857263 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.uart_csr_mem_rw_with_rand_reset.4198857263
Directory /workspace/6.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.uart_csr_rw.2044966086
Short name T1277
Test name
Test status
Simulation time 22968220 ps
CPU time 0.7 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:02 PM PDT 24
Peak memory 195672 kb
Host smart-efa22534-1799-40b9-96a3-d9cf6d709429
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044966086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_csr_rw.2044966086
Directory /workspace/6.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.uart_intr_test.2490284273
Short name T1254
Test name
Test status
Simulation time 94053037 ps
CPU time 0.57 seconds
Started Aug 03 04:16:19 PM PDT 24
Finished Aug 03 04:16:20 PM PDT 24
Peak memory 194556 kb
Host smart-26838017-81c3-465f-b886-1c7f31bbe2e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490284273 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_intr_test.2490284273
Directory /workspace/6.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.uart_same_csr_outstanding.1792275010
Short name T62
Test name
Test status
Simulation time 48217670 ps
CPU time 0.63 seconds
Started Aug 03 04:16:27 PM PDT 24
Finished Aug 03 04:16:28 PM PDT 24
Peak memory 195892 kb
Host smart-85af6567-a288-44fc-972b-a4dcefb88cfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792275010 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_same_csr
_outstanding.1792275010
Directory /workspace/6.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_errors.2499322692
Short name T1210
Test name
Test status
Simulation time 461782363 ps
CPU time 2.37 seconds
Started Aug 03 04:17:53 PM PDT 24
Finished Aug 03 04:17:55 PM PDT 24
Peak memory 199196 kb
Host smart-da0133fd-568c-494b-9d1e-7c3bc6588b08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499322692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_errors.2499322692
Directory /workspace/6.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.uart_tl_intg_err.3293445185
Short name T1291
Test name
Test status
Simulation time 261132803 ps
CPU time 1.3 seconds
Started Aug 03 04:18:04 PM PDT 24
Finished Aug 03 04:18:06 PM PDT 24
Peak memory 199588 kb
Host smart-0747681c-0fc0-498f-b10e-86551d4c0de4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293445185 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.uart_tl_intg_err.3293445185
Directory /workspace/6.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_mem_rw_with_rand_reset.815236241
Short name T1288
Test name
Test status
Simulation time 28852978 ps
CPU time 1.19 seconds
Started Aug 03 04:16:19 PM PDT 24
Finished Aug 03 04:16:20 PM PDT 24
Peak memory 200148 kb
Host smart-da38cbb4-b434-4801-a6b5-56ed5e90053e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815236241 -assert nopostproc +UVM_TESTNAME=
uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.uart_csr_mem_rw_with_rand_reset.815236241
Directory /workspace/7.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.uart_csr_rw.1827695753
Short name T1211
Test name
Test status
Simulation time 17786341 ps
CPU time 0.61 seconds
Started Aug 03 04:17:59 PM PDT 24
Finished Aug 03 04:18:00 PM PDT 24
Peak memory 195960 kb
Host smart-254cd224-8d54-4a4d-9dbb-388f476f29f9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827695753 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_csr_rw.1827695753
Directory /workspace/7.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.uart_intr_test.1994648571
Short name T1311
Test name
Test status
Simulation time 53844082 ps
CPU time 0.66 seconds
Started Aug 03 04:16:28 PM PDT 24
Finished Aug 03 04:16:29 PM PDT 24
Peak memory 194576 kb
Host smart-6a7f631c-1605-4484-8e60-2e9b2712faa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994648571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_intr_test.1994648571
Directory /workspace/7.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.uart_same_csr_outstanding.2164598051
Short name T1299
Test name
Test status
Simulation time 64638832 ps
CPU time 0.65 seconds
Started Aug 03 04:16:56 PM PDT 24
Finished Aug 03 04:16:57 PM PDT 24
Peak memory 195752 kb
Host smart-62281d66-e234-47c2-9408-3a447ab2a975
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164598051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_same_csr
_outstanding.2164598051
Directory /workspace/7.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_errors.2812816393
Short name T1179
Test name
Test status
Simulation time 301849816 ps
CPU time 1.38 seconds
Started Aug 03 04:18:08 PM PDT 24
Finished Aug 03 04:18:09 PM PDT 24
Peak memory 200224 kb
Host smart-74b9df74-4621-423f-9b60-45f1042de2c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812816393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_errors.2812816393
Directory /workspace/7.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.uart_tl_intg_err.2378373803
Short name T1278
Test name
Test status
Simulation time 118183886 ps
CPU time 0.96 seconds
Started Aug 03 04:24:00 PM PDT 24
Finished Aug 03 04:24:01 PM PDT 24
Peak memory 198180 kb
Host smart-3eb9aefc-47bd-4e90-8a3a-3e4212c05d00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378373803 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.uart_tl_intg_err.2378373803
Directory /workspace/7.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_mem_rw_with_rand_reset.3660482400
Short name T1243
Test name
Test status
Simulation time 31236670 ps
CPU time 0.75 seconds
Started Aug 03 04:23:00 PM PDT 24
Finished Aug 03 04:23:01 PM PDT 24
Peak memory 199276 kb
Host smart-ec791bef-786a-4001-b9cf-ffacbeb74725
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660482400 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.uart_csr_mem_rw_with_rand_reset.3660482400
Directory /workspace/8.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.uart_csr_rw.1719482601
Short name T56
Test name
Test status
Simulation time 13027933 ps
CPU time 0.69 seconds
Started Aug 03 04:18:24 PM PDT 24
Finished Aug 03 04:18:25 PM PDT 24
Peak memory 195980 kb
Host smart-cb076d8a-e513-4151-a241-c80374086915
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719482601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_csr_rw.1719482601
Directory /workspace/8.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.uart_intr_test.1195936053
Short name T1232
Test name
Test status
Simulation time 40173413 ps
CPU time 0.59 seconds
Started Aug 03 04:20:03 PM PDT 24
Finished Aug 03 04:20:04 PM PDT 24
Peak memory 194568 kb
Host smart-2a00b150-b766-4b00-841d-e34233d551b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195936053 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_intr_test.1195936053
Directory /workspace/8.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.uart_same_csr_outstanding.1742781312
Short name T1303
Test name
Test status
Simulation time 100074036 ps
CPU time 0.76 seconds
Started Aug 03 04:20:26 PM PDT 24
Finished Aug 03 04:20:27 PM PDT 24
Peak memory 197076 kb
Host smart-61493aaa-1681-4bee-a454-649f51f553e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742781312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_same_csr
_outstanding.1742781312
Directory /workspace/8.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_errors.2465497506
Short name T1264
Test name
Test status
Simulation time 190166153 ps
CPU time 2.08 seconds
Started Aug 03 04:21:25 PM PDT 24
Finished Aug 03 04:21:27 PM PDT 24
Peak memory 200276 kb
Host smart-e33f30e3-b592-490e-91ac-df78a56b1184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465497506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_errors.2465497506
Directory /workspace/8.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.uart_tl_intg_err.1335642242
Short name T75
Test name
Test status
Simulation time 45195830 ps
CPU time 0.94 seconds
Started Aug 03 04:18:56 PM PDT 24
Finished Aug 03 04:18:57 PM PDT 24
Peak memory 198812 kb
Host smart-e0532eab-ba25-48d1-bf1c-b716e09e72b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335642242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.uart_tl_intg_err.1335642242
Directory /workspace/8.uart_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_mem_rw_with_rand_reset.1398187820
Short name T1314
Test name
Test status
Simulation time 16551925 ps
CPU time 0.67 seconds
Started Aug 03 04:17:10 PM PDT 24
Finished Aug 03 04:17:10 PM PDT 24
Peak memory 197952 kb
Host smart-3931acd7-6e56-4dc8-bd9c-02f3ff0d5394
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398187820 -assert nopostproc +UVM_TESTNAME
=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.uart_csr_mem_rw_with_rand_reset.1398187820
Directory /workspace/9.uart_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.uart_csr_rw.1771098442
Short name T1226
Test name
Test status
Simulation time 24034385 ps
CPU time 0.57 seconds
Started Aug 03 04:16:37 PM PDT 24
Finished Aug 03 04:16:37 PM PDT 24
Peak memory 195608 kb
Host smart-8f49f304-a0d9-4c8b-b962-3acafec54aa2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771098442 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_csr_rw.1771098442
Directory /workspace/9.uart_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.uart_intr_test.816008425
Short name T1261
Test name
Test status
Simulation time 69180021 ps
CPU time 0.62 seconds
Started Aug 03 04:17:01 PM PDT 24
Finished Aug 03 04:17:02 PM PDT 24
Peak memory 194564 kb
Host smart-dc4f81a4-047b-41a3-9f19-4aa511b9fba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816008425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_intr_test.816008425
Directory /workspace/9.uart_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.uart_same_csr_outstanding.1587565858
Short name T1245
Test name
Test status
Simulation time 13509522 ps
CPU time 0.64 seconds
Started Aug 03 04:16:15 PM PDT 24
Finished Aug 03 04:16:16 PM PDT 24
Peak memory 195864 kb
Host smart-7e8caa1a-9520-4cf9-8130-bf78bcff7e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587565858 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_same_csr
_outstanding.1587565858
Directory /workspace/9.uart_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_errors.2525554277
Short name T1233
Test name
Test status
Simulation time 189265638 ps
CPU time 2.21 seconds
Started Aug 03 04:18:22 PM PDT 24
Finished Aug 03 04:18:25 PM PDT 24
Peak memory 200260 kb
Host smart-1f128053-a921-4fa0-a3b9-136497795efc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525554277 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_errors.2525554277
Directory /workspace/9.uart_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.uart_tl_intg_err.2351658244
Short name T1287
Test name
Test status
Simulation time 270677364 ps
CPU time 0.92 seconds
Started Aug 03 04:23:09 PM PDT 24
Finished Aug 03 04:23:11 PM PDT 24
Peak memory 198980 kb
Host smart-6a1b6937-fe51-488e-aafa-59a034b7033a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351658244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.uart_tl_intg_err.2351658244
Directory /workspace/9.uart_tl_intg_err/latest

Test location /workspace/coverage/default/0.uart_alert_test.516842341
Short name T427
Test name
Test status
Simulation time 38979153 ps
CPU time 0.58 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:51:42 PM PDT 24
Peak memory 195544 kb
Host smart-eff89c8c-b72e-4fa8-9be8-8d70829962ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516842341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_alert_test.516842341
Directory /workspace/0.uart_alert_test/latest

Test location /workspace/coverage/default/0.uart_fifo_full.1011025693
Short name T539
Test name
Test status
Simulation time 14336790888 ps
CPU time 11.96 seconds
Started Aug 03 04:51:44 PM PDT 24
Finished Aug 03 04:51:56 PM PDT 24
Peak memory 199772 kb
Host smart-b4510d5f-78e9-4cf2-9767-d0cbb43f59c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011025693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_full.1011025693
Directory /workspace/0.uart_fifo_full/latest

Test location /workspace/coverage/default/0.uart_fifo_overflow.3193694551
Short name T556
Test name
Test status
Simulation time 188321571734 ps
CPU time 50.13 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:52:36 PM PDT 24
Peak memory 199868 kb
Host smart-f72ddc64-5a9d-45b1-b736-91c34b28b6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193694551 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_fifo_overflow.3193694551
Directory /workspace/0.uart_fifo_overflow/latest

Test location /workspace/coverage/default/0.uart_intr.3065593575
Short name T948
Test name
Test status
Simulation time 10347795276 ps
CPU time 9.21 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 04:51:52 PM PDT 24
Peak memory 199684 kb
Host smart-3be6aa43-c049-4f72-b1cd-caf14f5b5d32
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065593575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_intr.3065593575
Directory /workspace/0.uart_intr/latest

Test location /workspace/coverage/default/0.uart_long_xfer_wo_dly.2376445715
Short name T779
Test name
Test status
Simulation time 108531958566 ps
CPU time 516.46 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 05:00:20 PM PDT 24
Peak memory 199896 kb
Host smart-44f8f65b-f5d7-4b88-8fed-3e9bd405413d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2376445715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_long_xfer_wo_dly.2376445715
Directory /workspace/0.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/0.uart_loopback.2093889957
Short name T834
Test name
Test status
Simulation time 5662986898 ps
CPU time 4.81 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 04:51:47 PM PDT 24
Peak memory 198336 kb
Host smart-490c0844-f8f8-487f-b7bf-eef081b932a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093889957 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_loopback.2093889957
Directory /workspace/0.uart_loopback/latest

Test location /workspace/coverage/default/0.uart_perf.939758822
Short name T854
Test name
Test status
Simulation time 2347975043 ps
CPU time 54.32 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 199896 kb
Host smart-3db631f2-21be-4ed5-ba59-1e8bed55a597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939758822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_perf.939758822
Directory /workspace/0.uart_perf/latest

Test location /workspace/coverage/default/0.uart_rx_oversample.3383932581
Short name T515
Test name
Test status
Simulation time 5053165616 ps
CPU time 21.54 seconds
Started Aug 03 04:51:45 PM PDT 24
Finished Aug 03 04:52:07 PM PDT 24
Peak memory 198036 kb
Host smart-cf4170b2-7adf-45b6-aa5f-02e7ed8644fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383932581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_oversample.3383932581
Directory /workspace/0.uart_rx_oversample/latest

Test location /workspace/coverage/default/0.uart_rx_parity_err.2700133524
Short name T535
Test name
Test status
Simulation time 117216029763 ps
CPU time 98.75 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 04:53:22 PM PDT 24
Peak memory 199940 kb
Host smart-84c4fdcd-cc7d-4011-9785-712e1e426fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700133524 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_parity_err.2700133524
Directory /workspace/0.uart_rx_parity_err/latest

Test location /workspace/coverage/default/0.uart_rx_start_bit_filter.2985987382
Short name T429
Test name
Test status
Simulation time 4106089055 ps
CPU time 1.72 seconds
Started Aug 03 04:51:39 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 196000 kb
Host smart-665b86c2-b470-48e6-b33a-5779e27e17ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985987382 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_rx_start_bit_filter.2985987382
Directory /workspace/0.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/0.uart_sec_cm.3746190019
Short name T83
Test name
Test status
Simulation time 72636471 ps
CPU time 0.86 seconds
Started Aug 03 04:51:45 PM PDT 24
Finished Aug 03 04:51:46 PM PDT 24
Peak memory 218228 kb
Host smart-523b7b61-de6d-491a-910e-825bf1243fa5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746190019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_sec_cm.3746190019
Directory /workspace/0.uart_sec_cm/latest

Test location /workspace/coverage/default/0.uart_smoke.1178867944
Short name T1004
Test name
Test status
Simulation time 283543165 ps
CPU time 1.13 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 198664 kb
Host smart-17753317-390b-4707-b72b-2c46da46f146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178867944 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_smoke.1178867944
Directory /workspace/0.uart_smoke/latest

Test location /workspace/coverage/default/0.uart_stress_all.747061939
Short name T698
Test name
Test status
Simulation time 144760799325 ps
CPU time 486.74 seconds
Started Aug 03 04:51:40 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 199856 kb
Host smart-218cf952-9efb-45b8-8029-ca5e9ed119a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747061939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_stress_all.747061939
Directory /workspace/0.uart_stress_all/latest

Test location /workspace/coverage/default/0.uart_stress_all_with_rand_reset.294121252
Short name T661
Test name
Test status
Simulation time 866663466299 ps
CPU time 1349.91 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 05:14:12 PM PDT 24
Peak memory 225132 kb
Host smart-02aeaeb2-96ea-409e-b15b-0b4389be6552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294121252 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 0.uart_stress_all_with_rand_reset.294121252
Directory /workspace/0.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.uart_tx_ovrd.1465698112
Short name T373
Test name
Test status
Simulation time 8132233719 ps
CPU time 1.62 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 199800 kb
Host smart-58b2c3c0-c0ea-415b-96de-e7935a813f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465698112 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_ovrd.1465698112
Directory /workspace/0.uart_tx_ovrd/latest

Test location /workspace/coverage/default/0.uart_tx_rx.2029246290
Short name T1019
Test name
Test status
Simulation time 106044081650 ps
CPU time 44.44 seconds
Started Aug 03 04:51:39 PM PDT 24
Finished Aug 03 04:52:23 PM PDT 24
Peak memory 199772 kb
Host smart-24da5141-8166-4a20-a17f-ecfba16c5809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029246290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.uart_tx_rx.2029246290
Directory /workspace/0.uart_tx_rx/latest

Test location /workspace/coverage/default/1.uart_alert_test.4113859295
Short name T1017
Test name
Test status
Simulation time 27614090 ps
CPU time 0.56 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:51:48 PM PDT 24
Peak memory 195580 kb
Host smart-42b4ac1e-f128-4757-baaa-fb97beea957a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113859295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_alert_test.4113859295
Directory /workspace/1.uart_alert_test/latest

Test location /workspace/coverage/default/1.uart_fifo_full.4179561108
Short name T1041
Test name
Test status
Simulation time 42518056309 ps
CPU time 62.71 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 199832 kb
Host smart-a2e7841d-e887-4df4-99cf-17f047e1ca30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179561108 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_full.4179561108
Directory /workspace/1.uart_fifo_full/latest

Test location /workspace/coverage/default/1.uart_fifo_reset.1963679623
Short name T328
Test name
Test status
Simulation time 52470058833 ps
CPU time 81.59 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 199900 kb
Host smart-4dad0943-6df3-4920-b495-e2ec5f75dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963679623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_fifo_reset.1963679623
Directory /workspace/1.uart_fifo_reset/latest

Test location /workspace/coverage/default/1.uart_intr.1291783466
Short name T296
Test name
Test status
Simulation time 165071048486 ps
CPU time 243.22 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:55:52 PM PDT 24
Peak memory 199864 kb
Host smart-21a5347d-b138-4beb-8a65-98ddb88686c6
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291783466 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_intr.1291783466
Directory /workspace/1.uart_intr/latest

Test location /workspace/coverage/default/1.uart_long_xfer_wo_dly.993989413
Short name T590
Test name
Test status
Simulation time 107852060905 ps
CPU time 1058.61 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 199876 kb
Host smart-5abced47-b444-4d8e-91ef-a18a4e1e4dd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=993989413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_long_xfer_wo_dly.993989413
Directory /workspace/1.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/1.uart_loopback.206169056
Short name T1061
Test name
Test status
Simulation time 1221564758 ps
CPU time 2.35 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:51:48 PM PDT 24
Peak memory 197252 kb
Host smart-6d0e76f7-90d0-450f-8f80-f7e3791d3c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206169056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_loopback.206169056
Directory /workspace/1.uart_loopback/latest

Test location /workspace/coverage/default/1.uart_noise_filter.107603124
Short name T957
Test name
Test status
Simulation time 20418158604 ps
CPU time 29.01 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 199888 kb
Host smart-2aab4cc7-0fec-4786-857e-523d0a1cb2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107603124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_noise_filter.107603124
Directory /workspace/1.uart_noise_filter/latest

Test location /workspace/coverage/default/1.uart_perf.1781715183
Short name T983
Test name
Test status
Simulation time 8547058348 ps
CPU time 500.27 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199848 kb
Host smart-903012b5-db95-4f53-8ac5-55378de1ca7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1781715183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_perf.1781715183
Directory /workspace/1.uart_perf/latest

Test location /workspace/coverage/default/1.uart_rx_oversample.2033540260
Short name T743
Test name
Test status
Simulation time 6605409726 ps
CPU time 27.61 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:52:14 PM PDT 24
Peak memory 198944 kb
Host smart-940e834c-3931-484a-8a0c-d468c128cc5c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2033540260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_oversample.2033540260
Directory /workspace/1.uart_rx_oversample/latest

Test location /workspace/coverage/default/1.uart_rx_parity_err.2445161695
Short name T793
Test name
Test status
Simulation time 86861017360 ps
CPU time 124.65 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 199912 kb
Host smart-6e5d930e-45e8-4fa9-a0a7-8454eb87e911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445161695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_parity_err.2445161695
Directory /workspace/1.uart_rx_parity_err/latest

Test location /workspace/coverage/default/1.uart_rx_start_bit_filter.288462956
Short name T1018
Test name
Test status
Simulation time 41628138491 ps
CPU time 62.19 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 195756 kb
Host smart-a8a9f1d2-48e8-4be4-b009-4180e2802659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288462956 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_rx_start_bit_filter.288462956
Directory /workspace/1.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/1.uart_sec_cm.2427466171
Short name T33
Test name
Test status
Simulation time 161878492 ps
CPU time 0.9 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:51:51 PM PDT 24
Peak memory 218432 kb
Host smart-41becd5c-5804-41b2-8734-0c5697a6a6e6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427466171 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_sec_cm.2427466171
Directory /workspace/1.uart_sec_cm/latest

Test location /workspace/coverage/default/1.uart_smoke.1425130229
Short name T303
Test name
Test status
Simulation time 5906787124 ps
CPU time 24.3 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:52:11 PM PDT 24
Peak memory 199860 kb
Host smart-d4d4d6f3-d69e-4e3d-9a4e-e7a6bb5b0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425130229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_smoke.1425130229
Directory /workspace/1.uart_smoke/latest

Test location /workspace/coverage/default/1.uart_stress_all_with_rand_reset.3546668542
Short name T57
Test name
Test status
Simulation time 201650994340 ps
CPU time 1722.25 seconds
Started Aug 03 04:51:44 PM PDT 24
Finished Aug 03 05:20:27 PM PDT 24
Peak memory 224712 kb
Host smart-86e7b66a-ae8f-4a47-9a4c-638ecc8ad056
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546668542 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 1.uart_stress_all_with_rand_reset.3546668542
Directory /workspace/1.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.uart_tx_ovrd.799668169
Short name T290
Test name
Test status
Simulation time 1157035470 ps
CPU time 1.86 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:51:51 PM PDT 24
Peak memory 198856 kb
Host smart-eccf30ba-cffd-4d28-ac2d-d97c4a7d02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799668169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_ovrd.799668169
Directory /workspace/1.uart_tx_ovrd/latest

Test location /workspace/coverage/default/1.uart_tx_rx.826507572
Short name T780
Test name
Test status
Simulation time 57038849198 ps
CPU time 110.53 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:53:40 PM PDT 24
Peak memory 199756 kb
Host smart-8ff2c377-f572-4257-92a8-76735f381a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826507572 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.uart_tx_rx.826507572
Directory /workspace/1.uart_tx_rx/latest

Test location /workspace/coverage/default/10.uart_fifo_full.2173148962
Short name T149
Test name
Test status
Simulation time 97445891772 ps
CPU time 40.39 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:52:50 PM PDT 24
Peak memory 199836 kb
Host smart-857ec26c-1513-4480-8fd0-4fdeaa3d8ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173148962 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_full.2173148962
Directory /workspace/10.uart_fifo_full/latest

Test location /workspace/coverage/default/10.uart_fifo_overflow.775631711
Short name T824
Test name
Test status
Simulation time 69603940587 ps
CPU time 32.65 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:52:38 PM PDT 24
Peak memory 199840 kb
Host smart-26794d43-9344-46b1-a7e4-95811dff5cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775631711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_overflow.775631711
Directory /workspace/10.uart_fifo_overflow/latest

Test location /workspace/coverage/default/10.uart_fifo_reset.127053399
Short name T851
Test name
Test status
Simulation time 104027271243 ps
CPU time 39.59 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:47 PM PDT 24
Peak memory 199692 kb
Host smart-40d1a075-f80f-48d1-bf40-f22c047db25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127053399 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_fifo_reset.127053399
Directory /workspace/10.uart_fifo_reset/latest

Test location /workspace/coverage/default/10.uart_intr.3861944898
Short name T897
Test name
Test status
Simulation time 38900881298 ps
CPU time 62.93 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:53:11 PM PDT 24
Peak memory 199812 kb
Host smart-d8e9c37a-25b1-4d2e-8d9b-417da925498f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861944898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_intr.3861944898
Directory /workspace/10.uart_intr/latest

Test location /workspace/coverage/default/10.uart_long_xfer_wo_dly.1053166317
Short name T343
Test name
Test status
Simulation time 162313246498 ps
CPU time 398.06 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:58:45 PM PDT 24
Peak memory 199892 kb
Host smart-33d6a3ae-2e0a-4bd0-be43-bcb364f1f574
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1053166317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_long_xfer_wo_dly.1053166317
Directory /workspace/10.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/10.uart_loopback.389702549
Short name T527
Test name
Test status
Simulation time 447036080 ps
CPU time 0.89 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 197408 kb
Host smart-9ac70435-0ad4-4b85-a1f2-a674d5231a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389702549 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_loopback.389702549
Directory /workspace/10.uart_loopback/latest

Test location /workspace/coverage/default/10.uart_noise_filter.3815114742
Short name T777
Test name
Test status
Simulation time 20735796073 ps
CPU time 37.99 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 200208 kb
Host smart-2a7db488-7cc6-46ab-98fa-217cc691fc42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815114742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_noise_filter.3815114742
Directory /workspace/10.uart_noise_filter/latest

Test location /workspace/coverage/default/10.uart_perf.2237073144
Short name T1139
Test name
Test status
Simulation time 14903091443 ps
CPU time 748.99 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 05:04:39 PM PDT 24
Peak memory 199832 kb
Host smart-be956a8e-0743-4310-8400-6e76982d16bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2237073144 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_perf.2237073144
Directory /workspace/10.uart_perf/latest

Test location /workspace/coverage/default/10.uart_rx_oversample.3899544719
Short name T336
Test name
Test status
Simulation time 2540898886 ps
CPU time 16.03 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:24 PM PDT 24
Peak memory 197808 kb
Host smart-7204db66-c938-4b4d-b48c-f78b1427bdde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3899544719 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_oversample.3899544719
Directory /workspace/10.uart_rx_oversample/latest

Test location /workspace/coverage/default/10.uart_rx_parity_err.3525571326
Short name T1077
Test name
Test status
Simulation time 131644136260 ps
CPU time 65.77 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:53:11 PM PDT 24
Peak memory 199480 kb
Host smart-fd7009dd-4678-43f5-80e6-f2dbbde63232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525571326 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_parity_err.3525571326
Directory /workspace/10.uart_rx_parity_err/latest

Test location /workspace/coverage/default/10.uart_rx_start_bit_filter.3779457855
Short name T790
Test name
Test status
Simulation time 687254235 ps
CPU time 0.94 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:09 PM PDT 24
Peak memory 195344 kb
Host smart-1902c562-633b-4b5b-8de0-c6cfffe7fadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779457855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_rx_start_bit_filter.3779457855
Directory /workspace/10.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/10.uart_smoke.2177234344
Short name T1038
Test name
Test status
Simulation time 294194545 ps
CPU time 1.26 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:08 PM PDT 24
Peak memory 198224 kb
Host smart-35833bfa-7e9d-477f-addb-9e4564db5c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177234344 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_smoke.2177234344
Directory /workspace/10.uart_smoke/latest

Test location /workspace/coverage/default/10.uart_stress_all.1176508469
Short name T168
Test name
Test status
Simulation time 170823474268 ps
CPU time 356.57 seconds
Started Aug 03 04:52:06 PM PDT 24
Finished Aug 03 04:58:03 PM PDT 24
Peak memory 199916 kb
Host smart-4569bb89-2bc8-4da2-a599-7b072649f4ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176508469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_stress_all.1176508469
Directory /workspace/10.uart_stress_all/latest

Test location /workspace/coverage/default/10.uart_tx_ovrd.3825931388
Short name T634
Test name
Test status
Simulation time 6372359252 ps
CPU time 17.34 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 04:52:28 PM PDT 24
Peak memory 199220 kb
Host smart-06538791-4943-4522-a83e-6c3462f34192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825931388 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_ovrd.3825931388
Directory /workspace/10.uart_tx_ovrd/latest

Test location /workspace/coverage/default/10.uart_tx_rx.2085525789
Short name T330
Test name
Test status
Simulation time 104226714448 ps
CPU time 71.8 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:53:21 PM PDT 24
Peak memory 199932 kb
Host smart-5164eb98-2f94-43db-96b3-36175b583662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085525789 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.uart_tx_rx.2085525789
Directory /workspace/10.uart_tx_rx/latest

Test location /workspace/coverage/default/100.uart_fifo_reset.227527007
Short name T499
Test name
Test status
Simulation time 134573548892 ps
CPU time 193.06 seconds
Started Aug 03 04:56:19 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 199816 kb
Host smart-631b04e2-40cc-4328-b88a-405b3e52334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227527007 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 100.uart_fifo_reset.227527007
Directory /workspace/100.uart_fifo_reset/latest

Test location /workspace/coverage/default/102.uart_fifo_reset.129298986
Short name T369
Test name
Test status
Simulation time 269848184048 ps
CPU time 34.42 seconds
Started Aug 03 04:56:25 PM PDT 24
Finished Aug 03 04:57:00 PM PDT 24
Peak memory 200072 kb
Host smart-c6708c80-7c8a-4a0b-a441-bf0430d475ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129298986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 102.uart_fifo_reset.129298986
Directory /workspace/102.uart_fifo_reset/latest

Test location /workspace/coverage/default/103.uart_fifo_reset.179980169
Short name T156
Test name
Test status
Simulation time 30194548504 ps
CPU time 49.12 seconds
Started Aug 03 04:56:24 PM PDT 24
Finished Aug 03 04:57:13 PM PDT 24
Peak memory 199812 kb
Host smart-e0033800-cfbc-4d8b-861f-ecc94f23778e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179980169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 103.uart_fifo_reset.179980169
Directory /workspace/103.uart_fifo_reset/latest

Test location /workspace/coverage/default/104.uart_fifo_reset.3015711866
Short name T1051
Test name
Test status
Simulation time 23207485652 ps
CPU time 19.22 seconds
Started Aug 03 04:56:23 PM PDT 24
Finished Aug 03 04:56:43 PM PDT 24
Peak memory 199820 kb
Host smart-c7ef9bce-b350-49fd-bb69-e879f4fc4861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015711866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 104.uart_fifo_reset.3015711866
Directory /workspace/104.uart_fifo_reset/latest

Test location /workspace/coverage/default/105.uart_fifo_reset.3932925432
Short name T165
Test name
Test status
Simulation time 259695772807 ps
CPU time 74.7 seconds
Started Aug 03 04:56:24 PM PDT 24
Finished Aug 03 04:57:39 PM PDT 24
Peak memory 199812 kb
Host smart-3d8eff83-5a70-46df-b9df-eeb3fd36a092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932925432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 105.uart_fifo_reset.3932925432
Directory /workspace/105.uart_fifo_reset/latest

Test location /workspace/coverage/default/106.uart_fifo_reset.4126651097
Short name T809
Test name
Test status
Simulation time 30462996500 ps
CPU time 12.32 seconds
Started Aug 03 04:56:23 PM PDT 24
Finished Aug 03 04:56:36 PM PDT 24
Peak memory 198808 kb
Host smart-cf02fc75-4895-4b11-9361-c2ddd8c15a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126651097 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 106.uart_fifo_reset.4126651097
Directory /workspace/106.uart_fifo_reset/latest

Test location /workspace/coverage/default/107.uart_fifo_reset.3683524749
Short name T624
Test name
Test status
Simulation time 69300353599 ps
CPU time 109.65 seconds
Started Aug 03 04:56:26 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 199768 kb
Host smart-79dec435-b93b-47c0-86d0-7cd3a4c620cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683524749 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 107.uart_fifo_reset.3683524749
Directory /workspace/107.uart_fifo_reset/latest

Test location /workspace/coverage/default/108.uart_fifo_reset.318768101
Short name T188
Test name
Test status
Simulation time 31740929475 ps
CPU time 51.86 seconds
Started Aug 03 04:56:22 PM PDT 24
Finished Aug 03 04:57:14 PM PDT 24
Peak memory 199868 kb
Host smart-2ee41be8-1fbe-4567-b077-3eb558754a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318768101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 108.uart_fifo_reset.318768101
Directory /workspace/108.uart_fifo_reset/latest

Test location /workspace/coverage/default/109.uart_fifo_reset.2346542415
Short name T572
Test name
Test status
Simulation time 36712612615 ps
CPU time 26.41 seconds
Started Aug 03 04:56:24 PM PDT 24
Finished Aug 03 04:56:50 PM PDT 24
Peak memory 199924 kb
Host smart-72e05845-98d3-49d5-a8e3-7c5443789300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346542415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 109.uart_fifo_reset.2346542415
Directory /workspace/109.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_alert_test.4267709138
Short name T640
Test name
Test status
Simulation time 12810498 ps
CPU time 0.55 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 195288 kb
Host smart-879d18cf-e768-424d-a337-67ddeb018583
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267709138 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_alert_test.4267709138
Directory /workspace/11.uart_alert_test/latest

Test location /workspace/coverage/default/11.uart_fifo_full.511264160
Short name T584
Test name
Test status
Simulation time 82824165913 ps
CPU time 109.38 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:53:55 PM PDT 24
Peak memory 199900 kb
Host smart-b15cdf84-78a6-47c6-ac7b-f2c563f56844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511264160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_full.511264160
Directory /workspace/11.uart_fifo_full/latest

Test location /workspace/coverage/default/11.uart_fifo_overflow.1492270947
Short name T271
Test name
Test status
Simulation time 183283113181 ps
CPU time 244.48 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:56:14 PM PDT 24
Peak memory 199904 kb
Host smart-5fecb7e2-922d-4537-b75f-8a1843b9c0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492270947 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_overflow.1492270947
Directory /workspace/11.uart_fifo_overflow/latest

Test location /workspace/coverage/default/11.uart_fifo_reset.3797719575
Short name T663
Test name
Test status
Simulation time 14713808656 ps
CPU time 25.03 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:33 PM PDT 24
Peak memory 199876 kb
Host smart-8d95a5df-a2e9-46ed-89c4-fdbd9b5f894a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797719575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_fifo_reset.3797719575
Directory /workspace/11.uart_fifo_reset/latest

Test location /workspace/coverage/default/11.uart_intr.1663914742
Short name T788
Test name
Test status
Simulation time 66435407479 ps
CPU time 43.94 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 197404 kb
Host smart-703b23f1-6f92-430f-a6bf-e877e39c9db5
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663914742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_intr.1663914742
Directory /workspace/11.uart_intr/latest

Test location /workspace/coverage/default/11.uart_long_xfer_wo_dly.585490327
Short name T399
Test name
Test status
Simulation time 87342158928 ps
CPU time 367.07 seconds
Started Aug 03 04:52:11 PM PDT 24
Finished Aug 03 04:58:18 PM PDT 24
Peak memory 200092 kb
Host smart-593e9633-2cd9-47d5-8722-26ba6bb97a25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=585490327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_long_xfer_wo_dly.585490327
Directory /workspace/11.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/11.uart_loopback.2865472310
Short name T610
Test name
Test status
Simulation time 729077356 ps
CPU time 1.97 seconds
Started Aug 03 04:52:06 PM PDT 24
Finished Aug 03 04:52:08 PM PDT 24
Peak memory 196792 kb
Host smart-f886764f-6205-4bc5-bd11-425f71cbd158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865472310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_loopback.2865472310
Directory /workspace/11.uart_loopback/latest

Test location /workspace/coverage/default/11.uart_noise_filter.2135024562
Short name T1131
Test name
Test status
Simulation time 36084903773 ps
CPU time 66.63 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:53:16 PM PDT 24
Peak memory 198920 kb
Host smart-c2794403-282b-4fba-adb9-5fd3c14b96e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135024562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_noise_filter.2135024562
Directory /workspace/11.uart_noise_filter/latest

Test location /workspace/coverage/default/11.uart_perf.3102712762
Short name T350
Test name
Test status
Simulation time 17295042786 ps
CPU time 248.66 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:56:14 PM PDT 24
Peak memory 199868 kb
Host smart-721bd08e-b064-48f5-86bc-cb2f1e75666d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3102712762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_perf.3102712762
Directory /workspace/11.uart_perf/latest

Test location /workspace/coverage/default/11.uart_rx_oversample.3559137154
Short name T346
Test name
Test status
Simulation time 5152050904 ps
CPU time 10.69 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:52:16 PM PDT 24
Peak memory 199000 kb
Host smart-0fdeb788-114f-450a-8f86-94e3ff0d3a48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559137154 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_oversample.3559137154
Directory /workspace/11.uart_rx_oversample/latest

Test location /workspace/coverage/default/11.uart_rx_parity_err.3379460089
Short name T16
Test name
Test status
Simulation time 19900745205 ps
CPU time 34.88 seconds
Started Aug 03 04:52:12 PM PDT 24
Finished Aug 03 04:52:46 PM PDT 24
Peak memory 200092 kb
Host smart-3461942e-cbce-4063-b1c6-dbaadb3bb9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379460089 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_parity_err.3379460089
Directory /workspace/11.uart_rx_parity_err/latest

Test location /workspace/coverage/default/11.uart_rx_start_bit_filter.3577054747
Short name T799
Test name
Test status
Simulation time 5287084632 ps
CPU time 9.2 seconds
Started Aug 03 04:52:06 PM PDT 24
Finished Aug 03 04:52:15 PM PDT 24
Peak memory 196012 kb
Host smart-f565090a-5478-43c5-8f09-30386da5418d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577054747 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_rx_start_bit_filter.3577054747
Directory /workspace/11.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/11.uart_smoke.988933736
Short name T571
Test name
Test status
Simulation time 255656593 ps
CPU time 1.15 seconds
Started Aug 03 04:52:06 PM PDT 24
Finished Aug 03 04:52:07 PM PDT 24
Peak memory 198144 kb
Host smart-cc697672-8907-4e46-a202-02bdd3e515aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988933736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_smoke.988933736
Directory /workspace/11.uart_smoke/latest

Test location /workspace/coverage/default/11.uart_stress_all_with_rand_reset.2758439234
Short name T321
Test name
Test status
Simulation time 79864439755 ps
CPU time 699.78 seconds
Started Aug 03 04:52:06 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 228248 kb
Host smart-2d871fff-5c78-4b7e-8578-1087f1946c15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758439234 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 11.uart_stress_all_with_rand_reset.2758439234
Directory /workspace/11.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.uart_tx_ovrd.591010393
Short name T479
Test name
Test status
Simulation time 1222424017 ps
CPU time 1.88 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 199428 kb
Host smart-9fee0b1f-83e5-489e-8fc4-81e53c4d0489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591010393 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_ovrd.591010393
Directory /workspace/11.uart_tx_ovrd/latest

Test location /workspace/coverage/default/11.uart_tx_rx.1977042673
Short name T390
Test name
Test status
Simulation time 61653409736 ps
CPU time 28.09 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:36 PM PDT 24
Peak memory 199840 kb
Host smart-d1b65c35-dbbf-4c61-aad5-1ba13bb9d0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977042673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.uart_tx_rx.1977042673
Directory /workspace/11.uart_tx_rx/latest

Test location /workspace/coverage/default/110.uart_fifo_reset.4044797275
Short name T400
Test name
Test status
Simulation time 60948370387 ps
CPU time 46.11 seconds
Started Aug 03 04:56:24 PM PDT 24
Finished Aug 03 04:57:10 PM PDT 24
Peak memory 199808 kb
Host smart-1fac34c1-b380-41b2-b14f-3e036b3ca31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044797275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 110.uart_fifo_reset.4044797275
Directory /workspace/110.uart_fifo_reset/latest

Test location /workspace/coverage/default/111.uart_fifo_reset.1674862417
Short name T1161
Test name
Test status
Simulation time 83921996618 ps
CPU time 33.31 seconds
Started Aug 03 04:56:25 PM PDT 24
Finished Aug 03 04:56:58 PM PDT 24
Peak memory 199908 kb
Host smart-c007009c-b497-4524-9ea8-aa10d9380b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674862417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 111.uart_fifo_reset.1674862417
Directory /workspace/111.uart_fifo_reset/latest

Test location /workspace/coverage/default/113.uart_fifo_reset.512867432
Short name T1075
Test name
Test status
Simulation time 32115760654 ps
CPU time 62.06 seconds
Started Aug 03 04:56:24 PM PDT 24
Finished Aug 03 04:57:26 PM PDT 24
Peak memory 199808 kb
Host smart-74ce5b41-0a95-42c2-a403-3d1bf07bcc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512867432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 113.uart_fifo_reset.512867432
Directory /workspace/113.uart_fifo_reset/latest

Test location /workspace/coverage/default/114.uart_fifo_reset.2185414578
Short name T170
Test name
Test status
Simulation time 62319009195 ps
CPU time 29.23 seconds
Started Aug 03 04:56:29 PM PDT 24
Finished Aug 03 04:56:59 PM PDT 24
Peak memory 199836 kb
Host smart-6b6012ad-0911-4b37-a20b-dbfce51b0c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185414578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 114.uart_fifo_reset.2185414578
Directory /workspace/114.uart_fifo_reset/latest

Test location /workspace/coverage/default/116.uart_fifo_reset.1191271124
Short name T8
Test name
Test status
Simulation time 65730508895 ps
CPU time 88.36 seconds
Started Aug 03 04:56:32 PM PDT 24
Finished Aug 03 04:58:00 PM PDT 24
Peak memory 199836 kb
Host smart-b0bc481c-263c-41a2-aa5c-cf7413967a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191271124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 116.uart_fifo_reset.1191271124
Directory /workspace/116.uart_fifo_reset/latest

Test location /workspace/coverage/default/12.uart_alert_test.3129799203
Short name T444
Test name
Test status
Simulation time 33608815 ps
CPU time 0.55 seconds
Started Aug 03 04:52:16 PM PDT 24
Finished Aug 03 04:52:16 PM PDT 24
Peak memory 195300 kb
Host smart-52b3d65a-9a1c-4f9f-9ad3-829f0d995fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129799203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_alert_test.3129799203
Directory /workspace/12.uart_alert_test/latest

Test location /workspace/coverage/default/12.uart_fifo_full.2591932764
Short name T410
Test name
Test status
Simulation time 41478637026 ps
CPU time 78.5 seconds
Started Aug 03 04:52:04 PM PDT 24
Finished Aug 03 04:53:23 PM PDT 24
Peak memory 199904 kb
Host smart-21a65de8-3145-43a6-863c-ab7717043804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591932764 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_full.2591932764
Directory /workspace/12.uart_fifo_full/latest

Test location /workspace/coverage/default/12.uart_fifo_overflow.3231721969
Short name T734
Test name
Test status
Simulation time 72243796080 ps
CPU time 48.37 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:56 PM PDT 24
Peak memory 199928 kb
Host smart-a0418fd7-d965-4f3d-86d5-e461b99de7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231721969 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_fifo_overflow.3231721969
Directory /workspace/12.uart_fifo_overflow/latest

Test location /workspace/coverage/default/12.uart_intr.1009414029
Short name T628
Test name
Test status
Simulation time 20854660350 ps
CPU time 4.36 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:12 PM PDT 24
Peak memory 199896 kb
Host smart-1afa04f8-5d41-4fbb-8e7a-907acfa7a52a
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009414029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_intr.1009414029
Directory /workspace/12.uart_intr/latest

Test location /workspace/coverage/default/12.uart_long_xfer_wo_dly.2293270002
Short name T735
Test name
Test status
Simulation time 134077881936 ps
CPU time 766.96 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 05:05:05 PM PDT 24
Peak memory 199896 kb
Host smart-d849ffcb-b043-4e85-94f3-872900fda00b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2293270002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_long_xfer_wo_dly.2293270002
Directory /workspace/12.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/12.uart_loopback.4090997714
Short name T1072
Test name
Test status
Simulation time 10298582021 ps
CPU time 7.58 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:52:25 PM PDT 24
Peak memory 198660 kb
Host smart-47667bc2-b4b6-4b20-9d8a-04698a236ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090997714 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_loopback.4090997714
Directory /workspace/12.uart_loopback/latest

Test location /workspace/coverage/default/12.uart_noise_filter.99618568
Short name T355
Test name
Test status
Simulation time 31859767440 ps
CPU time 5.51 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 04:52:15 PM PDT 24
Peak memory 195052 kb
Host smart-cc699815-08d7-4d41-bb35-22a24020341e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99618568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_noise_filter.99618568
Directory /workspace/12.uart_noise_filter/latest

Test location /workspace/coverage/default/12.uart_perf.3185356438
Short name T769
Test name
Test status
Simulation time 22921205073 ps
CPU time 1133 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 05:11:11 PM PDT 24
Peak memory 199844 kb
Host smart-5ef8952c-28d9-4974-a021-1efdf33df8da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3185356438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_perf.3185356438
Directory /workspace/12.uart_perf/latest

Test location /workspace/coverage/default/12.uart_rx_oversample.1809596196
Short name T366
Test name
Test status
Simulation time 3648345852 ps
CPU time 25.41 seconds
Started Aug 03 04:52:09 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 197836 kb
Host smart-1438243c-1843-47b2-b53f-ab19a71d88ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809596196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_oversample.1809596196
Directory /workspace/12.uart_rx_oversample/latest

Test location /workspace/coverage/default/12.uart_rx_parity_err.2425353206
Short name T519
Test name
Test status
Simulation time 118641551079 ps
CPU time 49.23 seconds
Started Aug 03 04:52:15 PM PDT 24
Finished Aug 03 04:53:04 PM PDT 24
Peak memory 199896 kb
Host smart-e2533ade-330b-4ba0-99d8-f9743612df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425353206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_parity_err.2425353206
Directory /workspace/12.uart_rx_parity_err/latest

Test location /workspace/coverage/default/12.uart_rx_start_bit_filter.2506862347
Short name T561
Test name
Test status
Simulation time 29446683999 ps
CPU time 11.58 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:30 PM PDT 24
Peak memory 196696 kb
Host smart-6e31595d-849f-41ff-b7a8-7235cc8bdaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506862347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_rx_start_bit_filter.2506862347
Directory /workspace/12.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/12.uart_smoke.2262891925
Short name T576
Test name
Test status
Simulation time 5807541403 ps
CPU time 6.67 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:14 PM PDT 24
Peak memory 199648 kb
Host smart-b43be27a-8e90-43c9-a70e-1d64507d1266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262891925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_smoke.2262891925
Directory /workspace/12.uart_smoke/latest

Test location /workspace/coverage/default/12.uart_stress_all.3174322212
Short name T766
Test name
Test status
Simulation time 110017131842 ps
CPU time 153.01 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:54:50 PM PDT 24
Peak memory 199844 kb
Host smart-a5dae53c-b58c-4f83-ab78-386be8502754
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174322212 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_stress_all.3174322212
Directory /workspace/12.uart_stress_all/latest

Test location /workspace/coverage/default/12.uart_stress_all_with_rand_reset.2201169937
Short name T843
Test name
Test status
Simulation time 26611412829 ps
CPU time 283.83 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:57:03 PM PDT 24
Peak memory 216552 kb
Host smart-e4f6e57d-4179-4b48-b750-4c6259711806
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201169937 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 12.uart_stress_all_with_rand_reset.2201169937
Directory /workspace/12.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.uart_tx_ovrd.1969889257
Short name T738
Test name
Test status
Simulation time 342687480 ps
CPU time 1.38 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 198076 kb
Host smart-f7039c64-aa39-46d1-8bfa-addb31e57405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969889257 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_ovrd.1969889257
Directory /workspace/12.uart_tx_ovrd/latest

Test location /workspace/coverage/default/12.uart_tx_rx.2757554691
Short name T263
Test name
Test status
Simulation time 123180987055 ps
CPU time 226.69 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:55:54 PM PDT 24
Peak memory 199908 kb
Host smart-5e8c7cc3-3027-401b-a4c3-c94342dc4e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757554691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.uart_tx_rx.2757554691
Directory /workspace/12.uart_tx_rx/latest

Test location /workspace/coverage/default/120.uart_fifo_reset.3701589814
Short name T125
Test name
Test status
Simulation time 43595252605 ps
CPU time 34.12 seconds
Started Aug 03 04:56:32 PM PDT 24
Finished Aug 03 04:57:07 PM PDT 24
Peak memory 199468 kb
Host smart-8d7321b6-791f-480f-83ee-e56600966ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701589814 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 120.uart_fifo_reset.3701589814
Directory /workspace/120.uart_fifo_reset/latest

Test location /workspace/coverage/default/121.uart_fifo_reset.3825167065
Short name T879
Test name
Test status
Simulation time 70000496828 ps
CPU time 113.72 seconds
Started Aug 03 04:56:31 PM PDT 24
Finished Aug 03 04:58:25 PM PDT 24
Peak memory 199916 kb
Host smart-460df3a9-74dd-4ddd-8800-0c2e406f6722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825167065 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 121.uart_fifo_reset.3825167065
Directory /workspace/121.uart_fifo_reset/latest

Test location /workspace/coverage/default/122.uart_fifo_reset.19775471
Short name T670
Test name
Test status
Simulation time 182963699370 ps
CPU time 37.4 seconds
Started Aug 03 04:56:30 PM PDT 24
Finished Aug 03 04:57:08 PM PDT 24
Peak memory 199856 kb
Host smart-05900ac4-93fc-41f9-8fdd-5896b3abb0ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19775471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 122.uart_fifo_reset.19775471
Directory /workspace/122.uart_fifo_reset/latest

Test location /workspace/coverage/default/125.uart_fifo_reset.2753825191
Short name T898
Test name
Test status
Simulation time 104808616811 ps
CPU time 26.12 seconds
Started Aug 03 04:56:36 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 198988 kb
Host smart-19b77f5a-fb7a-4d6d-a254-4fb94df693f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753825191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 125.uart_fifo_reset.2753825191
Directory /workspace/125.uart_fifo_reset/latest

Test location /workspace/coverage/default/126.uart_fifo_reset.1533519899
Short name T44
Test name
Test status
Simulation time 36495459640 ps
CPU time 30.88 seconds
Started Aug 03 04:56:38 PM PDT 24
Finished Aug 03 04:57:09 PM PDT 24
Peak memory 199908 kb
Host smart-f3d94390-3d1b-4637-b891-6500452b367b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533519899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 126.uart_fifo_reset.1533519899
Directory /workspace/126.uart_fifo_reset/latest

Test location /workspace/coverage/default/127.uart_fifo_reset.2908409758
Short name T362
Test name
Test status
Simulation time 16949670059 ps
CPU time 11 seconds
Started Aug 03 04:56:36 PM PDT 24
Finished Aug 03 04:56:47 PM PDT 24
Peak memory 199836 kb
Host smart-d0375ba3-59af-467a-8a4a-376a25135c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908409758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 127.uart_fifo_reset.2908409758
Directory /workspace/127.uart_fifo_reset/latest

Test location /workspace/coverage/default/128.uart_fifo_reset.3305946456
Short name T611
Test name
Test status
Simulation time 105861791695 ps
CPU time 20.09 seconds
Started Aug 03 04:56:38 PM PDT 24
Finished Aug 03 04:56:58 PM PDT 24
Peak memory 199832 kb
Host smart-6dc456c5-3be3-4e78-b7e2-fa89fce64fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305946456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 128.uart_fifo_reset.3305946456
Directory /workspace/128.uart_fifo_reset/latest

Test location /workspace/coverage/default/129.uart_fifo_reset.3436901530
Short name T196
Test name
Test status
Simulation time 126886715472 ps
CPU time 100.71 seconds
Started Aug 03 04:56:35 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 199864 kb
Host smart-7b8a3965-4671-4ca7-9ef3-758cb1dd58db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436901530 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 129.uart_fifo_reset.3436901530
Directory /workspace/129.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_alert_test.470813453
Short name T377
Test name
Test status
Simulation time 10961642 ps
CPU time 0.57 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:18 PM PDT 24
Peak memory 195304 kb
Host smart-802b2a22-fe3c-45b5-923b-bf5028fe80ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470813453 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_alert_test.470813453
Directory /workspace/13.uart_alert_test/latest

Test location /workspace/coverage/default/13.uart_fifo_full.3207170002
Short name T433
Test name
Test status
Simulation time 130833879046 ps
CPU time 267.01 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:56:45 PM PDT 24
Peak memory 199744 kb
Host smart-5b9362b5-f74a-4da2-8bf9-6ef6fe98b319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207170002 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_full.3207170002
Directory /workspace/13.uart_fifo_full/latest

Test location /workspace/coverage/default/13.uart_fifo_overflow.430565417
Short name T1076
Test name
Test status
Simulation time 19326390929 ps
CPU time 13.49 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:31 PM PDT 24
Peak memory 199896 kb
Host smart-dfff29a2-8eaa-475d-b15a-2cab6d255580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430565417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_overflow.430565417
Directory /workspace/13.uart_fifo_overflow/latest

Test location /workspace/coverage/default/13.uart_fifo_reset.1868639614
Short name T523
Test name
Test status
Simulation time 80826403806 ps
CPU time 293.3 seconds
Started Aug 03 04:52:16 PM PDT 24
Finished Aug 03 04:57:10 PM PDT 24
Peak memory 199848 kb
Host smart-bcc4f62b-b369-4c72-9a95-d159f2046e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868639614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_fifo_reset.1868639614
Directory /workspace/13.uart_fifo_reset/latest

Test location /workspace/coverage/default/13.uart_intr.1605641700
Short name T415
Test name
Test status
Simulation time 4833328780 ps
CPU time 2.35 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:21 PM PDT 24
Peak memory 196668 kb
Host smart-c033c9f9-daca-4408-8db7-a711105d2919
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605641700 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_intr.1605641700
Directory /workspace/13.uart_intr/latest

Test location /workspace/coverage/default/13.uart_long_xfer_wo_dly.1430464755
Short name T569
Test name
Test status
Simulation time 205757568632 ps
CPU time 131.12 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:54:32 PM PDT 24
Peak memory 199816 kb
Host smart-f89bf489-c370-4b4a-90fe-c238bd460723
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1430464755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_long_xfer_wo_dly.1430464755
Directory /workspace/13.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/13.uart_loopback.1707618827
Short name T794
Test name
Test status
Simulation time 650076968 ps
CPU time 1.1 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:18 PM PDT 24
Peak memory 197464 kb
Host smart-62d11f93-7451-4444-8fcd-0c2fc50b571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707618827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_loopback.1707618827
Directory /workspace/13.uart_loopback/latest

Test location /workspace/coverage/default/13.uart_noise_filter.1127932882
Short name T623
Test name
Test status
Simulation time 250741324368 ps
CPU time 104.56 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:54:05 PM PDT 24
Peak memory 200024 kb
Host smart-1307dfce-ccdd-4df6-b952-ce68cfde0003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127932882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_noise_filter.1127932882
Directory /workspace/13.uart_noise_filter/latest

Test location /workspace/coverage/default/13.uart_perf.143461471
Short name T258
Test name
Test status
Simulation time 10702752853 ps
CPU time 650.57 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 05:03:11 PM PDT 24
Peak memory 199844 kb
Host smart-28cadadc-cdc3-47ff-ad3f-645bcf72ceea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143461471 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_perf.143461471
Directory /workspace/13.uart_perf/latest

Test location /workspace/coverage/default/13.uart_rx_oversample.2233718208
Short name T477
Test name
Test status
Simulation time 5110536361 ps
CPU time 5.55 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 199148 kb
Host smart-4a9dcc4a-40de-4766-8b99-56979532291d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2233718208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_oversample.2233718208
Directory /workspace/13.uart_rx_oversample/latest

Test location /workspace/coverage/default/13.uart_rx_parity_err.415242160
Short name T282
Test name
Test status
Simulation time 96712461284 ps
CPU time 12.04 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:52:30 PM PDT 24
Peak memory 198548 kb
Host smart-1cc9bb82-cee0-4567-bcaf-2cbaa82f2087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415242160 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_parity_err.415242160
Directory /workspace/13.uart_rx_parity_err/latest

Test location /workspace/coverage/default/13.uart_rx_start_bit_filter.1842044016
Short name T311
Test name
Test status
Simulation time 5480245337 ps
CPU time 8.87 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 196044 kb
Host smart-1682fc51-538c-4946-abd7-e6255b9995de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842044016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_rx_start_bit_filter.1842044016
Directory /workspace/13.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/13.uart_smoke.3754010629
Short name T486
Test name
Test status
Simulation time 5871945550 ps
CPU time 11.4 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 199756 kb
Host smart-ee249901-c59a-4ce2-b729-5bf495006f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754010629 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_smoke.3754010629
Directory /workspace/13.uart_smoke/latest

Test location /workspace/coverage/default/13.uart_stress_all.44427809
Short name T184
Test name
Test status
Simulation time 178162706340 ps
CPU time 333.72 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:57:51 PM PDT 24
Peak memory 199892 kb
Host smart-93137058-eea5-41eb-80ad-540f0d1b5a04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44427809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_stress_all.44427809
Directory /workspace/13.uart_stress_all/latest

Test location /workspace/coverage/default/13.uart_stress_all_with_rand_reset.1949644438
Short name T1054
Test name
Test status
Simulation time 18910926983 ps
CPU time 197.38 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:55:36 PM PDT 24
Peak memory 216424 kb
Host smart-b4740ec6-3f1c-4e88-87da-c283a28f8026
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949644438 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 13.uart_stress_all_with_rand_reset.1949644438
Directory /workspace/13.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.uart_tx_ovrd.988427795
Short name T430
Test name
Test status
Simulation time 6542138039 ps
CPU time 20.24 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:52:38 PM PDT 24
Peak memory 199860 kb
Host smart-d73064b9-91a7-472d-a470-2016fcf29c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988427795 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.uart_tx_ovrd.988427795
Directory /workspace/13.uart_tx_ovrd/latest

Test location /workspace/coverage/default/130.uart_fifo_reset.845882117
Short name T703
Test name
Test status
Simulation time 210816276036 ps
CPU time 309.37 seconds
Started Aug 03 04:56:35 PM PDT 24
Finished Aug 03 05:01:45 PM PDT 24
Peak memory 199880 kb
Host smart-3e5f52c8-7471-4653-800c-3293c617eeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845882117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 130.uart_fifo_reset.845882117
Directory /workspace/130.uart_fifo_reset/latest

Test location /workspace/coverage/default/131.uart_fifo_reset.524139842
Short name T213
Test name
Test status
Simulation time 67999982547 ps
CPU time 10.58 seconds
Started Aug 03 04:56:39 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 199780 kb
Host smart-da38a17b-edfe-48be-87c5-d377cca2c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524139842 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 131.uart_fifo_reset.524139842
Directory /workspace/131.uart_fifo_reset/latest

Test location /workspace/coverage/default/133.uart_fifo_reset.2980815356
Short name T886
Test name
Test status
Simulation time 170424991638 ps
CPU time 137.08 seconds
Started Aug 03 04:56:45 PM PDT 24
Finished Aug 03 04:59:02 PM PDT 24
Peak memory 199876 kb
Host smart-805d1f7a-bef3-4d54-b353-6049de3dc3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980815356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 133.uart_fifo_reset.2980815356
Directory /workspace/133.uart_fifo_reset/latest

Test location /workspace/coverage/default/135.uart_fifo_reset.146671503
Short name T128
Test name
Test status
Simulation time 17173414951 ps
CPU time 19.77 seconds
Started Aug 03 04:56:43 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 199800 kb
Host smart-ff8e7374-baa1-40f4-8914-bec483488c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146671503 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 135.uart_fifo_reset.146671503
Directory /workspace/135.uart_fifo_reset/latest

Test location /workspace/coverage/default/136.uart_fifo_reset.2827351149
Short name T494
Test name
Test status
Simulation time 54793420678 ps
CPU time 24.9 seconds
Started Aug 03 04:56:45 PM PDT 24
Finished Aug 03 04:57:10 PM PDT 24
Peak memory 199904 kb
Host smart-ec54a57b-eadf-43e6-ae2e-fe02d57159e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827351149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 136.uart_fifo_reset.2827351149
Directory /workspace/136.uart_fifo_reset/latest

Test location /workspace/coverage/default/137.uart_fifo_reset.3766514064
Short name T929
Test name
Test status
Simulation time 82831512778 ps
CPU time 62.7 seconds
Started Aug 03 04:56:42 PM PDT 24
Finished Aug 03 04:57:45 PM PDT 24
Peak memory 199732 kb
Host smart-df2d1f99-67ca-44a4-93b2-3e7e98bfc741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766514064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 137.uart_fifo_reset.3766514064
Directory /workspace/137.uart_fifo_reset/latest

Test location /workspace/coverage/default/138.uart_fifo_reset.833823496
Short name T562
Test name
Test status
Simulation time 31688921349 ps
CPU time 46.2 seconds
Started Aug 03 04:56:42 PM PDT 24
Finished Aug 03 04:57:28 PM PDT 24
Peak memory 199780 kb
Host smart-f45d9b6c-02da-4399-a568-72368dd119c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833823496 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 138.uart_fifo_reset.833823496
Directory /workspace/138.uart_fifo_reset/latest

Test location /workspace/coverage/default/139.uart_fifo_reset.2042991682
Short name T1080
Test name
Test status
Simulation time 6640662835 ps
CPU time 10.77 seconds
Started Aug 03 04:56:46 PM PDT 24
Finished Aug 03 04:56:56 PM PDT 24
Peak memory 199744 kb
Host smart-3eeba561-35f5-4199-9372-9dd7eff2e5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042991682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 139.uart_fifo_reset.2042991682
Directory /workspace/139.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_alert_test.2615287125
Short name T719
Test name
Test status
Simulation time 12014867 ps
CPU time 0.56 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 195584 kb
Host smart-d02f1137-84b8-4db5-866a-623e67b04c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615287125 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_alert_test.2615287125
Directory /workspace/14.uart_alert_test/latest

Test location /workspace/coverage/default/14.uart_fifo_full.1914507427
Short name T402
Test name
Test status
Simulation time 46445511201 ps
CPU time 16.63 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 199784 kb
Host smart-b6f062f8-a527-4d95-9019-8db621638e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914507427 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_full.1914507427
Directory /workspace/14.uart_fifo_full/latest

Test location /workspace/coverage/default/14.uart_fifo_reset.437597735
Short name T10
Test name
Test status
Simulation time 159400706384 ps
CPU time 172.61 seconds
Started Aug 03 04:52:16 PM PDT 24
Finished Aug 03 04:55:09 PM PDT 24
Peak memory 199920 kb
Host smart-d15dc048-222c-4a3d-8ce7-ea5d4513b1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437597735 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_fifo_reset.437597735
Directory /workspace/14.uart_fifo_reset/latest

Test location /workspace/coverage/default/14.uart_intr.2013117499
Short name T481
Test name
Test status
Simulation time 458153537234 ps
CPU time 181.49 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:55:20 PM PDT 24
Peak memory 197924 kb
Host smart-ba4f409b-ff1d-4c58-8e68-b8f925d4ef3c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013117499 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_intr.2013117499
Directory /workspace/14.uart_intr/latest

Test location /workspace/coverage/default/14.uart_long_xfer_wo_dly.10382115
Short name T989
Test name
Test status
Simulation time 122618130376 ps
CPU time 559.32 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 05:01:41 PM PDT 24
Peak memory 199780 kb
Host smart-d53ed9d5-e502-4622-8e97-ad00c694faf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10382115 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_long_xfer_wo_dly.10382115
Directory /workspace/14.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/14.uart_loopback.2146166219
Short name T536
Test name
Test status
Simulation time 572004062 ps
CPU time 0.99 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:52:23 PM PDT 24
Peak memory 195912 kb
Host smart-c5eb391a-a0aa-43af-bc8f-de1aac91a9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146166219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_loopback.2146166219
Directory /workspace/14.uart_loopback/latest

Test location /workspace/coverage/default/14.uart_perf.716288288
Short name T493
Test name
Test status
Simulation time 18575158988 ps
CPU time 98.86 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 199896 kb
Host smart-a9041a90-3867-4494-a658-30ddc2dd5298
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=716288288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_perf.716288288
Directory /workspace/14.uart_perf/latest

Test location /workspace/coverage/default/14.uart_rx_oversample.54388012
Short name T603
Test name
Test status
Simulation time 5060847840 ps
CPU time 21.68 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 198876 kb
Host smart-01d84cc4-5a06-425c-8fd7-eab3579f3345
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=54388012 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_oversample.54388012
Directory /workspace/14.uart_rx_oversample/latest

Test location /workspace/coverage/default/14.uart_rx_parity_err.994514323
Short name T127
Test name
Test status
Simulation time 94180362977 ps
CPU time 69.17 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:53:29 PM PDT 24
Peak memory 199880 kb
Host smart-2729e481-0f28-4119-98be-2098290a7a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994514323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_parity_err.994514323
Directory /workspace/14.uart_rx_parity_err/latest

Test location /workspace/coverage/default/14.uart_rx_start_bit_filter.1646106425
Short name T964
Test name
Test status
Simulation time 5782136085 ps
CPU time 3.03 seconds
Started Aug 03 04:52:16 PM PDT 24
Finished Aug 03 04:52:19 PM PDT 24
Peak memory 196228 kb
Host smart-8c5992d5-102f-455b-be96-778199307fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646106425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_rx_start_bit_filter.1646106425
Directory /workspace/14.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/14.uart_smoke.3645571902
Short name T971
Test name
Test status
Simulation time 888198957 ps
CPU time 3.45 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:21 PM PDT 24
Peak memory 199400 kb
Host smart-c396ede1-5e45-4c6f-9f4f-b8800b683475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645571902 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_smoke.3645571902
Directory /workspace/14.uart_smoke/latest

Test location /workspace/coverage/default/14.uart_stress_all.3655833640
Short name T136
Test name
Test status
Simulation time 289749572759 ps
CPU time 820.63 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 05:06:01 PM PDT 24
Peak memory 199904 kb
Host smart-e8e206aa-1a06-4e42-8b46-17e48e061c20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655833640 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_stress_all.3655833640
Directory /workspace/14.uart_stress_all/latest

Test location /workspace/coverage/default/14.uart_stress_all_with_rand_reset.1526833188
Short name T96
Test name
Test status
Simulation time 89398964550 ps
CPU time 817.33 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 05:05:57 PM PDT 24
Peak memory 224696 kb
Host smart-df1b2caa-8f70-453d-9a13-13b7fec40d43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526833188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 14.uart_stress_all_with_rand_reset.1526833188
Directory /workspace/14.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.uart_tx_ovrd.1160286176
Short name T1164
Test name
Test status
Simulation time 1414008843 ps
CPU time 1.98 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:19 PM PDT 24
Peak memory 198980 kb
Host smart-6c90ca2b-258d-4c48-a91d-ed2edbb37d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160286176 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_ovrd.1160286176
Directory /workspace/14.uart_tx_ovrd/latest

Test location /workspace/coverage/default/14.uart_tx_rx.385368864
Short name T692
Test name
Test status
Simulation time 10309069171 ps
CPU time 16.71 seconds
Started Aug 03 04:52:17 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 199924 kb
Host smart-7b62516e-5113-4a73-b270-e6776fadfed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385368864 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.uart_tx_rx.385368864
Directory /workspace/14.uart_tx_rx/latest

Test location /workspace/coverage/default/141.uart_fifo_reset.1737367449
Short name T145
Test name
Test status
Simulation time 105308749180 ps
CPU time 72.85 seconds
Started Aug 03 04:56:50 PM PDT 24
Finished Aug 03 04:58:03 PM PDT 24
Peak memory 199828 kb
Host smart-3e35dd87-057e-41de-a2cc-bcb60444a4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737367449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 141.uart_fifo_reset.1737367449
Directory /workspace/141.uart_fifo_reset/latest

Test location /workspace/coverage/default/142.uart_fifo_reset.57021717
Short name T1163
Test name
Test status
Simulation time 155197794053 ps
CPU time 78.23 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:58:11 PM PDT 24
Peak memory 199840 kb
Host smart-319e2682-d094-44bb-b033-5b1b1ab55ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57021717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.uart_fifo_reset.57021717
Directory /workspace/142.uart_fifo_reset/latest

Test location /workspace/coverage/default/143.uart_fifo_reset.279164421
Short name T543
Test name
Test status
Simulation time 36665728048 ps
CPU time 28.1 seconds
Started Aug 03 04:56:50 PM PDT 24
Finished Aug 03 04:57:18 PM PDT 24
Peak memory 199900 kb
Host smart-1ae23a63-660b-4dcb-99ee-5e69f7bb35d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279164421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 143.uart_fifo_reset.279164421
Directory /workspace/143.uart_fifo_reset/latest

Test location /workspace/coverage/default/144.uart_fifo_reset.2470750733
Short name T792
Test name
Test status
Simulation time 19266373844 ps
CPU time 31.47 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:57:24 PM PDT 24
Peak memory 199916 kb
Host smart-e6be6ee8-5cd8-43db-a550-9ad0c80d92e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470750733 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 144.uart_fifo_reset.2470750733
Directory /workspace/144.uart_fifo_reset/latest

Test location /workspace/coverage/default/145.uart_fifo_reset.2252897949
Short name T903
Test name
Test status
Simulation time 18063325316 ps
CPU time 29.19 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:57:21 PM PDT 24
Peak memory 199880 kb
Host smart-474c9c83-78bd-47b5-bd9e-725ef3737d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252897949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 145.uart_fifo_reset.2252897949
Directory /workspace/145.uart_fifo_reset/latest

Test location /workspace/coverage/default/146.uart_fifo_reset.1166663288
Short name T1099
Test name
Test status
Simulation time 74187546902 ps
CPU time 38.53 seconds
Started Aug 03 04:56:53 PM PDT 24
Finished Aug 03 04:57:32 PM PDT 24
Peak memory 199908 kb
Host smart-4a653b36-e997-4650-9ced-efbdd7c5357c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166663288 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 146.uart_fifo_reset.1166663288
Directory /workspace/146.uart_fifo_reset/latest

Test location /workspace/coverage/default/147.uart_fifo_reset.3928490246
Short name T179
Test name
Test status
Simulation time 17326812585 ps
CPU time 10.81 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:57:03 PM PDT 24
Peak memory 199848 kb
Host smart-cd0e26a3-f4f3-4bd0-8b46-64b47a78f603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928490246 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.uart_fifo_reset.3928490246
Directory /workspace/147.uart_fifo_reset/latest

Test location /workspace/coverage/default/148.uart_fifo_reset.3186395462
Short name T464
Test name
Test status
Simulation time 108784568627 ps
CPU time 48.98 seconds
Started Aug 03 04:56:53 PM PDT 24
Finished Aug 03 04:57:42 PM PDT 24
Peak memory 199668 kb
Host smart-2b93aa9a-5270-4abf-b06d-7e8c2275146a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186395462 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 148.uart_fifo_reset.3186395462
Directory /workspace/148.uart_fifo_reset/latest

Test location /workspace/coverage/default/149.uart_fifo_reset.2419625157
Short name T412
Test name
Test status
Simulation time 26177795869 ps
CPU time 19.8 seconds
Started Aug 03 04:56:51 PM PDT 24
Finished Aug 03 04:57:11 PM PDT 24
Peak memory 199860 kb
Host smart-b18f7c8a-2c93-42df-86a8-d19f6fbc0d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419625157 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.uart_fifo_reset.2419625157
Directory /workspace/149.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_alert_test.428663060
Short name T443
Test name
Test status
Simulation time 11678428 ps
CPU time 0.55 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:52:21 PM PDT 24
Peak memory 194740 kb
Host smart-f6c2eef6-2279-40f2-b326-752a565ba16f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428663060 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_alert_test.428663060
Directory /workspace/15.uart_alert_test/latest

Test location /workspace/coverage/default/15.uart_fifo_full.1002143584
Short name T921
Test name
Test status
Simulation time 147443968431 ps
CPU time 59.27 seconds
Started Aug 03 04:52:29 PM PDT 24
Finished Aug 03 04:53:28 PM PDT 24
Peak memory 199908 kb
Host smart-aed47adb-7bf4-4693-96e1-ffc481699e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002143584 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_full.1002143584
Directory /workspace/15.uart_fifo_full/latest

Test location /workspace/coverage/default/15.uart_fifo_overflow.2279508207
Short name T126
Test name
Test status
Simulation time 14384654831 ps
CPU time 14.93 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 199876 kb
Host smart-95bd34fa-085c-4298-bb91-df7e1a7d06e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279508207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_overflow.2279508207
Directory /workspace/15.uart_fifo_overflow/latest

Test location /workspace/coverage/default/15.uart_fifo_reset.2342844511
Short name T728
Test name
Test status
Simulation time 31708258511 ps
CPU time 23.39 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:52:44 PM PDT 24
Peak memory 199936 kb
Host smart-9322618e-2264-423c-bb07-7e0db10f86d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342844511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_fifo_reset.2342844511
Directory /workspace/15.uart_fifo_reset/latest

Test location /workspace/coverage/default/15.uart_intr.3302875372
Short name T672
Test name
Test status
Simulation time 46391083981 ps
CPU time 19.09 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:38 PM PDT 24
Peak memory 198988 kb
Host smart-644fc12c-3f79-4876-b77f-31166d693c11
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302875372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_intr.3302875372
Directory /workspace/15.uart_intr/latest

Test location /workspace/coverage/default/15.uart_long_xfer_wo_dly.3559817266
Short name T1014
Test name
Test status
Simulation time 146133580084 ps
CPU time 246.83 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:56:32 PM PDT 24
Peak memory 199904 kb
Host smart-6fa300cf-dccf-44c0-b2ad-92f2a8b3837f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3559817266 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_long_xfer_wo_dly.3559817266
Directory /workspace/15.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/15.uart_loopback.3094925325
Short name T803
Test name
Test status
Simulation time 2717224986 ps
CPU time 1.85 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:27 PM PDT 24
Peak memory 197568 kb
Host smart-4628d57e-ef85-4b2d-8c59-4d75517404f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094925325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_loopback.3094925325
Directory /workspace/15.uart_loopback/latest

Test location /workspace/coverage/default/15.uart_noise_filter.3160248406
Short name T1064
Test name
Test status
Simulation time 77238758750 ps
CPU time 21.24 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 198928 kb
Host smart-9f9209e3-8643-4ea6-aa64-dd8028f0fdb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160248406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_noise_filter.3160248406
Directory /workspace/15.uart_noise_filter/latest

Test location /workspace/coverage/default/15.uart_perf.1398086823
Short name T392
Test name
Test status
Simulation time 9043707882 ps
CPU time 431.3 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 199920 kb
Host smart-10f164ab-0a1c-4865-b15a-cf3703909eb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398086823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_perf.1398086823
Directory /workspace/15.uart_perf/latest

Test location /workspace/coverage/default/15.uart_rx_oversample.3169067519
Short name T1149
Test name
Test status
Simulation time 4089698781 ps
CPU time 35.52 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:52:57 PM PDT 24
Peak memory 198008 kb
Host smart-b5db80e9-b8c5-4193-907d-df7ecf79b4c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169067519 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_oversample.3169067519
Directory /workspace/15.uart_rx_oversample/latest

Test location /workspace/coverage/default/15.uart_rx_parity_err.1421386341
Short name T868
Test name
Test status
Simulation time 26385862587 ps
CPU time 45.83 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 04:53:08 PM PDT 24
Peak memory 199868 kb
Host smart-159f5ecd-803a-4617-9cf8-06a73f13cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421386341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_parity_err.1421386341
Directory /workspace/15.uart_rx_parity_err/latest

Test location /workspace/coverage/default/15.uart_rx_start_bit_filter.797253268
Short name T275
Test name
Test status
Simulation time 4290057471 ps
CPU time 6.62 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:31 PM PDT 24
Peak memory 196756 kb
Host smart-2db83f87-5c0b-4715-8922-5d7745a867fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797253268 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_rx_start_bit_filter.797253268
Directory /workspace/15.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/15.uart_smoke.597322732
Short name T241
Test name
Test status
Simulation time 5668138389 ps
CPU time 22.31 seconds
Started Aug 03 04:52:18 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 199764 kb
Host smart-7851d5ff-eb4b-4ba4-b761-6ec34b2a7052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597322732 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_smoke.597322732
Directory /workspace/15.uart_smoke/latest

Test location /workspace/coverage/default/15.uart_stress_all.1201377612
Short name T630
Test name
Test status
Simulation time 72946474080 ps
CPU time 533.8 seconds
Started Aug 03 04:52:22 PM PDT 24
Finished Aug 03 05:01:16 PM PDT 24
Peak memory 199844 kb
Host smart-e28cc8cb-abe1-4081-aa94-65355b02825d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201377612 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_stress_all.1201377612
Directory /workspace/15.uart_stress_all/latest

Test location /workspace/coverage/default/15.uart_stress_all_with_rand_reset.2420187988
Short name T806
Test name
Test status
Simulation time 229041457357 ps
CPU time 764.91 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 05:05:10 PM PDT 24
Peak memory 216552 kb
Host smart-31489ee6-d6eb-4d9a-b861-8df409e583c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420187988 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 15.uart_stress_all_with_rand_reset.2420187988
Directory /workspace/15.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.uart_tx_ovrd.1242315952
Short name T547
Test name
Test status
Simulation time 1030582111 ps
CPU time 1.6 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:20 PM PDT 24
Peak memory 199168 kb
Host smart-8816ad98-9486-4a88-96ac-53415b8b1228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242315952 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_ovrd.1242315952
Directory /workspace/15.uart_tx_ovrd/latest

Test location /workspace/coverage/default/15.uart_tx_rx.3934149498
Short name T442
Test name
Test status
Simulation time 72262409817 ps
CPU time 45.63 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:53:05 PM PDT 24
Peak memory 199892 kb
Host smart-f4854153-ee45-4924-ba90-c69b92a62994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934149498 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.uart_tx_rx.3934149498
Directory /workspace/15.uart_tx_rx/latest

Test location /workspace/coverage/default/150.uart_fifo_reset.2502066315
Short name T671
Test name
Test status
Simulation time 139372284091 ps
CPU time 74.66 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:58:07 PM PDT 24
Peak memory 199916 kb
Host smart-723750c7-e45b-4b88-9dac-9230090792af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502066315 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 150.uart_fifo_reset.2502066315
Directory /workspace/150.uart_fifo_reset/latest

Test location /workspace/coverage/default/151.uart_fifo_reset.2089169954
Short name T229
Test name
Test status
Simulation time 39072928986 ps
CPU time 25.18 seconds
Started Aug 03 04:56:52 PM PDT 24
Finished Aug 03 04:57:18 PM PDT 24
Peak memory 199904 kb
Host smart-23a530d5-ecd3-49fe-a815-2e18b9d28c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089169954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 151.uart_fifo_reset.2089169954
Directory /workspace/151.uart_fifo_reset/latest

Test location /workspace/coverage/default/152.uart_fifo_reset.3699600601
Short name T105
Test name
Test status
Simulation time 19117098335 ps
CPU time 28.13 seconds
Started Aug 03 04:56:50 PM PDT 24
Finished Aug 03 04:57:18 PM PDT 24
Peak memory 199916 kb
Host smart-270a23b0-7841-4030-8270-1d2899d7eafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699600601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 152.uart_fifo_reset.3699600601
Directory /workspace/152.uart_fifo_reset/latest

Test location /workspace/coverage/default/154.uart_fifo_reset.2191979033
Short name T973
Test name
Test status
Simulation time 64333629633 ps
CPU time 102.58 seconds
Started Aug 03 04:57:08 PM PDT 24
Finished Aug 03 04:58:50 PM PDT 24
Peak memory 199868 kb
Host smart-cf700ebe-27b4-4796-aa36-76ad4739bf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191979033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 154.uart_fifo_reset.2191979033
Directory /workspace/154.uart_fifo_reset/latest

Test location /workspace/coverage/default/155.uart_fifo_reset.3172060263
Short name T395
Test name
Test status
Simulation time 57653274612 ps
CPU time 39.81 seconds
Started Aug 03 04:57:01 PM PDT 24
Finished Aug 03 04:57:41 PM PDT 24
Peak memory 199936 kb
Host smart-50287fde-78ae-414d-ac2b-e9b2aa285d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172060263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 155.uart_fifo_reset.3172060263
Directory /workspace/155.uart_fifo_reset/latest

Test location /workspace/coverage/default/156.uart_fifo_reset.3754990828
Short name T140
Test name
Test status
Simulation time 12023940856 ps
CPU time 14.13 seconds
Started Aug 03 04:57:00 PM PDT 24
Finished Aug 03 04:57:14 PM PDT 24
Peak memory 199872 kb
Host smart-49129d12-cd65-4056-9927-731a485fc839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754990828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 156.uart_fifo_reset.3754990828
Directory /workspace/156.uart_fifo_reset/latest

Test location /workspace/coverage/default/157.uart_fifo_reset.323129031
Short name T332
Test name
Test status
Simulation time 40635191962 ps
CPU time 65.68 seconds
Started Aug 03 04:56:57 PM PDT 24
Finished Aug 03 04:58:03 PM PDT 24
Peak memory 199692 kb
Host smart-d268209d-3b5e-4822-8a5b-0c9af047a3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323129031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 157.uart_fifo_reset.323129031
Directory /workspace/157.uart_fifo_reset/latest

Test location /workspace/coverage/default/158.uart_fifo_reset.2160488657
Short name T294
Test name
Test status
Simulation time 73326910690 ps
CPU time 144.03 seconds
Started Aug 03 04:57:08 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 199932 kb
Host smart-c0695d37-0c36-4325-a25e-f99af902f1d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160488657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 158.uart_fifo_reset.2160488657
Directory /workspace/158.uart_fifo_reset/latest

Test location /workspace/coverage/default/159.uart_fifo_reset.1556096404
Short name T850
Test name
Test status
Simulation time 28334217271 ps
CPU time 50.1 seconds
Started Aug 03 04:57:08 PM PDT 24
Finished Aug 03 04:57:58 PM PDT 24
Peak memory 199932 kb
Host smart-e0e972e2-f2e3-43f1-85d9-5465de9af6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556096404 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 159.uart_fifo_reset.1556096404
Directory /workspace/159.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_alert_test.3527329791
Short name T372
Test name
Test status
Simulation time 44204845 ps
CPU time 0.55 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 195296 kb
Host smart-934ce659-1f8e-4f7a-ac8f-ea3fee957d44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527329791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_alert_test.3527329791
Directory /workspace/16.uart_alert_test/latest

Test location /workspace/coverage/default/16.uart_fifo_full.10965245
Short name T969
Test name
Test status
Simulation time 18867680829 ps
CPU time 15.82 seconds
Started Aug 03 04:52:21 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 199716 kb
Host smart-845b0907-fd37-41e7-a861-35e9bbda62c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10965245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_full.10965245
Directory /workspace/16.uart_fifo_full/latest

Test location /workspace/coverage/default/16.uart_fifo_overflow.4094234439
Short name T838
Test name
Test status
Simulation time 63244258050 ps
CPU time 110.92 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:54:11 PM PDT 24
Peak memory 199876 kb
Host smart-6e60c87d-f35a-45d1-a3ed-11bb8c8467e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094234439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_overflow.4094234439
Directory /workspace/16.uart_fifo_overflow/latest

Test location /workspace/coverage/default/16.uart_fifo_reset.1745165414
Short name T1112
Test name
Test status
Simulation time 445120345577 ps
CPU time 35.79 seconds
Started Aug 03 04:52:23 PM PDT 24
Finished Aug 03 04:52:59 PM PDT 24
Peak memory 199652 kb
Host smart-4baabfe9-fc8c-4adb-999a-cf733459102f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745165414 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_fifo_reset.1745165414
Directory /workspace/16.uart_fifo_reset/latest

Test location /workspace/coverage/default/16.uart_intr.1785309595
Short name T928
Test name
Test status
Simulation time 5303616293 ps
CPU time 3.19 seconds
Started Aug 03 04:52:19 PM PDT 24
Finished Aug 03 04:52:22 PM PDT 24
Peak memory 198444 kb
Host smart-88b4271f-eab4-4d03-9088-5cb678d52b55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785309595 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_intr.1785309595
Directory /workspace/16.uart_intr/latest

Test location /workspace/coverage/default/16.uart_long_xfer_wo_dly.1018489857
Short name T583
Test name
Test status
Simulation time 120732529826 ps
CPU time 299.78 seconds
Started Aug 03 04:52:28 PM PDT 24
Finished Aug 03 04:57:28 PM PDT 24
Peak memory 199856 kb
Host smart-706d156b-986a-4c44-9d51-394b6433c1cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018489857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_long_xfer_wo_dly.1018489857
Directory /workspace/16.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/16.uart_loopback.1951920884
Short name T785
Test name
Test status
Simulation time 6449115104 ps
CPU time 8.98 seconds
Started Aug 03 04:52:26 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 198584 kb
Host smart-0ac1cde3-cd41-483d-a350-911d750e797f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951920884 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_loopback.1951920884
Directory /workspace/16.uart_loopback/latest

Test location /workspace/coverage/default/16.uart_noise_filter.778306014
Short name T709
Test name
Test status
Simulation time 79770270418 ps
CPU time 35.61 seconds
Started Aug 03 04:52:23 PM PDT 24
Finished Aug 03 04:52:59 PM PDT 24
Peak memory 207604 kb
Host smart-9b178e96-ef0c-4d75-8ff0-fcf28152e9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778306014 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_noise_filter.778306014
Directory /workspace/16.uart_noise_filter/latest

Test location /workspace/coverage/default/16.uart_perf.2464787669
Short name T437
Test name
Test status
Simulation time 16696999975 ps
CPU time 983.56 seconds
Started Aug 03 04:52:26 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 199844 kb
Host smart-4c3f067a-74eb-456d-a710-d945bd9b5fa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2464787669 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_perf.2464787669
Directory /workspace/16.uart_perf/latest

Test location /workspace/coverage/default/16.uart_rx_oversample.2212709602
Short name T813
Test name
Test status
Simulation time 4777262966 ps
CPU time 37 seconds
Started Aug 03 04:52:23 PM PDT 24
Finished Aug 03 04:53:00 PM PDT 24
Peak memory 197668 kb
Host smart-aefb418e-c825-4e0e-9a88-dd556a8e325a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212709602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_oversample.2212709602
Directory /workspace/16.uart_rx_oversample/latest

Test location /workspace/coverage/default/16.uart_rx_parity_err.227262134
Short name T283
Test name
Test status
Simulation time 290420944231 ps
CPU time 259.1 seconds
Started Aug 03 04:52:29 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 199868 kb
Host smart-29df23cd-aa63-41b6-9532-36e6e8b85cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227262134 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_parity_err.227262134
Directory /workspace/16.uart_rx_parity_err/latest

Test location /workspace/coverage/default/16.uart_rx_start_bit_filter.3329944998
Short name T756
Test name
Test status
Simulation time 43994473142 ps
CPU time 62.78 seconds
Started Aug 03 04:52:23 PM PDT 24
Finished Aug 03 04:53:26 PM PDT 24
Peak memory 196432 kb
Host smart-92c26bac-94a7-4f19-8d60-05695803312e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329944998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_rx_start_bit_filter.3329944998
Directory /workspace/16.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/16.uart_smoke.2355159250
Short name T349
Test name
Test status
Simulation time 965699876 ps
CPU time 2.23 seconds
Started Aug 03 04:52:20 PM PDT 24
Finished Aug 03 04:52:22 PM PDT 24
Peak memory 198724 kb
Host smart-9b2ba6e7-710d-48cb-b320-c98bf9eb2469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355159250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_smoke.2355159250
Directory /workspace/16.uart_smoke/latest

Test location /workspace/coverage/default/16.uart_stress_all.3202698695
Short name T784
Test name
Test status
Simulation time 281340288698 ps
CPU time 252.91 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:56:38 PM PDT 24
Peak memory 208244 kb
Host smart-35cbe423-23dd-4e26-bdac-ea53dd4cea47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202698695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_stress_all.3202698695
Directory /workspace/16.uart_stress_all/latest

Test location /workspace/coverage/default/16.uart_tx_ovrd.2088970910
Short name T255
Test name
Test status
Simulation time 1922320364 ps
CPU time 2 seconds
Started Aug 03 04:52:27 PM PDT 24
Finished Aug 03 04:52:29 PM PDT 24
Peak memory 199820 kb
Host smart-5317cd7e-580f-4665-aedf-6f470638422c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088970910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_ovrd.2088970910
Directory /workspace/16.uart_tx_ovrd/latest

Test location /workspace/coverage/default/16.uart_tx_rx.1504218559
Short name T559
Test name
Test status
Simulation time 86185453160 ps
CPU time 52.32 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:53:17 PM PDT 24
Peak memory 199864 kb
Host smart-c2036fe9-9e94-4b7b-b5d5-2e5d22906084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504218559 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.uart_tx_rx.1504218559
Directory /workspace/16.uart_tx_rx/latest

Test location /workspace/coverage/default/160.uart_fifo_reset.4022888843
Short name T982
Test name
Test status
Simulation time 161704666370 ps
CPU time 51.41 seconds
Started Aug 03 04:56:57 PM PDT 24
Finished Aug 03 04:57:49 PM PDT 24
Peak memory 199816 kb
Host smart-86e9b8dd-cbfc-4b41-b138-be9fd1a2a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022888843 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 160.uart_fifo_reset.4022888843
Directory /workspace/160.uart_fifo_reset/latest

Test location /workspace/coverage/default/161.uart_fifo_reset.3097453367
Short name T198
Test name
Test status
Simulation time 42456970954 ps
CPU time 78.27 seconds
Started Aug 03 04:56:59 PM PDT 24
Finished Aug 03 04:58:17 PM PDT 24
Peak memory 199888 kb
Host smart-42d054d8-5c57-4cf3-afe5-7de83473a4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097453367 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 161.uart_fifo_reset.3097453367
Directory /workspace/161.uart_fifo_reset/latest

Test location /workspace/coverage/default/162.uart_fifo_reset.1998227372
Short name T986
Test name
Test status
Simulation time 83241702915 ps
CPU time 121.57 seconds
Started Aug 03 04:57:00 PM PDT 24
Finished Aug 03 04:59:02 PM PDT 24
Peak memory 199920 kb
Host smart-232a7e9c-56a7-4f3b-8f19-2c879d189017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998227372 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 162.uart_fifo_reset.1998227372
Directory /workspace/162.uart_fifo_reset/latest

Test location /workspace/coverage/default/163.uart_fifo_reset.2939733954
Short name T795
Test name
Test status
Simulation time 56761351378 ps
CPU time 26.5 seconds
Started Aug 03 04:56:59 PM PDT 24
Finished Aug 03 04:57:25 PM PDT 24
Peak memory 199884 kb
Host smart-339e04be-6ee2-405b-b676-e190669ce55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939733954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 163.uart_fifo_reset.2939733954
Directory /workspace/163.uart_fifo_reset/latest

Test location /workspace/coverage/default/164.uart_fifo_reset.1652882965
Short name T823
Test name
Test status
Simulation time 97664975838 ps
CPU time 27.94 seconds
Started Aug 03 04:56:57 PM PDT 24
Finished Aug 03 04:57:25 PM PDT 24
Peak memory 199544 kb
Host smart-d2757efc-7152-40c6-9246-7a8cea3ba102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652882965 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 164.uart_fifo_reset.1652882965
Directory /workspace/164.uart_fifo_reset/latest

Test location /workspace/coverage/default/165.uart_fifo_reset.448137304
Short name T201
Test name
Test status
Simulation time 45520698907 ps
CPU time 19.77 seconds
Started Aug 03 04:56:59 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 199912 kb
Host smart-9e21805b-b4a6-4333-b625-106c3bda1235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448137304 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.uart_fifo_reset.448137304
Directory /workspace/165.uart_fifo_reset/latest

Test location /workspace/coverage/default/166.uart_fifo_reset.1229827970
Short name T577
Test name
Test status
Simulation time 17925930356 ps
CPU time 32.71 seconds
Started Aug 03 04:57:07 PM PDT 24
Finished Aug 03 04:57:40 PM PDT 24
Peak memory 199932 kb
Host smart-c142a990-7056-49de-8ec0-f1907321d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229827970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 166.uart_fifo_reset.1229827970
Directory /workspace/166.uart_fifo_reset/latest

Test location /workspace/coverage/default/167.uart_fifo_reset.3985308114
Short name T856
Test name
Test status
Simulation time 46190813730 ps
CPU time 32.57 seconds
Started Aug 03 04:57:08 PM PDT 24
Finished Aug 03 04:57:41 PM PDT 24
Peak memory 199820 kb
Host smart-fcc5d306-fe77-4b86-ba93-b4f02f93ef86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985308114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 167.uart_fifo_reset.3985308114
Directory /workspace/167.uart_fifo_reset/latest

Test location /workspace/coverage/default/168.uart_fifo_reset.2786292132
Short name T636
Test name
Test status
Simulation time 20555462518 ps
CPU time 19.73 seconds
Started Aug 03 04:57:05 PM PDT 24
Finished Aug 03 04:57:25 PM PDT 24
Peak memory 199864 kb
Host smart-f361ae30-c4fe-4e96-a61d-9ec62184cce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786292132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 168.uart_fifo_reset.2786292132
Directory /workspace/168.uart_fifo_reset/latest

Test location /workspace/coverage/default/169.uart_fifo_reset.3154114104
Short name T918
Test name
Test status
Simulation time 25948922038 ps
CPU time 14.15 seconds
Started Aug 03 04:57:03 PM PDT 24
Finished Aug 03 04:57:18 PM PDT 24
Peak memory 199900 kb
Host smart-72d30078-a404-48a9-a12f-d2a918ec7ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154114104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 169.uart_fifo_reset.3154114104
Directory /workspace/169.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_alert_test.4171231796
Short name T357
Test name
Test status
Simulation time 10995084 ps
CPU time 0.54 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 194724 kb
Host smart-18c74633-36d9-4b5a-b258-66c3f8bddeb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171231796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_alert_test.4171231796
Directory /workspace/17.uart_alert_test/latest

Test location /workspace/coverage/default/17.uart_fifo_full.2461866301
Short name T278
Test name
Test status
Simulation time 163716766455 ps
CPU time 37.11 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:53:02 PM PDT 24
Peak memory 199928 kb
Host smart-9e8501b6-eb5d-4ffc-8d4e-e3b3e7d93550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461866301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_full.2461866301
Directory /workspace/17.uart_fifo_full/latest

Test location /workspace/coverage/default/17.uart_fifo_overflow.2916210621
Short name T653
Test name
Test status
Simulation time 53197165455 ps
CPU time 46.24 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:53:11 PM PDT 24
Peak memory 199596 kb
Host smart-544e82f6-62e5-42ae-ada5-807898caefa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916210621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_overflow.2916210621
Directory /workspace/17.uart_fifo_overflow/latest

Test location /workspace/coverage/default/17.uart_fifo_reset.3309375821
Short name T708
Test name
Test status
Simulation time 98063704378 ps
CPU time 82.48 seconds
Started Aug 03 04:52:27 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 199828 kb
Host smart-be8935ed-8cf2-4abe-ba5a-3b4093ddca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309375821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_fifo_reset.3309375821
Directory /workspace/17.uart_fifo_reset/latest

Test location /workspace/coverage/default/17.uart_intr.1579174347
Short name T405
Test name
Test status
Simulation time 125234068336 ps
CPU time 26.08 seconds
Started Aug 03 04:52:26 PM PDT 24
Finished Aug 03 04:52:52 PM PDT 24
Peak memory 199776 kb
Host smart-ce7497d3-1c05-4a2b-a953-60083fd62ae4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579174347 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_intr.1579174347
Directory /workspace/17.uart_intr/latest

Test location /workspace/coverage/default/17.uart_long_xfer_wo_dly.4140654131
Short name T1175
Test name
Test status
Simulation time 139541827403 ps
CPU time 184.87 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 04:55:29 PM PDT 24
Peak memory 199908 kb
Host smart-8963abf9-e140-4e5b-bd44-d91367c38424
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4140654131 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_long_xfer_wo_dly.4140654131
Directory /workspace/17.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/17.uart_loopback.1865857330
Short name T322
Test name
Test status
Simulation time 10231385726 ps
CPU time 8.43 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 04:52:33 PM PDT 24
Peak memory 199848 kb
Host smart-5d908285-9309-4e9e-a262-7add3d846925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865857330 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_loopback.1865857330
Directory /workspace/17.uart_loopback/latest

Test location /workspace/coverage/default/17.uart_noise_filter.1152197056
Short name T1107
Test name
Test status
Simulation time 7121155752 ps
CPU time 12.09 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 04:52:36 PM PDT 24
Peak memory 195744 kb
Host smart-e6dfa25e-e820-4aef-9c4b-5d8233ab9e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152197056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_noise_filter.1152197056
Directory /workspace/17.uart_noise_filter/latest

Test location /workspace/coverage/default/17.uart_perf.2763116123
Short name T243
Test name
Test status
Simulation time 10516080833 ps
CPU time 452.21 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:59:57 PM PDT 24
Peak memory 199836 kb
Host smart-ea67e405-9337-4a07-8d30-82ac94f83a98
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2763116123 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_perf.2763116123
Directory /workspace/17.uart_perf/latest

Test location /workspace/coverage/default/17.uart_rx_oversample.775430604
Short name T997
Test name
Test status
Simulation time 5873943204 ps
CPU time 49.32 seconds
Started Aug 03 04:52:26 PM PDT 24
Finished Aug 03 04:53:15 PM PDT 24
Peak memory 198428 kb
Host smart-9fa05931-794f-4dbe-82b3-ed041c793785
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=775430604 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_oversample.775430604
Directory /workspace/17.uart_rx_oversample/latest

Test location /workspace/coverage/default/17.uart_rx_parity_err.595923536
Short name T568
Test name
Test status
Simulation time 165591786240 ps
CPU time 148.39 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 04:54:53 PM PDT 24
Peak memory 199872 kb
Host smart-ca27a718-f7c6-4731-b0ff-aed1e6f4adb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595923536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_parity_err.595923536
Directory /workspace/17.uart_rx_parity_err/latest

Test location /workspace/coverage/default/17.uart_rx_start_bit_filter.4042937143
Short name T958
Test name
Test status
Simulation time 4642625246 ps
CPU time 7.4 seconds
Started Aug 03 04:52:28 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 196464 kb
Host smart-426ba543-dc79-4ce5-b3df-1a175cb79e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042937143 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_rx_start_bit_filter.4042937143
Directory /workspace/17.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/17.uart_smoke.326768030
Short name T88
Test name
Test status
Simulation time 449608208 ps
CPU time 2.08 seconds
Started Aug 03 04:52:24 PM PDT 24
Finished Aug 03 04:52:27 PM PDT 24
Peak memory 198700 kb
Host smart-cb485e9f-7183-4f60-b944-ab8b59da4e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326768030 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_smoke.326768030
Directory /workspace/17.uart_smoke/latest

Test location /workspace/coverage/default/17.uart_stress_all.2046156338
Short name T431
Test name
Test status
Simulation time 194678256580 ps
CPU time 979.8 seconds
Started Aug 03 04:52:26 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 199860 kb
Host smart-49605d56-dc79-4503-b9b2-3a4456bf583b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046156338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_stress_all.2046156338
Directory /workspace/17.uart_stress_all/latest

Test location /workspace/coverage/default/17.uart_tx_ovrd.1581066090
Short name T24
Test name
Test status
Simulation time 7626611396 ps
CPU time 12.96 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:38 PM PDT 24
Peak memory 199364 kb
Host smart-2acf4941-5880-4dbd-a846-57683cb895c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581066090 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_ovrd.1581066090
Directory /workspace/17.uart_tx_ovrd/latest

Test location /workspace/coverage/default/17.uart_tx_rx.1095988416
Short name T884
Test name
Test status
Simulation time 43060848723 ps
CPU time 21.65 seconds
Started Aug 03 04:52:25 PM PDT 24
Finished Aug 03 04:52:47 PM PDT 24
Peak memory 199784 kb
Host smart-bc435c30-f99d-4912-8604-283814ba53bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095988416 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.uart_tx_rx.1095988416
Directory /workspace/17.uart_tx_rx/latest

Test location /workspace/coverage/default/170.uart_fifo_reset.838106371
Short name T309
Test name
Test status
Simulation time 194558668143 ps
CPU time 31.31 seconds
Started Aug 03 04:57:08 PM PDT 24
Finished Aug 03 04:57:39 PM PDT 24
Peak memory 199544 kb
Host smart-ea102f8d-0302-43dc-9f28-f39bb3ea3adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838106371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 170.uart_fifo_reset.838106371
Directory /workspace/170.uart_fifo_reset/latest

Test location /workspace/coverage/default/171.uart_fifo_reset.3044927860
Short name T804
Test name
Test status
Simulation time 16000114380 ps
CPU time 14.31 seconds
Started Aug 03 04:57:05 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 199848 kb
Host smart-e10201fa-79ce-42c4-8faa-d6b37bd2f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044927860 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 171.uart_fifo_reset.3044927860
Directory /workspace/171.uart_fifo_reset/latest

Test location /workspace/coverage/default/172.uart_fifo_reset.2775047410
Short name T381
Test name
Test status
Simulation time 54181181968 ps
CPU time 58.5 seconds
Started Aug 03 04:57:06 PM PDT 24
Finished Aug 03 04:58:05 PM PDT 24
Peak memory 199840 kb
Host smart-1d5306f8-36c9-48c2-81c3-447bb75961d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775047410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 172.uart_fifo_reset.2775047410
Directory /workspace/172.uart_fifo_reset/latest

Test location /workspace/coverage/default/173.uart_fifo_reset.2458955601
Short name T705
Test name
Test status
Simulation time 74486734757 ps
CPU time 457.36 seconds
Started Aug 03 04:57:07 PM PDT 24
Finished Aug 03 05:04:44 PM PDT 24
Peak memory 199816 kb
Host smart-a7475bc5-8b53-42e0-a503-4fefd3d543a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458955601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 173.uart_fifo_reset.2458955601
Directory /workspace/173.uart_fifo_reset/latest

Test location /workspace/coverage/default/176.uart_fifo_reset.571570673
Short name T707
Test name
Test status
Simulation time 106577460882 ps
CPU time 68.24 seconds
Started Aug 03 04:57:03 PM PDT 24
Finished Aug 03 04:58:11 PM PDT 24
Peak memory 199920 kb
Host smart-9c1dd1da-1102-4250-9e45-632682405e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571570673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.uart_fifo_reset.571570673
Directory /workspace/176.uart_fifo_reset/latest

Test location /workspace/coverage/default/177.uart_fifo_reset.3337439861
Short name T86
Test name
Test status
Simulation time 23715300659 ps
CPU time 34.21 seconds
Started Aug 03 04:57:05 PM PDT 24
Finished Aug 03 04:57:40 PM PDT 24
Peak memory 199636 kb
Host smart-032038fe-98cf-453c-915b-5db671c6f672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337439861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 177.uart_fifo_reset.3337439861
Directory /workspace/177.uart_fifo_reset/latest

Test location /workspace/coverage/default/178.uart_fifo_reset.868179895
Short name T772
Test name
Test status
Simulation time 28963601033 ps
CPU time 12.44 seconds
Started Aug 03 04:57:07 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 199808 kb
Host smart-1509a96c-1d4d-497f-9786-5fbd2aac4514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868179895 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 178.uart_fifo_reset.868179895
Directory /workspace/178.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_alert_test.2512812799
Short name T1043
Test name
Test status
Simulation time 29857982 ps
CPU time 0.57 seconds
Started Aug 03 04:52:34 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 194704 kb
Host smart-03273b13-d630-4488-9c28-d88253bc81ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512812799 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_alert_test.2512812799
Directory /workspace/18.uart_alert_test/latest

Test location /workspace/coverage/default/18.uart_fifo_full.203562975
Short name T1108
Test name
Test status
Simulation time 48223887119 ps
CPU time 34.92 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:08 PM PDT 24
Peak memory 199868 kb
Host smart-596ecaf4-a61a-49c2-ad6c-54a43c488119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203562975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_full.203562975
Directory /workspace/18.uart_fifo_full/latest

Test location /workspace/coverage/default/18.uart_fifo_overflow.2186821126
Short name T359
Test name
Test status
Simulation time 82202910258 ps
CPU time 9.47 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 199888 kb
Host smart-de62b843-1731-4dff-8c8c-00af16bfa73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186821126 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_overflow.2186821126
Directory /workspace/18.uart_fifo_overflow/latest

Test location /workspace/coverage/default/18.uart_fifo_reset.3048035275
Short name T239
Test name
Test status
Simulation time 34753735282 ps
CPU time 15.87 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 199920 kb
Host smart-dfd60bc1-e97a-438d-ac5d-4891e6fcf67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048035275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_fifo_reset.3048035275
Directory /workspace/18.uart_fifo_reset/latest

Test location /workspace/coverage/default/18.uart_intr.122321044
Short name T586
Test name
Test status
Simulation time 45085776172 ps
CPU time 73.24 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:46 PM PDT 24
Peak memory 199768 kb
Host smart-9ab3c78d-4acd-4d0f-855f-4a4965f4f314
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122321044 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_intr.122321044
Directory /workspace/18.uart_intr/latest

Test location /workspace/coverage/default/18.uart_long_xfer_wo_dly.1461294979
Short name T325
Test name
Test status
Simulation time 54619339695 ps
CPU time 162.53 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:55:14 PM PDT 24
Peak memory 199884 kb
Host smart-7598737d-fd29-4953-8515-aca4330e9a8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1461294979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_long_xfer_wo_dly.1461294979
Directory /workspace/18.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/18.uart_loopback.3273019844
Short name T545
Test name
Test status
Simulation time 2849125399 ps
CPU time 1.99 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 195784 kb
Host smart-6c84db20-2b9c-4e68-b6e6-083e33930ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273019844 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_loopback.3273019844
Directory /workspace/18.uart_loopback/latest

Test location /workspace/coverage/default/18.uart_noise_filter.3642341725
Short name T272
Test name
Test status
Simulation time 51909911032 ps
CPU time 105.94 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:54:18 PM PDT 24
Peak memory 199044 kb
Host smart-b6c580ab-93a3-47c6-a5cc-71255402064f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642341725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_noise_filter.3642341725
Directory /workspace/18.uart_noise_filter/latest

Test location /workspace/coverage/default/18.uart_perf.349167105
Short name T528
Test name
Test status
Simulation time 15627535495 ps
CPU time 399.42 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 199892 kb
Host smart-a910cda0-e34a-4de2-bbb1-2c6beb3cee79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=349167105 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_perf.349167105
Directory /workspace/18.uart_perf/latest

Test location /workspace/coverage/default/18.uart_rx_oversample.1348480657
Short name T970
Test name
Test status
Simulation time 7011409400 ps
CPU time 65.04 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:38 PM PDT 24
Peak memory 197728 kb
Host smart-b1f23365-8217-4527-80db-aea423658b18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348480657 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_oversample.1348480657
Directory /workspace/18.uart_rx_oversample/latest

Test location /workspace/coverage/default/18.uart_rx_parity_err.1913968396
Short name T1046
Test name
Test status
Simulation time 100931382494 ps
CPU time 156.8 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:55:09 PM PDT 24
Peak memory 199900 kb
Host smart-3ef66be6-0d31-4d2f-be98-fa46cae7882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913968396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_parity_err.1913968396
Directory /workspace/18.uart_rx_parity_err/latest

Test location /workspace/coverage/default/18.uart_rx_start_bit_filter.1446940857
Short name T808
Test name
Test status
Simulation time 1960973839 ps
CPU time 1.31 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 195536 kb
Host smart-a35510ac-3f4f-4be2-8770-14f770673fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446940857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_rx_start_bit_filter.1446940857
Directory /workspace/18.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/18.uart_smoke.2083581677
Short name T1097
Test name
Test status
Simulation time 431082368 ps
CPU time 2.19 seconds
Started Aug 03 04:52:27 PM PDT 24
Finished Aug 03 04:52:29 PM PDT 24
Peak memory 199496 kb
Host smart-4f7c5bc0-5e22-4ee0-9e5b-877b370370a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083581677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_smoke.2083581677
Directory /workspace/18.uart_smoke/latest

Test location /workspace/coverage/default/18.uart_stress_all.1582088571
Short name T581
Test name
Test status
Simulation time 122860747697 ps
CPU time 643.29 seconds
Started Aug 03 04:52:35 PM PDT 24
Finished Aug 03 05:03:18 PM PDT 24
Peak memory 199860 kb
Host smart-bc68b7ad-c709-46ca-9f3d-3e6ff54d2637
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582088571 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_stress_all.1582088571
Directory /workspace/18.uart_stress_all/latest

Test location /workspace/coverage/default/18.uart_tx_ovrd.1248363477
Short name T935
Test name
Test status
Simulation time 677795074 ps
CPU time 3.23 seconds
Started Aug 03 04:52:36 PM PDT 24
Finished Aug 03 04:52:39 PM PDT 24
Peak memory 199876 kb
Host smart-15a00069-d29d-4718-b28a-8bb616ad14b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248363477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_ovrd.1248363477
Directory /workspace/18.uart_tx_ovrd/latest

Test location /workspace/coverage/default/18.uart_tx_rx.1885443071
Short name T922
Test name
Test status
Simulation time 150098118645 ps
CPU time 59.09 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 199900 kb
Host smart-9d2c78de-b134-4812-bc09-af85344d686b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885443071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.uart_tx_rx.1885443071
Directory /workspace/18.uart_tx_rx/latest

Test location /workspace/coverage/default/180.uart_fifo_reset.1279048019
Short name T102
Test name
Test status
Simulation time 59830826429 ps
CPU time 18.83 seconds
Started Aug 03 04:57:12 PM PDT 24
Finished Aug 03 04:57:31 PM PDT 24
Peak memory 199728 kb
Host smart-5df481c9-dbb8-4783-8213-6f169056bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279048019 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 180.uart_fifo_reset.1279048019
Directory /workspace/180.uart_fifo_reset/latest

Test location /workspace/coverage/default/181.uart_fifo_reset.1449694633
Short name T917
Test name
Test status
Simulation time 89548120727 ps
CPU time 48.68 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 04:58:02 PM PDT 24
Peak memory 199860 kb
Host smart-eb4dc65e-9743-41e6-8493-2c3f94849513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449694633 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 181.uart_fifo_reset.1449694633
Directory /workspace/181.uart_fifo_reset/latest

Test location /workspace/coverage/default/182.uart_fifo_reset.1952430355
Short name T190
Test name
Test status
Simulation time 132777181188 ps
CPU time 229.84 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 05:01:03 PM PDT 24
Peak memory 199860 kb
Host smart-b9fece12-c173-434e-b735-5b3a01beddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952430355 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 182.uart_fifo_reset.1952430355
Directory /workspace/182.uart_fifo_reset/latest

Test location /workspace/coverage/default/183.uart_fifo_reset.659545124
Short name T916
Test name
Test status
Simulation time 137819145451 ps
CPU time 249.38 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 05:01:23 PM PDT 24
Peak memory 199924 kb
Host smart-dd59adb7-ec73-40f1-8873-c9d3fced2ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659545124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 183.uart_fifo_reset.659545124
Directory /workspace/183.uart_fifo_reset/latest

Test location /workspace/coverage/default/186.uart_fifo_reset.4022619056
Short name T1125
Test name
Test status
Simulation time 31546114088 ps
CPU time 21.13 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 04:57:34 PM PDT 24
Peak memory 199928 kb
Host smart-09528ba1-7135-4384-9bed-b4ac3dd40177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022619056 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 186.uart_fifo_reset.4022619056
Directory /workspace/186.uart_fifo_reset/latest

Test location /workspace/coverage/default/187.uart_fifo_reset.2683582174
Short name T549
Test name
Test status
Simulation time 68640740618 ps
CPU time 353.88 seconds
Started Aug 03 04:57:14 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 199848 kb
Host smart-dcb4f342-abdc-4d0b-8d61-70ace8bfc56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683582174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 187.uart_fifo_reset.2683582174
Directory /workspace/187.uart_fifo_reset/latest

Test location /workspace/coverage/default/188.uart_fifo_reset.976487576
Short name T138
Test name
Test status
Simulation time 94663645290 ps
CPU time 41.1 seconds
Started Aug 03 04:57:13 PM PDT 24
Finished Aug 03 04:57:54 PM PDT 24
Peak memory 199872 kb
Host smart-cbe7b367-8389-4584-974b-770f61ba96c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976487576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 188.uart_fifo_reset.976487576
Directory /workspace/188.uart_fifo_reset/latest

Test location /workspace/coverage/default/189.uart_fifo_reset.4062836986
Short name T248
Test name
Test status
Simulation time 33465644380 ps
CPU time 72.79 seconds
Started Aug 03 04:57:18 PM PDT 24
Finished Aug 03 04:58:31 PM PDT 24
Peak memory 199872 kb
Host smart-7da3ec50-d66d-43cd-8280-d6c6cfca80b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062836986 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 189.uart_fifo_reset.4062836986
Directory /workspace/189.uart_fifo_reset/latest

Test location /workspace/coverage/default/19.uart_alert_test.1328115132
Short name T829
Test name
Test status
Simulation time 15017816 ps
CPU time 0.56 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:52:42 PM PDT 24
Peak memory 195280 kb
Host smart-e854626f-b68a-4692-b37b-f3a70f94baf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328115132 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_alert_test.1328115132
Directory /workspace/19.uart_alert_test/latest

Test location /workspace/coverage/default/19.uart_fifo_full.2860593493
Short name T598
Test name
Test status
Simulation time 164843268452 ps
CPU time 233.02 seconds
Started Aug 03 04:52:32 PM PDT 24
Finished Aug 03 04:56:25 PM PDT 24
Peak memory 199888 kb
Host smart-1480435e-77df-4190-aee1-4c595412cadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860593493 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_full.2860593493
Directory /workspace/19.uart_fifo_full/latest

Test location /workspace/coverage/default/19.uart_fifo_overflow.3468100707
Short name T566
Test name
Test status
Simulation time 265252452647 ps
CPU time 26.81 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:00 PM PDT 24
Peak memory 199596 kb
Host smart-eaaa39cd-2c52-40eb-a7b9-320a0387676e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468100707 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_fifo_overflow.3468100707
Directory /workspace/19.uart_fifo_overflow/latest

Test location /workspace/coverage/default/19.uart_long_xfer_wo_dly.957693546
Short name T466
Test name
Test status
Simulation time 106406540908 ps
CPU time 840.81 seconds
Started Aug 03 04:52:39 PM PDT 24
Finished Aug 03 05:06:40 PM PDT 24
Peak memory 199912 kb
Host smart-c7731247-bdc9-47df-a5ba-159a6d7ad451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=957693546 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_long_xfer_wo_dly.957693546
Directory /workspace/19.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/19.uart_loopback.1938495905
Short name T467
Test name
Test status
Simulation time 2737215252 ps
CPU time 6.87 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 198668 kb
Host smart-b2b12234-1e2c-4840-810e-75b94b2756bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938495905 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_loopback.1938495905
Directory /workspace/19.uart_loopback/latest

Test location /workspace/coverage/default/19.uart_noise_filter.1994750951
Short name T1065
Test name
Test status
Simulation time 229323857242 ps
CPU time 64.88 seconds
Started Aug 03 04:52:34 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 200096 kb
Host smart-aa530923-0e3a-4c13-ac96-0378ea0a12ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994750951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_noise_filter.1994750951
Directory /workspace/19.uart_noise_filter/latest

Test location /workspace/coverage/default/19.uart_perf.3759551491
Short name T887
Test name
Test status
Simulation time 17832612090 ps
CPU time 59.99 seconds
Started Aug 03 04:52:39 PM PDT 24
Finished Aug 03 04:53:40 PM PDT 24
Peak memory 199884 kb
Host smart-edf95e71-aea7-4d17-a07c-b0a05aa9cefc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3759551491 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_perf.3759551491
Directory /workspace/19.uart_perf/latest

Test location /workspace/coverage/default/19.uart_rx_oversample.2634096468
Short name T580
Test name
Test status
Simulation time 5417925654 ps
CPU time 6.08 seconds
Started Aug 03 04:52:34 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 198140 kb
Host smart-7c0c7fc2-b3b2-4e10-9752-8beba3f7f23d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2634096468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_oversample.2634096468
Directory /workspace/19.uart_rx_oversample/latest

Test location /workspace/coverage/default/19.uart_rx_parity_err.1223246473
Short name T713
Test name
Test status
Simulation time 26126704982 ps
CPU time 40.81 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:53:22 PM PDT 24
Peak memory 199772 kb
Host smart-6437568c-13c8-44e1-86d9-02f2b9efbbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223246473 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_parity_err.1223246473
Directory /workspace/19.uart_rx_parity_err/latest

Test location /workspace/coverage/default/19.uart_rx_start_bit_filter.1866350242
Short name T942
Test name
Test status
Simulation time 4604095104 ps
CPU time 1.86 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 196412 kb
Host smart-267bf78d-930a-4c55-aab7-88f6941a37c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866350242 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_rx_start_bit_filter.1866350242
Directory /workspace/19.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/19.uart_smoke.2056690077
Short name T924
Test name
Test status
Simulation time 6291479571 ps
CPU time 18.12 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:52:51 PM PDT 24
Peak memory 199772 kb
Host smart-2ec6c880-8941-4921-829f-e546ab384b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056690077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_smoke.2056690077
Directory /workspace/19.uart_smoke/latest

Test location /workspace/coverage/default/19.uart_stress_all_with_rand_reset.3899853363
Short name T1120
Test name
Test status
Simulation time 196030155320 ps
CPU time 619.63 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 05:03:00 PM PDT 24
Peak memory 224744 kb
Host smart-a74b6a3f-2d11-4c1a-8cbe-bd0426578db3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899853363 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 19.uart_stress_all_with_rand_reset.3899853363
Directory /workspace/19.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.uart_tx_ovrd.20534880
Short name T923
Test name
Test status
Simulation time 869121950 ps
CPU time 3.01 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 198268 kb
Host smart-0b972052-38d3-420c-9371-02f4435f098b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20534880 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_ovrd.20534880
Directory /workspace/19.uart_tx_ovrd/latest

Test location /workspace/coverage/default/19.uart_tx_rx.936876900
Short name T875
Test name
Test status
Simulation time 147793427326 ps
CPU time 55.98 seconds
Started Aug 03 04:52:33 PM PDT 24
Finished Aug 03 04:53:29 PM PDT 24
Peak memory 199828 kb
Host smart-fea460bd-c939-4dc3-b075-78b89a1c6e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936876900 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.uart_tx_rx.936876900
Directory /workspace/19.uart_tx_rx/latest

Test location /workspace/coverage/default/190.uart_fifo_reset.3365701301
Short name T146
Test name
Test status
Simulation time 96655808859 ps
CPU time 64.91 seconds
Started Aug 03 04:57:18 PM PDT 24
Finished Aug 03 04:58:23 PM PDT 24
Peak memory 199904 kb
Host smart-41064e21-41b4-463e-9cce-a7843e388963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365701301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 190.uart_fifo_reset.3365701301
Directory /workspace/190.uart_fifo_reset/latest

Test location /workspace/coverage/default/191.uart_fifo_reset.4208356148
Short name T1167
Test name
Test status
Simulation time 38658558526 ps
CPU time 54.26 seconds
Started Aug 03 04:57:20 PM PDT 24
Finished Aug 03 04:58:14 PM PDT 24
Peak memory 199664 kb
Host smart-3d8161b6-5354-40ce-8bfd-02a4c889dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208356148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 191.uart_fifo_reset.4208356148
Directory /workspace/191.uart_fifo_reset/latest

Test location /workspace/coverage/default/192.uart_fifo_reset.3015101489
Short name T151
Test name
Test status
Simulation time 46893060931 ps
CPU time 25.3 seconds
Started Aug 03 04:57:17 PM PDT 24
Finished Aug 03 04:57:42 PM PDT 24
Peak memory 199900 kb
Host smart-911f06e7-081f-47f2-8189-ed1e1283d700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015101489 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 192.uart_fifo_reset.3015101489
Directory /workspace/192.uart_fifo_reset/latest

Test location /workspace/coverage/default/193.uart_fifo_reset.714526899
Short name T512
Test name
Test status
Simulation time 104941368037 ps
CPU time 157.73 seconds
Started Aug 03 04:57:18 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 199720 kb
Host smart-59e25343-aed9-4073-83ad-af81c9b712b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714526899 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.uart_fifo_reset.714526899
Directory /workspace/193.uart_fifo_reset/latest

Test location /workspace/coverage/default/194.uart_fifo_reset.3040624285
Short name T270
Test name
Test status
Simulation time 62620192972 ps
CPU time 22.75 seconds
Started Aug 03 04:57:20 PM PDT 24
Finished Aug 03 04:57:43 PM PDT 24
Peak memory 199920 kb
Host smart-4a1cedc0-da0d-478d-8f29-eaecdb3362d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040624285 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 194.uart_fifo_reset.3040624285
Directory /workspace/194.uart_fifo_reset/latest

Test location /workspace/coverage/default/195.uart_fifo_reset.3033585318
Short name T396
Test name
Test status
Simulation time 30380490959 ps
CPU time 49.42 seconds
Started Aug 03 04:57:18 PM PDT 24
Finished Aug 03 04:58:08 PM PDT 24
Peak memory 199936 kb
Host smart-139ca1c9-797b-4bf8-aadb-18b73c74242f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033585318 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 195.uart_fifo_reset.3033585318
Directory /workspace/195.uart_fifo_reset/latest

Test location /workspace/coverage/default/196.uart_fifo_reset.1976864406
Short name T621
Test name
Test status
Simulation time 80810105977 ps
CPU time 107.18 seconds
Started Aug 03 04:57:29 PM PDT 24
Finished Aug 03 04:59:16 PM PDT 24
Peak memory 199828 kb
Host smart-a6faf105-338d-494b-b99a-d0133cbfad82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976864406 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 196.uart_fifo_reset.1976864406
Directory /workspace/196.uart_fifo_reset/latest

Test location /workspace/coverage/default/197.uart_fifo_reset.2754417742
Short name T113
Test name
Test status
Simulation time 38711278636 ps
CPU time 65.64 seconds
Started Aug 03 04:57:27 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 199756 kb
Host smart-76c57cff-d419-48bc-b1e5-4c639cc8747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754417742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 197.uart_fifo_reset.2754417742
Directory /workspace/197.uart_fifo_reset/latest

Test location /workspace/coverage/default/198.uart_fifo_reset.1862221800
Short name T112
Test name
Test status
Simulation time 178905002593 ps
CPU time 107.87 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:59:13 PM PDT 24
Peak memory 199920 kb
Host smart-90847cf3-6324-4eb8-9f61-b769c56ec8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862221800 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 198.uart_fifo_reset.1862221800
Directory /workspace/198.uart_fifo_reset/latest

Test location /workspace/coverage/default/199.uart_fifo_reset.4026235484
Short name T202
Test name
Test status
Simulation time 36080501385 ps
CPU time 66.4 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:58:31 PM PDT 24
Peak memory 199824 kb
Host smart-a760a5bd-c3eb-4f13-81cc-8d75151e27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026235484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 199.uart_fifo_reset.4026235484
Directory /workspace/199.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_alert_test.3072873213
Short name T764
Test name
Test status
Simulation time 64520937 ps
CPU time 0.61 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:51:50 PM PDT 24
Peak memory 195476 kb
Host smart-fe2109f7-14cd-48f5-ac6e-d29bcc81e03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072873213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_alert_test.3072873213
Directory /workspace/2.uart_alert_test/latest

Test location /workspace/coverage/default/2.uart_fifo_full.1598251866
Short name T1022
Test name
Test status
Simulation time 45676571883 ps
CPU time 22.94 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 199936 kb
Host smart-0cbd8bb7-1ff7-42ab-b093-a62b0498f75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598251866 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_full.1598251866
Directory /workspace/2.uart_fifo_full/latest

Test location /workspace/coverage/default/2.uart_fifo_overflow.1000415376
Short name T972
Test name
Test status
Simulation time 88464269837 ps
CPU time 164.52 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199820 kb
Host smart-d226a2ed-449c-4f70-8fca-7ca9716ff558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000415376 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_overflow.1000415376
Directory /workspace/2.uart_fifo_overflow/latest

Test location /workspace/coverage/default/2.uart_fifo_reset.2722738698
Short name T1091
Test name
Test status
Simulation time 12938457321 ps
CPU time 20.17 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 199804 kb
Host smart-b1c598f1-8676-41cd-9558-c2f1a59964c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722738698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_fifo_reset.2722738698
Directory /workspace/2.uart_fifo_reset/latest

Test location /workspace/coverage/default/2.uart_intr.3653307960
Short name T961
Test name
Test status
Simulation time 44354718430 ps
CPU time 23.77 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:52:11 PM PDT 24
Peak memory 199832 kb
Host smart-e469e68d-ae86-4191-b315-9f390fc06346
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653307960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_intr.3653307960
Directory /workspace/2.uart_intr/latest

Test location /workspace/coverage/default/2.uart_long_xfer_wo_dly.1035219365
Short name T418
Test name
Test status
Simulation time 182785874305 ps
CPU time 233.2 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:55:44 PM PDT 24
Peak memory 200020 kb
Host smart-a54e5d7d-394b-4db8-afe2-ca6a3a76b656
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1035219365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_long_xfer_wo_dly.1035219365
Directory /workspace/2.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/2.uart_loopback.854353040
Short name T531
Test name
Test status
Simulation time 6594564580 ps
CPU time 7.33 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:51:55 PM PDT 24
Peak memory 199780 kb
Host smart-f0f04db0-be4f-4799-a2d6-67fbcef2a623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854353040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_loopback.854353040
Directory /workspace/2.uart_loopback/latest

Test location /workspace/coverage/default/2.uart_noise_filter.2188891136
Short name T1088
Test name
Test status
Simulation time 64044230204 ps
CPU time 23.58 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:52:13 PM PDT 24
Peak memory 199024 kb
Host smart-5c397d4d-4289-4313-a5c3-237e1798cc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188891136 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_noise_filter.2188891136
Directory /workspace/2.uart_noise_filter/latest

Test location /workspace/coverage/default/2.uart_perf.945345709
Short name T416
Test name
Test status
Simulation time 18952178076 ps
CPU time 223.52 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:55:33 PM PDT 24
Peak memory 199872 kb
Host smart-e1f74e02-5b15-472d-b4e7-34cfd3963d00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=945345709 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_perf.945345709
Directory /workspace/2.uart_perf/latest

Test location /workspace/coverage/default/2.uart_rx_oversample.2112915419
Short name T480
Test name
Test status
Simulation time 3541704392 ps
CPU time 4.88 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:51:54 PM PDT 24
Peak memory 198552 kb
Host smart-659e60a9-890e-43ba-8fc6-1a492963e40b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2112915419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_oversample.2112915419
Directory /workspace/2.uart_rx_oversample/latest

Test location /workspace/coverage/default/2.uart_rx_parity_err.2377967820
Short name T608
Test name
Test status
Simulation time 120898265208 ps
CPU time 36.98 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:27 PM PDT 24
Peak memory 199864 kb
Host smart-46c26485-a368-4c41-b421-31880135d3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377967820 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_parity_err.2377967820
Directory /workspace/2.uart_rx_parity_err/latest

Test location /workspace/coverage/default/2.uart_rx_start_bit_filter.4183020630
Short name T1010
Test name
Test status
Simulation time 4848683861 ps
CPU time 2.73 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:51:53 PM PDT 24
Peak memory 196240 kb
Host smart-bc1753a1-99fc-4cd1-a175-e2d3668eaffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183020630 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_rx_start_bit_filter.4183020630
Directory /workspace/2.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/2.uart_sec_cm.4246644106
Short name T34
Test name
Test status
Simulation time 35256846 ps
CPU time 0.75 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:51:48 PM PDT 24
Peak memory 218428 kb
Host smart-fd54437c-f31b-4991-b083-aebeab0bc690
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246644106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_sec_cm.4246644106
Directory /workspace/2.uart_sec_cm/latest

Test location /workspace/coverage/default/2.uart_smoke.275926907
Short name T326
Test name
Test status
Simulation time 276695001 ps
CPU time 1.49 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:51:49 PM PDT 24
Peak memory 198144 kb
Host smart-bfe3d4f6-4cbd-4426-abbb-ef2507c1697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275926907 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_smoke.275926907
Directory /workspace/2.uart_smoke/latest

Test location /workspace/coverage/default/2.uart_stress_all.1516007071
Short name T564
Test name
Test status
Simulation time 262458707762 ps
CPU time 422.67 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:58:52 PM PDT 24
Peak memory 215496 kb
Host smart-ec6c3882-68c9-494a-a96d-338ab52555e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516007071 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_stress_all.1516007071
Directory /workspace/2.uart_stress_all/latest

Test location /workspace/coverage/default/2.uart_stress_all_with_rand_reset.514375294
Short name T1084
Test name
Test status
Simulation time 42812049409 ps
CPU time 219.67 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:55:27 PM PDT 24
Peak memory 212020 kb
Host smart-bdc8372d-4ac7-4740-9376-5e89fbcc0ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514375294 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 2.uart_stress_all_with_rand_reset.514375294
Directory /workspace/2.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.uart_tx_ovrd.3725690917
Short name T643
Test name
Test status
Simulation time 520688104 ps
CPU time 1.71 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:51:48 PM PDT 24
Peak memory 198508 kb
Host smart-5a8d498f-8121-48a8-9739-ec8647dc99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725690917 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_ovrd.3725690917
Directory /workspace/2.uart_tx_ovrd/latest

Test location /workspace/coverage/default/2.uart_tx_rx.1215840804
Short name T1049
Test name
Test status
Simulation time 68295833233 ps
CPU time 56.71 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 199876 kb
Host smart-b88ee266-6059-4ef7-8b74-8eec1c36aefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215840804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.uart_tx_rx.1215840804
Directory /workspace/2.uart_tx_rx/latest

Test location /workspace/coverage/default/20.uart_alert_test.3119543829
Short name T1105
Test name
Test status
Simulation time 39744506 ps
CPU time 0.57 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:52:41 PM PDT 24
Peak memory 195572 kb
Host smart-46f7faa4-8630-4d02-8269-c2655dcb33be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119543829 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_alert_test.3119543829
Directory /workspace/20.uart_alert_test/latest

Test location /workspace/coverage/default/20.uart_fifo_overflow.2937209996
Short name T1157
Test name
Test status
Simulation time 235510504256 ps
CPU time 39.11 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:53:19 PM PDT 24
Peak memory 199924 kb
Host smart-07614337-b728-420d-a3d9-6135d7638d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937209996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_overflow.2937209996
Directory /workspace/20.uart_fifo_overflow/latest

Test location /workspace/coverage/default/20.uart_fifo_reset.524251758
Short name T657
Test name
Test status
Simulation time 8899926235 ps
CPU time 13.86 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:53:00 PM PDT 24
Peak memory 199812 kb
Host smart-0e7816c9-6639-4ea0-a43b-72673c13e9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524251758 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_fifo_reset.524251758
Directory /workspace/20.uart_fifo_reset/latest

Test location /workspace/coverage/default/20.uart_intr.3104603754
Short name T279
Test name
Test status
Simulation time 22038887681 ps
CPU time 31.68 seconds
Started Aug 03 04:52:42 PM PDT 24
Finished Aug 03 04:53:14 PM PDT 24
Peak memory 199816 kb
Host smart-cc4c2c88-28d1-4d96-8f87-c2a15b0f3eec
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104603754 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_intr.3104603754
Directory /workspace/20.uart_intr/latest

Test location /workspace/coverage/default/20.uart_long_xfer_wo_dly.3357596614
Short name T919
Test name
Test status
Simulation time 147144157854 ps
CPU time 271.22 seconds
Started Aug 03 04:52:38 PM PDT 24
Finished Aug 03 04:57:10 PM PDT 24
Peak memory 199892 kb
Host smart-0a3333f2-9297-47a8-88e2-2150e1da4c6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3357596614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_long_xfer_wo_dly.3357596614
Directory /workspace/20.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/20.uart_loopback.2895366621
Short name T1057
Test name
Test status
Simulation time 4480970115 ps
CPU time 7.43 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 199056 kb
Host smart-6454eb5b-20d7-4f0a-8f61-72ee578b44bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895366621 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_loopback.2895366621
Directory /workspace/20.uart_loopback/latest

Test location /workspace/coverage/default/20.uart_noise_filter.4265808482
Short name T247
Test name
Test status
Simulation time 35246721310 ps
CPU time 25.64 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:53:07 PM PDT 24
Peak memory 197912 kb
Host smart-4127bad4-cc25-404b-9416-f959d92c9770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265808482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_noise_filter.4265808482
Directory /workspace/20.uart_noise_filter/latest

Test location /workspace/coverage/default/20.uart_perf.1851639029
Short name T339
Test name
Test status
Simulation time 6329663502 ps
CPU time 276.76 seconds
Started Aug 03 04:52:42 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 199856 kb
Host smart-bf8ff1f6-f703-49b8-a275-9276563bf962
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851639029 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_perf.1851639029
Directory /workspace/20.uart_perf/latest

Test location /workspace/coverage/default/20.uart_rx_oversample.2412582430
Short name T379
Test name
Test status
Simulation time 4312338484 ps
CPU time 34.4 seconds
Started Aug 03 04:52:39 PM PDT 24
Finished Aug 03 04:53:14 PM PDT 24
Peak memory 199148 kb
Host smart-25771ed7-ee79-418a-8279-3bec4fefbb19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2412582430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_oversample.2412582430
Directory /workspace/20.uart_rx_oversample/latest

Test location /workspace/coverage/default/20.uart_rx_parity_err.4237082289
Short name T984
Test name
Test status
Simulation time 187486005747 ps
CPU time 102.12 seconds
Started Aug 03 04:52:43 PM PDT 24
Finished Aug 03 04:54:25 PM PDT 24
Peak memory 199640 kb
Host smart-60569960-5106-4428-b7eb-e600d8c1389d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237082289 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_parity_err.4237082289
Directory /workspace/20.uart_rx_parity_err/latest

Test location /workspace/coverage/default/20.uart_rx_start_bit_filter.87924772
Short name T1151
Test name
Test status
Simulation time 2262293054 ps
CPU time 2.3 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:52:44 PM PDT 24
Peak memory 195472 kb
Host smart-2edaa65f-f69a-4f29-b50e-1c94462f462c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87924772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_rx_start_bit_filter.87924772
Directory /workspace/20.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/20.uart_smoke.3163502688
Short name T686
Test name
Test status
Simulation time 934722704 ps
CPU time 3.15 seconds
Started Aug 03 04:52:39 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 199476 kb
Host smart-45812696-547a-467d-9e43-5441649128ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163502688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_smoke.3163502688
Directory /workspace/20.uart_smoke/latest

Test location /workspace/coverage/default/20.uart_stress_all.732339906
Short name T450
Test name
Test status
Simulation time 371365987676 ps
CPU time 550.22 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 05:01:51 PM PDT 24
Peak memory 199812 kb
Host smart-abfaebc1-6435-46aa-a21f-c2a74c722c1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732339906 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_stress_all.732339906
Directory /workspace/20.uart_stress_all/latest

Test location /workspace/coverage/default/20.uart_stress_all_with_rand_reset.4169122424
Short name T722
Test name
Test status
Simulation time 51481938962 ps
CPU time 375.74 seconds
Started Aug 03 04:52:41 PM PDT 24
Finished Aug 03 04:58:57 PM PDT 24
Peak memory 216296 kb
Host smart-574f6955-cca1-4e1a-b33d-60dc4fe1acd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169122424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 20.uart_stress_all_with_rand_reset.4169122424
Directory /workspace/20.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.uart_tx_ovrd.3844596172
Short name T344
Test name
Test status
Simulation time 1566554166 ps
CPU time 2 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:52:43 PM PDT 24
Peak memory 198248 kb
Host smart-2a43cd9e-cd46-4604-8989-8c610cf83c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844596172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_ovrd.3844596172
Directory /workspace/20.uart_tx_ovrd/latest

Test location /workspace/coverage/default/20.uart_tx_rx.3027324857
Short name T952
Test name
Test status
Simulation time 103538394391 ps
CPU time 174.9 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:55:35 PM PDT 24
Peak memory 199856 kb
Host smart-43be256e-672c-4541-9b59-d2203d5a6002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027324857 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.uart_tx_rx.3027324857
Directory /workspace/20.uart_tx_rx/latest

Test location /workspace/coverage/default/201.uart_fifo_reset.3785897245
Short name T280
Test name
Test status
Simulation time 61148155326 ps
CPU time 26.59 seconds
Started Aug 03 04:57:29 PM PDT 24
Finished Aug 03 04:57:55 PM PDT 24
Peak memory 199768 kb
Host smart-48efcebf-02c5-4912-a9e0-1a0d68da1e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785897245 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 201.uart_fifo_reset.3785897245
Directory /workspace/201.uart_fifo_reset/latest

Test location /workspace/coverage/default/203.uart_fifo_reset.710519438
Short name T207
Test name
Test status
Simulation time 12147154488 ps
CPU time 23.85 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:57:49 PM PDT 24
Peak memory 199820 kb
Host smart-5ae75e90-b134-4283-b65e-061f708f16cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710519438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 203.uart_fifo_reset.710519438
Directory /workspace/203.uart_fifo_reset/latest

Test location /workspace/coverage/default/204.uart_fifo_reset.1583041193
Short name T107
Test name
Test status
Simulation time 52478231365 ps
CPU time 98.5 seconds
Started Aug 03 04:57:25 PM PDT 24
Finished Aug 03 04:59:03 PM PDT 24
Peak memory 199788 kb
Host smart-3cd509a4-6246-449d-890c-65f1ca6d0e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583041193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 204.uart_fifo_reset.1583041193
Directory /workspace/204.uart_fifo_reset/latest

Test location /workspace/coverage/default/205.uart_fifo_reset.3316987834
Short name T682
Test name
Test status
Simulation time 41058164297 ps
CPU time 11.59 seconds
Started Aug 03 04:57:28 PM PDT 24
Finished Aug 03 04:57:40 PM PDT 24
Peak memory 199868 kb
Host smart-ce5c4e54-6357-4699-a03b-6347d8a5f7bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316987834 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 205.uart_fifo_reset.3316987834
Directory /workspace/205.uart_fifo_reset/latest

Test location /workspace/coverage/default/206.uart_fifo_reset.4124089886
Short name T197
Test name
Test status
Simulation time 30690241460 ps
CPU time 54.7 seconds
Started Aug 03 04:57:30 PM PDT 24
Finished Aug 03 04:58:24 PM PDT 24
Peak memory 199832 kb
Host smart-56ae128b-ef9a-4209-a3a0-5c5c42be15b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124089886 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 206.uart_fifo_reset.4124089886
Directory /workspace/206.uart_fifo_reset/latest

Test location /workspace/coverage/default/207.uart_fifo_reset.1574744675
Short name T993
Test name
Test status
Simulation time 245545505899 ps
CPU time 186.51 seconds
Started Aug 03 04:57:26 PM PDT 24
Finished Aug 03 05:00:32 PM PDT 24
Peak memory 199760 kb
Host smart-d0e08284-3464-4ce3-ac98-13d884216331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574744675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 207.uart_fifo_reset.1574744675
Directory /workspace/207.uart_fifo_reset/latest

Test location /workspace/coverage/default/208.uart_fifo_reset.636313815
Short name T988
Test name
Test status
Simulation time 32132665977 ps
CPU time 22.57 seconds
Started Aug 03 04:57:24 PM PDT 24
Finished Aug 03 04:57:46 PM PDT 24
Peak memory 199892 kb
Host smart-d3cddcc8-8d50-4808-98f8-6e356018e7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636313815 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 208.uart_fifo_reset.636313815
Directory /workspace/208.uart_fifo_reset/latest

Test location /workspace/coverage/default/209.uart_fifo_reset.3835410762
Short name T214
Test name
Test status
Simulation time 45449932910 ps
CPU time 14.6 seconds
Started Aug 03 04:57:32 PM PDT 24
Finished Aug 03 04:57:47 PM PDT 24
Peak memory 199832 kb
Host smart-d0e0759a-6b54-49e5-8ef7-8350f9ee3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835410762 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 209.uart_fifo_reset.3835410762
Directory /workspace/209.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_alert_test.1796086459
Short name T894
Test name
Test status
Simulation time 14219886 ps
CPU time 0.55 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:52:52 PM PDT 24
Peak memory 194260 kb
Host smart-e3df9a66-244d-413a-af4c-f97024b6ee60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796086459 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_alert_test.1796086459
Directory /workspace/21.uart_alert_test/latest

Test location /workspace/coverage/default/21.uart_fifo_full.3133770893
Short name T1153
Test name
Test status
Simulation time 111884993246 ps
CPU time 30.01 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 199800 kb
Host smart-78378f7b-21d0-42f9-963c-a267021b00c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133770893 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_full.3133770893
Directory /workspace/21.uart_fifo_full/latest

Test location /workspace/coverage/default/21.uart_fifo_overflow.1381754319
Short name T732
Test name
Test status
Simulation time 54368965799 ps
CPU time 92.49 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 199916 kb
Host smart-88b5cac0-c11b-4ec3-aef6-bf8792ffa31c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381754319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_overflow.1381754319
Directory /workspace/21.uart_fifo_overflow/latest

Test location /workspace/coverage/default/21.uart_fifo_reset.304302419
Short name T869
Test name
Test status
Simulation time 235371659834 ps
CPU time 704.18 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 05:04:30 PM PDT 24
Peak memory 199828 kb
Host smart-91f8317f-a38f-44bb-aa64-bd1bc97eb213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304302419 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_fifo_reset.304302419
Directory /workspace/21.uart_fifo_reset/latest

Test location /workspace/coverage/default/21.uart_intr.1665374437
Short name T778
Test name
Test status
Simulation time 19463096153 ps
CPU time 16.66 seconds
Started Aug 03 04:52:49 PM PDT 24
Finished Aug 03 04:53:06 PM PDT 24
Peak memory 198352 kb
Host smart-a30a84ee-7ca7-48c1-844d-e22323f7a4ab
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665374437 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_intr.1665374437
Directory /workspace/21.uart_intr/latest

Test location /workspace/coverage/default/21.uart_long_xfer_wo_dly.2500463766
Short name T324
Test name
Test status
Simulation time 142468881168 ps
CPU time 972.79 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 199828 kb
Host smart-097fa951-791a-433c-a07c-25324275a62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2500463766 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_long_xfer_wo_dly.2500463766
Directory /workspace/21.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/21.uart_loopback.613824929
Short name T1008
Test name
Test status
Simulation time 8153918680 ps
CPU time 15.12 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 198668 kb
Host smart-d8c40bf7-6c16-43a3-a7a5-8761861ebd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613824929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_loopback.613824929
Directory /workspace/21.uart_loopback/latest

Test location /workspace/coverage/default/21.uart_noise_filter.1901607219
Short name T876
Test name
Test status
Simulation time 48297143674 ps
CPU time 89.81 seconds
Started Aug 03 04:52:50 PM PDT 24
Finished Aug 03 04:54:20 PM PDT 24
Peak memory 208260 kb
Host smart-77c5ecf9-9e3f-497f-9d38-2e5733620b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901607219 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_noise_filter.1901607219
Directory /workspace/21.uart_noise_filter/latest

Test location /workspace/coverage/default/21.uart_perf.4156336100
Short name T516
Test name
Test status
Simulation time 23335240446 ps
CPU time 159.46 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:55:26 PM PDT 24
Peak memory 199776 kb
Host smart-e8d4ff25-eb48-47c4-bea5-7181fc375143
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156336100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_perf.4156336100
Directory /workspace/21.uart_perf/latest

Test location /workspace/coverage/default/21.uart_rx_oversample.1451246345
Short name T954
Test name
Test status
Simulation time 2445162520 ps
CPU time 12.76 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:52:59 PM PDT 24
Peak memory 198328 kb
Host smart-23d2af99-e04a-4936-a75c-dc781879aa0d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1451246345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_oversample.1451246345
Directory /workspace/21.uart_rx_oversample/latest

Test location /workspace/coverage/default/21.uart_rx_parity_err.1870749312
Short name T934
Test name
Test status
Simulation time 130967735214 ps
CPU time 56.62 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 04:53:43 PM PDT 24
Peak memory 199652 kb
Host smart-b88bf5a0-eb4e-486a-8c86-42f3973a7b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870749312 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_parity_err.1870749312
Directory /workspace/21.uart_rx_parity_err/latest

Test location /workspace/coverage/default/21.uart_rx_start_bit_filter.2061867049
Short name T759
Test name
Test status
Simulation time 37120837924 ps
CPU time 14.14 seconds
Started Aug 03 04:52:49 PM PDT 24
Finished Aug 03 04:53:04 PM PDT 24
Peak memory 195840 kb
Host smart-dbf432a7-ddda-4ac2-af09-10682fc3c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061867049 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_rx_start_bit_filter.2061867049
Directory /workspace/21.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/21.uart_smoke.1196461069
Short name T289
Test name
Test status
Simulation time 5346140125 ps
CPU time 18.1 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:53:04 PM PDT 24
Peak memory 199772 kb
Host smart-9b66e160-20c5-4513-a7a4-9d236b543771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196461069 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_smoke.1196461069
Directory /workspace/21.uart_smoke/latest

Test location /workspace/coverage/default/21.uart_stress_all.1698465033
Short name T175
Test name
Test status
Simulation time 538997024989 ps
CPU time 627.69 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 05:03:15 PM PDT 24
Peak memory 199872 kb
Host smart-ca2061af-d865-4f93-b271-d188cf311b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698465033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_stress_all.1698465033
Directory /workspace/21.uart_stress_all/latest

Test location /workspace/coverage/default/21.uart_stress_all_with_rand_reset.2990842364
Short name T974
Test name
Test status
Simulation time 26371128541 ps
CPU time 307.84 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 04:57:54 PM PDT 24
Peak memory 208236 kb
Host smart-9515e434-614e-48c9-b8fb-d98610f5ab09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990842364 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 21.uart_stress_all_with_rand_reset.2990842364
Directory /workspace/21.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.uart_tx_ovrd.930614190
Short name T284
Test name
Test status
Simulation time 1431964422 ps
CPU time 4.34 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:52:50 PM PDT 24
Peak memory 199296 kb
Host smart-9c2e92da-58f2-4e71-9223-d736691c9846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930614190 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_ovrd.930614190
Directory /workspace/21.uart_tx_ovrd/latest

Test location /workspace/coverage/default/21.uart_tx_rx.3157795083
Short name T882
Test name
Test status
Simulation time 129699581633 ps
CPU time 184.11 seconds
Started Aug 03 04:52:40 PM PDT 24
Finished Aug 03 04:55:45 PM PDT 24
Peak memory 199860 kb
Host smart-5c0314ca-07f0-430d-b954-7a65335ee306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157795083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.uart_tx_rx.3157795083
Directory /workspace/21.uart_tx_rx/latest

Test location /workspace/coverage/default/210.uart_fifo_reset.1676087455
Short name T574
Test name
Test status
Simulation time 141150896276 ps
CPU time 43.77 seconds
Started Aug 03 04:57:31 PM PDT 24
Finished Aug 03 04:58:15 PM PDT 24
Peak memory 199784 kb
Host smart-ce3fc1b3-941c-420c-895c-bb0562587d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676087455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 210.uart_fifo_reset.1676087455
Directory /workspace/210.uart_fifo_reset/latest

Test location /workspace/coverage/default/212.uart_fifo_reset.519392052
Short name T187
Test name
Test status
Simulation time 66898917968 ps
CPU time 39.01 seconds
Started Aug 03 04:57:34 PM PDT 24
Finished Aug 03 04:58:13 PM PDT 24
Peak memory 199856 kb
Host smart-1ca7ee79-f255-4b8b-9ee8-76c8e103f750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519392052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 212.uart_fifo_reset.519392052
Directory /workspace/212.uart_fifo_reset/latest

Test location /workspace/coverage/default/213.uart_fifo_reset.2863642208
Short name T329
Test name
Test status
Simulation time 25245112042 ps
CPU time 54.51 seconds
Started Aug 03 04:57:32 PM PDT 24
Finished Aug 03 04:58:26 PM PDT 24
Peak memory 199852 kb
Host smart-135f0067-7bf8-472e-ab7e-328f1b52d097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863642208 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 213.uart_fifo_reset.2863642208
Directory /workspace/213.uart_fifo_reset/latest

Test location /workspace/coverage/default/214.uart_fifo_reset.3306624187
Short name T1147
Test name
Test status
Simulation time 36214362903 ps
CPU time 13.2 seconds
Started Aug 03 04:57:35 PM PDT 24
Finished Aug 03 04:57:48 PM PDT 24
Peak memory 199904 kb
Host smart-2502355a-f4c0-46d7-98ab-5d73a11a49d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306624187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 214.uart_fifo_reset.3306624187
Directory /workspace/214.uart_fifo_reset/latest

Test location /workspace/coverage/default/215.uart_fifo_reset.681166639
Short name T235
Test name
Test status
Simulation time 32754100791 ps
CPU time 14.38 seconds
Started Aug 03 04:57:31 PM PDT 24
Finished Aug 03 04:57:45 PM PDT 24
Peak memory 199888 kb
Host smart-93918531-2d1e-4970-932f-7ade3c6dac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681166639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 215.uart_fifo_reset.681166639
Directory /workspace/215.uart_fifo_reset/latest

Test location /workspace/coverage/default/216.uart_fifo_reset.1817472696
Short name T180
Test name
Test status
Simulation time 39747165139 ps
CPU time 34.19 seconds
Started Aug 03 04:57:30 PM PDT 24
Finished Aug 03 04:58:04 PM PDT 24
Peak memory 199916 kb
Host smart-5b2d0e8d-6c23-4a12-ae10-3701a0639691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817472696 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 216.uart_fifo_reset.1817472696
Directory /workspace/216.uart_fifo_reset/latest

Test location /workspace/coverage/default/217.uart_fifo_reset.2111410948
Short name T552
Test name
Test status
Simulation time 34085497953 ps
CPU time 61.15 seconds
Started Aug 03 04:57:30 PM PDT 24
Finished Aug 03 04:58:31 PM PDT 24
Peak memory 199860 kb
Host smart-e03091d9-a60c-4830-b40b-86f54a2cac16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111410948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 217.uart_fifo_reset.2111410948
Directory /workspace/217.uart_fifo_reset/latest

Test location /workspace/coverage/default/218.uart_fifo_reset.440187325
Short name T757
Test name
Test status
Simulation time 81286052508 ps
CPU time 33.34 seconds
Started Aug 03 04:57:32 PM PDT 24
Finished Aug 03 04:58:05 PM PDT 24
Peak memory 199832 kb
Host smart-08aae3e3-0830-4ac4-b492-33d5741984a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440187325 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 218.uart_fifo_reset.440187325
Directory /workspace/218.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_alert_test.718219690
Short name T914
Test name
Test status
Simulation time 16401110 ps
CPU time 0.57 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 195540 kb
Host smart-ea9a01df-d973-4ea0-95f5-500279c71d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718219690 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_alert_test.718219690
Directory /workspace/22.uart_alert_test/latest

Test location /workspace/coverage/default/22.uart_fifo_full.2509489332
Short name T774
Test name
Test status
Simulation time 135137177950 ps
CPU time 222.12 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:56:28 PM PDT 24
Peak memory 199892 kb
Host smart-e9363a54-12cb-4788-ae93-6546fbba5f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509489332 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_full.2509489332
Directory /workspace/22.uart_fifo_full/latest

Test location /workspace/coverage/default/22.uart_fifo_overflow.2713199506
Short name T143
Test name
Test status
Simulation time 20738988793 ps
CPU time 17.09 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 04:53:05 PM PDT 24
Peak memory 199772 kb
Host smart-ae969e3c-8613-461f-a789-f74c4fef8dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713199506 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_overflow.2713199506
Directory /workspace/22.uart_fifo_overflow/latest

Test location /workspace/coverage/default/22.uart_fifo_reset.1204990677
Short name T484
Test name
Test status
Simulation time 27784509915 ps
CPU time 40.39 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:53:27 PM PDT 24
Peak memory 199892 kb
Host smart-021821cf-c95e-4802-950a-237b363adc68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204990677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_fifo_reset.1204990677
Directory /workspace/22.uart_fifo_reset/latest

Test location /workspace/coverage/default/22.uart_intr.754865301
Short name T1036
Test name
Test status
Simulation time 144974162387 ps
CPU time 234.91 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 04:56:43 PM PDT 24
Peak memory 199636 kb
Host smart-d7060fd5-81b3-43b7-8d8c-a068eaf85a07
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754865301 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_intr.754865301
Directory /workspace/22.uart_intr/latest

Test location /workspace/coverage/default/22.uart_long_xfer_wo_dly.4182884130
Short name T648
Test name
Test status
Simulation time 96752053265 ps
CPU time 476.35 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 05:00:42 PM PDT 24
Peak memory 199908 kb
Host smart-29e727bf-c3f3-48a2-9b22-cb349bc0db6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182884130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_long_xfer_wo_dly.4182884130
Directory /workspace/22.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/22.uart_loopback.3650608141
Short name T690
Test name
Test status
Simulation time 1871340577 ps
CPU time 3.74 seconds
Started Aug 03 04:52:50 PM PDT 24
Finished Aug 03 04:52:54 PM PDT 24
Peak memory 196144 kb
Host smart-1241dd7f-458a-4f6e-9916-ce238d9e5f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650608141 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_loopback.3650608141
Directory /workspace/22.uart_loopback/latest

Test location /workspace/coverage/default/22.uart_noise_filter.3974455469
Short name T1171
Test name
Test status
Simulation time 120722554641 ps
CPU time 57.24 seconds
Started Aug 03 04:52:49 PM PDT 24
Finished Aug 03 04:53:46 PM PDT 24
Peak memory 199392 kb
Host smart-61629c19-8434-43ca-8390-acc106a91a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974455469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_noise_filter.3974455469
Directory /workspace/22.uart_noise_filter/latest

Test location /workspace/coverage/default/22.uart_perf.146279717
Short name T1160
Test name
Test status
Simulation time 18260466080 ps
CPU time 398.75 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:59:30 PM PDT 24
Peak memory 199904 kb
Host smart-db1d0c77-4917-40bb-9021-9e9d67636e5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=146279717 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_perf.146279717
Directory /workspace/22.uart_perf/latest

Test location /workspace/coverage/default/22.uart_rx_oversample.1721263469
Short name T19
Test name
Test status
Simulation time 2952993845 ps
CPU time 2.18 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:52:49 PM PDT 24
Peak memory 198184 kb
Host smart-1dba92e6-be61-422b-ac6e-56631b9c3e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1721263469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_oversample.1721263469
Directory /workspace/22.uart_rx_oversample/latest

Test location /workspace/coverage/default/22.uart_rx_parity_err.1419120776
Short name T721
Test name
Test status
Simulation time 112294576697 ps
CPU time 169.97 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:55:36 PM PDT 24
Peak memory 199796 kb
Host smart-4d4eed62-de38-49d1-978c-92c9f91a4c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419120776 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_parity_err.1419120776
Directory /workspace/22.uart_rx_parity_err/latest

Test location /workspace/coverage/default/22.uart_rx_start_bit_filter.3510084088
Short name T1026
Test name
Test status
Simulation time 42261349610 ps
CPU time 7.22 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 04:52:54 PM PDT 24
Peak memory 196712 kb
Host smart-9317a369-7577-4592-bcf3-5d6a7faf4b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510084088 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_rx_start_bit_filter.3510084088
Directory /workspace/22.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/22.uart_smoke.3912024606
Short name T815
Test name
Test status
Simulation time 627194906 ps
CPU time 2.39 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 198280 kb
Host smart-77a4a870-b6bd-4824-8c78-8a843bd536f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912024606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_smoke.3912024606
Directory /workspace/22.uart_smoke/latest

Test location /workspace/coverage/default/22.uart_stress_all.1815368216
Short name T617
Test name
Test status
Simulation time 391259788230 ps
CPU time 1015.83 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 199816 kb
Host smart-7b31d5b6-8148-4348-a84b-d33980ef5762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815368216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_stress_all.1815368216
Directory /workspace/22.uart_stress_all/latest

Test location /workspace/coverage/default/22.uart_stress_all_with_rand_reset.3144891883
Short name T593
Test name
Test status
Simulation time 70248598359 ps
CPU time 817 seconds
Started Aug 03 04:52:46 PM PDT 24
Finished Aug 03 05:06:23 PM PDT 24
Peak memory 216460 kb
Host smart-da01d956-b7a5-4573-8430-3923ee0e8d3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144891883 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 22.uart_stress_all_with_rand_reset.3144891883
Directory /workspace/22.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.uart_tx_ovrd.2080285021
Short name T502
Test name
Test status
Simulation time 1089318747 ps
CPU time 3.69 seconds
Started Aug 03 04:52:47 PM PDT 24
Finished Aug 03 04:52:50 PM PDT 24
Peak memory 199412 kb
Host smart-afd38bdb-3fed-4ecb-8063-5f64c3694ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080285021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_ovrd.2080285021
Directory /workspace/22.uart_tx_ovrd/latest

Test location /workspace/coverage/default/22.uart_tx_rx.3734539656
Short name T697
Test name
Test status
Simulation time 25507115180 ps
CPU time 37.4 seconds
Started Aug 03 04:52:56 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 199276 kb
Host smart-e00c8920-39ec-4f5c-aa98-486509e1783a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734539656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.uart_tx_rx.3734539656
Directory /workspace/22.uart_tx_rx/latest

Test location /workspace/coverage/default/220.uart_fifo_reset.2054400988
Short name T946
Test name
Test status
Simulation time 44171207026 ps
CPU time 12.45 seconds
Started Aug 03 04:57:39 PM PDT 24
Finished Aug 03 04:57:52 PM PDT 24
Peak memory 199872 kb
Host smart-a8e82919-3df9-4533-abe9-c2d75173f738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054400988 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 220.uart_fifo_reset.2054400988
Directory /workspace/220.uart_fifo_reset/latest

Test location /workspace/coverage/default/221.uart_fifo_reset.3882288960
Short name T485
Test name
Test status
Simulation time 144039841787 ps
CPU time 68.32 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:58:52 PM PDT 24
Peak memory 199924 kb
Host smart-5ad460aa-a4be-4957-a04c-a049ed0743b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882288960 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 221.uart_fifo_reset.3882288960
Directory /workspace/221.uart_fifo_reset/latest

Test location /workspace/coverage/default/222.uart_fifo_reset.3778083689
Short name T101
Test name
Test status
Simulation time 17957416504 ps
CPU time 39.93 seconds
Started Aug 03 04:57:35 PM PDT 24
Finished Aug 03 04:58:15 PM PDT 24
Peak memory 199908 kb
Host smart-73a28709-c5ed-4e7d-ab4a-5dbc4a3cd4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778083689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 222.uart_fifo_reset.3778083689
Directory /workspace/222.uart_fifo_reset/latest

Test location /workspace/coverage/default/223.uart_fifo_reset.3636924691
Short name T285
Test name
Test status
Simulation time 13093118188 ps
CPU time 10.75 seconds
Started Aug 03 04:57:37 PM PDT 24
Finished Aug 03 04:57:48 PM PDT 24
Peak memory 199844 kb
Host smart-3c9f9297-6797-4e31-9ffc-e7556c53e934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636924691 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 223.uart_fifo_reset.3636924691
Directory /workspace/223.uart_fifo_reset/latest

Test location /workspace/coverage/default/224.uart_fifo_reset.69417982
Short name T907
Test name
Test status
Simulation time 34789180614 ps
CPU time 11.95 seconds
Started Aug 03 04:57:36 PM PDT 24
Finished Aug 03 04:57:48 PM PDT 24
Peak memory 199840 kb
Host smart-14ae6a2a-865c-4cc2-80dc-a55ca2e9f72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69417982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 224.uart_fifo_reset.69417982
Directory /workspace/224.uart_fifo_reset/latest

Test location /workspace/coverage/default/225.uart_fifo_reset.3634226461
Short name T745
Test name
Test status
Simulation time 108428709053 ps
CPU time 107.17 seconds
Started Aug 03 04:57:45 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 199712 kb
Host smart-97595189-fb86-4bb0-82f0-b979459a8588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634226461 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 225.uart_fifo_reset.3634226461
Directory /workspace/225.uart_fifo_reset/latest

Test location /workspace/coverage/default/226.uart_fifo_reset.170709966
Short name T368
Test name
Test status
Simulation time 35961029382 ps
CPU time 14.16 seconds
Started Aug 03 04:57:37 PM PDT 24
Finished Aug 03 04:57:51 PM PDT 24
Peak memory 199788 kb
Host smart-26d87e8c-8b01-4e19-a858-48e192f311c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170709966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 226.uart_fifo_reset.170709966
Directory /workspace/226.uart_fifo_reset/latest

Test location /workspace/coverage/default/227.uart_fifo_reset.3255343329
Short name T900
Test name
Test status
Simulation time 46806381367 ps
CPU time 39.04 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:58:23 PM PDT 24
Peak memory 199924 kb
Host smart-7885895a-1ed9-4637-a797-e32de8c2de7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255343329 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 227.uart_fifo_reset.3255343329
Directory /workspace/227.uart_fifo_reset/latest

Test location /workspace/coverage/default/228.uart_fifo_reset.1436191738
Short name T688
Test name
Test status
Simulation time 164335936415 ps
CPU time 47.32 seconds
Started Aug 03 04:57:39 PM PDT 24
Finished Aug 03 04:58:26 PM PDT 24
Peak memory 199848 kb
Host smart-cb57ea82-8b65-4a7a-845f-5bcad10e17ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436191738 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 228.uart_fifo_reset.1436191738
Directory /workspace/228.uart_fifo_reset/latest

Test location /workspace/coverage/default/229.uart_fifo_reset.868587637
Short name T863
Test name
Test status
Simulation time 95142865499 ps
CPU time 23.73 seconds
Started Aug 03 04:57:36 PM PDT 24
Finished Aug 03 04:58:00 PM PDT 24
Peak memory 199908 kb
Host smart-f74e8f5a-06c2-4972-a079-8c7f70ac72d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868587637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 229.uart_fifo_reset.868587637
Directory /workspace/229.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_alert_test.1140658474
Short name T440
Test name
Test status
Simulation time 225180177 ps
CPU time 0.56 seconds
Started Aug 03 04:52:55 PM PDT 24
Finished Aug 03 04:52:56 PM PDT 24
Peak memory 195300 kb
Host smart-87320a74-54e4-484e-aaf3-011f1071dea7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140658474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_alert_test.1140658474
Directory /workspace/23.uart_alert_test/latest

Test location /workspace/coverage/default/23.uart_fifo_full.1937486777
Short name T177
Test name
Test status
Simulation time 61029898155 ps
CPU time 32.85 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:24 PM PDT 24
Peak memory 199816 kb
Host smart-f4fdd2fb-2320-40a8-ad00-10cef90250ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937486777 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_full.1937486777
Directory /workspace/23.uart_fifo_full/latest

Test location /workspace/coverage/default/23.uart_fifo_overflow.1433396345
Short name T573
Test name
Test status
Simulation time 33763387965 ps
CPU time 48.93 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:53:50 PM PDT 24
Peak memory 199900 kb
Host smart-18f7d045-7e59-4db0-a0f0-d739d6d1bb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433396345 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_overflow.1433396345
Directory /workspace/23.uart_fifo_overflow/latest

Test location /workspace/coverage/default/23.uart_fifo_reset.1562080101
Short name T333
Test name
Test status
Simulation time 14847746822 ps
CPU time 22.65 seconds
Started Aug 03 04:53:01 PM PDT 24
Finished Aug 03 04:53:23 PM PDT 24
Peak memory 199884 kb
Host smart-ace8877c-32c8-4eca-b20c-bf2230f095f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562080101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_fifo_reset.1562080101
Directory /workspace/23.uart_fifo_reset/latest

Test location /workspace/coverage/default/23.uart_intr.55418569
Short name T749
Test name
Test status
Simulation time 30313500621 ps
CPU time 19.05 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 199900 kb
Host smart-361f7b1b-1742-4018-8c3c-b65c83abf32f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55418569 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_intr.55418569
Directory /workspace/23.uart_intr/latest

Test location /workspace/coverage/default/23.uart_long_xfer_wo_dly.1850294650
Short name T877
Test name
Test status
Simulation time 141038546569 ps
CPU time 1385.94 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 05:15:58 PM PDT 24
Peak memory 199800 kb
Host smart-ad59c7ef-efba-4cd7-a41c-5df689d8fcd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1850294650 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_long_xfer_wo_dly.1850294650
Directory /workspace/23.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/23.uart_loopback.2012118933
Short name T541
Test name
Test status
Simulation time 1523191813 ps
CPU time 3.31 seconds
Started Aug 03 04:52:55 PM PDT 24
Finished Aug 03 04:52:59 PM PDT 24
Peak memory 196168 kb
Host smart-788c2538-282e-42e6-8d56-66b1359c3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012118933 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_loopback.2012118933
Directory /workspace/23.uart_loopback/latest

Test location /workspace/coverage/default/23.uart_noise_filter.2802349647
Short name T872
Test name
Test status
Simulation time 98831878315 ps
CPU time 18.67 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 197648 kb
Host smart-e0d815bf-3a3f-445d-bd70-583d4273eff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802349647 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_noise_filter.2802349647
Directory /workspace/23.uart_noise_filter/latest

Test location /workspace/coverage/default/23.uart_perf.1411109423
Short name T827
Test name
Test status
Simulation time 5685779022 ps
CPU time 73.95 seconds
Started Aug 03 04:52:53 PM PDT 24
Finished Aug 03 04:54:07 PM PDT 24
Peak memory 199892 kb
Host smart-9abc55ed-d23e-425c-84f9-78b8cf2db418
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1411109423 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_perf.1411109423
Directory /workspace/23.uart_perf/latest

Test location /workspace/coverage/default/23.uart_rx_oversample.694423746
Short name T1001
Test name
Test status
Simulation time 4147303351 ps
CPU time 3.66 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:52:55 PM PDT 24
Peak memory 197892 kb
Host smart-7fd90491-2e93-4cb7-8353-43082bbe8950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694423746 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_oversample.694423746
Directory /workspace/23.uart_rx_oversample/latest

Test location /workspace/coverage/default/23.uart_rx_parity_err.1234895066
Short name T655
Test name
Test status
Simulation time 81083689545 ps
CPU time 67.1 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:58 PM PDT 24
Peak memory 199848 kb
Host smart-ddef049e-eae6-45b7-81a9-3b4116941fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234895066 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_parity_err.1234895066
Directory /workspace/23.uart_rx_parity_err/latest

Test location /workspace/coverage/default/23.uart_rx_start_bit_filter.1425879073
Short name T304
Test name
Test status
Simulation time 47455434436 ps
CPU time 37.45 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:29 PM PDT 24
Peak memory 196052 kb
Host smart-4cced8fa-7933-49c7-8c38-e6da648ab25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425879073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_rx_start_bit_filter.1425879073
Directory /workspace/23.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/23.uart_smoke.1073724064
Short name T852
Test name
Test status
Simulation time 448295645 ps
CPU time 1.94 seconds
Started Aug 03 04:52:56 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 198172 kb
Host smart-ae1f9850-0eb8-4082-877d-397f28e20c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073724064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_smoke.1073724064
Directory /workspace/23.uart_smoke/latest

Test location /workspace/coverage/default/23.uart_stress_all.9032119
Short name T665
Test name
Test status
Simulation time 83936412423 ps
CPU time 611.17 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 05:03:12 PM PDT 24
Peak memory 199864 kb
Host smart-97022008-2362-49e0-b673-8ad039f003f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9032119 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_stress_all.9032119
Directory /workspace/23.uart_stress_all/latest

Test location /workspace/coverage/default/23.uart_tx_ovrd.2225880575
Short name T1103
Test name
Test status
Simulation time 1375791657 ps
CPU time 2.44 seconds
Started Aug 03 04:52:53 PM PDT 24
Finished Aug 03 04:52:55 PM PDT 24
Peak memory 198388 kb
Host smart-1fb4ad07-d7fe-4e14-9c2f-7b252d726d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225880575 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_ovrd.2225880575
Directory /workspace/23.uart_tx_ovrd/latest

Test location /workspace/coverage/default/23.uart_tx_rx.405752827
Short name T354
Test name
Test status
Simulation time 36735301392 ps
CPU time 15.56 seconds
Started Aug 03 04:52:48 PM PDT 24
Finished Aug 03 04:53:04 PM PDT 24
Peak memory 199888 kb
Host smart-8acc3f05-1ec4-4c94-bc6b-38b9b5af3ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405752827 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.uart_tx_rx.405752827
Directory /workspace/23.uart_tx_rx/latest

Test location /workspace/coverage/default/230.uart_fifo_reset.2927093147
Short name T203
Test name
Test status
Simulation time 26107376068 ps
CPU time 37.62 seconds
Started Aug 03 04:57:38 PM PDT 24
Finished Aug 03 04:58:16 PM PDT 24
Peak memory 199904 kb
Host smart-7794e953-2f23-4031-afcf-60774c38b483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927093147 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 230.uart_fifo_reset.2927093147
Directory /workspace/230.uart_fifo_reset/latest

Test location /workspace/coverage/default/231.uart_fifo_reset.2989485456
Short name T981
Test name
Test status
Simulation time 143710373268 ps
CPU time 81.73 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:59:06 PM PDT 24
Peak memory 199828 kb
Host smart-a37ef98e-e0d3-479d-840c-b28cf018846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989485456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 231.uart_fifo_reset.2989485456
Directory /workspace/231.uart_fifo_reset/latest

Test location /workspace/coverage/default/232.uart_fifo_reset.1332092812
Short name T567
Test name
Test status
Simulation time 68569353799 ps
CPU time 137.94 seconds
Started Aug 03 04:57:46 PM PDT 24
Finished Aug 03 05:00:04 PM PDT 24
Peak memory 199784 kb
Host smart-710bee96-8da4-4f69-83ca-9bc1b0608dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332092812 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 232.uart_fifo_reset.1332092812
Directory /workspace/232.uart_fifo_reset/latest

Test location /workspace/coverage/default/233.uart_fifo_reset.313926468
Short name T130
Test name
Test status
Simulation time 10802041980 ps
CPU time 16.44 seconds
Started Aug 03 04:57:45 PM PDT 24
Finished Aug 03 04:58:01 PM PDT 24
Peak memory 199832 kb
Host smart-088cace3-cb46-4abe-9e62-89075101d27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313926468 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 233.uart_fifo_reset.313926468
Directory /workspace/233.uart_fifo_reset/latest

Test location /workspace/coverage/default/234.uart_fifo_reset.2674033628
Short name T478
Test name
Test status
Simulation time 162553118382 ps
CPU time 12.74 seconds
Started Aug 03 04:57:43 PM PDT 24
Finished Aug 03 04:57:56 PM PDT 24
Peak memory 200048 kb
Host smart-bfb746f2-e4c3-4fed-9f65-613d6ce14ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674033628 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 234.uart_fifo_reset.2674033628
Directory /workspace/234.uart_fifo_reset/latest

Test location /workspace/coverage/default/235.uart_fifo_reset.344321566
Short name T232
Test name
Test status
Simulation time 93092535524 ps
CPU time 80.74 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 199744 kb
Host smart-c0080e10-b686-4e81-a88e-2d3a9cad10b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344321566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 235.uart_fifo_reset.344321566
Directory /workspace/235.uart_fifo_reset/latest

Test location /workspace/coverage/default/236.uart_fifo_reset.3195881047
Short name T182
Test name
Test status
Simulation time 55630097683 ps
CPU time 25.39 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:58:09 PM PDT 24
Peak memory 199876 kb
Host smart-c5955625-d3b8-467a-b7cb-3c4f1ad6e426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195881047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 236.uart_fifo_reset.3195881047
Directory /workspace/236.uart_fifo_reset/latest

Test location /workspace/coverage/default/237.uart_fifo_reset.3582779653
Short name T185
Test name
Test status
Simulation time 52123332922 ps
CPU time 151.69 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 05:00:16 PM PDT 24
Peak memory 199892 kb
Host smart-d24ee18e-c6ab-4699-aaa6-46779190f940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582779653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 237.uart_fifo_reset.3582779653
Directory /workspace/237.uart_fifo_reset/latest

Test location /workspace/coverage/default/238.uart_fifo_reset.2999652705
Short name T684
Test name
Test status
Simulation time 103793844110 ps
CPU time 171.38 seconds
Started Aug 03 04:57:43 PM PDT 24
Finished Aug 03 05:00:34 PM PDT 24
Peak memory 199904 kb
Host smart-212ffc85-c479-44e1-9da6-57fe6c343e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999652705 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 238.uart_fifo_reset.2999652705
Directory /workspace/238.uart_fifo_reset/latest

Test location /workspace/coverage/default/239.uart_fifo_reset.170745740
Short name T664
Test name
Test status
Simulation time 14957963880 ps
CPU time 11.8 seconds
Started Aug 03 04:57:44 PM PDT 24
Finished Aug 03 04:57:56 PM PDT 24
Peak memory 199680 kb
Host smart-1851e7e6-6cd8-4353-b3bb-8f8da34c5c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170745740 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 239.uart_fifo_reset.170745740
Directory /workspace/239.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_alert_test.815319694
Short name T770
Test name
Test status
Simulation time 30612042 ps
CPU time 0.57 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:52:59 PM PDT 24
Peak memory 195300 kb
Host smart-1d54571a-bd9c-4ec0-8d41-f787aaebbf51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815319694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_alert_test.815319694
Directory /workspace/24.uart_alert_test/latest

Test location /workspace/coverage/default/24.uart_fifo_full.2288852130
Short name T825
Test name
Test status
Simulation time 129932709293 ps
CPU time 569.43 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 05:02:30 PM PDT 24
Peak memory 199780 kb
Host smart-2d419f82-ba88-4cd8-92ae-c709339ef0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288852130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_full.2288852130
Directory /workspace/24.uart_fifo_full/latest

Test location /workspace/coverage/default/24.uart_fifo_overflow.2696067488
Short name T171
Test name
Test status
Simulation time 153243407143 ps
CPU time 30.42 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:53:22 PM PDT 24
Peak memory 199880 kb
Host smart-3bb01564-c5a3-4786-8149-9c444548d20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696067488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_overflow.2696067488
Directory /workspace/24.uart_fifo_overflow/latest

Test location /workspace/coverage/default/24.uart_fifo_reset.181412835
Short name T166
Test name
Test status
Simulation time 167300861864 ps
CPU time 36.67 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:53:28 PM PDT 24
Peak memory 199856 kb
Host smart-e1bfd5e1-0b87-46ae-811a-eea55aa262ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181412835 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_fifo_reset.181412835
Directory /workspace/24.uart_fifo_reset/latest

Test location /workspace/coverage/default/24.uart_intr.4172781314
Short name T240
Test name
Test status
Simulation time 3498594738 ps
CPU time 6.08 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 196044 kb
Host smart-b47e5294-141e-47f7-b4f6-c774dd0f24ba
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172781314 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_intr.4172781314
Directory /workspace/24.uart_intr/latest

Test location /workspace/coverage/default/24.uart_long_xfer_wo_dly.3584270413
Short name T360
Test name
Test status
Simulation time 83262413079 ps
CPU time 229.28 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 199800 kb
Host smart-36c08d6d-a025-4cae-98f3-de53bb2395f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3584270413 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_long_xfer_wo_dly.3584270413
Directory /workspace/24.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/24.uart_loopback.3182815793
Short name T748
Test name
Test status
Simulation time 9658892265 ps
CPU time 22.15 seconds
Started Aug 03 04:52:57 PM PDT 24
Finished Aug 03 04:53:19 PM PDT 24
Peak memory 199912 kb
Host smart-3f004980-6e9b-4c2f-ac90-cc01aba64f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182815793 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_loopback.3182815793
Directory /workspace/24.uart_loopback/latest

Test location /workspace/coverage/default/24.uart_noise_filter.1869977889
Short name T268
Test name
Test status
Simulation time 64096069356 ps
CPU time 101.39 seconds
Started Aug 03 04:52:51 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199184 kb
Host smart-c135bf07-fa9c-4eab-a4e9-3b7b5e0d9a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869977889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_noise_filter.1869977889
Directory /workspace/24.uart_noise_filter/latest

Test location /workspace/coverage/default/24.uart_perf.2531346511
Short name T1096
Test name
Test status
Simulation time 10409954370 ps
CPU time 423.28 seconds
Started Aug 03 04:53:03 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199828 kb
Host smart-a9d55294-7387-445f-be1a-d9c1654b12b7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2531346511 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_perf.2531346511
Directory /workspace/24.uart_perf/latest

Test location /workspace/coverage/default/24.uart_rx_oversample.4289900847
Short name T625
Test name
Test status
Simulation time 5270980190 ps
CPU time 24.95 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:53:17 PM PDT 24
Peak memory 198132 kb
Host smart-9fa4f2a0-4738-4a85-83e9-951f5c50bf71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4289900847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_oversample.4289900847
Directory /workspace/24.uart_rx_oversample/latest

Test location /workspace/coverage/default/24.uart_rx_parity_err.3014864722
Short name T637
Test name
Test status
Simulation time 144874230300 ps
CPU time 249.55 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 199904 kb
Host smart-05e4da23-ab7e-4389-b3c2-79e4c2b971a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014864722 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_parity_err.3014864722
Directory /workspace/24.uart_rx_parity_err/latest

Test location /workspace/coverage/default/24.uart_rx_start_bit_filter.2057563206
Short name T767
Test name
Test status
Simulation time 28707656751 ps
CPU time 39.74 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:53:31 PM PDT 24
Peak memory 195916 kb
Host smart-192c2fb9-2831-4d5e-9385-e70e7ec577f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057563206 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_rx_start_bit_filter.2057563206
Directory /workspace/24.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/24.uart_smoke.3743889594
Short name T313
Test name
Test status
Simulation time 691989862 ps
CPU time 2.5 seconds
Started Aug 03 04:52:52 PM PDT 24
Finished Aug 03 04:52:55 PM PDT 24
Peak memory 198264 kb
Host smart-ccdf8b10-74c4-49ac-af7b-fc49509d9b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743889594 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_smoke.3743889594
Directory /workspace/24.uart_smoke/latest

Test location /workspace/coverage/default/24.uart_stress_all.2936323052
Short name T944
Test name
Test status
Simulation time 332442089938 ps
CPU time 503.25 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 05:01:21 PM PDT 24
Peak memory 199916 kb
Host smart-47d099f0-4fd9-4aaa-83bd-0e085472785e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936323052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_stress_all.2936323052
Directory /workspace/24.uart_stress_all/latest

Test location /workspace/coverage/default/24.uart_stress_all_with_rand_reset.112860577
Short name T176
Test name
Test status
Simulation time 93287451082 ps
CPU time 173.1 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:55:51 PM PDT 24
Peak memory 215688 kb
Host smart-55f93825-8e51-4e01-af5d-52e16e069d1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112860577 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 24.uart_stress_all_with_rand_reset.112860577
Directory /workspace/24.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.uart_tx_ovrd.2319354321
Short name T750
Test name
Test status
Simulation time 3439545054 ps
CPU time 2.28 seconds
Started Aug 03 04:52:55 PM PDT 24
Finished Aug 03 04:52:57 PM PDT 24
Peak memory 199020 kb
Host smart-20f44c7d-4fcc-4bcd-b772-efcff7c73c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319354321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.uart_tx_ovrd.2319354321
Directory /workspace/24.uart_tx_ovrd/latest

Test location /workspace/coverage/default/240.uart_fifo_reset.571796236
Short name T641
Test name
Test status
Simulation time 36888517719 ps
CPU time 21.82 seconds
Started Aug 03 04:57:45 PM PDT 24
Finished Aug 03 04:58:06 PM PDT 24
Peak memory 199888 kb
Host smart-6b4860a7-4d65-42d8-be48-8e8cf0ffae7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571796236 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 240.uart_fifo_reset.571796236
Directory /workspace/240.uart_fifo_reset/latest

Test location /workspace/coverage/default/241.uart_fifo_reset.1272787547
Short name T842
Test name
Test status
Simulation time 22784374881 ps
CPU time 28.51 seconds
Started Aug 03 04:57:50 PM PDT 24
Finished Aug 03 04:58:18 PM PDT 24
Peak memory 199760 kb
Host smart-35daa899-42f7-451e-8436-3e6848a80338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272787547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 241.uart_fifo_reset.1272787547
Directory /workspace/241.uart_fifo_reset/latest

Test location /workspace/coverage/default/242.uart_fifo_reset.2217704083
Short name T300
Test name
Test status
Simulation time 39320495212 ps
CPU time 51.44 seconds
Started Aug 03 04:57:49 PM PDT 24
Finished Aug 03 04:58:40 PM PDT 24
Peak memory 199892 kb
Host smart-81331728-20f3-41c8-9c26-8708e363d910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217704083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 242.uart_fifo_reset.2217704083
Directory /workspace/242.uart_fifo_reset/latest

Test location /workspace/coverage/default/243.uart_fifo_reset.3260945693
Short name T933
Test name
Test status
Simulation time 20695665330 ps
CPU time 32.6 seconds
Started Aug 03 04:57:50 PM PDT 24
Finished Aug 03 04:58:23 PM PDT 24
Peak memory 199816 kb
Host smart-47715295-0ce7-48e0-a183-e6d47e4b3d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260945693 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 243.uart_fifo_reset.3260945693
Directory /workspace/243.uart_fifo_reset/latest

Test location /workspace/coverage/default/244.uart_fifo_reset.1469489365
Short name T712
Test name
Test status
Simulation time 27331348044 ps
CPU time 12.49 seconds
Started Aug 03 04:57:53 PM PDT 24
Finished Aug 03 04:58:06 PM PDT 24
Peak memory 199824 kb
Host smart-7ae32d6c-4dc5-47ff-aa9e-52fd9891e42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469489365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 244.uart_fifo_reset.1469489365
Directory /workspace/244.uart_fifo_reset/latest

Test location /workspace/coverage/default/245.uart_fifo_reset.2452469634
Short name T592
Test name
Test status
Simulation time 70816669814 ps
CPU time 60.69 seconds
Started Aug 03 04:57:50 PM PDT 24
Finished Aug 03 04:58:51 PM PDT 24
Peak memory 199760 kb
Host smart-262fc082-33da-457d-bc3a-235957d2f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452469634 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 245.uart_fifo_reset.2452469634
Directory /workspace/245.uart_fifo_reset/latest

Test location /workspace/coverage/default/246.uart_fifo_reset.645424262
Short name T236
Test name
Test status
Simulation time 42820106289 ps
CPU time 90.77 seconds
Started Aug 03 04:57:51 PM PDT 24
Finished Aug 03 04:59:22 PM PDT 24
Peak memory 199892 kb
Host smart-e5179725-fc21-423d-b808-f46e66603817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645424262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 246.uart_fifo_reset.645424262
Directory /workspace/246.uart_fifo_reset/latest

Test location /workspace/coverage/default/247.uart_fifo_reset.2796219189
Short name T696
Test name
Test status
Simulation time 123434041856 ps
CPU time 201.48 seconds
Started Aug 03 04:57:51 PM PDT 24
Finished Aug 03 05:01:13 PM PDT 24
Peak memory 199908 kb
Host smart-aa184923-7738-43a1-88e8-817792b4b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796219189 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 247.uart_fifo_reset.2796219189
Directory /workspace/247.uart_fifo_reset/latest

Test location /workspace/coverage/default/249.uart_fifo_reset.2429945925
Short name T607
Test name
Test status
Simulation time 188181036155 ps
CPU time 23.01 seconds
Started Aug 03 04:57:51 PM PDT 24
Finished Aug 03 04:58:14 PM PDT 24
Peak memory 199644 kb
Host smart-b427adfa-19d6-4079-9e0d-8ccd08f021d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429945925 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 249.uart_fifo_reset.2429945925
Directory /workspace/249.uart_fifo_reset/latest

Test location /workspace/coverage/default/25.uart_alert_test.3662866195
Short name T616
Test name
Test status
Simulation time 90821528 ps
CPU time 0.54 seconds
Started Aug 03 04:53:06 PM PDT 24
Finished Aug 03 04:53:07 PM PDT 24
Peak memory 195276 kb
Host smart-0ba7627f-16fb-4690-9d78-3a95581f506a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662866195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_alert_test.3662866195
Directory /workspace/25.uart_alert_test/latest

Test location /workspace/coverage/default/25.uart_fifo_full.259139599
Short name T147
Test name
Test status
Simulation time 85539048934 ps
CPU time 33.7 seconds
Started Aug 03 04:52:57 PM PDT 24
Finished Aug 03 04:53:31 PM PDT 24
Peak memory 199880 kb
Host smart-ad04be13-543d-4f3a-a690-abe558de0744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259139599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_full.259139599
Directory /workspace/25.uart_fifo_full/latest

Test location /workspace/coverage/default/25.uart_fifo_overflow.2919668015
Short name T736
Test name
Test status
Simulation time 78455115612 ps
CPU time 106.86 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 199860 kb
Host smart-d3ae877e-0275-47e2-ac69-71180fd8eb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919668015 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_fifo_overflow.2919668015
Directory /workspace/25.uart_fifo_overflow/latest

Test location /workspace/coverage/default/25.uart_intr.1701116725
Short name T920
Test name
Test status
Simulation time 29605876799 ps
CPU time 7.1 seconds
Started Aug 03 04:52:59 PM PDT 24
Finished Aug 03 04:53:06 PM PDT 24
Peak memory 199120 kb
Host smart-6d424e68-3b5a-4355-b165-7536b7dc4eaa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701116725 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_intr.1701116725
Directory /workspace/25.uart_intr/latest

Test location /workspace/coverage/default/25.uart_long_xfer_wo_dly.1969039195
Short name T252
Test name
Test status
Simulation time 34047189889 ps
CPU time 208.95 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:56:28 PM PDT 24
Peak memory 199904 kb
Host smart-24e2a105-a8d6-4fe9-a952-73c80488c946
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1969039195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_long_xfer_wo_dly.1969039195
Directory /workspace/25.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/25.uart_loopback.2077367801
Short name T553
Test name
Test status
Simulation time 7758076289 ps
CPU time 6.43 seconds
Started Aug 03 04:52:59 PM PDT 24
Finished Aug 03 04:53:06 PM PDT 24
Peak memory 197796 kb
Host smart-5fcbe033-dc57-4240-bfb5-f3215f87f010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077367801 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_loopback.2077367801
Directory /workspace/25.uart_loopback/latest

Test location /workspace/coverage/default/25.uart_noise_filter.349729180
Short name T965
Test name
Test status
Simulation time 34768650266 ps
CPU time 19.08 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:53:17 PM PDT 24
Peak memory 199576 kb
Host smart-2a294815-ca03-4689-bb35-7aceb27bbd36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349729180 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_noise_filter.349729180
Directory /workspace/25.uart_noise_filter/latest

Test location /workspace/coverage/default/25.uart_perf.3531169663
Short name T393
Test name
Test status
Simulation time 11595391907 ps
CPU time 564.59 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 05:02:23 PM PDT 24
Peak memory 199868 kb
Host smart-c09072ee-5bef-4de0-aa48-96469c51d078
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531169663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_perf.3531169663
Directory /workspace/25.uart_perf/latest

Test location /workspace/coverage/default/25.uart_rx_oversample.1881900456
Short name T468
Test name
Test status
Simulation time 4812668859 ps
CPU time 42.69 seconds
Started Aug 03 04:52:56 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 198572 kb
Host smart-607d0b3f-c14c-4d05-99ae-1af17558367a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881900456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_oversample.1881900456
Directory /workspace/25.uart_rx_oversample/latest

Test location /workspace/coverage/default/25.uart_rx_parity_err.3389306779
Short name T619
Test name
Test status
Simulation time 126467317304 ps
CPU time 195.03 seconds
Started Aug 03 04:52:59 PM PDT 24
Finished Aug 03 04:56:14 PM PDT 24
Peak memory 199892 kb
Host smart-59f252a1-b862-4207-a9ce-28c99a8f6239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389306779 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_parity_err.3389306779
Directory /workspace/25.uart_rx_parity_err/latest

Test location /workspace/coverage/default/25.uart_rx_start_bit_filter.69626878
Short name T413
Test name
Test status
Simulation time 2032991348 ps
CPU time 3.66 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 195412 kb
Host smart-d4522a74-12b3-46a3-baf5-7723097042a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69626878 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_rx_start_bit_filter.69626878
Directory /workspace/25.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/25.uart_smoke.776884638
Short name T1063
Test name
Test status
Simulation time 513825367 ps
CPU time 1.31 seconds
Started Aug 03 04:53:01 PM PDT 24
Finished Aug 03 04:53:02 PM PDT 24
Peak memory 199836 kb
Host smart-9e5ff497-2da2-4ecd-8d53-f72c8fc8cda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776884638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_smoke.776884638
Directory /workspace/25.uart_smoke/latest

Test location /workspace/coverage/default/25.uart_stress_all.1860838582
Short name T947
Test name
Test status
Simulation time 182139419183 ps
CPU time 77.13 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 208176 kb
Host smart-8210a4c3-ace7-4be6-a7aa-d502b5116f79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860838582 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_stress_all.1860838582
Directory /workspace/25.uart_stress_all/latest

Test location /workspace/coverage/default/25.uart_stress_all_with_rand_reset.3613643677
Short name T58
Test name
Test status
Simulation time 14758283986 ps
CPU time 544.07 seconds
Started Aug 03 04:52:58 PM PDT 24
Finished Aug 03 05:02:02 PM PDT 24
Peak memory 208384 kb
Host smart-232b648c-8f66-4a12-8aeb-fe9fb0dfb60d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613643677 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 25.uart_stress_all_with_rand_reset.3613643677
Directory /workspace/25.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.uart_tx_ovrd.27342227
Short name T1145
Test name
Test status
Simulation time 7176922414 ps
CPU time 10.69 seconds
Started Aug 03 04:53:01 PM PDT 24
Finished Aug 03 04:53:12 PM PDT 24
Peak memory 199772 kb
Host smart-d912a8c2-314d-42f6-96bd-95924b31218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27342227 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_ovrd.27342227
Directory /workspace/25.uart_tx_ovrd/latest

Test location /workspace/coverage/default/25.uart_tx_rx.2446660816
Short name T503
Test name
Test status
Simulation time 80353094312 ps
CPU time 82.01 seconds
Started Aug 03 04:53:00 PM PDT 24
Finished Aug 03 04:54:22 PM PDT 24
Peak memory 199848 kb
Host smart-8b3e4820-c5ee-406d-9aa6-bda42e264a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446660816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.uart_tx_rx.2446660816
Directory /workspace/25.uart_tx_rx/latest

Test location /workspace/coverage/default/250.uart_fifo_reset.2616418751
Short name T943
Test name
Test status
Simulation time 66310774156 ps
CPU time 54.86 seconds
Started Aug 03 04:57:51 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 199828 kb
Host smart-4d58034e-51e9-40a4-a93a-a72cd1c0bfc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616418751 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 250.uart_fifo_reset.2616418751
Directory /workspace/250.uart_fifo_reset/latest

Test location /workspace/coverage/default/251.uart_fifo_reset.651355083
Short name T109
Test name
Test status
Simulation time 91294093268 ps
CPU time 71.36 seconds
Started Aug 03 04:57:51 PM PDT 24
Finished Aug 03 04:59:02 PM PDT 24
Peak memory 199892 kb
Host smart-9d62d34f-a072-40fc-8386-da1b48e1226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651355083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 251.uart_fifo_reset.651355083
Directory /workspace/251.uart_fifo_reset/latest

Test location /workspace/coverage/default/252.uart_fifo_reset.3202988104
Short name T1060
Test name
Test status
Simulation time 14342182168 ps
CPU time 19.16 seconds
Started Aug 03 04:57:50 PM PDT 24
Finished Aug 03 04:58:09 PM PDT 24
Peak memory 199456 kb
Host smart-c9651036-25a9-4445-895e-43c702eb9def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202988104 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 252.uart_fifo_reset.3202988104
Directory /workspace/252.uart_fifo_reset/latest

Test location /workspace/coverage/default/253.uart_fifo_reset.3390591903
Short name T192
Test name
Test status
Simulation time 38428912529 ps
CPU time 31.96 seconds
Started Aug 03 04:57:53 PM PDT 24
Finished Aug 03 04:58:25 PM PDT 24
Peak memory 199920 kb
Host smart-55ed9506-979b-4b41-92e8-94725f1081d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390591903 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 253.uart_fifo_reset.3390591903
Directory /workspace/253.uart_fifo_reset/latest

Test location /workspace/coverage/default/254.uart_fifo_reset.3620599816
Short name T135
Test name
Test status
Simulation time 195149712858 ps
CPU time 75.99 seconds
Started Aug 03 04:57:50 PM PDT 24
Finished Aug 03 04:59:07 PM PDT 24
Peak memory 199852 kb
Host smart-affc1f30-e913-4dea-8ff4-fec66e3fa244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620599816 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 254.uart_fifo_reset.3620599816
Directory /workspace/254.uart_fifo_reset/latest

Test location /workspace/coverage/default/255.uart_fifo_reset.2394641197
Short name T470
Test name
Test status
Simulation time 37500903580 ps
CPU time 35.08 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 199856 kb
Host smart-0f8ae406-7070-4e68-9f43-d5b7b3a65857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394641197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 255.uart_fifo_reset.2394641197
Directory /workspace/255.uart_fifo_reset/latest

Test location /workspace/coverage/default/256.uart_fifo_reset.2940722573
Short name T111
Test name
Test status
Simulation time 9416189979 ps
CPU time 16.47 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:13 PM PDT 24
Peak memory 199800 kb
Host smart-d555f5f0-5f86-48d3-8812-53572ed30d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940722573 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 256.uart_fifo_reset.2940722573
Directory /workspace/256.uart_fifo_reset/latest

Test location /workspace/coverage/default/257.uart_fifo_reset.1128527529
Short name T906
Test name
Test status
Simulation time 77257012359 ps
CPU time 187.84 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 05:01:05 PM PDT 24
Peak memory 199848 kb
Host smart-9de429b7-664f-4680-b612-8ea6e5358660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128527529 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 257.uart_fifo_reset.1128527529
Directory /workspace/257.uart_fifo_reset/latest

Test location /workspace/coverage/default/258.uart_fifo_reset.457920383
Short name T3
Test name
Test status
Simulation time 40784897125 ps
CPU time 62.55 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:59 PM PDT 24
Peak memory 199900 kb
Host smart-19cce3af-abbb-46e1-821d-aacf0c7b8b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457920383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 258.uart_fifo_reset.457920383
Directory /workspace/258.uart_fifo_reset/latest

Test location /workspace/coverage/default/259.uart_fifo_reset.3570120934
Short name T291
Test name
Test status
Simulation time 37863631675 ps
CPU time 119.77 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:59:57 PM PDT 24
Peak memory 199788 kb
Host smart-87c9bf8d-0436-4721-b53e-3a4b39349027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570120934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 259.uart_fifo_reset.3570120934
Directory /workspace/259.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_alert_test.929428340
Short name T1087
Test name
Test status
Simulation time 30224788 ps
CPU time 0.54 seconds
Started Aug 03 04:53:06 PM PDT 24
Finished Aug 03 04:53:06 PM PDT 24
Peak memory 195300 kb
Host smart-a245246e-54ab-4d09-87d7-145c2eb76146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929428340 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_alert_test.929428340
Directory /workspace/26.uart_alert_test/latest

Test location /workspace/coverage/default/26.uart_fifo_full.2488328279
Short name T962
Test name
Test status
Simulation time 45003464916 ps
CPU time 17.04 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:53:21 PM PDT 24
Peak memory 199904 kb
Host smart-f227f08d-124a-44ad-9d21-c6a98e62ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488328279 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_full.2488328279
Directory /workspace/26.uart_fifo_full/latest

Test location /workspace/coverage/default/26.uart_fifo_overflow.682260167
Short name T1117
Test name
Test status
Simulation time 20287288847 ps
CPU time 29.83 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:35 PM PDT 24
Peak memory 199812 kb
Host smart-ed3a6144-3201-4a45-9a7f-348feed5b063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682260167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_overflow.682260167
Directory /workspace/26.uart_fifo_overflow/latest

Test location /workspace/coverage/default/26.uart_fifo_reset.1072475915
Short name T668
Test name
Test status
Simulation time 18307112723 ps
CPU time 16.29 seconds
Started Aug 03 04:53:06 PM PDT 24
Finished Aug 03 04:53:22 PM PDT 24
Peak memory 198868 kb
Host smart-608e2353-77e8-47a6-9463-38b015b1e5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072475915 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_fifo_reset.1072475915
Directory /workspace/26.uart_fifo_reset/latest

Test location /workspace/coverage/default/26.uart_intr.2391643253
Short name T397
Test name
Test status
Simulation time 42769503712 ps
CPU time 39.85 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:53:44 PM PDT 24
Peak memory 199888 kb
Host smart-315b1e69-d602-46f6-bdf0-16b49adfdd73
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391643253 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_intr.2391643253
Directory /workspace/26.uart_intr/latest

Test location /workspace/coverage/default/26.uart_long_xfer_wo_dly.2982352869
Short name T260
Test name
Test status
Simulation time 200049216514 ps
CPU time 243.21 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:57:09 PM PDT 24
Peak memory 199768 kb
Host smart-8b9153e3-12c3-47f2-86bc-fc6f775fafe5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982352869 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_long_xfer_wo_dly.2982352869
Directory /workspace/26.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/26.uart_loopback.3748309166
Short name T807
Test name
Test status
Simulation time 11635941929 ps
CPU time 19.27 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:53:23 PM PDT 24
Peak memory 199340 kb
Host smart-71f94fac-224a-4ccd-9f79-1f277a8956c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748309166 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_loopback.3748309166
Directory /workspace/26.uart_loopback/latest

Test location /workspace/coverage/default/26.uart_noise_filter.3784147515
Short name T1002
Test name
Test status
Simulation time 217118814424 ps
CPU time 104.67 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:54:49 PM PDT 24
Peak memory 199900 kb
Host smart-e7ccccb6-898c-4a90-a9b9-75b40838dd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784147515 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_noise_filter.3784147515
Directory /workspace/26.uart_noise_filter/latest

Test location /workspace/coverage/default/26.uart_perf.4162951275
Short name T716
Test name
Test status
Simulation time 16189877058 ps
CPU time 108.33 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:54:53 PM PDT 24
Peak memory 199896 kb
Host smart-8528edaa-2c3e-405f-9a3e-c715d5157954
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4162951275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_perf.4162951275
Directory /workspace/26.uart_perf/latest

Test location /workspace/coverage/default/26.uart_rx_oversample.4277235384
Short name T1104
Test name
Test status
Simulation time 7775650113 ps
CPU time 33.93 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:53:38 PM PDT 24
Peak memory 199080 kb
Host smart-2202785b-118f-429d-b909-de78850a6d30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4277235384 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_oversample.4277235384
Directory /workspace/26.uart_rx_oversample/latest

Test location /workspace/coverage/default/26.uart_rx_parity_err.557222763
Short name T818
Test name
Test status
Simulation time 13908313824 ps
CPU time 21.05 seconds
Started Aug 03 04:53:04 PM PDT 24
Finished Aug 03 04:53:26 PM PDT 24
Peak memory 199848 kb
Host smart-c1bfd5f5-ee28-4ff1-a6e5-41c706ac0f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557222763 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_parity_err.557222763
Directory /workspace/26.uart_rx_parity_err/latest

Test location /workspace/coverage/default/26.uart_rx_start_bit_filter.1047930331
Short name T995
Test name
Test status
Simulation time 3178160850 ps
CPU time 4.87 seconds
Started Aug 03 04:53:07 PM PDT 24
Finished Aug 03 04:53:12 PM PDT 24
Peak memory 196440 kb
Host smart-dbc03a51-bf88-44ec-8ed2-ac4bc44d3a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047930331 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_rx_start_bit_filter.1047930331
Directory /workspace/26.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/26.uart_smoke.2668780995
Short name T782
Test name
Test status
Simulation time 5843973345 ps
CPU time 3.93 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:10 PM PDT 24
Peak memory 199760 kb
Host smart-21421211-1179-48f8-9eba-e52d4b978ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668780995 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_smoke.2668780995
Directory /workspace/26.uart_smoke/latest

Test location /workspace/coverage/default/26.uart_stress_all.1491141152
Short name T683
Test name
Test status
Simulation time 353908721520 ps
CPU time 404.02 seconds
Started Aug 03 04:53:03 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 199812 kb
Host smart-6dfe4ae1-5132-46e4-9dd4-f55ea915a5c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491141152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_stress_all.1491141152
Directory /workspace/26.uart_stress_all/latest

Test location /workspace/coverage/default/26.uart_tx_ovrd.1990305839
Short name T518
Test name
Test status
Simulation time 1672087306 ps
CPU time 4.16 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:09 PM PDT 24
Peak memory 199664 kb
Host smart-001845e8-4912-4446-adc5-d85f34636630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990305839 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_ovrd.1990305839
Directory /workspace/26.uart_tx_ovrd/latest

Test location /workspace/coverage/default/26.uart_tx_rx.2161873417
Short name T281
Test name
Test status
Simulation time 50877908792 ps
CPU time 88.32 seconds
Started Aug 03 04:53:03 PM PDT 24
Finished Aug 03 04:54:32 PM PDT 24
Peak memory 199868 kb
Host smart-fa0fd518-6a20-4021-9c2c-6fdf40e70b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161873417 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.uart_tx_rx.2161873417
Directory /workspace/26.uart_tx_rx/latest

Test location /workspace/coverage/default/260.uart_fifo_reset.139876954
Short name T951
Test name
Test status
Simulation time 102935881477 ps
CPU time 183.31 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 05:01:01 PM PDT 24
Peak memory 199824 kb
Host smart-0265718c-d737-49b5-bd44-94b4a1e8f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139876954 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 260.uart_fifo_reset.139876954
Directory /workspace/260.uart_fifo_reset/latest

Test location /workspace/coverage/default/261.uart_fifo_reset.1318098554
Short name T652
Test name
Test status
Simulation time 176694698079 ps
CPU time 122.61 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:59:59 PM PDT 24
Peak memory 199892 kb
Host smart-fad08a39-152d-4899-97f3-4ee94a038b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318098554 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 261.uart_fifo_reset.1318098554
Directory /workspace/261.uart_fifo_reset/latest

Test location /workspace/coverage/default/262.uart_fifo_reset.3442790086
Short name T796
Test name
Test status
Simulation time 80735886979 ps
CPU time 33.34 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:30 PM PDT 24
Peak memory 199904 kb
Host smart-f0d936b6-6534-4bd4-8fd1-4f4d27e81562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442790086 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 262.uart_fifo_reset.3442790086
Directory /workspace/262.uart_fifo_reset/latest

Test location /workspace/coverage/default/263.uart_fifo_reset.3400987247
Short name T680
Test name
Test status
Simulation time 26712108944 ps
CPU time 40.37 seconds
Started Aug 03 04:57:57 PM PDT 24
Finished Aug 03 04:58:37 PM PDT 24
Peak memory 199912 kb
Host smart-dc9fb0b5-19fc-49a2-9848-a7ff06c01f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400987247 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 263.uart_fifo_reset.3400987247
Directory /workspace/263.uart_fifo_reset/latest

Test location /workspace/coverage/default/264.uart_fifo_reset.3871061741
Short name T832
Test name
Test status
Simulation time 35720792336 ps
CPU time 51.76 seconds
Started Aug 03 04:57:58 PM PDT 24
Finished Aug 03 04:58:50 PM PDT 24
Peak memory 199924 kb
Host smart-09424486-d0df-42ff-825c-46f995dc606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871061741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 264.uart_fifo_reset.3871061741
Directory /workspace/264.uart_fifo_reset/latest

Test location /workspace/coverage/default/266.uart_fifo_reset.2225061168
Short name T1176
Test name
Test status
Simulation time 37783501047 ps
CPU time 28.99 seconds
Started Aug 03 04:57:56 PM PDT 24
Finished Aug 03 04:58:25 PM PDT 24
Peak memory 199860 kb
Host smart-929c37e5-ddb4-4407-bace-189b77e39226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225061168 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 266.uart_fifo_reset.2225061168
Directory /workspace/266.uart_fifo_reset/latest

Test location /workspace/coverage/default/268.uart_fifo_reset.3355413286
Short name T231
Test name
Test status
Simulation time 138492697554 ps
CPU time 111.2 seconds
Started Aug 03 04:57:56 PM PDT 24
Finished Aug 03 04:59:47 PM PDT 24
Peak memory 199908 kb
Host smart-dac86a22-ed21-477c-a9b9-a00f4b3b32e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355413286 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 268.uart_fifo_reset.3355413286
Directory /workspace/268.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_alert_test.3879272576
Short name T859
Test name
Test status
Simulation time 29050520 ps
CPU time 0.59 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:11 PM PDT 24
Peak memory 195288 kb
Host smart-5f707503-8c48-4172-88eb-fc437db5f38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879272576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_alert_test.3879272576
Directory /workspace/27.uart_alert_test/latest

Test location /workspace/coverage/default/27.uart_fifo_full.4072544889
Short name T975
Test name
Test status
Simulation time 31858634655 ps
CPU time 25.65 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:31 PM PDT 24
Peak memory 199832 kb
Host smart-7491ea80-e630-490d-a828-bde9fc5b8f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072544889 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_full.4072544889
Directory /workspace/27.uart_fifo_full/latest

Test location /workspace/coverage/default/27.uart_fifo_overflow.3190704207
Short name T425
Test name
Test status
Simulation time 54481873282 ps
CPU time 20.39 seconds
Started Aug 03 04:53:06 PM PDT 24
Finished Aug 03 04:53:27 PM PDT 24
Peak memory 199880 kb
Host smart-eeed5a8d-f994-4e85-85f8-d15e21c471fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190704207 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_overflow.3190704207
Directory /workspace/27.uart_fifo_overflow/latest

Test location /workspace/coverage/default/27.uart_fifo_reset.2632821440
Short name T476
Test name
Test status
Simulation time 89027751852 ps
CPU time 129.06 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:55:14 PM PDT 24
Peak memory 199892 kb
Host smart-fcee70fb-a90e-4fc3-8b3d-55c7bc437cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632821440 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_fifo_reset.2632821440
Directory /workspace/27.uart_fifo_reset/latest

Test location /workspace/coverage/default/27.uart_intr.2382531452
Short name T118
Test name
Test status
Simulation time 33861244577 ps
CPU time 24.1 seconds
Started Aug 03 04:53:12 PM PDT 24
Finished Aug 03 04:53:36 PM PDT 24
Peak memory 199844 kb
Host smart-6761f256-b008-4e19-967a-ab2f6ef9d07e
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382531452 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_intr.2382531452
Directory /workspace/27.uart_intr/latest

Test location /workspace/coverage/default/27.uart_long_xfer_wo_dly.2275721348
Short name T941
Test name
Test status
Simulation time 96190835316 ps
CPU time 660.57 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 05:04:12 PM PDT 24
Peak memory 199840 kb
Host smart-eb7433ea-f807-415b-abb9-af32628b1e67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275721348 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_long_xfer_wo_dly.2275721348
Directory /workspace/27.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/27.uart_loopback.2895647526
Short name T909
Test name
Test status
Simulation time 8182225755 ps
CPU time 14.95 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 04:53:29 PM PDT 24
Peak memory 199600 kb
Host smart-ccd1d458-1420-4a2c-acf2-d2e34645df59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895647526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_loopback.2895647526
Directory /workspace/27.uart_loopback/latest

Test location /workspace/coverage/default/27.uart_noise_filter.3527174566
Short name T1052
Test name
Test status
Simulation time 70169427966 ps
CPU time 42.93 seconds
Started Aug 03 04:53:12 PM PDT 24
Finished Aug 03 04:53:55 PM PDT 24
Peak memory 199968 kb
Host smart-3be2964b-b681-46d8-aabe-eccb911811ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527174566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_noise_filter.3527174566
Directory /workspace/27.uart_noise_filter/latest

Test location /workspace/coverage/default/27.uart_perf.1220716455
Short name T605
Test name
Test status
Simulation time 18068755337 ps
CPU time 463.98 seconds
Started Aug 03 04:53:13 PM PDT 24
Finished Aug 03 05:00:57 PM PDT 24
Peak memory 199844 kb
Host smart-0d99808b-1bca-49cc-864c-6b1dab385dd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1220716455 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_perf.1220716455
Directory /workspace/27.uart_perf/latest

Test location /workspace/coverage/default/27.uart_rx_oversample.1162407217
Short name T473
Test name
Test status
Simulation time 4337734056 ps
CPU time 4.69 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:09 PM PDT 24
Peak memory 198028 kb
Host smart-be74d645-efc4-481b-8fb6-c6c8535256cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1162407217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_oversample.1162407217
Directory /workspace/27.uart_rx_oversample/latest

Test location /workspace/coverage/default/27.uart_rx_parity_err.2030838456
Short name T414
Test name
Test status
Simulation time 56053222505 ps
CPU time 22.19 seconds
Started Aug 03 04:53:10 PM PDT 24
Finished Aug 03 04:53:32 PM PDT 24
Peak memory 199876 kb
Host smart-23cdf008-0cde-4595-9f6f-ef71767ba3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030838456 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_parity_err.2030838456
Directory /workspace/27.uart_rx_parity_err/latest

Test location /workspace/coverage/default/27.uart_rx_start_bit_filter.801872172
Short name T337
Test name
Test status
Simulation time 3035850997 ps
CPU time 1.24 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:18 PM PDT 24
Peak memory 196000 kb
Host smart-52478679-cffb-4542-af3f-1fa3b382b377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801872172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_rx_start_bit_filter.801872172
Directory /workspace/27.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/27.uart_smoke.2114497077
Short name T371
Test name
Test status
Simulation time 630668259 ps
CPU time 1.54 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:07 PM PDT 24
Peak memory 198828 kb
Host smart-67fb8e2b-6a7d-41ba-b4b3-9b5953d58fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114497077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_smoke.2114497077
Directory /workspace/27.uart_smoke/latest

Test location /workspace/coverage/default/27.uart_stress_all.879365274
Short name T880
Test name
Test status
Simulation time 455232936823 ps
CPU time 643.24 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 05:03:54 PM PDT 24
Peak memory 200032 kb
Host smart-d0e85647-508e-473b-b046-3445acdd2c87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879365274 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_stress_all.879365274
Directory /workspace/27.uart_stress_all/latest

Test location /workspace/coverage/default/27.uart_stress_all_with_rand_reset.1644647160
Short name T318
Test name
Test status
Simulation time 182818876457 ps
CPU time 368.73 seconds
Started Aug 03 04:53:12 PM PDT 24
Finished Aug 03 04:59:20 PM PDT 24
Peak memory 224696 kb
Host smart-3a5cca74-2bc0-494d-8fce-9a7738c5483c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644647160 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 27.uart_stress_all_with_rand_reset.1644647160
Directory /workspace/27.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.uart_tx_ovrd.1157832072
Short name T542
Test name
Test status
Simulation time 668479478 ps
CPU time 1.79 seconds
Started Aug 03 04:53:13 PM PDT 24
Finished Aug 03 04:53:15 PM PDT 24
Peak memory 197772 kb
Host smart-a2fbab54-3660-4dd0-9dc1-ef8c17225e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157832072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_ovrd.1157832072
Directory /workspace/27.uart_tx_ovrd/latest

Test location /workspace/coverage/default/27.uart_tx_rx.105950723
Short name T288
Test name
Test status
Simulation time 58142423497 ps
CPU time 54.41 seconds
Started Aug 03 04:53:05 PM PDT 24
Finished Aug 03 04:53:59 PM PDT 24
Peak memory 199832 kb
Host smart-2ce20f90-b5e3-4d22-85b4-6f5862b970e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105950723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.uart_tx_rx.105950723
Directory /workspace/27.uart_tx_rx/latest

Test location /workspace/coverage/default/271.uart_fifo_reset.3053571663
Short name T802
Test name
Test status
Simulation time 70518277732 ps
CPU time 30.11 seconds
Started Aug 03 04:58:06 PM PDT 24
Finished Aug 03 04:58:37 PM PDT 24
Peak memory 199880 kb
Host smart-5c2cff76-8a76-4042-a636-ab0ffe38f5ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053571663 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 271.uart_fifo_reset.3053571663
Directory /workspace/271.uart_fifo_reset/latest

Test location /workspace/coverage/default/272.uart_fifo_reset.102623932
Short name T1048
Test name
Test status
Simulation time 40677768715 ps
CPU time 56.26 seconds
Started Aug 03 04:58:05 PM PDT 24
Finished Aug 03 04:59:01 PM PDT 24
Peak memory 199864 kb
Host smart-40bd2119-b85a-4dac-a71b-a7018eb272a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102623932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 272.uart_fifo_reset.102623932
Directory /workspace/272.uart_fifo_reset/latest

Test location /workspace/coverage/default/273.uart_fifo_reset.1968633250
Short name T173
Test name
Test status
Simulation time 199334267826 ps
CPU time 44.54 seconds
Started Aug 03 04:58:04 PM PDT 24
Finished Aug 03 04:58:49 PM PDT 24
Peak memory 199936 kb
Host smart-5d201e15-e6f4-4e7e-afc4-ad336aabadcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968633250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 273.uart_fifo_reset.1968633250
Directory /workspace/273.uart_fifo_reset/latest

Test location /workspace/coverage/default/274.uart_fifo_reset.3625097615
Short name T193
Test name
Test status
Simulation time 151374988932 ps
CPU time 152.92 seconds
Started Aug 03 04:58:03 PM PDT 24
Finished Aug 03 05:00:36 PM PDT 24
Peak memory 199824 kb
Host smart-d4a18902-200d-4ead-8bb4-d45bad88c545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625097615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 274.uart_fifo_reset.3625097615
Directory /workspace/274.uart_fifo_reset/latest

Test location /workspace/coverage/default/275.uart_fifo_reset.2382548617
Short name T331
Test name
Test status
Simulation time 50087304853 ps
CPU time 31.18 seconds
Started Aug 03 04:58:04 PM PDT 24
Finished Aug 03 04:58:35 PM PDT 24
Peak memory 199900 kb
Host smart-e4567ce3-0e36-4271-973a-e8c5a80e5654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382548617 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 275.uart_fifo_reset.2382548617
Directory /workspace/275.uart_fifo_reset/latest

Test location /workspace/coverage/default/276.uart_fifo_reset.367614780
Short name T1159
Test name
Test status
Simulation time 33950269715 ps
CPU time 55.98 seconds
Started Aug 03 04:58:07 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 199896 kb
Host smart-289ad77c-172a-4e2e-9bb3-c2c29d5d5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367614780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 276.uart_fifo_reset.367614780
Directory /workspace/276.uart_fifo_reset/latest

Test location /workspace/coverage/default/277.uart_fifo_reset.3200320195
Short name T1098
Test name
Test status
Simulation time 52318214397 ps
CPU time 37.9 seconds
Started Aug 03 04:58:07 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 199896 kb
Host smart-614e9095-0017-47cc-a62a-6a07b610ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200320195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 277.uart_fifo_reset.3200320195
Directory /workspace/277.uart_fifo_reset/latest

Test location /workspace/coverage/default/278.uart_fifo_reset.2701594006
Short name T234
Test name
Test status
Simulation time 50224267974 ps
CPU time 55.77 seconds
Started Aug 03 04:58:07 PM PDT 24
Finished Aug 03 04:59:03 PM PDT 24
Peak memory 199920 kb
Host smart-adeaa681-94c0-4df8-8097-1d40fdfc50c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701594006 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 278.uart_fifo_reset.2701594006
Directory /workspace/278.uart_fifo_reset/latest

Test location /workspace/coverage/default/279.uart_fifo_reset.1589198786
Short name T529
Test name
Test status
Simulation time 34671420797 ps
CPU time 86.6 seconds
Started Aug 03 04:58:05 PM PDT 24
Finished Aug 03 04:59:32 PM PDT 24
Peak memory 199936 kb
Host smart-b0b96b21-b824-48b3-8bd2-e042a61173ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589198786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 279.uart_fifo_reset.1589198786
Directory /workspace/279.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_alert_test.1444695790
Short name T1135
Test name
Test status
Simulation time 34316934 ps
CPU time 0.56 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:12 PM PDT 24
Peak memory 195540 kb
Host smart-26757c65-04c7-4e7f-9d04-c4389e062508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444695790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_alert_test.1444695790
Directory /workspace/28.uart_alert_test/latest

Test location /workspace/coverage/default/28.uart_fifo_full.2018948042
Short name T301
Test name
Test status
Simulation time 18419730963 ps
CPU time 40.29 seconds
Started Aug 03 04:53:13 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 199788 kb
Host smart-a1ffb7cc-8e03-4324-b052-0eddd62225e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018948042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_full.2018948042
Directory /workspace/28.uart_fifo_full/latest

Test location /workspace/coverage/default/28.uart_fifo_overflow.2866762252
Short name T314
Test name
Test status
Simulation time 128980506810 ps
CPU time 185.85 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 04:56:20 PM PDT 24
Peak memory 199932 kb
Host smart-b34b78ef-2e71-4d75-b811-c856210b896c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866762252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_overflow.2866762252
Directory /workspace/28.uart_fifo_overflow/latest

Test location /workspace/coverage/default/28.uart_fifo_reset.1069025875
Short name T836
Test name
Test status
Simulation time 20995516948 ps
CPU time 35.64 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 199912 kb
Host smart-1261a58c-797b-44aa-8e40-3a74a6658110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069025875 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_fifo_reset.1069025875
Directory /workspace/28.uart_fifo_reset/latest

Test location /workspace/coverage/default/28.uart_intr.464152204
Short name T878
Test name
Test status
Simulation time 29380579312 ps
CPU time 24.89 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:36 PM PDT 24
Peak memory 199904 kb
Host smart-063d27b6-c86d-44d1-a8e2-2b3be5081332
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464152204 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_intr.464152204
Directory /workspace/28.uart_intr/latest

Test location /workspace/coverage/default/28.uart_long_xfer_wo_dly.3632182476
Short name T364
Test name
Test status
Simulation time 84286337296 ps
CPU time 78.97 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:54:30 PM PDT 24
Peak memory 199908 kb
Host smart-8db4bcc0-ff31-46d4-b1b8-e5d67121a5ab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3632182476 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_long_xfer_wo_dly.3632182476
Directory /workspace/28.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/28.uart_loopback.3602987936
Short name T340
Test name
Test status
Simulation time 1349741216 ps
CPU time 1.88 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:13 PM PDT 24
Peak memory 195324 kb
Host smart-29ff688a-2d56-4d74-a918-a85d4561489e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602987936 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_loopback.3602987936
Directory /workspace/28.uart_loopback/latest

Test location /workspace/coverage/default/28.uart_noise_filter.4017394681
Short name T505
Test name
Test status
Simulation time 77636971823 ps
CPU time 32.59 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 04:53:46 PM PDT 24
Peak memory 208336 kb
Host smart-3cbcf0cd-b85d-4b33-bb2d-aa22d77a1d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017394681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_noise_filter.4017394681
Directory /workspace/28.uart_noise_filter/latest

Test location /workspace/coverage/default/28.uart_perf.1855790870
Short name T1062
Test name
Test status
Simulation time 28960577977 ps
CPU time 1161.51 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 05:12:35 PM PDT 24
Peak memory 199788 kb
Host smart-276f2f70-2555-4f9a-92db-371c5af4e7ca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1855790870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_perf.1855790870
Directory /workspace/28.uart_perf/latest

Test location /workspace/coverage/default/28.uart_rx_oversample.815591547
Short name T394
Test name
Test status
Simulation time 5357670949 ps
CPU time 8 seconds
Started Aug 03 04:53:12 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 198016 kb
Host smart-c1846f9d-be8d-4a1e-88a1-c3db94413c74
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=815591547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_oversample.815591547
Directory /workspace/28.uart_rx_oversample/latest

Test location /workspace/coverage/default/28.uart_rx_parity_err.3010613291
Short name T417
Test name
Test status
Simulation time 174990765495 ps
CPU time 367 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:59:18 PM PDT 24
Peak memory 199936 kb
Host smart-bb91abe4-706d-41d0-b972-868f6ea9b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010613291 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_parity_err.3010613291
Directory /workspace/28.uart_rx_parity_err/latest

Test location /workspace/coverage/default/28.uart_rx_start_bit_filter.3258121036
Short name T30
Test name
Test status
Simulation time 35225680355 ps
CPU time 27.86 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:45 PM PDT 24
Peak memory 196220 kb
Host smart-c4a5b8e6-2d20-4a30-8294-f886d4bc95ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258121036 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_rx_start_bit_filter.3258121036
Directory /workspace/28.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/28.uart_smoke.403286821
Short name T612
Test name
Test status
Simulation time 834492424 ps
CPU time 1.54 seconds
Started Aug 03 04:53:13 PM PDT 24
Finished Aug 03 04:53:14 PM PDT 24
Peak memory 198044 kb
Host smart-f86ae614-df14-4520-b76e-5c7ba748c3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403286821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_smoke.403286821
Directory /workspace/28.uart_smoke/latest

Test location /workspace/coverage/default/28.uart_stress_all.3369054223
Short name T1092
Test name
Test status
Simulation time 373255850458 ps
CPU time 998.15 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 05:09:49 PM PDT 24
Peak memory 199872 kb
Host smart-a7778796-21f9-4b3e-806f-3856e218969c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369054223 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_stress_all.3369054223
Directory /workspace/28.uart_stress_all/latest

Test location /workspace/coverage/default/28.uart_stress_all_with_rand_reset.2015745060
Short name T857
Test name
Test status
Simulation time 737518362195 ps
CPU time 889.12 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 224732 kb
Host smart-9d9cdcee-4451-45e9-8a1a-a5fe6280eeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015745060 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 28.uart_stress_all_with_rand_reset.2015745060
Directory /workspace/28.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.uart_tx_ovrd.1140172675
Short name T459
Test name
Test status
Simulation time 7123001896 ps
CPU time 7.75 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:19 PM PDT 24
Peak memory 199584 kb
Host smart-83bdcc8a-398f-4b61-bf8c-b649a22cc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140172675 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_ovrd.1140172675
Directory /workspace/28.uart_tx_ovrd/latest

Test location /workspace/coverage/default/28.uart_tx_rx.1625125216
Short name T455
Test name
Test status
Simulation time 50259033318 ps
CPU time 115.63 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:55:07 PM PDT 24
Peak memory 199932 kb
Host smart-12596033-3c40-4afd-aa28-ccc393c2f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625125216 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.uart_tx_rx.1625125216
Directory /workspace/28.uart_tx_rx/latest

Test location /workspace/coverage/default/280.uart_fifo_reset.2081540371
Short name T211
Test name
Test status
Simulation time 23702682705 ps
CPU time 47.13 seconds
Started Aug 03 04:58:04 PM PDT 24
Finished Aug 03 04:58:51 PM PDT 24
Peak memory 199856 kb
Host smart-ed814393-5918-4ce0-a7a9-2b6b90075adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081540371 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 280.uart_fifo_reset.2081540371
Directory /workspace/280.uart_fifo_reset/latest

Test location /workspace/coverage/default/281.uart_fifo_reset.2938956243
Short name T342
Test name
Test status
Simulation time 45814494467 ps
CPU time 63.47 seconds
Started Aug 03 04:58:04 PM PDT 24
Finished Aug 03 04:59:08 PM PDT 24
Peak memory 199912 kb
Host smart-2602e30b-4971-46a0-bbd3-da5208d787c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938956243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 281.uart_fifo_reset.2938956243
Directory /workspace/281.uart_fifo_reset/latest

Test location /workspace/coverage/default/283.uart_fifo_reset.3581498615
Short name T1013
Test name
Test status
Simulation time 98578508936 ps
CPU time 44.28 seconds
Started Aug 03 04:58:08 PM PDT 24
Finished Aug 03 04:58:52 PM PDT 24
Peak memory 199836 kb
Host smart-536789c8-735e-44af-b00b-8d96afa56bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581498615 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 283.uart_fifo_reset.3581498615
Directory /workspace/283.uart_fifo_reset/latest

Test location /workspace/coverage/default/285.uart_fifo_reset.494596784
Short name T420
Test name
Test status
Simulation time 105466294078 ps
CPU time 42.99 seconds
Started Aug 03 04:58:08 PM PDT 24
Finished Aug 03 04:58:51 PM PDT 24
Peak memory 199828 kb
Host smart-67aa9415-f79b-4818-9af3-e05b9bf5dcca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494596784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 285.uart_fifo_reset.494596784
Directory /workspace/285.uart_fifo_reset/latest

Test location /workspace/coverage/default/286.uart_fifo_reset.3345305109
Short name T814
Test name
Test status
Simulation time 14879346967 ps
CPU time 19.69 seconds
Started Aug 03 04:58:08 PM PDT 24
Finished Aug 03 04:58:28 PM PDT 24
Peak memory 199888 kb
Host smart-2e94a965-36d3-480a-8ced-e92666caee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345305109 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 286.uart_fifo_reset.3345305109
Directory /workspace/286.uart_fifo_reset/latest

Test location /workspace/coverage/default/288.uart_fifo_reset.2768186943
Short name T17
Test name
Test status
Simulation time 96492026844 ps
CPU time 21.79 seconds
Started Aug 03 04:58:11 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 199840 kb
Host smart-321bb94e-e907-412e-a3f9-a1d0a2fcbb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768186943 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 288.uart_fifo_reset.2768186943
Directory /workspace/288.uart_fifo_reset/latest

Test location /workspace/coverage/default/289.uart_fifo_reset.453871775
Short name T1082
Test name
Test status
Simulation time 48222535011 ps
CPU time 114.81 seconds
Started Aug 03 04:58:11 PM PDT 24
Finished Aug 03 05:00:06 PM PDT 24
Peak memory 199816 kb
Host smart-eba43e6f-6204-436e-a74e-78c59d603f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453871775 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 289.uart_fifo_reset.453871775
Directory /workspace/289.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_alert_test.560679306
Short name T844
Test name
Test status
Simulation time 33144232 ps
CPU time 0.54 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:19 PM PDT 24
Peak memory 195280 kb
Host smart-4845377f-6a2b-46c8-a5ee-2a43462ca6ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560679306 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_alert_test.560679306
Directory /workspace/29.uart_alert_test/latest

Test location /workspace/coverage/default/29.uart_fifo_full.2575547961
Short name T1067
Test name
Test status
Simulation time 45705116289 ps
CPU time 14.44 seconds
Started Aug 03 04:53:13 PM PDT 24
Finished Aug 03 04:53:28 PM PDT 24
Peak memory 199892 kb
Host smart-a2d95b2f-7b4a-4401-8f32-8eee27bba52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575547961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_full.2575547961
Directory /workspace/29.uart_fifo_full/latest

Test location /workspace/coverage/default/29.uart_fifo_overflow.3155407865
Short name T370
Test name
Test status
Simulation time 111323779955 ps
CPU time 82.24 seconds
Started Aug 03 04:53:14 PM PDT 24
Finished Aug 03 04:54:36 PM PDT 24
Peak memory 199288 kb
Host smart-7b75423f-56e3-4f6d-a683-b66e7afbdc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155407865 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_overflow.3155407865
Directory /workspace/29.uart_fifo_overflow/latest

Test location /workspace/coverage/default/29.uart_fifo_reset.129676802
Short name T98
Test name
Test status
Simulation time 16785426462 ps
CPU time 35.28 seconds
Started Aug 03 04:53:11 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 199876 kb
Host smart-49a4fd35-6874-4873-a1ef-ce93e73a3292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129676802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_fifo_reset.129676802
Directory /workspace/29.uart_fifo_reset/latest

Test location /workspace/coverage/default/29.uart_intr.1526964879
Short name T812
Test name
Test status
Simulation time 40168411007 ps
CPU time 72.1 seconds
Started Aug 03 04:53:21 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199772 kb
Host smart-19aecafb-43a0-4b5e-b984-83bd5f033e08
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526964879 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_intr.1526964879
Directory /workspace/29.uart_intr/latest

Test location /workspace/coverage/default/29.uart_long_xfer_wo_dly.4268719436
Short name T847
Test name
Test status
Simulation time 75225742767 ps
CPU time 552.4 seconds
Started Aug 03 04:53:18 PM PDT 24
Finished Aug 03 05:02:31 PM PDT 24
Peak memory 199928 kb
Host smart-2d44a0ff-dd92-47ef-9671-edac9d996ac9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4268719436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_long_xfer_wo_dly.4268719436
Directory /workspace/29.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/29.uart_loopback.3297788720
Short name T1114
Test name
Test status
Simulation time 7027816903 ps
CPU time 4.17 seconds
Started Aug 03 04:53:20 PM PDT 24
Finished Aug 03 04:53:24 PM PDT 24
Peak memory 199836 kb
Host smart-d999b89d-cc5b-400c-9ffd-541c750e1adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297788720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_loopback.3297788720
Directory /workspace/29.uart_loopback/latest

Test location /workspace/coverage/default/29.uart_noise_filter.2812673689
Short name T991
Test name
Test status
Simulation time 37430930765 ps
CPU time 42.31 seconds
Started Aug 03 04:53:18 PM PDT 24
Finished Aug 03 04:54:00 PM PDT 24
Peak memory 200000 kb
Host smart-8c6d1faa-2240-4aa9-988f-3301d8ed4c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812673689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_noise_filter.2812673689
Directory /workspace/29.uart_noise_filter/latest

Test location /workspace/coverage/default/29.uart_perf.2886641220
Short name T100
Test name
Test status
Simulation time 12811505337 ps
CPU time 629.26 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 05:03:46 PM PDT 24
Peak memory 199832 kb
Host smart-fb2e0086-1aeb-4294-8417-766090a31526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886641220 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_perf.2886641220
Directory /workspace/29.uart_perf/latest

Test location /workspace/coverage/default/29.uart_rx_oversample.1015704701
Short name T939
Test name
Test status
Simulation time 5087114829 ps
CPU time 44.59 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:54:02 PM PDT 24
Peak memory 198020 kb
Host smart-3c2dbfc6-4302-4b8f-a16e-4f93bd743612
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1015704701 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_oversample.1015704701
Directory /workspace/29.uart_rx_oversample/latest

Test location /workspace/coverage/default/29.uart_rx_parity_err.9514145
Short name T312
Test name
Test status
Simulation time 5256098741 ps
CPU time 7.55 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:26 PM PDT 24
Peak memory 196788 kb
Host smart-195bd790-eb37-403f-ab11-cfa1b7237f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9514145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_parity_err.9514145
Directory /workspace/29.uart_rx_parity_err/latest

Test location /workspace/coverage/default/29.uart_rx_start_bit_filter.647363736
Short name T1086
Test name
Test status
Simulation time 2665100040 ps
CPU time 1.65 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 195924 kb
Host smart-a7cbad67-21ca-4e5e-99d8-8304b4b95aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647363736 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_rx_start_bit_filter.647363736
Directory /workspace/29.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/29.uart_smoke.393504794
Short name T375
Test name
Test status
Simulation time 5913775772 ps
CPU time 25.57 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:43 PM PDT 24
Peak memory 199164 kb
Host smart-4d61df84-6b18-4cf4-8e45-857ae74eb864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393504794 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_smoke.393504794
Directory /workspace/29.uart_smoke/latest

Test location /workspace/coverage/default/29.uart_stress_all.89021966
Short name T460
Test name
Test status
Simulation time 435979480658 ps
CPU time 315.73 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 208120 kb
Host smart-8c132646-a5b4-4ff3-8a4b-c47bb4d469ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89021966 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_stress_all.89021966
Directory /workspace/29.uart_stress_all/latest

Test location /workspace/coverage/default/29.uart_stress_all_with_rand_reset.130064961
Short name T866
Test name
Test status
Simulation time 28765288297 ps
CPU time 781.48 seconds
Started Aug 03 04:53:18 PM PDT 24
Finished Aug 03 05:06:19 PM PDT 24
Peak memory 216192 kb
Host smart-cfb6cda0-7b7a-439f-8f41-bb287d633d3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130064961 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 29.uart_stress_all_with_rand_reset.130064961
Directory /workspace/29.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.uart_tx_ovrd.2687695514
Short name T441
Test name
Test status
Simulation time 575046716 ps
CPU time 1.97 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:19 PM PDT 24
Peak memory 198220 kb
Host smart-a827bec6-4d2a-4e0e-ba53-65ce755d6652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687695514 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.uart_tx_ovrd.2687695514
Directory /workspace/29.uart_tx_ovrd/latest

Test location /workspace/coverage/default/290.uart_fifo_reset.3626075729
Short name T191
Test name
Test status
Simulation time 319607655031 ps
CPU time 179.7 seconds
Started Aug 03 04:58:18 PM PDT 24
Finished Aug 03 05:01:18 PM PDT 24
Peak memory 199636 kb
Host smart-f4b0fa1c-a3f2-4d62-900f-ac8ee5cf6c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626075729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 290.uart_fifo_reset.3626075729
Directory /workspace/290.uart_fifo_reset/latest

Test location /workspace/coverage/default/291.uart_fifo_reset.375168681
Short name T1174
Test name
Test status
Simulation time 165116342428 ps
CPU time 69.82 seconds
Started Aug 03 04:58:18 PM PDT 24
Finished Aug 03 04:59:28 PM PDT 24
Peak memory 199408 kb
Host smart-9101a6bc-e600-4846-a581-3f87b42f4983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375168681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 291.uart_fifo_reset.375168681
Directory /workspace/291.uart_fifo_reset/latest

Test location /workspace/coverage/default/292.uart_fifo_reset.1450786996
Short name T513
Test name
Test status
Simulation time 83156977469 ps
CPU time 125.77 seconds
Started Aug 03 04:58:15 PM PDT 24
Finished Aug 03 05:00:21 PM PDT 24
Peak memory 199892 kb
Host smart-cc22a216-dd01-4eda-a0d9-8a0f00d68f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450786996 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 292.uart_fifo_reset.1450786996
Directory /workspace/292.uart_fifo_reset/latest

Test location /workspace/coverage/default/293.uart_fifo_reset.4104898191
Short name T148
Test name
Test status
Simulation time 17669293567 ps
CPU time 14.72 seconds
Started Aug 03 04:58:15 PM PDT 24
Finished Aug 03 04:58:29 PM PDT 24
Peak memory 199856 kb
Host smart-1dfad8a1-db5e-49ea-a44f-a2eb81851c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104898191 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 293.uart_fifo_reset.4104898191
Directory /workspace/293.uart_fifo_reset/latest

Test location /workspace/coverage/default/294.uart_fifo_reset.3646768608
Short name T218
Test name
Test status
Simulation time 138663133364 ps
CPU time 60.68 seconds
Started Aug 03 04:58:17 PM PDT 24
Finished Aug 03 04:59:17 PM PDT 24
Peak memory 199624 kb
Host smart-e494cf12-7db1-45c8-9430-ca862350d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646768608 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 294.uart_fifo_reset.3646768608
Directory /workspace/294.uart_fifo_reset/latest

Test location /workspace/coverage/default/295.uart_fifo_reset.525095955
Short name T1053
Test name
Test status
Simulation time 74425068507 ps
CPU time 135.19 seconds
Started Aug 03 04:58:15 PM PDT 24
Finished Aug 03 05:00:31 PM PDT 24
Peak memory 199900 kb
Host smart-89bd2e4d-5398-4065-848f-f0caf9d8cac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525095955 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 295.uart_fifo_reset.525095955
Directory /workspace/295.uart_fifo_reset/latest

Test location /workspace/coverage/default/296.uart_fifo_reset.2107100805
Short name T945
Test name
Test status
Simulation time 66941939654 ps
CPU time 32.92 seconds
Started Aug 03 04:58:15 PM PDT 24
Finished Aug 03 04:58:48 PM PDT 24
Peak memory 199936 kb
Host smart-9b04d35b-1d5b-47ba-a890-b34444e2ffd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107100805 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 296.uart_fifo_reset.2107100805
Directory /workspace/296.uart_fifo_reset/latest

Test location /workspace/coverage/default/297.uart_fifo_reset.1322579054
Short name T131
Test name
Test status
Simulation time 25508002837 ps
CPU time 37.21 seconds
Started Aug 03 04:58:17 PM PDT 24
Finished Aug 03 04:58:55 PM PDT 24
Peak memory 199880 kb
Host smart-ebb59ac4-fe86-4d19-a37c-d8ea41ef8751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322579054 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 297.uart_fifo_reset.1322579054
Directory /workspace/297.uart_fifo_reset/latest

Test location /workspace/coverage/default/298.uart_fifo_reset.4068565346
Short name T718
Test name
Test status
Simulation time 60801317760 ps
CPU time 16.57 seconds
Started Aug 03 04:58:15 PM PDT 24
Finished Aug 03 04:58:32 PM PDT 24
Peak memory 199812 kb
Host smart-9c1039b7-e232-4ca9-9b14-a9dc9252c405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068565346 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 298.uart_fifo_reset.4068565346
Directory /workspace/298.uart_fifo_reset/latest

Test location /workspace/coverage/default/299.uart_fifo_reset.1752511500
Short name T454
Test name
Test status
Simulation time 64957615191 ps
CPU time 17.73 seconds
Started Aug 03 04:58:16 PM PDT 24
Finished Aug 03 04:58:33 PM PDT 24
Peak memory 199928 kb
Host smart-5afae5ee-6dfc-4b56-be5b-232a9a3db71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752511500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 299.uart_fifo_reset.1752511500
Directory /workspace/299.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_alert_test.2386062680
Short name T699
Test name
Test status
Simulation time 33311364 ps
CPU time 0.54 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:51:48 PM PDT 24
Peak memory 194700 kb
Host smart-77908042-bd2a-4dd8-9396-b4ec63ebc8ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386062680 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_alert_test.2386062680
Directory /workspace/3.uart_alert_test/latest

Test location /workspace/coverage/default/3.uart_fifo_full.2304319580
Short name T1128
Test name
Test status
Simulation time 61865877262 ps
CPU time 46.08 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:36 PM PDT 24
Peak memory 199768 kb
Host smart-cb7cb2bb-bd65-44a0-82f0-9a0140f1ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304319580 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_full.2304319580
Directory /workspace/3.uart_fifo_full/latest

Test location /workspace/coverage/default/3.uart_fifo_overflow.454339606
Short name T299
Test name
Test status
Simulation time 82898114373 ps
CPU time 129.45 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 199792 kb
Host smart-ec312d7c-b88f-4ddc-ac82-1f9e016895eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454339606 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_overflow.454339606
Directory /workspace/3.uart_fifo_overflow/latest

Test location /workspace/coverage/default/3.uart_fifo_reset.64068451
Short name T633
Test name
Test status
Simulation time 82116465914 ps
CPU time 18.66 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:52:08 PM PDT 24
Peak memory 198728 kb
Host smart-ef174016-1207-44c4-86e3-a7fb34c4b8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64068451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_fifo_reset.64068451
Directory /workspace/3.uart_fifo_reset/latest

Test location /workspace/coverage/default/3.uart_intr.3567317784
Short name T679
Test name
Test status
Simulation time 64189967795 ps
CPU time 78.43 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:53:09 PM PDT 24
Peak memory 199912 kb
Host smart-711f5c70-76e3-451f-9156-6e650c791a3d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567317784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_intr.3567317784
Directory /workspace/3.uart_intr/latest

Test location /workspace/coverage/default/3.uart_long_xfer_wo_dly.2734215535
Short name T805
Test name
Test status
Simulation time 68149176003 ps
CPU time 273.91 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:56:22 PM PDT 24
Peak memory 199884 kb
Host smart-0d5870d2-b699-4edd-99bf-6fc215eaf163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734215535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_long_xfer_wo_dly.2734215535
Directory /workspace/3.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/3.uart_loopback.876620786
Short name T474
Test name
Test status
Simulation time 5726158281 ps
CPU time 5.82 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:51:55 PM PDT 24
Peak memory 198608 kb
Host smart-bcc1bba3-4c4d-41e6-91d8-b092147a301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876620786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_loopback.876620786
Directory /workspace/3.uart_loopback/latest

Test location /workspace/coverage/default/3.uart_noise_filter.1886702748
Short name T504
Test name
Test status
Simulation time 32758873818 ps
CPU time 72.93 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 199948 kb
Host smart-cf2f42d5-902f-41fd-9039-a13df5ab278c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886702748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_noise_filter.1886702748
Directory /workspace/3.uart_noise_filter/latest

Test location /workspace/coverage/default/3.uart_perf.2662045187
Short name T1003
Test name
Test status
Simulation time 19056920873 ps
CPU time 284.09 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:56:34 PM PDT 24
Peak memory 199912 kb
Host smart-998f79af-2846-4239-8c80-813f355fb30e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2662045187 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_perf.2662045187
Directory /workspace/3.uart_perf/latest

Test location /workspace/coverage/default/3.uart_rx_oversample.3049922726
Short name T932
Test name
Test status
Simulation time 7768890890 ps
CPU time 59.9 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 198724 kb
Host smart-aee703dd-e510-405a-9e16-4bef6f91687a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049922726 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_oversample.3049922726
Directory /workspace/3.uart_rx_oversample/latest

Test location /workspace/coverage/default/3.uart_rx_parity_err.2532270932
Short name T845
Test name
Test status
Simulation time 54928201805 ps
CPU time 72.56 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 199864 kb
Host smart-3916ba68-4f46-405c-807b-72be090d7f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532270932 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_parity_err.2532270932
Directory /workspace/3.uart_rx_parity_err/latest

Test location /workspace/coverage/default/3.uart_rx_start_bit_filter.1896547358
Short name T99
Test name
Test status
Simulation time 3287722923 ps
CPU time 3.1 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:51:54 PM PDT 24
Peak memory 196504 kb
Host smart-c41372fb-b147-4e5e-8b98-ca03aae0c278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896547358 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_rx_start_bit_filter.1896547358
Directory /workspace/3.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/3.uart_sec_cm.1771867502
Short name T84
Test name
Test status
Simulation time 69244369 ps
CPU time 0.76 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:51:50 PM PDT 24
Peak memory 218312 kb
Host smart-3852501f-9585-463a-b1f5-b723daf3ba49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771867502 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_sec_cm.1771867502
Directory /workspace/3.uart_sec_cm/latest

Test location /workspace/coverage/default/3.uart_smoke.1411159295
Short name T411
Test name
Test status
Simulation time 895831749 ps
CPU time 3.45 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:51:52 PM PDT 24
Peak memory 198788 kb
Host smart-94220941-944f-437c-a9ae-57e031a46a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411159295 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_smoke.1411159295
Directory /workspace/3.uart_smoke/latest

Test location /workspace/coverage/default/3.uart_stress_all.2468764297
Short name T451
Test name
Test status
Simulation time 333954693548 ps
CPU time 140.96 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:54:09 PM PDT 24
Peak memory 199844 kb
Host smart-06e1173f-d2d5-45b9-8c61-01c46fb627b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468764297 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_stress_all.2468764297
Directory /workspace/3.uart_stress_all/latest

Test location /workspace/coverage/default/3.uart_stress_all_with_rand_reset.3037128429
Short name T164
Test name
Test status
Simulation time 442764339264 ps
CPU time 769.49 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 05:04:36 PM PDT 24
Peak memory 224708 kb
Host smart-111cdde6-4eba-4924-81a9-c0ad66640198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037128429 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 3.uart_stress_all_with_rand_reset.3037128429
Directory /workspace/3.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.uart_tx_ovrd.3622249958
Short name T1074
Test name
Test status
Simulation time 7967003629 ps
CPU time 11.21 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:51:58 PM PDT 24
Peak memory 199668 kb
Host smart-5f7ee21b-901a-4bfd-b5ed-064160db5f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622249958 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_ovrd.3622249958
Directory /workspace/3.uart_tx_ovrd/latest

Test location /workspace/coverage/default/3.uart_tx_rx.3065535338
Short name T352
Test name
Test status
Simulation time 18484400500 ps
CPU time 10.31 seconds
Started Aug 03 04:51:46 PM PDT 24
Finished Aug 03 04:51:56 PM PDT 24
Peak memory 199892 kb
Host smart-61abc3ee-2b18-43b1-8c78-70ecddab6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065535338 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.uart_tx_rx.3065535338
Directory /workspace/3.uart_tx_rx/latest

Test location /workspace/coverage/default/30.uart_alert_test.3092432649
Short name T787
Test name
Test status
Simulation time 21892827 ps
CPU time 0.57 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 195584 kb
Host smart-c82381e9-1dde-4149-a982-ecc2e97c8516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092432649 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_alert_test.3092432649
Directory /workspace/30.uart_alert_test/latest

Test location /workspace/coverage/default/30.uart_fifo_full.3168296500
Short name T841
Test name
Test status
Simulation time 21945514140 ps
CPU time 41.14 seconds
Started Aug 03 04:53:22 PM PDT 24
Finished Aug 03 04:54:03 PM PDT 24
Peak memory 199844 kb
Host smart-2bd23b09-8e1e-45d6-a8fe-0377c72d9561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168296500 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_full.3168296500
Directory /workspace/30.uart_fifo_full/latest

Test location /workspace/coverage/default/30.uart_fifo_overflow.1483576677
Short name T990
Test name
Test status
Simulation time 24901748413 ps
CPU time 37.42 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 199888 kb
Host smart-af55309a-fdd0-45af-a8fa-c1e895d652d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483576677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_overflow.1483576677
Directory /workspace/30.uart_fifo_overflow/latest

Test location /workspace/coverage/default/30.uart_fifo_reset.2272053142
Short name T820
Test name
Test status
Simulation time 161432750128 ps
CPU time 62.98 seconds
Started Aug 03 04:53:15 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 199912 kb
Host smart-615ac034-c3f4-462b-9d96-1a0d5ea63312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272053142 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_fifo_reset.2272053142
Directory /workspace/30.uart_fifo_reset/latest

Test location /workspace/coverage/default/30.uart_intr.4074384998
Short name T1170
Test name
Test status
Simulation time 1670689656 ps
CPU time 3.13 seconds
Started Aug 03 04:53:16 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 195628 kb
Host smart-decc7841-acf0-4a14-9902-7855bb4c7886
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074384998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_intr.4074384998
Directory /workspace/30.uart_intr/latest

Test location /workspace/coverage/default/30.uart_long_xfer_wo_dly.2868433979
Short name T374
Test name
Test status
Simulation time 119792782486 ps
CPU time 543.05 seconds
Started Aug 03 04:53:21 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 199776 kb
Host smart-b6caae45-19e5-47fb-98f3-7f866bc741c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2868433979 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_long_xfer_wo_dly.2868433979
Directory /workspace/30.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/30.uart_loopback.4117795729
Short name T1021
Test name
Test status
Simulation time 7889509107 ps
CPU time 5.42 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:24 PM PDT 24
Peak memory 199808 kb
Host smart-bfff5d41-b255-4225-888a-ebf44c828b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117795729 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_loopback.4117795729
Directory /workspace/30.uart_loopback/latest

Test location /workspace/coverage/default/30.uart_noise_filter.1409032702
Short name T597
Test name
Test status
Simulation time 98745942402 ps
CPU time 38.81 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 199344 kb
Host smart-7dd54abd-6940-4aab-81de-d30b3968fea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409032702 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_noise_filter.1409032702
Directory /workspace/30.uart_noise_filter/latest

Test location /workspace/coverage/default/30.uart_perf.3530035668
Short name T858
Test name
Test status
Simulation time 2067347324 ps
CPU time 25.55 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:42 PM PDT 24
Peak memory 199768 kb
Host smart-c398b916-aaae-4a66-be8a-ad0c69fd4d53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3530035668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_perf.3530035668
Directory /workspace/30.uart_perf/latest

Test location /workspace/coverage/default/30.uart_rx_oversample.3692190912
Short name T810
Test name
Test status
Simulation time 4409869700 ps
CPU time 30.15 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 199244 kb
Host smart-57cd1e7d-aa61-4639-8ddb-a7af5f0ed8c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692190912 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_oversample.3692190912
Directory /workspace/30.uart_rx_oversample/latest

Test location /workspace/coverage/default/30.uart_rx_parity_err.2312458784
Short name T742
Test name
Test status
Simulation time 29336328964 ps
CPU time 40.28 seconds
Started Aug 03 04:53:17 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 199832 kb
Host smart-3c701d19-37a3-419b-9e5e-be342f7250d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312458784 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_parity_err.2312458784
Directory /workspace/30.uart_rx_parity_err/latest

Test location /workspace/coverage/default/30.uart_rx_start_bit_filter.453871229
Short name T901
Test name
Test status
Simulation time 3335639539 ps
CPU time 1.12 seconds
Started Aug 03 04:53:20 PM PDT 24
Finished Aug 03 04:53:21 PM PDT 24
Peak memory 196420 kb
Host smart-c104f972-2f0c-415d-adda-16c70e1fdaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453871229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_rx_start_bit_filter.453871229
Directory /workspace/30.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/30.uart_smoke.2498296723
Short name T821
Test name
Test status
Simulation time 523945904 ps
CPU time 1.1 seconds
Started Aug 03 04:53:19 PM PDT 24
Finished Aug 03 04:53:20 PM PDT 24
Peak memory 198184 kb
Host smart-dd0f6bd5-708c-4b35-b79a-fd135164395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498296723 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_smoke.2498296723
Directory /workspace/30.uart_smoke/latest

Test location /workspace/coverage/default/30.uart_stress_all.3918612824
Short name T596
Test name
Test status
Simulation time 188927483882 ps
CPU time 492.74 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 05:01:36 PM PDT 24
Peak memory 208252 kb
Host smart-b30da449-55d4-4ffa-8be1-0115b38c8b6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918612824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_stress_all.3918612824
Directory /workspace/30.uart_stress_all/latest

Test location /workspace/coverage/default/30.uart_stress_all_with_rand_reset.3254441328
Short name T839
Test name
Test status
Simulation time 26746738316 ps
CPU time 999.54 seconds
Started Aug 03 04:53:18 PM PDT 24
Finished Aug 03 05:09:58 PM PDT 24
Peak memory 215880 kb
Host smart-50955dbb-5c8a-46e1-8cee-e6ae60d6eba0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254441328 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 30.uart_stress_all_with_rand_reset.3254441328
Directory /workspace/30.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.uart_tx_ovrd.3130760681
Short name T1015
Test name
Test status
Simulation time 13667679428 ps
CPU time 20.06 seconds
Started Aug 03 04:53:20 PM PDT 24
Finished Aug 03 04:53:41 PM PDT 24
Peak memory 199784 kb
Host smart-8b897fd7-55da-41f5-9c42-788a35ddd3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130760681 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_ovrd.3130760681
Directory /workspace/30.uart_tx_ovrd/latest

Test location /workspace/coverage/default/30.uart_tx_rx.2829244567
Short name T401
Test name
Test status
Simulation time 36840832395 ps
CPU time 74.58 seconds
Started Aug 03 04:53:20 PM PDT 24
Finished Aug 03 04:54:35 PM PDT 24
Peak memory 199776 kb
Host smart-0d1ea561-7a54-42eb-8131-830e7ed6c1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829244567 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.uart_tx_rx.2829244567
Directory /workspace/30.uart_tx_rx/latest

Test location /workspace/coverage/default/31.uart_alert_test.186927852
Short name T32
Test name
Test status
Simulation time 14257237 ps
CPU time 0.55 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 04:53:24 PM PDT 24
Peak memory 195284 kb
Host smart-87956d30-ec9a-456e-9308-ab79dbe2dec8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186927852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_alert_test.186927852
Directory /workspace/31.uart_alert_test/latest

Test location /workspace/coverage/default/31.uart_fifo_full.1608011408
Short name T885
Test name
Test status
Simulation time 55265573994 ps
CPU time 43.78 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 04:54:06 PM PDT 24
Peak memory 199876 kb
Host smart-ab2174f1-bd18-495c-a045-aa0d3f456836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608011408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_full.1608011408
Directory /workspace/31.uart_fifo_full/latest

Test location /workspace/coverage/default/31.uart_fifo_overflow.2037495195
Short name T902
Test name
Test status
Simulation time 69009701261 ps
CPU time 29.55 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 199756 kb
Host smart-a0f5b397-1b52-4ec9-bf9f-1ff862130748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037495195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_overflow.2037495195
Directory /workspace/31.uart_fifo_overflow/latest

Test location /workspace/coverage/default/31.uart_fifo_reset.893952260
Short name T1033
Test name
Test status
Simulation time 115781636686 ps
CPU time 141.04 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:55:45 PM PDT 24
Peak memory 199804 kb
Host smart-0187a63b-3265-49cd-9889-e09d43ebeb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893952260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_fifo_reset.893952260
Directory /workspace/31.uart_fifo_reset/latest

Test location /workspace/coverage/default/31.uart_intr.67681718
Short name T452
Test name
Test status
Simulation time 42452044424 ps
CPU time 18.76 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:53:43 PM PDT 24
Peak memory 199716 kb
Host smart-14ac3778-e07a-4bb8-b7bc-f8b17ef86087
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67681718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_intr.67681718
Directory /workspace/31.uart_intr/latest

Test location /workspace/coverage/default/31.uart_long_xfer_wo_dly.3410182067
Short name T1150
Test name
Test status
Simulation time 116880292390 ps
CPU time 729.44 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 05:05:35 PM PDT 24
Peak memory 199844 kb
Host smart-2d8e2f55-aac6-491a-beef-18602aecec38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3410182067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_long_xfer_wo_dly.3410182067
Directory /workspace/31.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/31.uart_loopback.4164237711
Short name T482
Test name
Test status
Simulation time 1840375857 ps
CPU time 1.42 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:53:27 PM PDT 24
Peak memory 195540 kb
Host smart-11995773-0ad4-41d9-b324-214a66a2fc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164237711 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_loopback.4164237711
Directory /workspace/31.uart_loopback/latest

Test location /workspace/coverage/default/31.uart_noise_filter.3440031383
Short name T816
Test name
Test status
Simulation time 187170662816 ps
CPU time 89.79 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:54:55 PM PDT 24
Peak memory 208208 kb
Host smart-cf6fa7c2-548e-464a-9b31-e149cdf0a341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440031383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_noise_filter.3440031383
Directory /workspace/31.uart_noise_filter/latest

Test location /workspace/coverage/default/31.uart_perf.1075927374
Short name T439
Test name
Test status
Simulation time 20601419738 ps
CPU time 319.98 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 04:58:43 PM PDT 24
Peak memory 199836 kb
Host smart-07d943f7-8f35-4911-8436-5e14a1f872dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075927374 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_perf.1075927374
Directory /workspace/31.uart_perf/latest

Test location /workspace/coverage/default/31.uart_rx_oversample.552634170
Short name T521
Test name
Test status
Simulation time 3147747792 ps
CPU time 13.4 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:53:38 PM PDT 24
Peak memory 199216 kb
Host smart-8b1079cc-e880-4f51-85b1-90eae33a5ba6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=552634170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_oversample.552634170
Directory /workspace/31.uart_rx_oversample/latest

Test location /workspace/coverage/default/31.uart_rx_parity_err.1169781110
Short name T595
Test name
Test status
Simulation time 55782289102 ps
CPU time 28.69 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 04:53:51 PM PDT 24
Peak memory 199892 kb
Host smart-61583d4a-5be7-4c61-9157-0eda2b7d1477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169781110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_parity_err.1169781110
Directory /workspace/31.uart_rx_parity_err/latest

Test location /workspace/coverage/default/31.uart_rx_start_bit_filter.585850401
Short name T548
Test name
Test status
Simulation time 1557145418 ps
CPU time 1.24 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:53:26 PM PDT 24
Peak memory 195548 kb
Host smart-51df7b52-9da7-4dff-9d18-6dc4e9ec1d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585850401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_rx_start_bit_filter.585850401
Directory /workspace/31.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/31.uart_smoke.3406407251
Short name T1124
Test name
Test status
Simulation time 721787829 ps
CPU time 1.58 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:53:26 PM PDT 24
Peak memory 198596 kb
Host smart-1022e1be-5f50-4c6d-9580-ef3c8bbf64b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406407251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_smoke.3406407251
Directory /workspace/31.uart_smoke/latest

Test location /workspace/coverage/default/31.uart_stress_all.1748238118
Short name T327
Test name
Test status
Simulation time 267517564636 ps
CPU time 717.33 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 05:05:22 PM PDT 24
Peak memory 200116 kb
Host smart-a37d951f-7dc1-48b2-949c-3ef65c3af94f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748238118 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_stress_all.1748238118
Directory /workspace/31.uart_stress_all/latest

Test location /workspace/coverage/default/31.uart_stress_all_with_rand_reset.2178836317
Short name T223
Test name
Test status
Simulation time 145482686036 ps
CPU time 405.69 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 05:00:11 PM PDT 24
Peak memory 216332 kb
Host smart-37006a6c-94a7-4cf0-88fb-90209a3962a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178836317 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 31.uart_stress_all_with_rand_reset.2178836317
Directory /workspace/31.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.uart_tx_ovrd.497679715
Short name T558
Test name
Test status
Simulation time 770577053 ps
CPU time 2.58 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:53:27 PM PDT 24
Peak memory 199180 kb
Host smart-570f3235-e41e-42ae-a26a-f8f16987e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497679715 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_ovrd.497679715
Directory /workspace/31.uart_tx_ovrd/latest

Test location /workspace/coverage/default/31.uart_tx_rx.3642617087
Short name T242
Test name
Test status
Simulation time 73059412934 ps
CPU time 126.47 seconds
Started Aug 03 04:53:23 PM PDT 24
Finished Aug 03 04:55:30 PM PDT 24
Peak memory 199844 kb
Host smart-0635459f-442e-4dfb-89d1-18cec66f5d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642617087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.uart_tx_rx.3642617087
Directory /workspace/31.uart_tx_rx/latest

Test location /workspace/coverage/default/32.uart_alert_test.2179961970
Short name T687
Test name
Test status
Simulation time 14183781 ps
CPU time 0.58 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:53:32 PM PDT 24
Peak memory 194724 kb
Host smart-0f18c70e-e037-4e11-bb08-35f03a94318a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179961970 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_alert_test.2179961970
Directory /workspace/32.uart_alert_test/latest

Test location /workspace/coverage/default/32.uart_fifo_full.1037176333
Short name T758
Test name
Test status
Simulation time 97105342432 ps
CPU time 145.85 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:55:51 PM PDT 24
Peak memory 199892 kb
Host smart-39673365-1d2d-45e7-a543-f0a2d5048ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037176333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_full.1037176333
Directory /workspace/32.uart_fifo_full/latest

Test location /workspace/coverage/default/32.uart_fifo_overflow.1025997914
Short name T771
Test name
Test status
Simulation time 48258802134 ps
CPU time 36.6 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:54:02 PM PDT 24
Peak memory 199808 kb
Host smart-1e016bb6-d485-4d99-8f65-da33ddd35e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025997914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_overflow.1025997914
Directory /workspace/32.uart_fifo_overflow/latest

Test location /workspace/coverage/default/32.uart_fifo_reset.1775163742
Short name T998
Test name
Test status
Simulation time 28019849893 ps
CPU time 41.86 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:54:06 PM PDT 24
Peak memory 199892 kb
Host smart-7b5b8a8f-f4a8-46ae-b595-1e79acb349ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775163742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_fifo_reset.1775163742
Directory /workspace/32.uart_fifo_reset/latest

Test location /workspace/coverage/default/32.uart_intr.494199183
Short name T456
Test name
Test status
Simulation time 374464799871 ps
CPU time 408.88 seconds
Started Aug 03 04:53:26 PM PDT 24
Finished Aug 03 05:00:15 PM PDT 24
Peak memory 199968 kb
Host smart-50e44f71-4410-4aec-af4b-6dbe74f4511c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494199183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_intr.494199183
Directory /workspace/32.uart_intr/latest

Test location /workspace/coverage/default/32.uart_long_xfer_wo_dly.778377639
Short name T1094
Test name
Test status
Simulation time 235030722369 ps
CPU time 234.14 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:57:27 PM PDT 24
Peak memory 199728 kb
Host smart-8e83256b-5ada-4d00-9c5f-2a2f4cf4f750
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=778377639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_long_xfer_wo_dly.778377639
Directory /workspace/32.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/32.uart_loopback.3084567706
Short name T345
Test name
Test status
Simulation time 6508664738 ps
CPU time 5.15 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:53:37 PM PDT 24
Peak memory 199888 kb
Host smart-7f568995-6b24-4e13-80b4-7ddc44641e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084567706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_loopback.3084567706
Directory /workspace/32.uart_loopback/latest

Test location /workspace/coverage/default/32.uart_noise_filter.2507491558
Short name T723
Test name
Test status
Simulation time 25842919495 ps
CPU time 40.38 seconds
Started Aug 03 04:53:27 PM PDT 24
Finished Aug 03 04:54:07 PM PDT 24
Peak memory 199616 kb
Host smart-12224f35-bab6-4c4f-a2ac-c0e486743c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507491558 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_noise_filter.2507491558
Directory /workspace/32.uart_noise_filter/latest

Test location /workspace/coverage/default/32.uart_perf.2736437284
Short name T676
Test name
Test status
Simulation time 23866174889 ps
CPU time 1429.9 seconds
Started Aug 03 04:53:30 PM PDT 24
Finished Aug 03 05:17:21 PM PDT 24
Peak memory 199928 kb
Host smart-34338ace-94f4-4011-a368-109def01c561
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2736437284 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_perf.2736437284
Directory /workspace/32.uart_perf/latest

Test location /workspace/coverage/default/32.uart_rx_oversample.134167688
Short name T892
Test name
Test status
Simulation time 4622688103 ps
CPU time 26.43 seconds
Started Aug 03 04:53:25 PM PDT 24
Finished Aug 03 04:53:51 PM PDT 24
Peak memory 199148 kb
Host smart-8eeeddc6-023c-46fd-8b94-48c5d9ea1cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134167688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_oversample.134167688
Directory /workspace/32.uart_rx_oversample/latest

Test location /workspace/coverage/default/32.uart_rx_parity_err.3429571547
Short name T1123
Test name
Test status
Simulation time 110657676068 ps
CPU time 46.92 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:54:18 PM PDT 24
Peak memory 199532 kb
Host smart-8ea9d938-76cd-476f-b6ed-82cfe8482ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429571547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_parity_err.3429571547
Directory /workspace/32.uart_rx_parity_err/latest

Test location /workspace/coverage/default/32.uart_rx_start_bit_filter.2818006921
Short name T711
Test name
Test status
Simulation time 460483996 ps
CPU time 0.98 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 195472 kb
Host smart-d4cf09eb-0c7b-451a-be09-4e887183a464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818006921 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_rx_start_bit_filter.2818006921
Directory /workspace/32.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/32.uart_smoke.2543590850
Short name T453
Test name
Test status
Simulation time 6208829676 ps
CPU time 15.91 seconds
Started Aug 03 04:53:24 PM PDT 24
Finished Aug 03 04:53:40 PM PDT 24
Peak memory 199948 kb
Host smart-f3a6191f-a54f-4bc3-825c-04a0d670bc1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543590850 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_smoke.2543590850
Directory /workspace/32.uart_smoke/latest

Test location /workspace/coverage/default/32.uart_stress_all.1481545786
Short name T1115
Test name
Test status
Simulation time 118103942658 ps
CPU time 178.79 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:56:30 PM PDT 24
Peak memory 216304 kb
Host smart-adb8247a-a746-45ba-b2fa-831a9b30fa61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481545786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_stress_all.1481545786
Directory /workspace/32.uart_stress_all/latest

Test location /workspace/coverage/default/32.uart_tx_ovrd.1403116244
Short name T351
Test name
Test status
Simulation time 1620429207 ps
CPU time 1.89 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 198636 kb
Host smart-79a62b26-5ef9-44e5-9fcf-1c2e5f770fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403116244 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_ovrd.1403116244
Directory /workspace/32.uart_tx_ovrd/latest

Test location /workspace/coverage/default/32.uart_tx_rx.1036423780
Short name T678
Test name
Test status
Simulation time 239102000526 ps
CPU time 36.79 seconds
Started Aug 03 04:53:26 PM PDT 24
Finished Aug 03 04:54:03 PM PDT 24
Peak memory 199852 kb
Host smart-3ebe4dc6-fdfe-482d-9a78-c8d054ba7bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036423780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.uart_tx_rx.1036423780
Directory /workspace/32.uart_tx_rx/latest

Test location /workspace/coverage/default/33.uart_alert_test.44990064
Short name T426
Test name
Test status
Simulation time 13446951 ps
CPU time 0.58 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 195512 kb
Host smart-85ba6d52-c6c6-4210-9939-0d04bdde3aec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44990064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_alert_test.44990064
Directory /workspace/33.uart_alert_test/latest

Test location /workspace/coverage/default/33.uart_fifo_full.2210290484
Short name T629
Test name
Test status
Simulation time 71005416855 ps
CPU time 111.4 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:55:23 PM PDT 24
Peak memory 199888 kb
Host smart-0df51f72-d99b-48b7-9861-68c41b72075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210290484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_full.2210290484
Directory /workspace/33.uart_fifo_full/latest

Test location /workspace/coverage/default/33.uart_fifo_overflow.855121064
Short name T1122
Test name
Test status
Simulation time 38240973685 ps
CPU time 73.41 seconds
Started Aug 03 04:53:33 PM PDT 24
Finished Aug 03 04:54:46 PM PDT 24
Peak memory 199916 kb
Host smart-d31b0b32-cdcf-4c5e-a8db-70df774b2608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855121064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_overflow.855121064
Directory /workspace/33.uart_fifo_overflow/latest

Test location /workspace/coverage/default/33.uart_fifo_reset.123972706
Short name T822
Test name
Test status
Simulation time 234957825975 ps
CPU time 628.67 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 05:04:00 PM PDT 24
Peak memory 199848 kb
Host smart-8eb9ab67-dae1-4d6b-aca3-2bcab13ab5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123972706 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_fifo_reset.123972706
Directory /workspace/33.uart_fifo_reset/latest

Test location /workspace/coverage/default/33.uart_intr.2947879867
Short name T380
Test name
Test status
Simulation time 128772616378 ps
CPU time 102.21 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:55:14 PM PDT 24
Peak memory 196152 kb
Host smart-2e2d419c-8165-4c32-b156-6469cc505443
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947879867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_intr.2947879867
Directory /workspace/33.uart_intr/latest

Test location /workspace/coverage/default/33.uart_long_xfer_wo_dly.2275186566
Short name T1031
Test name
Test status
Simulation time 161559621748 ps
CPU time 781.98 seconds
Started Aug 03 04:53:42 PM PDT 24
Finished Aug 03 05:06:44 PM PDT 24
Peak memory 199936 kb
Host smart-ad545994-9fb4-4ca3-ad1a-ce5246c51802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2275186566 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_long_xfer_wo_dly.2275186566
Directory /workspace/33.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/33.uart_loopback.3027582783
Short name T544
Test name
Test status
Simulation time 6376972610 ps
CPU time 6.17 seconds
Started Aug 03 04:53:33 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 198620 kb
Host smart-a17c60f4-23a4-4fe8-94ee-dde46b8c5b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027582783 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_loopback.3027582783
Directory /workspace/33.uart_loopback/latest

Test location /workspace/coverage/default/33.uart_noise_filter.2388603033
Short name T1166
Test name
Test status
Simulation time 417973637276 ps
CPU time 40.89 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:54:13 PM PDT 24
Peak memory 200032 kb
Host smart-7fe563c2-22c9-449e-bd36-db7ca3f4936d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388603033 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_noise_filter.2388603033
Directory /workspace/33.uart_noise_filter/latest

Test location /workspace/coverage/default/33.uart_perf.431630397
Short name T677
Test name
Test status
Simulation time 5380368750 ps
CPU time 166.07 seconds
Started Aug 03 04:53:33 PM PDT 24
Finished Aug 03 04:56:19 PM PDT 24
Peak memory 199876 kb
Host smart-94d8c44b-35a3-4604-b2b1-c3f0376470ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=431630397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_perf.431630397
Directory /workspace/33.uart_perf/latest

Test location /workspace/coverage/default/33.uart_rx_oversample.3116928182
Short name T11
Test name
Test status
Simulation time 5405232168 ps
CPU time 48.34 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:54:20 PM PDT 24
Peak memory 198064 kb
Host smart-b3317a96-155b-45ec-9181-6818b7624ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116928182 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_oversample.3116928182
Directory /workspace/33.uart_rx_oversample/latest

Test location /workspace/coverage/default/33.uart_rx_parity_err.811191016
Short name T783
Test name
Test status
Simulation time 27503099664 ps
CPU time 47.71 seconds
Started Aug 03 04:53:33 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 199832 kb
Host smart-4c3baf4b-c199-4828-a294-66802b136e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811191016 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_parity_err.811191016
Directory /workspace/33.uart_rx_parity_err/latest

Test location /workspace/coverage/default/33.uart_rx_start_bit_filter.2312177809
Short name T1042
Test name
Test status
Simulation time 1283153578 ps
CPU time 2.35 seconds
Started Aug 03 04:53:32 PM PDT 24
Finished Aug 03 04:53:34 PM PDT 24
Peak memory 195388 kb
Host smart-02eae5d7-85fc-435c-a8b4-ba3ff566aa3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312177809 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_rx_start_bit_filter.2312177809
Directory /workspace/33.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/33.uart_smoke.1645551525
Short name T509
Test name
Test status
Simulation time 677322038 ps
CPU time 2.07 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:53:33 PM PDT 24
Peak memory 198164 kb
Host smart-5377c2bc-d7f2-4a91-8611-6a8033b2fb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645551525 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_smoke.1645551525
Directory /workspace/33.uart_smoke/latest

Test location /workspace/coverage/default/33.uart_stress_all_with_rand_reset.296161562
Short name T53
Test name
Test status
Simulation time 49108715305 ps
CPU time 163.58 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:56:22 PM PDT 24
Peak memory 215520 kb
Host smart-9406fc0e-8f14-4c37-9328-18e04817009d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296161562 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 33.uart_stress_all_with_rand_reset.296161562
Directory /workspace/33.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.uart_tx_ovrd.893583643
Short name T365
Test name
Test status
Simulation time 7262784878 ps
CPU time 11.4 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:53:43 PM PDT 24
Peak memory 200012 kb
Host smart-f6ac58ce-8736-444a-b916-c3f4cf144e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893583643 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_ovrd.893583643
Directory /workspace/33.uart_tx_ovrd/latest

Test location /workspace/coverage/default/33.uart_tx_rx.2972673161
Short name T913
Test name
Test status
Simulation time 101739313589 ps
CPU time 46.23 seconds
Started Aug 03 04:53:31 PM PDT 24
Finished Aug 03 04:54:18 PM PDT 24
Peak memory 199800 kb
Host smart-6a18b7bf-cc9e-4ef7-8304-bd353ab382d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972673161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.uart_tx_rx.2972673161
Directory /workspace/33.uart_tx_rx/latest

Test location /workspace/coverage/default/34.uart_alert_test.3075114998
Short name T1056
Test name
Test status
Simulation time 13393184 ps
CPU time 0.55 seconds
Started Aug 03 04:53:40 PM PDT 24
Finished Aug 03 04:53:41 PM PDT 24
Peak memory 195308 kb
Host smart-3de5ba02-cf1c-46c5-a229-a9bb89bcb90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075114998 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_alert_test.3075114998
Directory /workspace/34.uart_alert_test/latest

Test location /workspace/coverage/default/34.uart_fifo_full.235353368
Short name T669
Test name
Test status
Simulation time 185925151325 ps
CPU time 325.34 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:59:04 PM PDT 24
Peak memory 199916 kb
Host smart-412c06aa-e872-495e-9bde-efeb3dd921d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235353368 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_full.235353368
Directory /workspace/34.uart_fifo_full/latest

Test location /workspace/coverage/default/34.uart_fifo_overflow.3616013679
Short name T775
Test name
Test status
Simulation time 200980175400 ps
CPU time 17.83 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 199864 kb
Host smart-fed03488-a9a2-45b6-ac19-1973b2d8595b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616013679 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_fifo_overflow.3616013679
Directory /workspace/34.uart_fifo_overflow/latest

Test location /workspace/coverage/default/34.uart_intr.1381847101
Short name T120
Test name
Test status
Simulation time 61031157509 ps
CPU time 45.39 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:54:25 PM PDT 24
Peak memory 198956 kb
Host smart-3c423409-8c4f-4c23-84d7-93970e674c04
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381847101 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_intr.1381847101
Directory /workspace/34.uart_intr/latest

Test location /workspace/coverage/default/34.uart_long_xfer_wo_dly.3417293589
Short name T978
Test name
Test status
Simulation time 69894209643 ps
CPU time 258.16 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:57:57 PM PDT 24
Peak memory 199848 kb
Host smart-07215865-4f6d-47e5-88d0-96f23eb318f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3417293589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_long_xfer_wo_dly.3417293589
Directory /workspace/34.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/34.uart_loopback.2939073847
Short name T338
Test name
Test status
Simulation time 7958639759 ps
CPU time 20.68 seconds
Started Aug 03 04:53:40 PM PDT 24
Finished Aug 03 04:54:01 PM PDT 24
Peak memory 199892 kb
Host smart-f04bd0d1-5018-4164-a186-c24e4a64c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939073847 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_loopback.2939073847
Directory /workspace/34.uart_loopback/latest

Test location /workspace/coverage/default/34.uart_noise_filter.1485837434
Short name T423
Test name
Test status
Simulation time 47082804965 ps
CPU time 70.6 seconds
Started Aug 03 04:53:40 PM PDT 24
Finished Aug 03 04:54:51 PM PDT 24
Peak memory 200020 kb
Host smart-b2fdc696-d963-409e-9069-37ef11730402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485837434 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_noise_filter.1485837434
Directory /workspace/34.uart_noise_filter/latest

Test location /workspace/coverage/default/34.uart_perf.1775180203
Short name T915
Test name
Test status
Simulation time 3454346638 ps
CPU time 151.56 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:56:10 PM PDT 24
Peak memory 199844 kb
Host smart-6669c0b9-7c48-4b95-aaf3-15502af4715d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1775180203 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_perf.1775180203
Directory /workspace/34.uart_perf/latest

Test location /workspace/coverage/default/34.uart_rx_oversample.2399999526
Short name T347
Test name
Test status
Simulation time 3081493294 ps
CPU time 6.15 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:53:51 PM PDT 24
Peak memory 197956 kb
Host smart-4d27043e-a290-4971-9ce3-3214a12cf659
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2399999526 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_oversample.2399999526
Directory /workspace/34.uart_rx_oversample/latest

Test location /workspace/coverage/default/34.uart_rx_parity_err.1972192408
Short name T589
Test name
Test status
Simulation time 34417150414 ps
CPU time 20.19 seconds
Started Aug 03 04:53:40 PM PDT 24
Finished Aug 03 04:54:00 PM PDT 24
Peak memory 199908 kb
Host smart-97a3878f-f158-46fa-b05b-143c9381f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972192408 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_parity_err.1972192408
Directory /workspace/34.uart_rx_parity_err/latest

Test location /workspace/coverage/default/34.uart_rx_start_bit_filter.3626667073
Short name T388
Test name
Test status
Simulation time 1464510197 ps
CPU time 1.74 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 195592 kb
Host smart-7a89c603-4287-46d2-87dd-fa24be34312c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626667073 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_rx_start_bit_filter.3626667073
Directory /workspace/34.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/34.uart_smoke.2984507017
Short name T1144
Test name
Test status
Simulation time 687549374 ps
CPU time 2.74 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 198704 kb
Host smart-790d028b-c9b7-4ccd-b223-ecae2359ddea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984507017 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_smoke.2984507017
Directory /workspace/34.uart_smoke/latest

Test location /workspace/coverage/default/34.uart_stress_all_with_rand_reset.3246491262
Short name T926
Test name
Test status
Simulation time 203758025064 ps
CPU time 695.07 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 05:05:13 PM PDT 24
Peak memory 216420 kb
Host smart-809a8a9c-3811-4e2c-9b41-dae2730f86ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246491262 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 34.uart_stress_all_with_rand_reset.3246491262
Directory /workspace/34.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.uart_tx_ovrd.1231093433
Short name T578
Test name
Test status
Simulation time 1131900964 ps
CPU time 1.23 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:53:40 PM PDT 24
Peak memory 197684 kb
Host smart-0ddef2f1-d730-4aa5-abc2-8ac70ee82942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231093433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_ovrd.1231093433
Directory /workspace/34.uart_tx_ovrd/latest

Test location /workspace/coverage/default/34.uart_tx_rx.3037095505
Short name T383
Test name
Test status
Simulation time 8325143852 ps
CPU time 14.69 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 199916 kb
Host smart-858f624d-f3de-4408-98d3-c0fd825c6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037095505 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.uart_tx_rx.3037095505
Directory /workspace/34.uart_tx_rx/latest

Test location /workspace/coverage/default/35.uart_alert_test.3171578181
Short name T5
Test name
Test status
Simulation time 110671139 ps
CPU time 0.54 seconds
Started Aug 03 04:53:47 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 195580 kb
Host smart-4a268bba-d5a1-4a83-9596-6deb26981324
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171578181 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_alert_test.3171578181
Directory /workspace/35.uart_alert_test/latest

Test location /workspace/coverage/default/35.uart_fifo_full.928182796
Short name T103
Test name
Test status
Simulation time 16743222823 ps
CPU time 17.87 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:56 PM PDT 24
Peak memory 200112 kb
Host smart-a7fbf975-8e65-47b1-9da0-50cfa7f5b91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928182796 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_full.928182796
Directory /workspace/35.uart_fifo_full/latest

Test location /workspace/coverage/default/35.uart_fifo_overflow.856894982
Short name T391
Test name
Test status
Simulation time 85007121439 ps
CPU time 125.51 seconds
Started Aug 03 04:53:42 PM PDT 24
Finished Aug 03 04:55:47 PM PDT 24
Peak memory 199936 kb
Host smart-6a8e0e91-8c67-4748-898c-26654f96771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856894982 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_overflow.856894982
Directory /workspace/35.uart_fifo_overflow/latest

Test location /workspace/coverage/default/35.uart_fifo_reset.3957885214
Short name T189
Test name
Test status
Simulation time 20361964444 ps
CPU time 19.93 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:54:05 PM PDT 24
Peak memory 199936 kb
Host smart-20ebd256-9732-44e1-a9b6-7e70c82b73c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957885214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_fifo_reset.3957885214
Directory /workspace/35.uart_fifo_reset/latest

Test location /workspace/coverage/default/35.uart_intr.2816068610
Short name T1009
Test name
Test status
Simulation time 61876447163 ps
CPU time 91.56 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:55:16 PM PDT 24
Peak memory 199844 kb
Host smart-11234d64-9b66-4824-8ab4-32f4ee4f458d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816068610 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_intr.2816068610
Directory /workspace/35.uart_intr/latest

Test location /workspace/coverage/default/35.uart_long_xfer_wo_dly.2078116310
Short name T14
Test name
Test status
Simulation time 109100062015 ps
CPU time 520.3 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 05:02:24 PM PDT 24
Peak memory 199828 kb
Host smart-0fc8f94e-8682-4b87-b490-67a7fb13e4ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2078116310 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_long_xfer_wo_dly.2078116310
Directory /workspace/35.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/35.uart_loopback.3145689972
Short name T615
Test name
Test status
Simulation time 5036506518 ps
CPU time 3.16 seconds
Started Aug 03 04:53:43 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 198984 kb
Host smart-25bf2ced-9418-4a93-aec5-cd3e9f56ae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145689972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_loopback.3145689972
Directory /workspace/35.uart_loopback/latest

Test location /workspace/coverage/default/35.uart_noise_filter.682548451
Short name T254
Test name
Test status
Simulation time 71805573555 ps
CPU time 112.41 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:55:32 PM PDT 24
Peak memory 198840 kb
Host smart-31a2b1ae-ea73-43bd-b07c-acb92dccc604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682548451 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_noise_filter.682548451
Directory /workspace/35.uart_noise_filter/latest

Test location /workspace/coverage/default/35.uart_perf.3979646951
Short name T471
Test name
Test status
Simulation time 18129587225 ps
CPU time 299.06 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 04:58:47 PM PDT 24
Peak memory 199924 kb
Host smart-1edee4e1-21d3-44fd-a622-546ae7bd22ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979646951 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_perf.3979646951
Directory /workspace/35.uart_perf/latest

Test location /workspace/coverage/default/35.uart_rx_oversample.403665926
Short name T873
Test name
Test status
Simulation time 4215405804 ps
CPU time 36.38 seconds
Started Aug 03 04:53:40 PM PDT 24
Finished Aug 03 04:54:16 PM PDT 24
Peak memory 199124 kb
Host smart-08156b33-d7de-4c40-901d-ca2054d543f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403665926 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_oversample.403665926
Directory /workspace/35.uart_rx_oversample/latest

Test location /workspace/coverage/default/35.uart_rx_parity_err.1487539870
Short name T306
Test name
Test status
Simulation time 60571972779 ps
CPU time 78.76 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 199908 kb
Host smart-89002e96-629b-4163-acad-db7f3445de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487539870 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_parity_err.1487539870
Directory /workspace/35.uart_rx_parity_err/latest

Test location /workspace/coverage/default/35.uart_rx_start_bit_filter.618248949
Short name T1110
Test name
Test status
Simulation time 5116982019 ps
CPU time 2.57 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 196256 kb
Host smart-d3378b4d-3b01-4ca0-b49a-e2bff7d6fed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618248949 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_rx_start_bit_filter.618248949
Directory /workspace/35.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/35.uart_smoke.4147100057
Short name T828
Test name
Test status
Simulation time 603678411 ps
CPU time 2.51 seconds
Started Aug 03 04:53:41 PM PDT 24
Finished Aug 03 04:53:44 PM PDT 24
Peak memory 199568 kb
Host smart-c3840c1f-5c86-45fb-9374-48af9a62bbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147100057 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_smoke.4147100057
Directory /workspace/35.uart_smoke/latest

Test location /workspace/coverage/default/35.uart_stress_all_with_rand_reset.3533843057
Short name T94
Test name
Test status
Simulation time 64174106142 ps
CPU time 501.88 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 05:02:10 PM PDT 24
Peak memory 211856 kb
Host smart-ca983aaf-2c9f-4a23-8c60-4d63477d2a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533843057 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 35.uart_stress_all_with_rand_reset.3533843057
Directory /workspace/35.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.uart_tx_ovrd.706642920
Short name T1140
Test name
Test status
Simulation time 511092962 ps
CPU time 1.73 seconds
Started Aug 03 04:53:38 PM PDT 24
Finished Aug 03 04:53:40 PM PDT 24
Peak memory 198196 kb
Host smart-2fd4e8c9-f3da-4ddf-9e6a-94d0a0c39424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706642920 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_ovrd.706642920
Directory /workspace/35.uart_tx_ovrd/latest

Test location /workspace/coverage/default/35.uart_tx_rx.1854058309
Short name T262
Test name
Test status
Simulation time 13664144404 ps
CPU time 21.61 seconds
Started Aug 03 04:53:39 PM PDT 24
Finished Aug 03 04:54:01 PM PDT 24
Peak memory 197056 kb
Host smart-cd58518a-cc62-4653-887c-474bf9d04374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854058309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.uart_tx_rx.1854058309
Directory /workspace/35.uart_tx_rx/latest

Test location /workspace/coverage/default/36.uart_alert_test.1686162218
Short name T438
Test name
Test status
Simulation time 24451772 ps
CPU time 0.55 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 04:53:48 PM PDT 24
Peak memory 195300 kb
Host smart-af651eea-bd13-4338-bd64-8e54ec082b30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686162218 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_alert_test.1686162218
Directory /workspace/36.uart_alert_test/latest

Test location /workspace/coverage/default/36.uart_fifo_full.535914602
Short name T1137
Test name
Test status
Simulation time 205145406271 ps
CPU time 279.97 seconds
Started Aug 03 04:53:47 PM PDT 24
Finished Aug 03 04:58:27 PM PDT 24
Peak memory 199944 kb
Host smart-133f18c8-4446-4ab5-b4ce-7f5d873c4971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535914602 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_full.535914602
Directory /workspace/36.uart_fifo_full/latest

Test location /workspace/coverage/default/36.uart_fifo_overflow.2702839309
Short name T649
Test name
Test status
Simulation time 20857624313 ps
CPU time 34.98 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 199176 kb
Host smart-67660b03-46f1-4e5b-ae99-3b9f563ef7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702839309 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_overflow.2702839309
Directory /workspace/36.uart_fifo_overflow/latest

Test location /workspace/coverage/default/36.uart_fifo_reset.2714260385
Short name T216
Test name
Test status
Simulation time 37371275478 ps
CPU time 34.04 seconds
Started Aug 03 04:53:43 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 199916 kb
Host smart-17cbad69-f60e-4b17-a1f6-8d74b77f3627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714260385 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_fifo_reset.2714260385
Directory /workspace/36.uart_fifo_reset/latest

Test location /workspace/coverage/default/36.uart_intr.2697102392
Short name T488
Test name
Test status
Simulation time 9144661238 ps
CPU time 7.86 seconds
Started Aug 03 04:53:43 PM PDT 24
Finished Aug 03 04:53:51 PM PDT 24
Peak memory 199296 kb
Host smart-10de2029-ed39-43ed-93e5-b60b7b6377ca
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697102392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_intr.2697102392
Directory /workspace/36.uart_intr/latest

Test location /workspace/coverage/default/36.uart_long_xfer_wo_dly.3096986262
Short name T609
Test name
Test status
Simulation time 216526051102 ps
CPU time 463.19 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 05:01:28 PM PDT 24
Peak memory 199788 kb
Host smart-79d713fb-3d13-449e-a30d-3d991f7edcdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096986262 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_long_xfer_wo_dly.3096986262
Directory /workspace/36.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/36.uart_loopback.2783742145
Short name T532
Test name
Test status
Simulation time 2281941341 ps
CPU time 5.39 seconds
Started Aug 03 04:53:44 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 198268 kb
Host smart-b16e9ed5-cee2-4072-bc32-9ab5e7a838b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783742145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_loopback.2783742145
Directory /workspace/36.uart_loopback/latest

Test location /workspace/coverage/default/36.uart_noise_filter.3764536221
Short name T639
Test name
Test status
Simulation time 32941470730 ps
CPU time 55.09 seconds
Started Aug 03 04:53:47 PM PDT 24
Finished Aug 03 04:54:42 PM PDT 24
Peak memory 199988 kb
Host smart-4163fd37-1de5-49c9-b3bd-68c622a3de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764536221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_noise_filter.3764536221
Directory /workspace/36.uart_noise_filter/latest

Test location /workspace/coverage/default/36.uart_perf.1756371848
Short name T510
Test name
Test status
Simulation time 14217374037 ps
CPU time 200.75 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:57:05 PM PDT 24
Peak memory 199808 kb
Host smart-2ea0a210-f708-4c65-b5a4-4660424c97f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1756371848 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_perf.1756371848
Directory /workspace/36.uart_perf/latest

Test location /workspace/coverage/default/36.uart_rx_oversample.3628119755
Short name T472
Test name
Test status
Simulation time 6945312058 ps
CPU time 60.88 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:54:46 PM PDT 24
Peak memory 198764 kb
Host smart-7cda9946-9fac-4560-a9b6-852e4a2d5add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3628119755 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_oversample.3628119755
Directory /workspace/36.uart_rx_oversample/latest

Test location /workspace/coverage/default/36.uart_rx_parity_err.625486898
Short name T1152
Test name
Test status
Simulation time 151239311816 ps
CPU time 15.37 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 04:54:03 PM PDT 24
Peak memory 199932 kb
Host smart-e5d85e5f-ade0-45f9-8049-b76559d7e41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625486898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_parity_err.625486898
Directory /workspace/36.uart_rx_parity_err/latest

Test location /workspace/coverage/default/36.uart_rx_start_bit_filter.163348994
Short name T1154
Test name
Test status
Simulation time 3556477874 ps
CPU time 2.13 seconds
Started Aug 03 04:53:48 PM PDT 24
Finished Aug 03 04:53:50 PM PDT 24
Peak memory 195448 kb
Host smart-76141650-5f27-4cce-87e1-8a9c5e81fff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163348994 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_rx_start_bit_filter.163348994
Directory /workspace/36.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/36.uart_smoke.3378718786
Short name T517
Test name
Test status
Simulation time 496262948 ps
CPU time 1.32 seconds
Started Aug 03 04:53:46 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 198528 kb
Host smart-a32f5f99-f047-4f3f-b2d9-41829b457ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378718786 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_smoke.3378718786
Directory /workspace/36.uart_smoke/latest

Test location /workspace/coverage/default/36.uart_tx_ovrd.492461051
Short name T1045
Test name
Test status
Simulation time 1073911720 ps
CPU time 2.85 seconds
Started Aug 03 04:53:46 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 198540 kb
Host smart-0e07b2e8-9345-4e51-b1ec-8fcda398e250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492461051 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_ovrd.492461051
Directory /workspace/36.uart_tx_ovrd/latest

Test location /workspace/coverage/default/36.uart_tx_rx.2268214261
Short name T6
Test name
Test status
Simulation time 74332687940 ps
CPU time 125.45 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:55:50 PM PDT 24
Peak memory 199844 kb
Host smart-889d9558-7db3-4458-8ac0-3d6dd11af8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268214261 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.uart_tx_rx.2268214261
Directory /workspace/36.uart_tx_rx/latest

Test location /workspace/coverage/default/37.uart_alert_test.1163228806
Short name T701
Test name
Test status
Simulation time 12389287 ps
CPU time 0.59 seconds
Started Aug 03 04:53:53 PM PDT 24
Finished Aug 03 04:53:54 PM PDT 24
Peak memory 195272 kb
Host smart-90dcc096-a584-4943-8af3-4c501d6222a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163228806 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_alert_test.1163228806
Directory /workspace/37.uart_alert_test/latest

Test location /workspace/coverage/default/37.uart_fifo_full.1521870008
Short name T853
Test name
Test status
Simulation time 22128240576 ps
CPU time 32.62 seconds
Started Aug 03 04:53:46 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 199884 kb
Host smart-0f638d72-bcaa-4f8a-9d93-8e50d94cacf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521870008 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_full.1521870008
Directory /workspace/37.uart_fifo_full/latest

Test location /workspace/coverage/default/37.uart_fifo_overflow.4124815581
Short name T1142
Test name
Test status
Simulation time 215907193760 ps
CPU time 360.02 seconds
Started Aug 03 04:53:55 PM PDT 24
Finished Aug 03 04:59:55 PM PDT 24
Peak memory 199888 kb
Host smart-b399dd4b-09dd-40a9-a664-82bb7295f8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124815581 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_overflow.4124815581
Directory /workspace/37.uart_fifo_overflow/latest

Test location /workspace/coverage/default/37.uart_fifo_reset.2555385861
Short name T1121
Test name
Test status
Simulation time 127827511903 ps
CPU time 67.75 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:54:59 PM PDT 24
Peak memory 199920 kb
Host smart-8775e643-1ac5-4c95-bc57-5efe981899f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555385861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_fifo_reset.2555385861
Directory /workspace/37.uart_fifo_reset/latest

Test location /workspace/coverage/default/37.uart_intr.535095407
Short name T398
Test name
Test status
Simulation time 49853116300 ps
CPU time 24.31 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:54:15 PM PDT 24
Peak memory 199852 kb
Host smart-9e3d7e7d-e1dc-4d1f-8ab7-7f8a4c0834c9
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535095407 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_intr.535095407
Directory /workspace/37.uart_intr/latest

Test location /workspace/coverage/default/37.uart_long_xfer_wo_dly.3523387369
Short name T557
Test name
Test status
Simulation time 64478164971 ps
CPU time 92.07 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:55:23 PM PDT 24
Peak memory 199800 kb
Host smart-85690002-74fc-4737-9b52-8d9251f934f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3523387369 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_long_xfer_wo_dly.3523387369
Directory /workspace/37.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/37.uart_loopback.1844480183
Short name T955
Test name
Test status
Simulation time 837103463 ps
CPU time 1.88 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:53:52 PM PDT 24
Peak memory 195992 kb
Host smart-6e65953d-9637-4e0b-8fdd-742d4ee78306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844480183 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_loopback.1844480183
Directory /workspace/37.uart_loopback/latest

Test location /workspace/coverage/default/37.uart_noise_filter.2113403432
Short name T293
Test name
Test status
Simulation time 86347786890 ps
CPU time 254.4 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:58:04 PM PDT 24
Peak memory 200060 kb
Host smart-a4f49d0b-8ea7-45c2-b367-30ed91f9ba24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113403432 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_noise_filter.2113403432
Directory /workspace/37.uart_noise_filter/latest

Test location /workspace/coverage/default/37.uart_rx_oversample.1954185544
Short name T1070
Test name
Test status
Simulation time 2666160763 ps
CPU time 4.4 seconds
Started Aug 03 04:53:52 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 197804 kb
Host smart-6d7cf787-203b-4dad-ab49-9d2a0d1d4291
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1954185544 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_oversample.1954185544
Directory /workspace/37.uart_rx_oversample/latest

Test location /workspace/coverage/default/37.uart_rx_parity_err.2080714527
Short name T753
Test name
Test status
Simulation time 20804310689 ps
CPU time 27.63 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:54:18 PM PDT 24
Peak memory 199788 kb
Host smart-5a0f5465-968f-413c-8545-6c225f22e118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080714527 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_parity_err.2080714527
Directory /workspace/37.uart_rx_parity_err/latest

Test location /workspace/coverage/default/37.uart_rx_start_bit_filter.1777510077
Short name T747
Test name
Test status
Simulation time 37797232002 ps
CPU time 13.37 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:54:04 PM PDT 24
Peak memory 196112 kb
Host smart-c96adad6-16d7-44aa-83cf-9229edb62854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777510077 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_rx_start_bit_filter.1777510077
Directory /workspace/37.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/37.uart_smoke.1232276620
Short name T715
Test name
Test status
Simulation time 943698702 ps
CPU time 2.52 seconds
Started Aug 03 04:53:47 PM PDT 24
Finished Aug 03 04:53:49 PM PDT 24
Peak memory 199552 kb
Host smart-0ecdbcbc-37e7-42b1-8f82-9d6abe192d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232276620 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_smoke.1232276620
Directory /workspace/37.uart_smoke/latest

Test location /workspace/coverage/default/37.uart_stress_all.2150404357
Short name T560
Test name
Test status
Simulation time 144844366032 ps
CPU time 77.82 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:55:09 PM PDT 24
Peak memory 199844 kb
Host smart-0b9f7bfd-f103-43f1-8fac-d79d30ddcc1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150404357 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_stress_all.2150404357
Directory /workspace/37.uart_stress_all/latest

Test location /workspace/coverage/default/37.uart_stress_all_with_rand_reset.2081143992
Short name T967
Test name
Test status
Simulation time 62340077256 ps
CPU time 307.12 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:58:58 PM PDT 24
Peak memory 216584 kb
Host smart-81e76613-81d8-4115-bb55-e994cf955ba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081143992 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 37.uart_stress_all_with_rand_reset.2081143992
Directory /workspace/37.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.uart_tx_ovrd.4140812052
Short name T448
Test name
Test status
Simulation time 2499482877 ps
CPU time 1.36 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:53:52 PM PDT 24
Peak memory 199036 kb
Host smart-298c97fe-0a3f-49e1-90b6-bc7cb1cf99f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140812052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_ovrd.4140812052
Directory /workspace/37.uart_tx_ovrd/latest

Test location /workspace/coverage/default/37.uart_tx_rx.2842722197
Short name T985
Test name
Test status
Simulation time 53051506594 ps
CPU time 28.9 seconds
Started Aug 03 04:53:45 PM PDT 24
Finished Aug 03 04:54:14 PM PDT 24
Peak memory 199924 kb
Host smart-0bae279b-3acb-43f7-9223-d7c18ba5bb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842722197 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.uart_tx_rx.2842722197
Directory /workspace/37.uart_tx_rx/latest

Test location /workspace/coverage/default/38.uart_alert_test.4273551214
Short name T1090
Test name
Test status
Simulation time 38463628 ps
CPU time 0.56 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:04 PM PDT 24
Peak memory 195540 kb
Host smart-132132aa-f896-4394-b8a3-7ede05d455fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273551214 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_alert_test.4273551214
Directory /workspace/38.uart_alert_test/latest

Test location /workspace/coverage/default/38.uart_fifo_full.4290293698
Short name T768
Test name
Test status
Simulation time 186210894295 ps
CPU time 180.73 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:56:52 PM PDT 24
Peak memory 199852 kb
Host smart-d1068041-8149-4e8c-a607-2019003217b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290293698 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_full.4290293698
Directory /workspace/38.uart_fifo_full/latest

Test location /workspace/coverage/default/38.uart_fifo_overflow.2176812667
Short name T305
Test name
Test status
Simulation time 51475144776 ps
CPU time 16.65 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:54:08 PM PDT 24
Peak memory 199868 kb
Host smart-83d58528-87ad-4aa1-8c81-94facae1e413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176812667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_overflow.2176812667
Directory /workspace/38.uart_fifo_overflow/latest

Test location /workspace/coverage/default/38.uart_fifo_reset.841305589
Short name T760
Test name
Test status
Simulation time 22667592201 ps
CPU time 6.19 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 199664 kb
Host smart-d261af01-919a-4de7-b411-acc5c2e7308d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841305589 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_fifo_reset.841305589
Directory /workspace/38.uart_fifo_reset/latest

Test location /workspace/coverage/default/38.uart_intr.2811053934
Short name T266
Test name
Test status
Simulation time 43776973914 ps
CPU time 18.51 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:23 PM PDT 24
Peak memory 199900 kb
Host smart-51c58e6c-e22c-4c95-9f2a-1bca9d4564d3
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811053934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_intr.2811053934
Directory /workspace/38.uart_intr/latest

Test location /workspace/coverage/default/38.uart_long_xfer_wo_dly.3770204130
Short name T645
Test name
Test status
Simulation time 65283999626 ps
CPU time 592.46 seconds
Started Aug 03 04:54:03 PM PDT 24
Finished Aug 03 05:03:55 PM PDT 24
Peak memory 199848 kb
Host smart-fd99ee23-9e6e-4669-91db-0d6733882456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3770204130 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_long_xfer_wo_dly.3770204130
Directory /workspace/38.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/38.uart_loopback.1739310840
Short name T570
Test name
Test status
Simulation time 643717223 ps
CPU time 0.8 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:05 PM PDT 24
Peak memory 195400 kb
Host smart-b61c6eb7-ee26-4ab1-8035-c0bfcd28010b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739310840 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_loopback.1739310840
Directory /workspace/38.uart_loopback/latest

Test location /workspace/coverage/default/38.uart_noise_filter.1618683488
Short name T930
Test name
Test status
Simulation time 64598404378 ps
CPU time 51.9 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:54:48 PM PDT 24
Peak memory 199976 kb
Host smart-e086193a-d530-4c23-a18c-c44bb4146b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618683488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_noise_filter.1618683488
Directory /workspace/38.uart_noise_filter/latest

Test location /workspace/coverage/default/38.uart_perf.41612697
Short name T386
Test name
Test status
Simulation time 20640224117 ps
CPU time 71.13 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:55:07 PM PDT 24
Peak memory 199916 kb
Host smart-ff8f9fa4-55e4-4eb2-84bf-6b805424909b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=41612697 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_perf.41612697
Directory /workspace/38.uart_perf/latest

Test location /workspace/coverage/default/38.uart_rx_oversample.4169043124
Short name T855
Test name
Test status
Simulation time 2129673777 ps
CPU time 3.97 seconds
Started Aug 03 04:53:57 PM PDT 24
Finished Aug 03 04:54:01 PM PDT 24
Peak memory 198196 kb
Host smart-99aa1d80-85cc-463a-83a8-5af0168a8976
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4169043124 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_oversample.4169043124
Directory /workspace/38.uart_rx_oversample/latest

Test location /workspace/coverage/default/38.uart_rx_parity_err.1408187861
Short name T2
Test name
Test status
Simulation time 28978567687 ps
CPU time 41.1 seconds
Started Aug 03 04:54:02 PM PDT 24
Finished Aug 03 04:54:43 PM PDT 24
Peak memory 199876 kb
Host smart-830317aa-84d9-4632-9e10-53a018b90d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408187861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_parity_err.1408187861
Directory /workspace/38.uart_rx_parity_err/latest

Test location /workspace/coverage/default/38.uart_rx_start_bit_filter.375390535
Short name T733
Test name
Test status
Simulation time 3674325157 ps
CPU time 6.41 seconds
Started Aug 03 04:53:58 PM PDT 24
Finished Aug 03 04:54:05 PM PDT 24
Peak memory 196180 kb
Host smart-f37a844e-1e3c-4744-aefe-31bd933bc9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375390535 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_rx_start_bit_filter.375390535
Directory /workspace/38.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/38.uart_smoke.2310228114
Short name T702
Test name
Test status
Simulation time 124050854 ps
CPU time 0.91 seconds
Started Aug 03 04:53:51 PM PDT 24
Finished Aug 03 04:53:52 PM PDT 24
Peak memory 197296 kb
Host smart-1904b98d-fc76-4770-9920-8bd12fe9c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310228114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_smoke.2310228114
Directory /workspace/38.uart_smoke/latest

Test location /workspace/coverage/default/38.uart_stress_all.1734762068
Short name T153
Test name
Test status
Simulation time 410428388543 ps
CPU time 156.98 seconds
Started Aug 03 04:54:01 PM PDT 24
Finished Aug 03 04:56:38 PM PDT 24
Peak memory 199860 kb
Host smart-b432c40d-e863-41db-998d-caccfe6f64cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734762068 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_stress_all.1734762068
Directory /workspace/38.uart_stress_all/latest

Test location /workspace/coverage/default/38.uart_stress_all_with_rand_reset.2715293325
Short name T638
Test name
Test status
Simulation time 100427365447 ps
CPU time 266.96 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:58:23 PM PDT 24
Peak memory 215644 kb
Host smart-f3df575e-9345-47c2-8d7b-1e35b4867497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715293325 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 38.uart_stress_all_with_rand_reset.2715293325
Directory /workspace/38.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.uart_tx_ovrd.2660357791
Short name T646
Test name
Test status
Simulation time 388053689 ps
CPU time 1.96 seconds
Started Aug 03 04:53:57 PM PDT 24
Finished Aug 03 04:53:59 PM PDT 24
Peak memory 197996 kb
Host smart-5fad914b-4521-4a87-863c-0bca6e4c3964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660357791 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_ovrd.2660357791
Directory /workspace/38.uart_tx_ovrd/latest

Test location /workspace/coverage/default/38.uart_tx_rx.2234599536
Short name T1155
Test name
Test status
Simulation time 35414563659 ps
CPU time 14.53 seconds
Started Aug 03 04:53:50 PM PDT 24
Finished Aug 03 04:54:04 PM PDT 24
Peak memory 198212 kb
Host smart-b21e1a18-dd04-4870-b22a-57284ce5069b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234599536 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.uart_tx_rx.2234599536
Directory /workspace/38.uart_tx_rx/latest

Test location /workspace/coverage/default/39.uart_alert_test.1529308576
Short name T424
Test name
Test status
Simulation time 42643718 ps
CPU time 0.54 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:05 PM PDT 24
Peak memory 194544 kb
Host smart-41cdb436-2694-4425-9c09-063dcfd04cd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529308576 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_alert_test.1529308576
Directory /workspace/39.uart_alert_test/latest

Test location /workspace/coverage/default/39.uart_fifo_full.3384642292
Short name T763
Test name
Test status
Simulation time 38001800037 ps
CPU time 56.3 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:55:00 PM PDT 24
Peak memory 199896 kb
Host smart-4039385c-0d65-4d8d-91c1-76be77d207a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384642292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_full.3384642292
Directory /workspace/39.uart_fifo_full/latest

Test location /workspace/coverage/default/39.uart_fifo_overflow.8224040
Short name T490
Test name
Test status
Simulation time 131558783465 ps
CPU time 130.44 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:56:06 PM PDT 24
Peak memory 199844 kb
Host smart-6fccdbca-aad6-4c60-9501-450db95cdd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8224040 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_fifo_overflow.8224040
Directory /workspace/39.uart_fifo_overflow/latest

Test location /workspace/coverage/default/39.uart_intr.1044614587
Short name T786
Test name
Test status
Simulation time 41995654397 ps
CPU time 36.68 seconds
Started Aug 03 04:54:03 PM PDT 24
Finished Aug 03 04:54:39 PM PDT 24
Peak memory 198656 kb
Host smart-7a49f3b2-b0f5-48c0-83b4-d6b52d91b976
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044614587 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_intr.1044614587
Directory /workspace/39.uart_intr/latest

Test location /workspace/coverage/default/39.uart_loopback.2899274424
Short name T1071
Test name
Test status
Simulation time 2265648547 ps
CPU time 3.16 seconds
Started Aug 03 04:54:03 PM PDT 24
Finished Aug 03 04:54:07 PM PDT 24
Peak memory 199112 kb
Host smart-62c53e4f-b7aa-470a-87c3-361c173aff09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899274424 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_loopback.2899274424
Directory /workspace/39.uart_loopback/latest

Test location /workspace/coverage/default/39.uart_noise_filter.148291411
Short name T514
Test name
Test status
Simulation time 131478265918 ps
CPU time 80.74 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:55:17 PM PDT 24
Peak memory 208184 kb
Host smart-d66d98b3-207d-4f6b-bbb2-db4b28882bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148291411 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_noise_filter.148291411
Directory /workspace/39.uart_noise_filter/latest

Test location /workspace/coverage/default/39.uart_perf.2936741188
Short name T463
Test name
Test status
Simulation time 19529705594 ps
CPU time 669.75 seconds
Started Aug 03 04:54:02 PM PDT 24
Finished Aug 03 05:05:12 PM PDT 24
Peak memory 199868 kb
Host smart-c7a95d4e-c6fb-415b-b7ca-4b4e01bda76b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2936741188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_perf.2936741188
Directory /workspace/39.uart_perf/latest

Test location /workspace/coverage/default/39.uart_rx_oversample.1809427823
Short name T1081
Test name
Test status
Simulation time 6972292511 ps
CPU time 16.82 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 198020 kb
Host smart-2aff3c98-a6c0-4c7e-a845-0eee34bcc08f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1809427823 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_oversample.1809427823
Directory /workspace/39.uart_rx_oversample/latest

Test location /workspace/coverage/default/39.uart_rx_parity_err.3109230542
Short name T150
Test name
Test status
Simulation time 78054648736 ps
CPU time 31.04 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:36 PM PDT 24
Peak memory 199708 kb
Host smart-a2163d4d-2c52-4643-beed-d376763bf4a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109230542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_parity_err.3109230542
Directory /workspace/39.uart_rx_parity_err/latest

Test location /workspace/coverage/default/39.uart_rx_start_bit_filter.2257083186
Short name T87
Test name
Test status
Simulation time 28773686954 ps
CPU time 30.29 seconds
Started Aug 03 04:53:57 PM PDT 24
Finished Aug 03 04:54:27 PM PDT 24
Peak memory 195792 kb
Host smart-7f79a972-3138-4dd5-a242-0527b91f826a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257083186 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_rx_start_bit_filter.2257083186
Directory /workspace/39.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/39.uart_smoke.1118905882
Short name T1106
Test name
Test status
Simulation time 655321931 ps
CPU time 1.34 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:06 PM PDT 24
Peak memory 198048 kb
Host smart-80fdbc82-3067-4e42-999a-c5f185710525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118905882 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_smoke.1118905882
Directory /workspace/39.uart_smoke/latest

Test location /workspace/coverage/default/39.uart_stress_all.2039052989
Short name T29
Test name
Test status
Simulation time 131745540524 ps
CPU time 61.25 seconds
Started Aug 03 04:53:55 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 199880 kb
Host smart-48d89868-55fd-4b42-8e89-c27db6b1a7ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039052989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_stress_all.2039052989
Directory /workspace/39.uart_stress_all/latest

Test location /workspace/coverage/default/39.uart_stress_all_with_rand_reset.4092408608
Short name T319
Test name
Test status
Simulation time 71686154592 ps
CPU time 479.63 seconds
Started Aug 03 04:54:02 PM PDT 24
Finished Aug 03 05:02:02 PM PDT 24
Peak memory 216444 kb
Host smart-d572436a-32b0-42b5-97a6-d3bf51005326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092408608 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 39.uart_stress_all_with_rand_reset.4092408608
Directory /workspace/39.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.uart_tx_ovrd.1614217748
Short name T530
Test name
Test status
Simulation time 1274051897 ps
CPU time 1.63 seconds
Started Aug 03 04:53:56 PM PDT 24
Finished Aug 03 04:53:58 PM PDT 24
Peak memory 199780 kb
Host smart-bb092f8f-7767-49ae-9032-e641ee8cc498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614217748 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_ovrd.1614217748
Directory /workspace/39.uart_tx_ovrd/latest

Test location /workspace/coverage/default/39.uart_tx_rx.24429148
Short name T546
Test name
Test status
Simulation time 121507730986 ps
CPU time 87.48 seconds
Started Aug 03 04:53:57 PM PDT 24
Finished Aug 03 04:55:24 PM PDT 24
Peak memory 199844 kb
Host smart-5ed5b1ce-f3b6-4d9c-bf63-221f15867b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24429148 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.uart_tx_rx.24429148
Directory /workspace/39.uart_tx_rx/latest

Test location /workspace/coverage/default/4.uart_alert_test.2100683482
Short name T741
Test name
Test status
Simulation time 19488998 ps
CPU time 0.55 seconds
Started Aug 03 04:51:57 PM PDT 24
Finished Aug 03 04:51:58 PM PDT 24
Peak memory 195568 kb
Host smart-099bab52-4663-4be6-ae5d-82718460b78e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100683482 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_alert_test.2100683482
Directory /workspace/4.uart_alert_test/latest

Test location /workspace/coverage/default/4.uart_fifo_full.1008946771
Short name T1169
Test name
Test status
Simulation time 138751532802 ps
CPU time 68.44 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:52:58 PM PDT 24
Peak memory 199836 kb
Host smart-848daf3c-898a-417b-b900-ec5eba24db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008946771 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_full.1008946771
Directory /workspace/4.uart_fifo_full/latest

Test location /workspace/coverage/default/4.uart_fifo_overflow.2577652209
Short name T361
Test name
Test status
Simulation time 20691025609 ps
CPU time 42.48 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:32 PM PDT 24
Peak memory 199840 kb
Host smart-6b81bced-a7c0-476a-8c12-c8c45b100b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577652209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_overflow.2577652209
Directory /workspace/4.uart_fifo_overflow/latest

Test location /workspace/coverage/default/4.uart_fifo_reset.185704230
Short name T613
Test name
Test status
Simulation time 57268250617 ps
CPU time 89.42 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:53:18 PM PDT 24
Peak memory 199896 kb
Host smart-c8bb8fbd-c219-48f2-b3d5-94b26d174cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185704230 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_fifo_reset.185704230
Directory /workspace/4.uart_fifo_reset/latest

Test location /workspace/coverage/default/4.uart_intr.1009826195
Short name T588
Test name
Test status
Simulation time 203150320144 ps
CPU time 266.21 seconds
Started Aug 03 04:51:48 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 199784 kb
Host smart-cb58436e-b9f3-4820-8600-9fb016a7239c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009826195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_intr.1009826195
Directory /workspace/4.uart_intr/latest

Test location /workspace/coverage/default/4.uart_long_xfer_wo_dly.1290322435
Short name T406
Test name
Test status
Simulation time 46252718729 ps
CPU time 209.01 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:55:22 PM PDT 24
Peak memory 199884 kb
Host smart-72d0bc06-db5f-4803-b5c7-974851fcfef2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1290322435 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_long_xfer_wo_dly.1290322435
Directory /workspace/4.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/4.uart_loopback.3247517877
Short name T861
Test name
Test status
Simulation time 6156010779 ps
CPU time 6.38 seconds
Started Aug 03 04:51:56 PM PDT 24
Finished Aug 03 04:52:02 PM PDT 24
Peak memory 199864 kb
Host smart-237e65c4-1f9f-4037-b874-dc9fb2e7db57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247517877 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_loopback.3247517877
Directory /workspace/4.uart_loopback/latest

Test location /workspace/coverage/default/4.uart_noise_filter.3102652021
Short name T789
Test name
Test status
Simulation time 52314270032 ps
CPU time 20.82 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:52:11 PM PDT 24
Peak memory 197252 kb
Host smart-38d68669-dd92-4914-b708-e221408a7846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102652021 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_noise_filter.3102652021
Directory /workspace/4.uart_noise_filter/latest

Test location /workspace/coverage/default/4.uart_perf.1177883593
Short name T551
Test name
Test status
Simulation time 12355578229 ps
CPU time 630.04 seconds
Started Aug 03 04:51:57 PM PDT 24
Finished Aug 03 05:02:27 PM PDT 24
Peak memory 199904 kb
Host smart-837e2280-3617-411a-b3b6-b5a3f83825ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1177883593 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_perf.1177883593
Directory /workspace/4.uart_perf/latest

Test location /workspace/coverage/default/4.uart_rx_oversample.1178372908
Short name T647
Test name
Test status
Simulation time 4299451944 ps
CPU time 9 seconds
Started Aug 03 04:51:49 PM PDT 24
Finished Aug 03 04:51:59 PM PDT 24
Peak memory 198312 kb
Host smart-df8efbe1-3dae-4661-bf29-9f6a81a9ae04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1178372908 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_oversample.1178372908
Directory /workspace/4.uart_rx_oversample/latest

Test location /workspace/coverage/default/4.uart_rx_parity_err.109439627
Short name T565
Test name
Test status
Simulation time 94535395878 ps
CPU time 72.38 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:53:05 PM PDT 24
Peak memory 199876 kb
Host smart-c4edf85e-2b30-4e35-a560-1d6b583192a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109439627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_parity_err.109439627
Directory /workspace/4.uart_rx_parity_err/latest

Test location /workspace/coverage/default/4.uart_rx_start_bit_filter.2389229673
Short name T487
Test name
Test status
Simulation time 37388162862 ps
CPU time 14.94 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:52:07 PM PDT 24
Peak memory 195888 kb
Host smart-daee2656-3b57-4952-80c6-413baf5f7a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389229673 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_rx_start_bit_filter.2389229673
Directory /workspace/4.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/4.uart_smoke.1192058989
Short name T277
Test name
Test status
Simulation time 607312957 ps
CPU time 2.3 seconds
Started Aug 03 04:51:50 PM PDT 24
Finished Aug 03 04:51:53 PM PDT 24
Peak memory 198588 kb
Host smart-3e854a3e-5edf-49fd-b1d6-19f7491dd595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192058989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_smoke.1192058989
Directory /workspace/4.uart_smoke/latest

Test location /workspace/coverage/default/4.uart_stress_all.2811607627
Short name T1030
Test name
Test status
Simulation time 253434414546 ps
CPU time 1619.82 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 05:18:54 PM PDT 24
Peak memory 199900 kb
Host smart-a69158c6-3bd7-44f1-96c8-bebc2f0deb2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811607627 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_stress_all.2811607627
Directory /workspace/4.uart_stress_all/latest

Test location /workspace/coverage/default/4.uart_tx_ovrd.3521750667
Short name T389
Test name
Test status
Simulation time 2193679261 ps
CPU time 1.89 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:51:54 PM PDT 24
Peak memory 199708 kb
Host smart-816c9ae9-dad0-43ec-a9ad-91e0ae3a7fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521750667 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_ovrd.3521750667
Directory /workspace/4.uart_tx_ovrd/latest

Test location /workspace/coverage/default/4.uart_tx_rx.2502914317
Short name T976
Test name
Test status
Simulation time 26458997879 ps
CPU time 27.84 seconds
Started Aug 03 04:51:47 PM PDT 24
Finished Aug 03 04:52:15 PM PDT 24
Peak memory 199916 kb
Host smart-2e74d3a0-8d85-4386-9a50-d86ed1521b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502914317 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.uart_tx_rx.2502914317
Directory /workspace/4.uart_tx_rx/latest

Test location /workspace/coverage/default/40.uart_alert_test.3855666319
Short name T495
Test name
Test status
Simulation time 19655506 ps
CPU time 0.55 seconds
Started Aug 03 04:54:08 PM PDT 24
Finished Aug 03 04:54:09 PM PDT 24
Peak memory 194104 kb
Host smart-b8dc518a-9a02-45b7-8786-b8f2038b9623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855666319 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_alert_test.3855666319
Directory /workspace/40.uart_alert_test/latest

Test location /workspace/coverage/default/40.uart_fifo_full.3322445990
Short name T1177
Test name
Test status
Simulation time 67425486378 ps
CPU time 27.46 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199596 kb
Host smart-0fc626c8-44c7-485b-b28d-488e77ca1773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322445990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_full.3322445990
Directory /workspace/40.uart_fifo_full/latest

Test location /workspace/coverage/default/40.uart_fifo_overflow.176275122
Short name T996
Test name
Test status
Simulation time 101971326521 ps
CPU time 40.78 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:46 PM PDT 24
Peak memory 199668 kb
Host smart-78b5c34e-17fb-407d-b2db-43f3e688ed7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176275122 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_overflow.176275122
Directory /workspace/40.uart_fifo_overflow/latest

Test location /workspace/coverage/default/40.uart_fifo_reset.1790343249
Short name T726
Test name
Test status
Simulation time 36372232187 ps
CPU time 30.27 seconds
Started Aug 03 04:54:04 PM PDT 24
Finished Aug 03 04:54:35 PM PDT 24
Peak memory 199824 kb
Host smart-edf268d5-c2b1-403a-bd32-cd71ea7694d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790343249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_fifo_reset.1790343249
Directory /workspace/40.uart_fifo_reset/latest

Test location /workspace/coverage/default/40.uart_intr.1886941876
Short name T116
Test name
Test status
Simulation time 29400661984 ps
CPU time 45.56 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:51 PM PDT 24
Peak memory 198824 kb
Host smart-ed8d6a81-6f65-4c5a-b3f5-ab5df7fb676d
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886941876 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_intr.1886941876
Directory /workspace/40.uart_intr/latest

Test location /workspace/coverage/default/40.uart_long_xfer_wo_dly.3833958948
Short name T1093
Test name
Test status
Simulation time 175385942889 ps
CPU time 223.93 seconds
Started Aug 03 04:54:06 PM PDT 24
Finished Aug 03 04:57:50 PM PDT 24
Peak memory 199796 kb
Host smart-bfec040e-bf20-4fdb-87cf-66b7b25e6489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3833958948 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_long_xfer_wo_dly.3833958948
Directory /workspace/40.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/40.uart_loopback.2464914518
Short name T323
Test name
Test status
Simulation time 1405065039 ps
CPU time 3.06 seconds
Started Aug 03 04:54:06 PM PDT 24
Finished Aug 03 04:54:09 PM PDT 24
Peak memory 198192 kb
Host smart-3ddf7807-dbd2-47cc-9687-4b8f84c6e26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464914518 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_loopback.2464914518
Directory /workspace/40.uart_loopback/latest

Test location /workspace/coverage/default/40.uart_noise_filter.1267430557
Short name T1146
Test name
Test status
Simulation time 83063245154 ps
CPU time 135.94 seconds
Started Aug 03 04:54:06 PM PDT 24
Finished Aug 03 04:56:22 PM PDT 24
Peak memory 200056 kb
Host smart-3d20fd6c-51f9-4c77-b141-668a3da50706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267430557 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_noise_filter.1267430557
Directory /workspace/40.uart_noise_filter/latest

Test location /workspace/coverage/default/40.uart_perf.3935582807
Short name T635
Test name
Test status
Simulation time 19329384877 ps
CPU time 69.4 seconds
Started Aug 03 04:54:08 PM PDT 24
Finished Aug 03 04:55:17 PM PDT 24
Peak memory 199696 kb
Host smart-e9cf5774-3403-45bd-a142-3850e895d970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3935582807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_perf.3935582807
Directory /workspace/40.uart_perf/latest

Test location /workspace/coverage/default/40.uart_rx_oversample.3599175562
Short name T658
Test name
Test status
Simulation time 4760741856 ps
CPU time 7.52 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:12 PM PDT 24
Peak memory 198116 kb
Host smart-c6641503-84c0-44f9-916f-5a65366cbdba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599175562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_oversample.3599175562
Directory /workspace/40.uart_rx_oversample/latest

Test location /workspace/coverage/default/40.uart_rx_parity_err.802627781
Short name T1024
Test name
Test status
Simulation time 55554176859 ps
CPU time 81.51 seconds
Started Aug 03 04:54:08 PM PDT 24
Finished Aug 03 04:55:29 PM PDT 24
Peak memory 199812 kb
Host smart-f5a8820d-6d92-482b-80f3-a07f4b83d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802627781 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_parity_err.802627781
Directory /workspace/40.uart_rx_parity_err/latest

Test location /workspace/coverage/default/40.uart_rx_start_bit_filter.1310232222
Short name T849
Test name
Test status
Simulation time 45251142089 ps
CPU time 17.27 seconds
Started Aug 03 04:54:07 PM PDT 24
Finished Aug 03 04:54:24 PM PDT 24
Peak memory 195744 kb
Host smart-10986e85-4725-4c8d-b669-244f3771dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310232222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_rx_start_bit_filter.1310232222
Directory /workspace/40.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/40.uart_smoke.3065412047
Short name T1100
Test name
Test status
Simulation time 6082458585 ps
CPU time 8.26 seconds
Started Aug 03 04:54:06 PM PDT 24
Finished Aug 03 04:54:14 PM PDT 24
Peak memory 199668 kb
Host smart-4c697171-9079-447c-bc31-53bc9532e4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065412047 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_smoke.3065412047
Directory /workspace/40.uart_smoke/latest

Test location /workspace/coverage/default/40.uart_stress_all.150540167
Short name T891
Test name
Test status
Simulation time 286912217788 ps
CPU time 1815.21 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 05:24:20 PM PDT 24
Peak memory 199284 kb
Host smart-64979bed-2a5a-46fe-8052-b68287f0f64d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150540167 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_stress_all.150540167
Directory /workspace/40.uart_stress_all/latest

Test location /workspace/coverage/default/40.uart_stress_all_with_rand_reset.1676476157
Short name T1034
Test name
Test status
Simulation time 14875548938 ps
CPU time 178.92 seconds
Started Aug 03 04:54:03 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 215616 kb
Host smart-2060bd23-d019-4722-9c33-95af82f0b505
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676476157 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 40.uart_stress_all_with_rand_reset.1676476157
Directory /workspace/40.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.uart_tx_ovrd.3042966275
Short name T297
Test name
Test status
Simulation time 1017657157 ps
CPU time 2.98 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:08 PM PDT 24
Peak memory 199584 kb
Host smart-e6a83bd2-6f01-4603-b729-80a1ba906fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042966275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_ovrd.3042966275
Directory /workspace/40.uart_tx_ovrd/latest

Test location /workspace/coverage/default/40.uart_tx_rx.2147743883
Short name T659
Test name
Test status
Simulation time 65628693075 ps
CPU time 26.37 seconds
Started Aug 03 04:53:59 PM PDT 24
Finished Aug 03 04:54:25 PM PDT 24
Peak memory 199856 kb
Host smart-03ca706c-697c-4871-a274-290ab5913588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147743883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.uart_tx_rx.2147743883
Directory /workspace/40.uart_tx_rx/latest

Test location /workspace/coverage/default/41.uart_alert_test.4206871931
Short name T632
Test name
Test status
Simulation time 39460314 ps
CPU time 0.62 seconds
Started Aug 03 04:54:10 PM PDT 24
Finished Aug 03 04:54:10 PM PDT 24
Peak memory 195276 kb
Host smart-c7c211d8-2b2d-467d-90a8-9267a69d80df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206871931 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_alert_test.4206871931
Directory /workspace/41.uart_alert_test/latest

Test location /workspace/coverage/default/41.uart_fifo_full.4046650759
Short name T1158
Test name
Test status
Simulation time 103034949343 ps
CPU time 277.98 seconds
Started Aug 03 04:54:08 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 199812 kb
Host smart-0d5cf6ba-954c-4641-9e5a-d7437021ef54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046650759 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_full.4046650759
Directory /workspace/41.uart_fifo_full/latest

Test location /workspace/coverage/default/41.uart_fifo_overflow.2747419193
Short name T563
Test name
Test status
Simulation time 49994764504 ps
CPU time 44.87 seconds
Started Aug 03 04:54:03 PM PDT 24
Finished Aug 03 04:54:48 PM PDT 24
Peak memory 199836 kb
Host smart-e0590ca6-bde4-4efe-add9-d9f6b6b6b2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747419193 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_overflow.2747419193
Directory /workspace/41.uart_fifo_overflow/latest

Test location /workspace/coverage/default/41.uart_fifo_reset.3137175704
Short name T537
Test name
Test status
Simulation time 27662651131 ps
CPU time 38.09 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:44 PM PDT 24
Peak memory 199772 kb
Host smart-d6e9462b-b906-4363-8e75-bd950306936e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137175704 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_fifo_reset.3137175704
Directory /workspace/41.uart_fifo_reset/latest

Test location /workspace/coverage/default/41.uart_intr.1675067003
Short name T1101
Test name
Test status
Simulation time 38986823707 ps
CPU time 72.57 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:55:24 PM PDT 24
Peak memory 199852 kb
Host smart-7cd0e230-7b0d-40e0-b9d3-5f6b8a2395cc
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675067003 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_intr.1675067003
Directory /workspace/41.uart_intr/latest

Test location /workspace/coverage/default/41.uart_long_xfer_wo_dly.4176931179
Short name T781
Test name
Test status
Simulation time 141063532747 ps
CPU time 263.42 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:58:34 PM PDT 24
Peak memory 199808 kb
Host smart-ec484718-e9b9-4bd0-8ffc-4e40e9026af7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4176931179 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_long_xfer_wo_dly.4176931179
Directory /workspace/41.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/41.uart_loopback.2359427855
Short name T662
Test name
Test status
Simulation time 937040992 ps
CPU time 1.93 seconds
Started Aug 03 04:54:14 PM PDT 24
Finished Aug 03 04:54:16 PM PDT 24
Peak memory 195376 kb
Host smart-e1c28d2c-0cb9-49fe-8bce-72ff8f2c0d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359427855 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_loopback.2359427855
Directory /workspace/41.uart_loopback/latest

Test location /workspace/coverage/default/41.uart_noise_filter.1347559100
Short name T651
Test name
Test status
Simulation time 47015636241 ps
CPU time 74.43 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:55:26 PM PDT 24
Peak memory 199348 kb
Host smart-ba2b49e8-7047-4912-96d6-dad806d58424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347559100 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_noise_filter.1347559100
Directory /workspace/41.uart_noise_filter/latest

Test location /workspace/coverage/default/41.uart_perf.4194545517
Short name T265
Test name
Test status
Simulation time 18708223340 ps
CPU time 316.74 seconds
Started Aug 03 04:54:10 PM PDT 24
Finished Aug 03 04:59:27 PM PDT 24
Peak memory 199916 kb
Host smart-1f39f274-d8a9-4dab-8c68-be30086d9a3e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4194545517 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_perf.4194545517
Directory /workspace/41.uart_perf/latest

Test location /workspace/coverage/default/41.uart_rx_oversample.4226390804
Short name T950
Test name
Test status
Simulation time 1377718964 ps
CPU time 2.56 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:08 PM PDT 24
Peak memory 196856 kb
Host smart-b48a4e66-40b0-4703-b263-a785cdfffac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4226390804 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_oversample.4226390804
Directory /workspace/41.uart_rx_oversample/latest

Test location /workspace/coverage/default/41.uart_rx_parity_err.4165544209
Short name T1133
Test name
Test status
Simulation time 33129252003 ps
CPU time 24.15 seconds
Started Aug 03 04:54:09 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199908 kb
Host smart-39baf708-9e68-4416-837e-8c119eb53224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165544209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_parity_err.4165544209
Directory /workspace/41.uart_rx_parity_err/latest

Test location /workspace/coverage/default/41.uart_rx_start_bit_filter.3821749072
Short name T1172
Test name
Test status
Simulation time 42596812273 ps
CPU time 35.34 seconds
Started Aug 03 04:54:09 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 196184 kb
Host smart-31d7c794-feaf-4c34-aa59-4f52c3514b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821749072 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_rx_start_bit_filter.3821749072
Directory /workspace/41.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/41.uart_smoke.2927424993
Short name T681
Test name
Test status
Simulation time 503302249 ps
CPU time 2.31 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:07 PM PDT 24
Peak memory 198108 kb
Host smart-c6eea7a6-6984-48dc-a666-6a8d5e6c1c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927424993 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_smoke.2927424993
Directory /workspace/41.uart_smoke/latest

Test location /workspace/coverage/default/41.uart_stress_all.1653552867
Short name T940
Test name
Test status
Simulation time 219146493571 ps
CPU time 202.47 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:57:34 PM PDT 24
Peak memory 199920 kb
Host smart-6f88b741-87cb-4780-b444-a35cd5c3f795
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653552867 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_stress_all.1653552867
Directory /workspace/41.uart_stress_all/latest

Test location /workspace/coverage/default/41.uart_tx_ovrd.871468668
Short name T434
Test name
Test status
Simulation time 2225381145 ps
CPU time 2.68 seconds
Started Aug 03 04:54:10 PM PDT 24
Finished Aug 03 04:54:13 PM PDT 24
Peak memory 199928 kb
Host smart-c93cfa8d-7879-4238-a239-70bab6477b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871468668 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_ovrd.871468668
Directory /workspace/41.uart_tx_ovrd/latest

Test location /workspace/coverage/default/41.uart_tx_rx.3900462264
Short name T317
Test name
Test status
Simulation time 11949379777 ps
CPU time 19.44 seconds
Started Aug 03 04:54:05 PM PDT 24
Finished Aug 03 04:54:25 PM PDT 24
Peak memory 197712 kb
Host smart-35f96e0e-dc40-485e-957c-7cfa74c0f4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900462264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.uart_tx_rx.3900462264
Directory /workspace/41.uart_tx_rx/latest

Test location /workspace/coverage/default/42.uart_alert_test.3086924305
Short name T604
Test name
Test status
Simulation time 216244662 ps
CPU time 0.55 seconds
Started Aug 03 04:54:20 PM PDT 24
Finished Aug 03 04:54:20 PM PDT 24
Peak memory 195280 kb
Host smart-e734114d-45e8-4ab3-a432-82d06b99da43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086924305 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_alert_test.3086924305
Directory /workspace/42.uart_alert_test/latest

Test location /workspace/coverage/default/42.uart_fifo_full.3636191172
Short name T992
Test name
Test status
Simulation time 114776805389 ps
CPU time 18.01 seconds
Started Aug 03 04:54:13 PM PDT 24
Finished Aug 03 04:54:31 PM PDT 24
Peak memory 199892 kb
Host smart-9d8bf7b5-6648-49fd-897d-d1f907100c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636191172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_full.3636191172
Directory /workspace/42.uart_fifo_full/latest

Test location /workspace/coverage/default/42.uart_fifo_overflow.427619373
Short name T367
Test name
Test status
Simulation time 116815526291 ps
CPU time 156.91 seconds
Started Aug 03 04:54:14 PM PDT 24
Finished Aug 03 04:56:51 PM PDT 24
Peak memory 199808 kb
Host smart-575cb928-e55f-436f-83e7-18c96154c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427619373 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_overflow.427619373
Directory /workspace/42.uart_fifo_overflow/latest

Test location /workspace/coverage/default/42.uart_fifo_reset.4046159712
Short name T221
Test name
Test status
Simulation time 114071865201 ps
CPU time 75.23 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:55:27 PM PDT 24
Peak memory 199872 kb
Host smart-aa1feaf5-ecf4-4207-a3d2-31adbf46a53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046159712 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_fifo_reset.4046159712
Directory /workspace/42.uart_fifo_reset/latest

Test location /workspace/coverage/default/42.uart_intr.1086697161
Short name T833
Test name
Test status
Simulation time 11920993825 ps
CPU time 6.84 seconds
Started Aug 03 04:54:14 PM PDT 24
Finished Aug 03 04:54:21 PM PDT 24
Peak memory 199612 kb
Host smart-4c7b4ce9-06b3-4e44-ad7d-aca7d4e0e303
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086697161 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_intr.1086697161
Directory /workspace/42.uart_intr/latest

Test location /workspace/coverage/default/42.uart_long_xfer_wo_dly.1965865222
Short name T257
Test name
Test status
Simulation time 112607892555 ps
CPU time 270.82 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:58:47 PM PDT 24
Peak memory 199944 kb
Host smart-0ff522f9-b9d7-47bd-b7a1-cf7851be028d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1965865222 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_long_xfer_wo_dly.1965865222
Directory /workspace/42.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/42.uart_loopback.3705188300
Short name T579
Test name
Test status
Simulation time 841956403 ps
CPU time 1.99 seconds
Started Aug 03 04:54:15 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 196848 kb
Host smart-285b6842-f8e8-4062-94a9-a3774a7fc78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705188300 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_loopback.3705188300
Directory /workspace/42.uart_loopback/latest

Test location /workspace/coverage/default/42.uart_noise_filter.1767116542
Short name T835
Test name
Test status
Simulation time 343723536682 ps
CPU time 80.61 seconds
Started Aug 03 04:54:09 PM PDT 24
Finished Aug 03 04:55:30 PM PDT 24
Peak memory 208184 kb
Host smart-a711f2f8-42d7-4dff-a604-4cc0fbab0c2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767116542 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_noise_filter.1767116542
Directory /workspace/42.uart_noise_filter/latest

Test location /workspace/coverage/default/42.uart_rx_oversample.153329042
Short name T744
Test name
Test status
Simulation time 3994869259 ps
CPU time 9.22 seconds
Started Aug 03 04:54:09 PM PDT 24
Finished Aug 03 04:54:18 PM PDT 24
Peak memory 197768 kb
Host smart-8844e119-13c6-4a0c-8fa0-dbb6e615edbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=153329042 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_oversample.153329042
Directory /workspace/42.uart_rx_oversample/latest

Test location /workspace/coverage/default/42.uart_rx_parity_err.2507576741
Short name T469
Test name
Test status
Simulation time 66704735340 ps
CPU time 98.79 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:55:55 PM PDT 24
Peak memory 199892 kb
Host smart-152e25b3-461a-4bdd-ac15-eeee55fb7fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507576741 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_parity_err.2507576741
Directory /workspace/42.uart_rx_parity_err/latest

Test location /workspace/coverage/default/42.uart_rx_start_bit_filter.1464299093
Short name T408
Test name
Test status
Simulation time 768695000 ps
CPU time 1.29 seconds
Started Aug 03 04:54:10 PM PDT 24
Finished Aug 03 04:54:12 PM PDT 24
Peak memory 195384 kb
Host smart-91d73765-e9ac-4b76-a4b3-30ed24f3b6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464299093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_rx_start_bit_filter.1464299093
Directory /workspace/42.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/42.uart_smoke.3340001240
Short name T737
Test name
Test status
Simulation time 6064801779 ps
CPU time 17.82 seconds
Started Aug 03 04:54:11 PM PDT 24
Finished Aug 03 04:54:29 PM PDT 24
Peak memory 199700 kb
Host smart-ca1aef8a-2753-40db-8772-ba3668d02244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340001240 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_smoke.3340001240
Directory /workspace/42.uart_smoke/latest

Test location /workspace/coverage/default/42.uart_stress_all.1526176052
Short name T883
Test name
Test status
Simulation time 168165492576 ps
CPU time 804.84 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 05:07:41 PM PDT 24
Peak memory 208172 kb
Host smart-efa7f193-a258-4fda-9b92-ad53ee66d13e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526176052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_stress_all.1526176052
Directory /workspace/42.uart_stress_all/latest

Test location /workspace/coverage/default/42.uart_stress_all_with_rand_reset.841741411
Short name T1141
Test name
Test status
Simulation time 38488574099 ps
CPU time 363.07 seconds
Started Aug 03 04:54:21 PM PDT 24
Finished Aug 03 05:00:24 PM PDT 24
Peak memory 215676 kb
Host smart-993efa0b-a265-4799-979e-6363c52c3628
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841741411 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 42.uart_stress_all_with_rand_reset.841741411
Directory /workspace/42.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.uart_tx_ovrd.1211659474
Short name T1006
Test name
Test status
Simulation time 814934537 ps
CPU time 1.44 seconds
Started Aug 03 04:54:15 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 198324 kb
Host smart-d849457a-fd2c-4307-99e3-9646ff6e2583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211659474 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.uart_tx_ovrd.1211659474
Directory /workspace/42.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_alert_test.2145512282
Short name T447
Test name
Test status
Simulation time 42438916 ps
CPU time 0.54 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:54:24 PM PDT 24
Peak memory 195300 kb
Host smart-99df1fb1-6329-4a3f-ad96-6a832bb32956
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145512282 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_alert_test.2145512282
Directory /workspace/43.uart_alert_test/latest

Test location /workspace/coverage/default/43.uart_fifo_full.3263566961
Short name T642
Test name
Test status
Simulation time 80649626950 ps
CPU time 36.79 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:54:53 PM PDT 24
Peak memory 199804 kb
Host smart-475f95b4-70b9-4095-af02-0ff8ebe95087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263566961 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_full.3263566961
Directory /workspace/43.uart_fifo_full/latest

Test location /workspace/coverage/default/43.uart_fifo_overflow.4166362600
Short name T622
Test name
Test status
Simulation time 112770719121 ps
CPU time 162.02 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:56:58 PM PDT 24
Peak memory 199936 kb
Host smart-4b70ee99-8ea2-419f-9bc5-2c78ebbd1a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166362600 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_overflow.4166362600
Directory /workspace/43.uart_fifo_overflow/latest

Test location /workspace/coverage/default/43.uart_fifo_reset.3186329808
Short name T199
Test name
Test status
Simulation time 9064045395 ps
CPU time 14.01 seconds
Started Aug 03 04:54:21 PM PDT 24
Finished Aug 03 04:54:35 PM PDT 24
Peak memory 198468 kb
Host smart-de2d0678-79f5-4ab8-bef0-12127b115985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186329808 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_fifo_reset.3186329808
Directory /workspace/43.uart_fifo_reset/latest

Test location /workspace/coverage/default/43.uart_intr.1957227280
Short name T1020
Test name
Test status
Simulation time 404555666045 ps
CPU time 665.26 seconds
Started Aug 03 04:54:18 PM PDT 24
Finished Aug 03 05:05:23 PM PDT 24
Peak memory 199516 kb
Host smart-ca8fd072-f317-42f0-bdce-c2bab0ab2e55
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957227280 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_intr.1957227280
Directory /workspace/43.uart_intr/latest

Test location /workspace/coverage/default/43.uart_long_xfer_wo_dly.3050562898
Short name T244
Test name
Test status
Simulation time 71496859182 ps
CPU time 131.62 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:56:35 PM PDT 24
Peak memory 199828 kb
Host smart-d9ea0d9d-00f1-4d43-9bdd-35a5e2ddb47a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050562898 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_long_xfer_wo_dly.3050562898
Directory /workspace/43.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/43.uart_loopback.290271824
Short name T846
Test name
Test status
Simulation time 10004768271 ps
CPU time 26.24 seconds
Started Aug 03 04:54:21 PM PDT 24
Finished Aug 03 04:54:47 PM PDT 24
Peak memory 199920 kb
Host smart-7cf044ab-3870-4d56-8b08-afe0f963a54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290271824 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_loopback.290271824
Directory /workspace/43.uart_loopback/latest

Test location /workspace/coverage/default/43.uart_noise_filter.647823689
Short name T428
Test name
Test status
Simulation time 25500670119 ps
CPU time 38.43 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:54:54 PM PDT 24
Peak memory 200000 kb
Host smart-59c659cd-faa9-4eea-9e16-e93717efac14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647823689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_noise_filter.647823689
Directory /workspace/43.uart_noise_filter/latest

Test location /workspace/coverage/default/43.uart_perf.4209238648
Short name T650
Test name
Test status
Simulation time 24951693677 ps
CPU time 386.37 seconds
Started Aug 03 04:54:20 PM PDT 24
Finished Aug 03 05:00:46 PM PDT 24
Peak memory 199904 kb
Host smart-9c612e4e-cfaf-448a-9c63-6a7fb9c2eaf4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4209238648 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_perf.4209238648
Directory /workspace/43.uart_perf/latest

Test location /workspace/coverage/default/43.uart_rx_oversample.3818392937
Short name T893
Test name
Test status
Simulation time 1815412322 ps
CPU time 2.89 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 198008 kb
Host smart-4832d80b-64dd-4ed4-9590-5adbab693d93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3818392937 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_oversample.3818392937
Directory /workspace/43.uart_rx_oversample/latest

Test location /workspace/coverage/default/43.uart_rx_parity_err.1373599790
Short name T936
Test name
Test status
Simulation time 17646510283 ps
CPU time 24.55 seconds
Started Aug 03 04:54:17 PM PDT 24
Finished Aug 03 04:54:41 PM PDT 24
Peak memory 199908 kb
Host smart-8eeefa4a-4a75-422e-adc4-1541f1938469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373599790 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_parity_err.1373599790
Directory /workspace/43.uart_rx_parity_err/latest

Test location /workspace/coverage/default/43.uart_rx_start_bit_filter.3824871978
Short name T9
Test name
Test status
Simulation time 39681036025 ps
CPU time 9.15 seconds
Started Aug 03 04:54:18 PM PDT 24
Finished Aug 03 04:54:28 PM PDT 24
Peak memory 196432 kb
Host smart-e95e8dea-aac5-4cfc-9ad3-77a0b7f9c044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824871978 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_rx_start_bit_filter.3824871978
Directory /workspace/43.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/43.uart_smoke.1319129828
Short name T620
Test name
Test status
Simulation time 512189771 ps
CPU time 2.24 seconds
Started Aug 03 04:54:16 PM PDT 24
Finished Aug 03 04:54:19 PM PDT 24
Peak memory 199492 kb
Host smart-d27c4109-665a-491b-905c-f1b6bd2da482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319129828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_smoke.1319129828
Directory /workspace/43.uart_smoke/latest

Test location /workspace/coverage/default/43.uart_stress_all.1872168445
Short name T269
Test name
Test status
Simulation time 316629695806 ps
CPU time 357.63 seconds
Started Aug 03 04:54:25 PM PDT 24
Finished Aug 03 05:00:23 PM PDT 24
Peak memory 199868 kb
Host smart-bea86dfc-34fc-40b6-9980-f9822b20aff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872168445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_stress_all.1872168445
Directory /workspace/43.uart_stress_all/latest

Test location /workspace/coverage/default/43.uart_stress_all_with_rand_reset.2072459976
Short name T706
Test name
Test status
Simulation time 7722045301 ps
CPU time 33.83 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 215736 kb
Host smart-4de3a1ab-901e-443c-856e-3ec2016281d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072459976 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 43.uart_stress_all_with_rand_reset.2072459976
Directory /workspace/43.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.uart_tx_ovrd.3309730198
Short name T953
Test name
Test status
Simulation time 843160604 ps
CPU time 2.89 seconds
Started Aug 03 04:54:20 PM PDT 24
Finished Aug 03 04:54:23 PM PDT 24
Peak memory 198760 kb
Host smart-191a3901-5548-43a9-ac49-a09c54de7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309730198 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_ovrd.3309730198
Directory /workspace/43.uart_tx_ovrd/latest

Test location /workspace/coverage/default/43.uart_tx_rx.2537363540
Short name T600
Test name
Test status
Simulation time 54360668998 ps
CPU time 42.08 seconds
Started Aug 03 04:54:20 PM PDT 24
Finished Aug 03 04:55:02 PM PDT 24
Peak memory 199924 kb
Host smart-745d58fa-e262-482f-8b4a-11b2c2afc7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537363540 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.uart_tx_rx.2537363540
Directory /workspace/43.uart_tx_rx/latest

Test location /workspace/coverage/default/44.uart_alert_test.2551749076
Short name T538
Test name
Test status
Simulation time 33437961 ps
CPU time 0.55 seconds
Started Aug 03 04:54:25 PM PDT 24
Finished Aug 03 04:54:25 PM PDT 24
Peak memory 195764 kb
Host smart-6dc56922-9039-46d5-a7be-31382c9d0039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551749076 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_alert_test.2551749076
Directory /workspace/44.uart_alert_test/latest

Test location /workspace/coverage/default/44.uart_fifo_full.1895005328
Short name T1085
Test name
Test status
Simulation time 122224145006 ps
CPU time 12.42 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:54:36 PM PDT 24
Peak memory 199800 kb
Host smart-6902649f-03c4-4803-b76b-78f60388b588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895005328 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_full.1895005328
Directory /workspace/44.uart_fifo_full/latest

Test location /workspace/coverage/default/44.uart_fifo_overflow.3287273396
Short name T730
Test name
Test status
Simulation time 39940269877 ps
CPU time 19.63 seconds
Started Aug 03 04:54:25 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 199924 kb
Host smart-312ec69c-f6e8-454d-8baf-d8ee1b0d0331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287273396 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_overflow.3287273396
Directory /workspace/44.uart_fifo_overflow/latest

Test location /workspace/coverage/default/44.uart_fifo_reset.742120438
Short name T693
Test name
Test status
Simulation time 123254571849 ps
CPU time 182.99 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:57:26 PM PDT 24
Peak memory 199920 kb
Host smart-cc42a94f-569d-4e9f-906b-28fcf8a5fad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742120438 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_fifo_reset.742120438
Directory /workspace/44.uart_fifo_reset/latest

Test location /workspace/coverage/default/44.uart_intr.4095136195
Short name T461
Test name
Test status
Simulation time 57428066762 ps
CPU time 9.11 seconds
Started Aug 03 04:54:25 PM PDT 24
Finished Aug 03 04:54:34 PM PDT 24
Peak memory 199876 kb
Host smart-998ce391-efc3-43a5-93e6-94ad6db722fa
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095136195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_intr.4095136195
Directory /workspace/44.uart_intr/latest

Test location /workspace/coverage/default/44.uart_long_xfer_wo_dly.58578110
Short name T273
Test name
Test status
Simulation time 237374165095 ps
CPU time 456.07 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 05:01:59 PM PDT 24
Peak memory 199872 kb
Host smart-235399e0-4136-4cba-8e66-34df83f8b9e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58578110 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_long_xfer_wo_dly.58578110
Directory /workspace/44.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/44.uart_loopback.1368761127
Short name T526
Test name
Test status
Simulation time 3559821230 ps
CPU time 4.11 seconds
Started Aug 03 04:54:26 PM PDT 24
Finished Aug 03 04:54:30 PM PDT 24
Peak memory 198772 kb
Host smart-f527c186-71b7-49a2-853f-6800650fc3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368761127 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_loopback.1368761127
Directory /workspace/44.uart_loopback/latest

Test location /workspace/coverage/default/44.uart_noise_filter.367785024
Short name T41
Test name
Test status
Simulation time 231464926491 ps
CPU time 102.91 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:56:06 PM PDT 24
Peak memory 200056 kb
Host smart-3c7264d2-6760-4471-9f34-46b609f3c6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367785024 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_noise_filter.367785024
Directory /workspace/44.uart_noise_filter/latest

Test location /workspace/coverage/default/44.uart_perf.2999302638
Short name T1143
Test name
Test status
Simulation time 20424778872 ps
CPU time 254.48 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:58:37 PM PDT 24
Peak memory 199924 kb
Host smart-b7c4cad3-f170-4ca4-abf9-09a6993c1600
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999302638 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_perf.2999302638
Directory /workspace/44.uart_perf/latest

Test location /workspace/coverage/default/44.uart_rx_oversample.3486280349
Short name T626
Test name
Test status
Simulation time 7582008335 ps
CPU time 8.71 seconds
Started Aug 03 04:54:24 PM PDT 24
Finished Aug 03 04:54:32 PM PDT 24
Peak memory 197976 kb
Host smart-fafe3336-5fcf-4278-b25a-9a3e4e435a70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3486280349 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_oversample.3486280349
Directory /workspace/44.uart_rx_oversample/latest

Test location /workspace/coverage/default/44.uart_rx_parity_err.4231085677
Short name T497
Test name
Test status
Simulation time 112482696869 ps
CPU time 10.79 seconds
Started Aug 03 04:54:26 PM PDT 24
Finished Aug 03 04:54:37 PM PDT 24
Peak memory 199004 kb
Host smart-fc8e4d2f-ea84-44ac-b7a4-8fb536e99ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231085677 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_parity_err.4231085677
Directory /workspace/44.uart_rx_parity_err/latest

Test location /workspace/coverage/default/44.uart_rx_start_bit_filter.2597563341
Short name T865
Test name
Test status
Simulation time 36941301821 ps
CPU time 14.88 seconds
Started Aug 03 04:54:22 PM PDT 24
Finished Aug 03 04:54:37 PM PDT 24
Peak memory 195716 kb
Host smart-fd8bbdfd-deb6-4263-9ba2-c64c232cd830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597563341 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_rx_start_bit_filter.2597563341
Directory /workspace/44.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/44.uart_smoke.953049278
Short name T966
Test name
Test status
Simulation time 521006970 ps
CPU time 1.51 seconds
Started Aug 03 04:54:24 PM PDT 24
Finished Aug 03 04:54:26 PM PDT 24
Peak memory 198572 kb
Host smart-211b069d-356a-40f6-ace8-fa1e4bd15b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953049278 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_smoke.953049278
Directory /workspace/44.uart_smoke/latest

Test location /workspace/coverage/default/44.uart_stress_all.1900006439
Short name T158
Test name
Test status
Simulation time 233187804051 ps
CPU time 514.07 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 05:02:58 PM PDT 24
Peak memory 200036 kb
Host smart-cfcfef17-1596-40bd-ac96-748c6d76b8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900006439 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_stress_all.1900006439
Directory /workspace/44.uart_stress_all/latest

Test location /workspace/coverage/default/44.uart_stress_all_with_rand_reset.976429492
Short name T925
Test name
Test status
Simulation time 14116940276 ps
CPU time 120.01 seconds
Started Aug 03 04:54:24 PM PDT 24
Finished Aug 03 04:56:24 PM PDT 24
Peak memory 215492 kb
Host smart-4c01f50b-7af9-4bbd-956b-ba9a044c7159
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976429492 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 44.uart_stress_all_with_rand_reset.976429492
Directory /workspace/44.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.uart_tx_ovrd.1056260281
Short name T496
Test name
Test status
Simulation time 7690671401 ps
CPU time 9.59 seconds
Started Aug 03 04:54:23 PM PDT 24
Finished Aug 03 04:54:32 PM PDT 24
Peak memory 199916 kb
Host smart-33880a39-62b6-4972-b5a2-af9644fe2527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056260281 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_ovrd.1056260281
Directory /workspace/44.uart_tx_ovrd/latest

Test location /workspace/coverage/default/44.uart_tx_rx.169211444
Short name T791
Test name
Test status
Simulation time 31298511439 ps
CPU time 22.43 seconds
Started Aug 03 04:54:27 PM PDT 24
Finished Aug 03 04:54:49 PM PDT 24
Peak memory 199708 kb
Host smart-08f256b7-334d-4e1b-90db-0170b9ec688c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169211444 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.uart_tx_rx.169211444
Directory /workspace/44.uart_tx_rx/latest

Test location /workspace/coverage/default/45.uart_alert_test.544218601
Short name T7
Test name
Test status
Simulation time 64259372 ps
CPU time 0.59 seconds
Started Aug 03 04:54:39 PM PDT 24
Finished Aug 03 04:54:40 PM PDT 24
Peak memory 195300 kb
Host smart-981eac65-a9fd-4194-8650-f4bdcf046997
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544218601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_alert_test.544218601
Directory /workspace/45.uart_alert_test/latest

Test location /workspace/coverage/default/45.uart_fifo_full.2079372258
Short name T462
Test name
Test status
Simulation time 156753028493 ps
CPU time 40.48 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:55:09 PM PDT 24
Peak memory 199832 kb
Host smart-773725c4-9858-4214-b1f9-865e88b95c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079372258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_full.2079372258
Directory /workspace/45.uart_fifo_full/latest

Test location /workspace/coverage/default/45.uart_fifo_reset.1200295111
Short name T90
Test name
Test status
Simulation time 47742715175 ps
CPU time 67.76 seconds
Started Aug 03 04:54:30 PM PDT 24
Finished Aug 03 04:55:37 PM PDT 24
Peak memory 199816 kb
Host smart-87fad562-cb44-4eb5-9706-eac14837ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200295111 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_fifo_reset.1200295111
Directory /workspace/45.uart_fifo_reset/latest

Test location /workspace/coverage/default/45.uart_intr.839378822
Short name T550
Test name
Test status
Simulation time 24268539218 ps
CPU time 19.89 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:54:49 PM PDT 24
Peak memory 199572 kb
Host smart-56dcada5-a1a4-4321-bcbf-f1130fa00f1f
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839378822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_intr.839378822
Directory /workspace/45.uart_intr/latest

Test location /workspace/coverage/default/45.uart_long_xfer_wo_dly.253392137
Short name T253
Test name
Test status
Simulation time 94205613921 ps
CPU time 110.59 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:56:20 PM PDT 24
Peak memory 199912 kb
Host smart-00c7b6b5-a6bc-4f84-bdba-5459242009e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=253392137 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_long_xfer_wo_dly.253392137
Directory /workspace/45.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/45.uart_loopback.1996856363
Short name T501
Test name
Test status
Simulation time 9675385167 ps
CPU time 35.77 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:55:05 PM PDT 24
Peak memory 199884 kb
Host smart-f7b3c8c8-ddde-4e71-af1e-3ccc2f6236a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996856363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_loopback.1996856363
Directory /workspace/45.uart_loopback/latest

Test location /workspace/coverage/default/45.uart_noise_filter.1327157601
Short name T606
Test name
Test status
Simulation time 262378225525 ps
CPU time 60.34 seconds
Started Aug 03 04:54:31 PM PDT 24
Finished Aug 03 04:55:31 PM PDT 24
Peak memory 199992 kb
Host smart-39970d8a-cf1f-4280-b711-5c02ae9c354c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327157601 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_noise_filter.1327157601
Directory /workspace/45.uart_noise_filter/latest

Test location /workspace/coverage/default/45.uart_perf.1992149397
Short name T931
Test name
Test status
Simulation time 15937977272 ps
CPU time 408.16 seconds
Started Aug 03 04:54:28 PM PDT 24
Finished Aug 03 05:01:16 PM PDT 24
Peak memory 199900 kb
Host smart-f9f1adcc-22fe-415f-91c0-060ba832d4f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1992149397 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_perf.1992149397
Directory /workspace/45.uart_perf/latest

Test location /workspace/coverage/default/45.uart_rx_oversample.1603586145
Short name T656
Test name
Test status
Simulation time 1610026505 ps
CPU time 2.16 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:54:31 PM PDT 24
Peak memory 197812 kb
Host smart-92030e81-9449-4ffc-a571-4d126cd19567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1603586145 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_oversample.1603586145
Directory /workspace/45.uart_rx_oversample/latest

Test location /workspace/coverage/default/45.uart_rx_parity_err.3386987172
Short name T15
Test name
Test status
Simulation time 121581199969 ps
CPU time 35.98 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 04:55:05 PM PDT 24
Peak memory 199864 kb
Host smart-c9db8090-f06d-4d7b-89b4-6e84e070c5e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386987172 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_parity_err.3386987172
Directory /workspace/45.uart_rx_parity_err/latest

Test location /workspace/coverage/default/45.uart_rx_start_bit_filter.2904157363
Short name T751
Test name
Test status
Simulation time 3258976397 ps
CPU time 0.96 seconds
Started Aug 03 04:54:30 PM PDT 24
Finished Aug 03 04:54:31 PM PDT 24
Peak memory 196404 kb
Host smart-768a383f-94de-495d-bb37-0529e34a0ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904157363 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_rx_start_bit_filter.2904157363
Directory /workspace/45.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/45.uart_smoke.3502936862
Short name T264
Test name
Test status
Simulation time 11591358806 ps
CPU time 17.97 seconds
Started Aug 03 04:54:31 PM PDT 24
Finished Aug 03 04:54:49 PM PDT 24
Peak memory 199612 kb
Host smart-432288d8-7c20-401d-a8ae-cfd5e708d659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502936862 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_smoke.3502936862
Directory /workspace/45.uart_smoke/latest

Test location /workspace/coverage/default/45.uart_stress_all.92582323
Short name T435
Test name
Test status
Simulation time 141416469692 ps
CPU time 386.04 seconds
Started Aug 03 04:54:35 PM PDT 24
Finished Aug 03 05:01:01 PM PDT 24
Peak memory 208432 kb
Host smart-796c50ef-2e7c-4cd6-b93b-ef8dad41d0de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92582323 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_stress_all.92582323
Directory /workspace/45.uart_stress_all/latest

Test location /workspace/coverage/default/45.uart_stress_all_with_rand_reset.2910979522
Short name T45
Test name
Test status
Simulation time 90818147199 ps
CPU time 1239.6 seconds
Started Aug 03 04:54:29 PM PDT 24
Finished Aug 03 05:15:08 PM PDT 24
Peak memory 216596 kb
Host smart-f695916e-cfd5-4d25-9122-bc043e1b898e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910979522 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 45.uart_stress_all_with_rand_reset.2910979522
Directory /workspace/45.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.uart_tx_ovrd.2510216188
Short name T618
Test name
Test status
Simulation time 1461148132 ps
CPU time 1.85 seconds
Started Aug 03 04:54:28 PM PDT 24
Finished Aug 03 04:54:30 PM PDT 24
Peak memory 198232 kb
Host smart-27b98f02-bbc3-4e50-b6b5-c1d8aee94855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510216188 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_ovrd.2510216188
Directory /workspace/45.uart_tx_ovrd/latest

Test location /workspace/coverage/default/45.uart_tx_rx.1954140742
Short name T1178
Test name
Test status
Simulation time 23354299808 ps
CPU time 26.56 seconds
Started Aug 03 04:54:30 PM PDT 24
Finished Aug 03 04:54:56 PM PDT 24
Peak memory 199936 kb
Host smart-9643eb39-2beb-4193-9c76-a90d3784d976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954140742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.uart_tx_rx.1954140742
Directory /workspace/45.uart_tx_rx/latest

Test location /workspace/coverage/default/46.uart_alert_test.193106861
Short name T660
Test name
Test status
Simulation time 21525281 ps
CPU time 0.54 seconds
Started Aug 03 04:54:49 PM PDT 24
Finished Aug 03 04:54:50 PM PDT 24
Peak memory 195256 kb
Host smart-1a502a25-290e-451e-af0a-c20f07c6c5be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193106861 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_alert_test.193106861
Directory /workspace/46.uart_alert_test/latest

Test location /workspace/coverage/default/46.uart_fifo_full.2074624052
Short name T731
Test name
Test status
Simulation time 26350700837 ps
CPU time 48.38 seconds
Started Aug 03 04:54:35 PM PDT 24
Finished Aug 03 04:55:24 PM PDT 24
Peak memory 199884 kb
Host smart-559115b6-d2f4-46de-8fe7-4cfe5ebe59ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074624052 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_full.2074624052
Directory /workspace/46.uart_fifo_full/latest

Test location /workspace/coverage/default/46.uart_fifo_overflow.886060773
Short name T1111
Test name
Test status
Simulation time 125306702672 ps
CPU time 172.77 seconds
Started Aug 03 04:54:37 PM PDT 24
Finished Aug 03 04:57:30 PM PDT 24
Peak memory 199668 kb
Host smart-edda1038-a726-496d-b360-cd4579b87aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886060773 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_overflow.886060773
Directory /workspace/46.uart_fifo_overflow/latest

Test location /workspace/coverage/default/46.uart_fifo_reset.2777066942
Short name T714
Test name
Test status
Simulation time 263582226293 ps
CPU time 99.18 seconds
Started Aug 03 04:54:38 PM PDT 24
Finished Aug 03 04:56:17 PM PDT 24
Peak memory 199768 kb
Host smart-feb3db62-d7c5-40c1-b997-478c23aed240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777066942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_fifo_reset.2777066942
Directory /workspace/46.uart_fifo_reset/latest

Test location /workspace/coverage/default/46.uart_intr.3895666624
Short name T421
Test name
Test status
Simulation time 155411238807 ps
CPU time 97.96 seconds
Started Aug 03 04:54:35 PM PDT 24
Finished Aug 03 04:56:13 PM PDT 24
Peak memory 199832 kb
Host smart-0681942d-3db3-4559-bf99-539c33178027
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895666624 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_intr.3895666624
Directory /workspace/46.uart_intr/latest

Test location /workspace/coverage/default/46.uart_long_xfer_wo_dly.4197167356
Short name T1032
Test name
Test status
Simulation time 92575744680 ps
CPU time 325.46 seconds
Started Aug 03 04:54:47 PM PDT 24
Finished Aug 03 05:00:12 PM PDT 24
Peak memory 199928 kb
Host smart-055fa4d3-ddde-40d4-b3c3-45903f6ec75a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4197167356 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_long_xfer_wo_dly.4197167356
Directory /workspace/46.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/46.uart_loopback.2152617989
Short name T1138
Test name
Test status
Simulation time 12323470679 ps
CPU time 7.07 seconds
Started Aug 03 04:54:37 PM PDT 24
Finished Aug 03 04:54:44 PM PDT 24
Peak memory 199704 kb
Host smart-f229f50e-6b8c-4d85-9929-c15e0874a73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152617989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_loopback.2152617989
Directory /workspace/46.uart_loopback/latest

Test location /workspace/coverage/default/46.uart_noise_filter.4107789637
Short name T446
Test name
Test status
Simulation time 198395842199 ps
CPU time 57.02 seconds
Started Aug 03 04:54:37 PM PDT 24
Finished Aug 03 04:55:35 PM PDT 24
Peak memory 199964 kb
Host smart-1a6743cc-f2f0-426a-9630-381f9de702fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107789637 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_noise_filter.4107789637
Directory /workspace/46.uart_noise_filter/latest

Test location /workspace/coverage/default/46.uart_perf.1598534428
Short name T765
Test name
Test status
Simulation time 32758992737 ps
CPU time 511.45 seconds
Started Aug 03 04:54:36 PM PDT 24
Finished Aug 03 05:03:08 PM PDT 24
Peak memory 199916 kb
Host smart-559fcecd-c589-4659-9be2-3e9c3a3fec32
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598534428 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_perf.1598534428
Directory /workspace/46.uart_perf/latest

Test location /workspace/coverage/default/46.uart_rx_oversample.3412915121
Short name T353
Test name
Test status
Simulation time 7272779043 ps
CPU time 8.95 seconds
Started Aug 03 04:54:36 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 198880 kb
Host smart-7cc3f351-9992-4ce5-84f7-915923ce410f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3412915121 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_oversample.3412915121
Directory /workspace/46.uart_rx_oversample/latest

Test location /workspace/coverage/default/46.uart_rx_parity_err.1531993415
Short name T458
Test name
Test status
Simulation time 226363329823 ps
CPU time 368.39 seconds
Started Aug 03 04:54:36 PM PDT 24
Finished Aug 03 05:00:44 PM PDT 24
Peak memory 199892 kb
Host smart-e50fe967-ad0e-437d-bd84-f6df3713350e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531993415 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_parity_err.1531993415
Directory /workspace/46.uart_rx_parity_err/latest

Test location /workspace/coverage/default/46.uart_rx_start_bit_filter.193576703
Short name T689
Test name
Test status
Simulation time 1215764761 ps
CPU time 1.11 seconds
Started Aug 03 04:54:34 PM PDT 24
Finished Aug 03 04:54:36 PM PDT 24
Peak memory 195560 kb
Host smart-f62399a5-c934-4201-a791-770fce782e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193576703 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_rx_start_bit_filter.193576703
Directory /workspace/46.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/46.uart_smoke.294546436
Short name T378
Test name
Test status
Simulation time 247620645 ps
CPU time 1.4 seconds
Started Aug 03 04:54:36 PM PDT 24
Finished Aug 03 04:54:38 PM PDT 24
Peak memory 198112 kb
Host smart-8475533e-f62d-4f14-8704-89ccb8aa4b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294546436 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_smoke.294546436
Directory /workspace/46.uart_smoke/latest

Test location /workspace/coverage/default/46.uart_stress_all.2431079828
Short name T507
Test name
Test status
Simulation time 107291903952 ps
CPU time 200.78 seconds
Started Aug 03 04:54:46 PM PDT 24
Finished Aug 03 04:58:07 PM PDT 24
Peak memory 199812 kb
Host smart-89e868fa-0c1b-4d85-ae64-9c678aeb03df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431079828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_stress_all.2431079828
Directory /workspace/46.uart_stress_all/latest

Test location /workspace/coverage/default/46.uart_stress_all_with_rand_reset.283368540
Short name T904
Test name
Test status
Simulation time 96457692730 ps
CPU time 778.23 seconds
Started Aug 03 04:54:45 PM PDT 24
Finished Aug 03 05:07:43 PM PDT 24
Peak memory 224728 kb
Host smart-266cbb5e-82b8-47e7-9e66-7541dfcb07cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283368540 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 46.uart_stress_all_with_rand_reset.283368540
Directory /workspace/46.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.uart_tx_ovrd.603429107
Short name T761
Test name
Test status
Simulation time 1805543112 ps
CPU time 3 seconds
Started Aug 03 04:54:35 PM PDT 24
Finished Aug 03 04:54:38 PM PDT 24
Peak memory 198356 kb
Host smart-3511d7f9-fa4b-4566-8564-9eedd0e02334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603429107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_ovrd.603429107
Directory /workspace/46.uart_tx_ovrd/latest

Test location /workspace/coverage/default/46.uart_tx_rx.3578506260
Short name T1130
Test name
Test status
Simulation time 32006680321 ps
CPU time 25.32 seconds
Started Aug 03 04:54:35 PM PDT 24
Finished Aug 03 04:55:01 PM PDT 24
Peak memory 199932 kb
Host smart-2284bbcb-d81c-4dd7-970f-0fc82f518ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578506260 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.uart_tx_rx.3578506260
Directory /workspace/46.uart_tx_rx/latest

Test location /workspace/coverage/default/47.uart_alert_test.1937686521
Short name T525
Test name
Test status
Simulation time 13751274 ps
CPU time 0.54 seconds
Started Aug 03 04:54:49 PM PDT 24
Finished Aug 03 04:54:50 PM PDT 24
Peak memory 195280 kb
Host smart-5a3abb0f-78e7-4bb4-ba8d-8fc4642c2151
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937686521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_alert_test.1937686521
Directory /workspace/47.uart_alert_test/latest

Test location /workspace/coverage/default/47.uart_fifo_full.4189435656
Short name T139
Test name
Test status
Simulation time 19495649765 ps
CPU time 42.19 seconds
Started Aug 03 04:54:49 PM PDT 24
Finished Aug 03 04:55:31 PM PDT 24
Peak memory 199812 kb
Host smart-e7a77359-6fbd-456f-adac-8208d8b0fbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189435656 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_full.4189435656
Directory /workspace/47.uart_fifo_full/latest

Test location /workspace/coverage/default/47.uart_fifo_overflow.3598461563
Short name T1011
Test name
Test status
Simulation time 59129031345 ps
CPU time 93.5 seconds
Started Aug 03 04:54:41 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 199592 kb
Host smart-0399e9eb-b658-4e4c-bd17-8c7e3cf219ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598461563 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_overflow.3598461563
Directory /workspace/47.uart_fifo_overflow/latest

Test location /workspace/coverage/default/47.uart_fifo_reset.3022672140
Short name T209
Test name
Test status
Simulation time 22402597535 ps
CPU time 32.37 seconds
Started Aug 03 04:54:41 PM PDT 24
Finished Aug 03 04:55:14 PM PDT 24
Peak memory 199912 kb
Host smart-803008a5-d334-4526-ab7e-b839a9831a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022672140 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_fifo_reset.3022672140
Directory /workspace/47.uart_fifo_reset/latest

Test location /workspace/coverage/default/47.uart_intr.3857033321
Short name T720
Test name
Test status
Simulation time 10054736144 ps
CPU time 1.49 seconds
Started Aug 03 04:54:46 PM PDT 24
Finished Aug 03 04:54:47 PM PDT 24
Peak memory 196936 kb
Host smart-c869e69f-ac57-4ebc-8060-f828cca32017
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857033321 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_intr.3857033321
Directory /workspace/47.uart_intr/latest

Test location /workspace/coverage/default/47.uart_long_xfer_wo_dly.2309919674
Short name T387
Test name
Test status
Simulation time 148924382170 ps
CPU time 617.12 seconds
Started Aug 03 04:54:51 PM PDT 24
Finished Aug 03 05:05:09 PM PDT 24
Peak memory 199892 kb
Host smart-e009d9d0-66ed-4b61-a621-7590674f53c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309919674 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_long_xfer_wo_dly.2309919674
Directory /workspace/47.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/47.uart_loopback.2447222235
Short name T508
Test name
Test status
Simulation time 7488328338 ps
CPU time 13.89 seconds
Started Aug 03 04:54:48 PM PDT 24
Finished Aug 03 04:55:02 PM PDT 24
Peak memory 199744 kb
Host smart-1059c055-9d8f-455b-988c-b93337f8e632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447222235 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_loopback.2447222235
Directory /workspace/47.uart_loopback/latest

Test location /workspace/coverage/default/47.uart_noise_filter.1650441037
Short name T727
Test name
Test status
Simulation time 175431019713 ps
CPU time 93.42 seconds
Started Aug 03 04:54:43 PM PDT 24
Finished Aug 03 04:56:16 PM PDT 24
Peak memory 207948 kb
Host smart-32c2400d-15d7-4a6f-a9fa-e2e1810a2a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650441037 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_noise_filter.1650441037
Directory /workspace/47.uart_noise_filter/latest

Test location /workspace/coverage/default/47.uart_perf.869219662
Short name T492
Test name
Test status
Simulation time 17204028700 ps
CPU time 214.92 seconds
Started Aug 03 04:54:50 PM PDT 24
Finished Aug 03 04:58:26 PM PDT 24
Peak memory 199728 kb
Host smart-09eea59c-8ad0-486c-9103-c512651504be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=869219662 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_perf.869219662
Directory /workspace/47.uart_perf/latest

Test location /workspace/coverage/default/47.uart_rx_oversample.2677704064
Short name T704
Test name
Test status
Simulation time 1685695921 ps
CPU time 5.98 seconds
Started Aug 03 04:54:43 PM PDT 24
Finished Aug 03 04:54:49 PM PDT 24
Peak memory 197700 kb
Host smart-cefee7cb-f844-43ef-a890-40d51a58f9a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677704064 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_oversample.2677704064
Directory /workspace/47.uart_rx_oversample/latest

Test location /workspace/coverage/default/47.uart_rx_parity_err.2629235653
Short name T674
Test name
Test status
Simulation time 202474026825 ps
CPU time 33.98 seconds
Started Aug 03 04:54:45 PM PDT 24
Finished Aug 03 04:55:19 PM PDT 24
Peak memory 199816 kb
Host smart-ddb66a6c-3cda-476c-bc07-ec7759870776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629235653 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_parity_err.2629235653
Directory /workspace/47.uart_rx_parity_err/latest

Test location /workspace/coverage/default/47.uart_rx_start_bit_filter.1717163561
Short name T286
Test name
Test status
Simulation time 3360852867 ps
CPU time 3.27 seconds
Started Aug 03 04:54:42 PM PDT 24
Finished Aug 03 04:54:45 PM PDT 24
Peak memory 196228 kb
Host smart-494f90e9-dcb4-49e5-94d3-6dadfbc40b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717163561 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_rx_start_bit_filter.1717163561
Directory /workspace/47.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/47.uart_smoke.1396193928
Short name T540
Test name
Test status
Simulation time 5617666423 ps
CPU time 3.94 seconds
Started Aug 03 04:54:42 PM PDT 24
Finished Aug 03 04:54:46 PM PDT 24
Peak memory 199212 kb
Host smart-1214a600-e8c6-491e-a67f-1a85c60aea49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396193928 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_smoke.1396193928
Directory /workspace/47.uart_smoke/latest

Test location /workspace/coverage/default/47.uart_stress_all.4031385929
Short name T1073
Test name
Test status
Simulation time 512357925922 ps
CPU time 755.43 seconds
Started Aug 03 04:54:50 PM PDT 24
Finished Aug 03 05:07:25 PM PDT 24
Peak memory 199816 kb
Host smart-33cdb4ee-32bc-4cf4-aa1b-529680a541dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031385929 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_stress_all.4031385929
Directory /workspace/47.uart_stress_all/latest

Test location /workspace/coverage/default/47.uart_stress_all_with_rand_reset.2671888844
Short name T47
Test name
Test status
Simulation time 80648033424 ps
CPU time 370.94 seconds
Started Aug 03 04:54:51 PM PDT 24
Finished Aug 03 05:01:02 PM PDT 24
Peak memory 216572 kb
Host smart-acde7bd0-59e7-4d1b-8870-a2d5cfc4107c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671888844 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 47.uart_stress_all_with_rand_reset.2671888844
Directory /workspace/47.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.uart_tx_ovrd.2462083221
Short name T895
Test name
Test status
Simulation time 7225264282 ps
CPU time 13.3 seconds
Started Aug 03 04:54:50 PM PDT 24
Finished Aug 03 04:55:03 PM PDT 24
Peak memory 199784 kb
Host smart-28cc37cb-cbdd-4761-87d8-ca8268432921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462083221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_ovrd.2462083221
Directory /workspace/47.uart_tx_ovrd/latest

Test location /workspace/coverage/default/47.uart_tx_rx.1580239258
Short name T500
Test name
Test status
Simulation time 16415962303 ps
CPU time 14.45 seconds
Started Aug 03 04:54:44 PM PDT 24
Finished Aug 03 04:54:59 PM PDT 24
Peak memory 199784 kb
Host smart-eea335b5-f3cb-45ed-ab86-06d327d73465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580239258 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.uart_tx_rx.1580239258
Directory /workspace/47.uart_tx_rx/latest

Test location /workspace/coverage/default/48.uart_alert_test.705910521
Short name T382
Test name
Test status
Simulation time 26098849 ps
CPU time 0.54 seconds
Started Aug 03 04:54:56 PM PDT 24
Finished Aug 03 04:54:56 PM PDT 24
Peak memory 195224 kb
Host smart-d83e34d1-92a5-4f2d-ad2f-4bfd9b497259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705910521 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_alert_test.705910521
Directory /workspace/48.uart_alert_test/latest

Test location /workspace/coverage/default/48.uart_fifo_full.3933794645
Short name T1058
Test name
Test status
Simulation time 19395528945 ps
CPU time 30.5 seconds
Started Aug 03 04:55:00 PM PDT 24
Finished Aug 03 04:55:31 PM PDT 24
Peak memory 199836 kb
Host smart-ee6a6534-1ee1-4b98-a324-f6d549d7e737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933794645 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_full.3933794645
Directory /workspace/48.uart_fifo_full/latest

Test location /workspace/coverage/default/48.uart_fifo_overflow.309919873
Short name T691
Test name
Test status
Simulation time 47244501908 ps
CPU time 30.82 seconds
Started Aug 03 04:54:55 PM PDT 24
Finished Aug 03 04:55:26 PM PDT 24
Peak memory 199888 kb
Host smart-4ba22bd4-44be-49a3-ba16-d3a2ac782808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309919873 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_overflow.309919873
Directory /workspace/48.uart_fifo_overflow/latest

Test location /workspace/coverage/default/48.uart_fifo_reset.3828129217
Short name T419
Test name
Test status
Simulation time 9793342887 ps
CPU time 16.77 seconds
Started Aug 03 04:54:59 PM PDT 24
Finished Aug 03 04:55:16 PM PDT 24
Peak memory 199856 kb
Host smart-88e0fb18-9fbe-44dc-bbd6-e82faa6242f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828129217 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_fifo_reset.3828129217
Directory /workspace/48.uart_fifo_reset/latest

Test location /workspace/coverage/default/48.uart_intr.1825963063
Short name T21
Test name
Test status
Simulation time 40735677198 ps
CPU time 16.48 seconds
Started Aug 03 04:54:57 PM PDT 24
Finished Aug 03 04:55:14 PM PDT 24
Peak memory 199804 kb
Host smart-0b0fa8e4-31cd-4a02-9ecd-68f619b4aee4
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825963063 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_intr.1825963063
Directory /workspace/48.uart_intr/latest

Test location /workspace/coverage/default/48.uart_long_xfer_wo_dly.267488195
Short name T587
Test name
Test status
Simulation time 51130771873 ps
CPU time 228.44 seconds
Started Aug 03 04:54:58 PM PDT 24
Finished Aug 03 04:58:46 PM PDT 24
Peak memory 199904 kb
Host smart-7f24392e-78e6-4d82-a5bc-cb0ea0dde546
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267488195 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_long_xfer_wo_dly.267488195
Directory /workspace/48.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/48.uart_loopback.1458532039
Short name T695
Test name
Test status
Simulation time 8942398270 ps
CPU time 17.77 seconds
Started Aug 03 04:54:59 PM PDT 24
Finished Aug 03 04:55:17 PM PDT 24
Peak memory 199844 kb
Host smart-52fc6e8d-92e4-48eb-8f15-82f25309d331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458532039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_loopback.1458532039
Directory /workspace/48.uart_loopback/latest

Test location /workspace/coverage/default/48.uart_noise_filter.518007229
Short name T1029
Test name
Test status
Simulation time 51621913208 ps
CPU time 80.49 seconds
Started Aug 03 04:54:58 PM PDT 24
Finished Aug 03 04:56:18 PM PDT 24
Peak memory 198080 kb
Host smart-541d5b76-d6e8-4542-8fd8-d8cd1e383e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518007229 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_noise_filter.518007229
Directory /workspace/48.uart_noise_filter/latest

Test location /workspace/coverage/default/48.uart_perf.894128488
Short name T896
Test name
Test status
Simulation time 4556080182 ps
CPU time 47.79 seconds
Started Aug 03 04:54:56 PM PDT 24
Finished Aug 03 04:55:44 PM PDT 24
Peak memory 199900 kb
Host smart-5521ac30-ec6b-4594-b9e3-5033acfa6a18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=894128488 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_perf.894128488
Directory /workspace/48.uart_perf/latest

Test location /workspace/coverage/default/48.uart_rx_oversample.3895646659
Short name T675
Test name
Test status
Simulation time 6021902974 ps
CPU time 52.22 seconds
Started Aug 03 04:55:00 PM PDT 24
Finished Aug 03 04:55:53 PM PDT 24
Peak memory 199780 kb
Host smart-6ab430db-1941-418b-bf15-8890f83c384f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3895646659 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_oversample.3895646659
Directory /workspace/48.uart_rx_oversample/latest

Test location /workspace/coverage/default/48.uart_rx_start_bit_filter.3775339365
Short name T1047
Test name
Test status
Simulation time 2138047389 ps
CPU time 2.15 seconds
Started Aug 03 04:54:55 PM PDT 24
Finished Aug 03 04:54:57 PM PDT 24
Peak memory 195448 kb
Host smart-c5bae1d6-66c9-40ce-b29e-48e602d94c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775339365 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_rx_start_bit_filter.3775339365
Directory /workspace/48.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/48.uart_smoke.2406241322
Short name T755
Test name
Test status
Simulation time 693264074 ps
CPU time 1.68 seconds
Started Aug 03 04:54:49 PM PDT 24
Finished Aug 03 04:54:51 PM PDT 24
Peak memory 198576 kb
Host smart-2fa8e84b-fa2c-4fdb-86f0-afeab7d4b3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406241322 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_smoke.2406241322
Directory /workspace/48.uart_smoke/latest

Test location /workspace/coverage/default/48.uart_stress_all_with_rand_reset.2764182091
Short name T811
Test name
Test status
Simulation time 88049718940 ps
CPU time 582.35 seconds
Started Aug 03 04:54:58 PM PDT 24
Finished Aug 03 05:04:40 PM PDT 24
Peak memory 225952 kb
Host smart-42103773-1aa9-4c2c-b444-553ff0ac2405
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764182091 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 48.uart_stress_all_with_rand_reset.2764182091
Directory /workspace/48.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.uart_tx_ovrd.1178791117
Short name T627
Test name
Test status
Simulation time 1435663453 ps
CPU time 1.81 seconds
Started Aug 03 04:54:58 PM PDT 24
Finished Aug 03 04:55:00 PM PDT 24
Peak memory 198804 kb
Host smart-d9e1eecf-2e1c-4cf1-8b0d-a0fed6691e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178791117 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_ovrd.1178791117
Directory /workspace/48.uart_tx_ovrd/latest

Test location /workspace/coverage/default/48.uart_tx_rx.4159956802
Short name T106
Test name
Test status
Simulation time 71970704352 ps
CPU time 11.47 seconds
Started Aug 03 04:54:48 PM PDT 24
Finished Aug 03 04:55:00 PM PDT 24
Peak memory 199908 kb
Host smart-c2e4c8cc-466b-4411-9405-4a575a5360e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159956802 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.uart_tx_rx.4159956802
Directory /workspace/48.uart_tx_rx/latest

Test location /workspace/coverage/default/49.uart_alert_test.2053284484
Short name T1127
Test name
Test status
Simulation time 43895487 ps
CPU time 0.61 seconds
Started Aug 03 04:55:09 PM PDT 24
Finished Aug 03 04:55:10 PM PDT 24
Peak memory 195252 kb
Host smart-bbbb5cc7-74d4-487d-906e-2f241ddde3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053284484 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_alert_test.2053284484
Directory /workspace/49.uart_alert_test/latest

Test location /workspace/coverage/default/49.uart_fifo_full.3400760114
Short name T445
Test name
Test status
Simulation time 114020609526 ps
CPU time 183.88 seconds
Started Aug 03 04:55:04 PM PDT 24
Finished Aug 03 04:58:07 PM PDT 24
Peak memory 199660 kb
Host smart-ee95a236-db89-4a71-aa01-8675198a9029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400760114 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_full.3400760114
Directory /workspace/49.uart_fifo_full/latest

Test location /workspace/coverage/default/49.uart_fifo_overflow.2564505772
Short name T912
Test name
Test status
Simulation time 28481589581 ps
CPU time 53.22 seconds
Started Aug 03 04:55:05 PM PDT 24
Finished Aug 03 04:55:59 PM PDT 24
Peak memory 199796 kb
Host smart-236ff58c-4292-4d4c-8a27-920d12a453b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564505772 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_overflow.2564505772
Directory /workspace/49.uart_fifo_overflow/latest

Test location /workspace/coverage/default/49.uart_fifo_reset.2437341450
Short name T960
Test name
Test status
Simulation time 36264290012 ps
CPU time 13.48 seconds
Started Aug 03 04:55:01 PM PDT 24
Finished Aug 03 04:55:15 PM PDT 24
Peak memory 199876 kb
Host smart-2a12431b-6205-41e3-9018-b92a518b09f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437341450 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_fifo_reset.2437341450
Directory /workspace/49.uart_fifo_reset/latest

Test location /workspace/coverage/default/49.uart_intr.3191060022
Short name T25
Test name
Test status
Simulation time 178818459903 ps
CPU time 67.92 seconds
Started Aug 03 04:55:03 PM PDT 24
Finished Aug 03 04:56:11 PM PDT 24
Peak memory 197136 kb
Host smart-60034853-7f5e-4213-8e9a-0ad5e04aa827
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191060022 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_intr.3191060022
Directory /workspace/49.uart_intr/latest

Test location /workspace/coverage/default/49.uart_long_xfer_wo_dly.3276211742
Short name T249
Test name
Test status
Simulation time 102398777274 ps
CPU time 874.43 seconds
Started Aug 03 04:55:10 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 199884 kb
Host smart-c40e19cf-9207-4f77-905d-03fe2293796d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3276211742 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_long_xfer_wo_dly.3276211742
Directory /workspace/49.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/49.uart_loopback.1969415614
Short name T348
Test name
Test status
Simulation time 9629903613 ps
CPU time 20.32 seconds
Started Aug 03 04:55:11 PM PDT 24
Finished Aug 03 04:55:31 PM PDT 24
Peak memory 199844 kb
Host smart-006dd42f-f146-4b7d-a955-1ea13a235aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969415614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_loopback.1969415614
Directory /workspace/49.uart_loopback/latest

Test location /workspace/coverage/default/49.uart_noise_filter.395432421
Short name T457
Test name
Test status
Simulation time 257993429971 ps
CPU time 112.17 seconds
Started Aug 03 04:55:02 PM PDT 24
Finished Aug 03 04:56:55 PM PDT 24
Peak memory 199612 kb
Host smart-5f2e2985-c52e-49d6-b5e3-d7e60f80694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395432421 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_noise_filter.395432421
Directory /workspace/49.uart_noise_filter/latest

Test location /workspace/coverage/default/49.uart_perf.446154251
Short name T1000
Test name
Test status
Simulation time 12110623614 ps
CPU time 132.34 seconds
Started Aug 03 04:55:08 PM PDT 24
Finished Aug 03 04:57:21 PM PDT 24
Peak memory 199912 kb
Host smart-3b922795-5c8d-4cb1-b618-88e3f5ba0a7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=446154251 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_perf.446154251
Directory /workspace/49.uart_perf/latest

Test location /workspace/coverage/default/49.uart_rx_oversample.248897252
Short name T26
Test name
Test status
Simulation time 6289608028 ps
CPU time 14.83 seconds
Started Aug 03 04:55:03 PM PDT 24
Finished Aug 03 04:55:18 PM PDT 24
Peak memory 199168 kb
Host smart-72ce1de4-d799-4e71-8ae6-595380756a64
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248897252 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_oversample.248897252
Directory /workspace/49.uart_rx_oversample/latest

Test location /workspace/coverage/default/49.uart_rx_parity_err.2805366832
Short name T533
Test name
Test status
Simulation time 77131698939 ps
CPU time 29.11 seconds
Started Aug 03 04:55:02 PM PDT 24
Finished Aug 03 04:55:32 PM PDT 24
Peak memory 199892 kb
Host smart-90c0214b-8aed-4a05-bfd9-82b1fa644867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805366832 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_parity_err.2805366832
Directory /workspace/49.uart_rx_parity_err/latest

Test location /workspace/coverage/default/49.uart_rx_start_bit_filter.1153510683
Short name T407
Test name
Test status
Simulation time 3641791793 ps
CPU time 3.73 seconds
Started Aug 03 04:55:02 PM PDT 24
Finished Aug 03 04:55:06 PM PDT 24
Peak memory 196064 kb
Host smart-d681f6dc-9c08-402a-8594-ccd431253b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153510683 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_rx_start_bit_filter.1153510683
Directory /workspace/49.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/49.uart_smoke.2977655750
Short name T1027
Test name
Test status
Simulation time 454077084 ps
CPU time 1.92 seconds
Started Aug 03 04:54:56 PM PDT 24
Finished Aug 03 04:54:58 PM PDT 24
Peak memory 199228 kb
Host smart-f4265e51-19ba-44ab-8b81-ee8fd9f957f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977655750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_smoke.2977655750
Directory /workspace/49.uart_smoke/latest

Test location /workspace/coverage/default/49.uart_stress_all.3102284992
Short name T927
Test name
Test status
Simulation time 294295377145 ps
CPU time 366.46 seconds
Started Aug 03 04:55:08 PM PDT 24
Finished Aug 03 05:01:14 PM PDT 24
Peak memory 199848 kb
Host smart-8972c1a7-83e7-42b3-a5fe-5cbd7dfbd767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102284992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_stress_all.3102284992
Directory /workspace/49.uart_stress_all/latest

Test location /workspace/coverage/default/49.uart_stress_all_with_rand_reset.920914061
Short name T61
Test name
Test status
Simulation time 254725074594 ps
CPU time 387.19 seconds
Started Aug 03 04:55:09 PM PDT 24
Finished Aug 03 05:01:37 PM PDT 24
Peak memory 216572 kb
Host smart-7dd51364-18de-4f7f-9d0d-58adac253281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920914061 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 49.uart_stress_all_with_rand_reset.920914061
Directory /workspace/49.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.uart_tx_ovrd.2432466401
Short name T724
Test name
Test status
Simulation time 1362451563 ps
CPU time 1.74 seconds
Started Aug 03 04:55:11 PM PDT 24
Finished Aug 03 04:55:13 PM PDT 24
Peak memory 198720 kb
Host smart-dd697328-b97b-455a-9071-c578a7070527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432466401 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_ovrd.2432466401
Directory /workspace/49.uart_tx_ovrd/latest

Test location /workspace/coverage/default/49.uart_tx_rx.1577608990
Short name T862
Test name
Test status
Simulation time 23460722647 ps
CPU time 35.59 seconds
Started Aug 03 04:55:02 PM PDT 24
Finished Aug 03 04:55:38 PM PDT 24
Peak memory 199848 kb
Host smart-fa83562c-067e-4a29-a5b5-622d9d48e23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577608990 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.uart_tx_rx.1577608990
Directory /workspace/49.uart_tx_rx/latest

Test location /workspace/coverage/default/5.uart_alert_test.1352654975
Short name T1012
Test name
Test status
Simulation time 32987302 ps
CPU time 0.55 seconds
Started Aug 03 04:51:58 PM PDT 24
Finished Aug 03 04:51:59 PM PDT 24
Peak memory 194256 kb
Host smart-32ce3938-c370-4dde-8573-aab10ebc5f12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352654975 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_alert_test.1352654975
Directory /workspace/5.uart_alert_test/latest

Test location /workspace/coverage/default/5.uart_fifo_full.3879577083
Short name T1126
Test name
Test status
Simulation time 37335613019 ps
CPU time 31.67 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:52:25 PM PDT 24
Peak memory 199900 kb
Host smart-f1603d3e-503f-46f3-95bf-14f00248a20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879577083 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_full.3879577083
Directory /workspace/5.uart_fifo_full/latest

Test location /workspace/coverage/default/5.uart_fifo_overflow.1737536149
Short name T602
Test name
Test status
Simulation time 114601395704 ps
CPU time 40.49 seconds
Started Aug 03 04:51:57 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 199816 kb
Host smart-66bdc5e0-4ff8-4675-a0b7-f25bd6692aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737536149 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_overflow.1737536149
Directory /workspace/5.uart_fifo_overflow/latest

Test location /workspace/coverage/default/5.uart_fifo_reset.1762298562
Short name T159
Test name
Test status
Simulation time 200677020119 ps
CPU time 136 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:54:17 PM PDT 24
Peak memory 199796 kb
Host smart-50cc3f28-f91c-4ebe-8bd9-14163b60e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762298562 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_fifo_reset.1762298562
Directory /workspace/5.uart_fifo_reset/latest

Test location /workspace/coverage/default/5.uart_intr.689472464
Short name T385
Test name
Test status
Simulation time 75508705583 ps
CPU time 116.76 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:53:51 PM PDT 24
Peak memory 199892 kb
Host smart-1a8ee783-2970-48cb-bb86-10e54098de9c
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689472464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_intr.689472464
Directory /workspace/5.uart_intr/latest

Test location /workspace/coverage/default/5.uart_long_xfer_wo_dly.403517532
Short name T1078
Test name
Test status
Simulation time 88016491548 ps
CPU time 603.37 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 05:01:58 PM PDT 24
Peak memory 199780 kb
Host smart-5ebf36a0-1153-4406-b8be-e738d91d5b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403517532 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_long_xfer_wo_dly.403517532
Directory /workspace/5.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/5.uart_loopback.3770115720
Short name T358
Test name
Test status
Simulation time 1421527737 ps
CPU time 2.71 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:51:55 PM PDT 24
Peak memory 197140 kb
Host smart-1bc4ed0f-3a14-4bbf-add0-4c18382eb744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770115720 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_loopback.3770115720
Directory /workspace/5.uart_loopback/latest

Test location /workspace/coverage/default/5.uart_noise_filter.2870385264
Short name T315
Test name
Test status
Simulation time 19653526238 ps
CPU time 33.39 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 198116 kb
Host smart-7f66412e-2581-47da-adbf-84251ba91398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870385264 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_noise_filter.2870385264
Directory /workspace/5.uart_noise_filter/latest

Test location /workspace/coverage/default/5.uart_perf.2587079688
Short name T1119
Test name
Test status
Simulation time 17409392166 ps
CPU time 254.37 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:56:09 PM PDT 24
Peak memory 199832 kb
Host smart-15830763-69a8-4e7c-8ea0-074494d4ddbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2587079688 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_perf.2587079688
Directory /workspace/5.uart_perf/latest

Test location /workspace/coverage/default/5.uart_rx_oversample.1501651477
Short name T1037
Test name
Test status
Simulation time 5817598333 ps
CPU time 53.97 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:52:48 PM PDT 24
Peak memory 197984 kb
Host smart-007ea88d-9131-4e20-947d-3e0575e2149b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1501651477 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_oversample.1501651477
Directory /workspace/5.uart_rx_oversample/latest

Test location /workspace/coverage/default/5.uart_rx_parity_err.1952589531
Short name T1066
Test name
Test status
Simulation time 101073789099 ps
CPU time 68.38 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:53:01 PM PDT 24
Peak memory 199936 kb
Host smart-b1072f1c-1d57-4660-8628-5639ffad8853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952589531 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_parity_err.1952589531
Directory /workspace/5.uart_rx_parity_err/latest

Test location /workspace/coverage/default/5.uart_rx_start_bit_filter.1128662430
Short name T949
Test name
Test status
Simulation time 33518020004 ps
CPU time 38.69 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 196212 kb
Host smart-fcd9d6cc-9030-4385-9601-0fc5f24ee893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128662430 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_rx_start_bit_filter.1128662430
Directory /workspace/5.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/5.uart_smoke.2471663263
Short name T1148
Test name
Test status
Simulation time 6191417720 ps
CPU time 38.18 seconds
Started Aug 03 04:51:51 PM PDT 24
Finished Aug 03 04:52:29 PM PDT 24
Peak memory 199872 kb
Host smart-9ec55d45-fbf6-4062-b0cf-0e3ae6829bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471663263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_smoke.2471663263
Directory /workspace/5.uart_smoke/latest

Test location /workspace/coverage/default/5.uart_stress_all.883629032
Short name T994
Test name
Test status
Simulation time 154247402094 ps
CPU time 72 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:53:04 PM PDT 24
Peak memory 199756 kb
Host smart-931b7a36-93b0-4505-8178-62d8cd140511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883629032 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_stress_all.883629032
Directory /workspace/5.uart_stress_all/latest

Test location /workspace/coverage/default/5.uart_stress_all_with_rand_reset.1821043875
Short name T773
Test name
Test status
Simulation time 46698315573 ps
CPU time 519.89 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 05:00:35 PM PDT 24
Peak memory 216608 kb
Host smart-d1193a82-94fb-4f59-acde-80f3b982fc08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821043875 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 5.uart_stress_all_with_rand_reset.1821043875
Directory /workspace/5.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.uart_tx_ovrd.2799215403
Short name T1059
Test name
Test status
Simulation time 1016266116 ps
CPU time 2.93 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:51:56 PM PDT 24
Peak memory 199880 kb
Host smart-0f9b82ad-e077-4f14-835d-24f1a46cc09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799215403 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_ovrd.2799215403
Directory /workspace/5.uart_tx_ovrd/latest

Test location /workspace/coverage/default/5.uart_tx_rx.2727680433
Short name T310
Test name
Test status
Simulation time 51862857609 ps
CPU time 116.86 seconds
Started Aug 03 04:51:56 PM PDT 24
Finished Aug 03 04:53:53 PM PDT 24
Peak memory 199932 kb
Host smart-f7f2a923-b9e7-451e-9029-503d2871797a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727680433 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.uart_tx_rx.2727680433
Directory /workspace/5.uart_tx_rx/latest

Test location /workspace/coverage/default/50.uart_fifo_reset.2899238822
Short name T1055
Test name
Test status
Simulation time 26324507589 ps
CPU time 43.5 seconds
Started Aug 03 04:55:11 PM PDT 24
Finished Aug 03 04:55:55 PM PDT 24
Peak memory 199836 kb
Host smart-41595af0-17ed-434c-9178-958e58c337e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899238822 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.uart_fifo_reset.2899238822
Directory /workspace/50.uart_fifo_reset/latest

Test location /workspace/coverage/default/50.uart_stress_all_with_rand_reset.1944148725
Short name T848
Test name
Test status
Simulation time 636324384598 ps
CPU time 1001.59 seconds
Started Aug 03 04:55:11 PM PDT 24
Finished Aug 03 05:11:52 PM PDT 24
Peak memory 225928 kb
Host smart-5a5d7407-c702-4e53-bd9f-5ca103782220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944148725 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 50.uart_stress_all_with_rand_reset.1944148725
Directory /workspace/50.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/51.uart_fifo_reset.3436004547
Short name T1162
Test name
Test status
Simulation time 19986853008 ps
CPU time 29.21 seconds
Started Aug 03 04:55:08 PM PDT 24
Finished Aug 03 04:55:38 PM PDT 24
Peak memory 199860 kb
Host smart-b2aa0683-2d41-4b92-a0ab-1034f6243026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436004547 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.uart_fifo_reset.3436004547
Directory /workspace/51.uart_fifo_reset/latest

Test location /workspace/coverage/default/51.uart_stress_all_with_rand_reset.1229370399
Short name T631
Test name
Test status
Simulation time 263344052311 ps
CPU time 1016.06 seconds
Started Aug 03 04:55:14 PM PDT 24
Finished Aug 03 05:12:10 PM PDT 24
Peak memory 224716 kb
Host smart-e13e90ef-8e72-48b6-bf3a-30204a3a56b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229370399 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 51.uart_stress_all_with_rand_reset.1229370399
Directory /workspace/51.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/52.uart_fifo_reset.2283256686
Short name T1089
Test name
Test status
Simulation time 211379683782 ps
CPU time 25.96 seconds
Started Aug 03 04:55:19 PM PDT 24
Finished Aug 03 04:55:45 PM PDT 24
Peak memory 199876 kb
Host smart-943fefac-f67d-4ee8-88b7-3156f5571962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283256686 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.uart_fifo_reset.2283256686
Directory /workspace/52.uart_fifo_reset/latest

Test location /workspace/coverage/default/52.uart_stress_all_with_rand_reset.2785340424
Short name T37
Test name
Test status
Simulation time 10124232748 ps
CPU time 125.21 seconds
Started Aug 03 04:55:14 PM PDT 24
Finished Aug 03 04:57:19 PM PDT 24
Peak memory 215848 kb
Host smart-4857d89d-7363-480d-8514-c34cf512ef3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785340424 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 52.uart_stress_all_with_rand_reset.2785340424
Directory /workspace/52.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/53.uart_fifo_reset.1451407490
Short name T161
Test name
Test status
Simulation time 76446884545 ps
CPU time 51.58 seconds
Started Aug 03 04:55:13 PM PDT 24
Finished Aug 03 04:56:04 PM PDT 24
Peak memory 199900 kb
Host smart-8c7e01b8-eef2-486f-8df6-46520b781909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451407490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.uart_fifo_reset.1451407490
Directory /workspace/53.uart_fifo_reset/latest

Test location /workspace/coverage/default/53.uart_stress_all_with_rand_reset.3749137148
Short name T95
Test name
Test status
Simulation time 132292670469 ps
CPU time 758.56 seconds
Started Aug 03 04:55:14 PM PDT 24
Finished Aug 03 05:07:52 PM PDT 24
Peak memory 216572 kb
Host smart-ef1e5377-e8a9-45d2-8d48-4258c647a7f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749137148 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 53.uart_stress_all_with_rand_reset.3749137148
Directory /workspace/53.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/54.uart_stress_all_with_rand_reset.280788622
Short name T826
Test name
Test status
Simulation time 30865014385 ps
CPU time 177.45 seconds
Started Aug 03 04:55:15 PM PDT 24
Finished Aug 03 04:58:13 PM PDT 24
Peak memory 208188 kb
Host smart-b316348f-148c-412e-9793-bd72ac6e3af5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280788622 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 54.uart_stress_all_with_rand_reset.280788622
Directory /workspace/54.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/55.uart_fifo_reset.1740683170
Short name T717
Test name
Test status
Simulation time 9355098902 ps
CPU time 15.33 seconds
Started Aug 03 04:55:25 PM PDT 24
Finished Aug 03 04:55:40 PM PDT 24
Peak memory 199936 kb
Host smart-64da82fe-2e57-41db-a257-86e82d331a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740683170 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.uart_fifo_reset.1740683170
Directory /workspace/55.uart_fifo_reset/latest

Test location /workspace/coverage/default/55.uart_stress_all_with_rand_reset.4254675709
Short name T48
Test name
Test status
Simulation time 187769052777 ps
CPU time 1070.75 seconds
Started Aug 03 04:55:22 PM PDT 24
Finished Aug 03 05:13:13 PM PDT 24
Peak memory 226912 kb
Host smart-a0df5beb-452a-48e1-9691-24ee1fd7f310
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254675709 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 55.uart_stress_all_with_rand_reset.4254675709
Directory /workspace/55.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/56.uart_stress_all_with_rand_reset.3751336397
Short name T870
Test name
Test status
Simulation time 599863503073 ps
CPU time 716.53 seconds
Started Aug 03 04:55:20 PM PDT 24
Finished Aug 03 05:07:16 PM PDT 24
Peak memory 224696 kb
Host smart-306ee7c8-3b39-48af-b6a5-fa4b59faa93a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751336397 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 56.uart_stress_all_with_rand_reset.3751336397
Directory /workspace/56.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/57.uart_fifo_reset.1377481989
Short name T819
Test name
Test status
Simulation time 18454661890 ps
CPU time 19.42 seconds
Started Aug 03 04:55:25 PM PDT 24
Finished Aug 03 04:55:44 PM PDT 24
Peak memory 199420 kb
Host smart-edec09bc-a464-4308-a080-0ca34f90478c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377481989 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.uart_fifo_reset.1377481989
Directory /workspace/57.uart_fifo_reset/latest

Test location /workspace/coverage/default/57.uart_stress_all_with_rand_reset.1122120375
Short name T1025
Test name
Test status
Simulation time 23893384790 ps
CPU time 283.66 seconds
Started Aug 03 04:55:21 PM PDT 24
Finished Aug 03 05:00:05 PM PDT 24
Peak memory 216368 kb
Host smart-1f646de7-6683-4d9b-9720-502f638cfcbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122120375 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 57.uart_stress_all_with_rand_reset.1122120375
Directory /workspace/57.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/58.uart_fifo_reset.4091642972
Short name T217
Test name
Test status
Simulation time 64850423769 ps
CPU time 23.45 seconds
Started Aug 03 04:55:22 PM PDT 24
Finished Aug 03 04:55:46 PM PDT 24
Peak memory 199912 kb
Host smart-61434d3e-7f4e-4546-b1fd-37e2dad2cee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091642972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.uart_fifo_reset.4091642972
Directory /workspace/58.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_fifo_reset.1176444495
Short name T594
Test name
Test status
Simulation time 47843743794 ps
CPU time 82.8 seconds
Started Aug 03 04:55:24 PM PDT 24
Finished Aug 03 04:56:47 PM PDT 24
Peak memory 199892 kb
Host smart-9802d904-93ab-44c6-a0db-05acb50e7492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176444495 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.uart_fifo_reset.1176444495
Directory /workspace/59.uart_fifo_reset/latest

Test location /workspace/coverage/default/59.uart_stress_all_with_rand_reset.985688756
Short name T725
Test name
Test status
Simulation time 253093546147 ps
CPU time 1376.26 seconds
Started Aug 03 04:55:27 PM PDT 24
Finished Aug 03 05:18:24 PM PDT 24
Peak memory 224552 kb
Host smart-fba8e073-1153-41b9-90a5-58ba4e8d409f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985688756 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 59.uart_stress_all_with_rand_reset.985688756
Directory /workspace/59.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_alert_test.1276964001
Short name T817
Test name
Test status
Simulation time 40210718 ps
CPU time 0.59 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:51:55 PM PDT 24
Peak memory 195564 kb
Host smart-a9fb6121-0b26-44e7-974b-3992683ab87b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276964001 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_alert_test.1276964001
Directory /workspace/6.uart_alert_test/latest

Test location /workspace/coverage/default/6.uart_fifo_full.2644405210
Short name T276
Test name
Test status
Simulation time 65915929822 ps
CPU time 115.95 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:53:50 PM PDT 24
Peak memory 199932 kb
Host smart-ef505e1d-978c-4ba0-807a-000454cc3bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644405210 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_full.2644405210
Directory /workspace/6.uart_fifo_full/latest

Test location /workspace/coverage/default/6.uart_fifo_overflow.2685229694
Short name T899
Test name
Test status
Simulation time 217247154315 ps
CPU time 213.32 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:55:29 PM PDT 24
Peak memory 199932 kb
Host smart-71aa3302-958b-4f5c-a350-2cc6f9cec3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685229694 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_overflow.2685229694
Directory /workspace/6.uart_fifo_overflow/latest

Test location /workspace/coverage/default/6.uart_fifo_reset.765544642
Short name T889
Test name
Test status
Simulation time 166289522752 ps
CPU time 107.44 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:53:41 PM PDT 24
Peak memory 199836 kb
Host smart-49e02dc7-346c-4bdf-a887-d9c6ed045d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765544642 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_fifo_reset.765544642
Directory /workspace/6.uart_fifo_reset/latest

Test location /workspace/coverage/default/6.uart_intr.2338221031
Short name T316
Test name
Test status
Simulation time 18816449057 ps
CPU time 11.02 seconds
Started Aug 03 04:52:02 PM PDT 24
Finished Aug 03 04:52:13 PM PDT 24
Peak memory 197088 kb
Host smart-889b144a-c386-4840-853d-c5fb117c29f7
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338221031 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_intr.2338221031
Directory /workspace/6.uart_intr/latest

Test location /workspace/coverage/default/6.uart_long_xfer_wo_dly.2742920856
Short name T797
Test name
Test status
Simulation time 57943729632 ps
CPU time 336.48 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:57:37 PM PDT 24
Peak memory 199864 kb
Host smart-8026c6c8-5aa8-4531-afec-9883e761f519
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742920856 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_long_xfer_wo_dly.2742920856
Directory /workspace/6.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/6.uart_loopback.723128209
Short name T363
Test name
Test status
Simulation time 7514529377 ps
CPU time 13.64 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:52:09 PM PDT 24
Peak memory 199168 kb
Host smart-5c68421f-9b06-403f-8b4f-2a8a9e6ca0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723128209 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_loopback.723128209
Directory /workspace/6.uart_loopback/latest

Test location /workspace/coverage/default/6.uart_noise_filter.3832363689
Short name T905
Test name
Test status
Simulation time 44411658627 ps
CPU time 63.83 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:52:57 PM PDT 24
Peak memory 200044 kb
Host smart-51e4a1a6-70f2-4aad-b0bd-bb61799a6de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832363689 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_noise_filter.3832363689
Directory /workspace/6.uart_noise_filter/latest

Test location /workspace/coverage/default/6.uart_perf.246838425
Short name T867
Test name
Test status
Simulation time 5513214329 ps
CPU time 105.83 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:53:47 PM PDT 24
Peak memory 199876 kb
Host smart-ccbdc908-17f1-4d6c-9725-add309e018c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246838425 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_perf.246838425
Directory /workspace/6.uart_perf/latest

Test location /workspace/coverage/default/6.uart_rx_oversample.2655487039
Short name T409
Test name
Test status
Simulation time 2654814589 ps
CPU time 2.73 seconds
Started Aug 03 04:51:57 PM PDT 24
Finished Aug 03 04:52:00 PM PDT 24
Peak memory 198012 kb
Host smart-f07de303-6e27-4372-a15f-fecf2c25fa30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2655487039 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_oversample.2655487039
Directory /workspace/6.uart_rx_oversample/latest

Test location /workspace/coverage/default/6.uart_rx_parity_err.1638954967
Short name T685
Test name
Test status
Simulation time 211170179647 ps
CPU time 98.24 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:53:39 PM PDT 24
Peak memory 199916 kb
Host smart-2bc0073d-62de-47eb-9773-d8f45f492cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638954967 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_parity_err.1638954967
Directory /workspace/6.uart_rx_parity_err/latest

Test location /workspace/coverage/default/6.uart_rx_start_bit_filter.3488805152
Short name T422
Test name
Test status
Simulation time 4486997970 ps
CPU time 7.75 seconds
Started Aug 03 04:51:53 PM PDT 24
Finished Aug 03 04:52:01 PM PDT 24
Peak memory 196000 kb
Host smart-808bcbcd-6de4-42d1-8d64-dd462d42afc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488805152 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_rx_start_bit_filter.3488805152
Directory /workspace/6.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/6.uart_smoke.3212626290
Short name T356
Test name
Test status
Simulation time 692653920 ps
CPU time 2.78 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:51:58 PM PDT 24
Peak memory 199600 kb
Host smart-f6c0f0ab-bcc0-4cb4-9066-51e815819c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212626290 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_smoke.3212626290
Directory /workspace/6.uart_smoke/latest

Test location /workspace/coverage/default/6.uart_stress_all.354521107
Short name T840
Test name
Test status
Simulation time 417117816197 ps
CPU time 506.9 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 05:00:19 PM PDT 24
Peak memory 199892 kb
Host smart-e9ab1f89-6a5f-4f71-a563-e0c4e6ae3682
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354521107 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_stress_all.354521107
Directory /workspace/6.uart_stress_all/latest

Test location /workspace/coverage/default/6.uart_stress_all_with_rand_reset.2140458845
Short name T977
Test name
Test status
Simulation time 37986575462 ps
CPU time 350.73 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:57:45 PM PDT 24
Peak memory 213216 kb
Host smart-717b3cf1-c123-463f-a9e6-69041084245e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140458845 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 6.uart_stress_all_with_rand_reset.2140458845
Directory /workspace/6.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.uart_tx_ovrd.3624381828
Short name T1068
Test name
Test status
Simulation time 6121040505 ps
CPU time 22.15 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:52:17 PM PDT 24
Peak memory 199824 kb
Host smart-81e24d7b-3017-4641-9e52-fb5101d9cdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624381828 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_ovrd.3624381828
Directory /workspace/6.uart_tx_ovrd/latest

Test location /workspace/coverage/default/6.uart_tx_rx.1576498871
Short name T245
Test name
Test status
Simulation time 24408058731 ps
CPU time 10.93 seconds
Started Aug 03 04:51:54 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 199660 kb
Host smart-b900657b-def1-4d2d-a5eb-28d4e5bdb490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576498871 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.uart_tx_rx.1576498871
Directory /workspace/6.uart_tx_rx/latest

Test location /workspace/coverage/default/60.uart_fifo_reset.1954817727
Short name T267
Test name
Test status
Simulation time 27158713931 ps
CPU time 38.48 seconds
Started Aug 03 04:55:28 PM PDT 24
Finished Aug 03 04:56:06 PM PDT 24
Peak memory 199788 kb
Host smart-ea8d80c7-3c1f-4cf0-a1a4-119fb66a1cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954817727 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.uart_fifo_reset.1954817727
Directory /workspace/60.uart_fifo_reset/latest

Test location /workspace/coverage/default/60.uart_stress_all_with_rand_reset.2605274540
Short name T554
Test name
Test status
Simulation time 72317663322 ps
CPU time 683.47 seconds
Started Aug 03 04:55:26 PM PDT 24
Finished Aug 03 05:06:50 PM PDT 24
Peak memory 216420 kb
Host smart-10ae650f-d2fc-46f1-9561-6a52c1b6684a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605274540 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 60.uart_stress_all_with_rand_reset.2605274540
Directory /workspace/60.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/61.uart_fifo_reset.2503524106
Short name T575
Test name
Test status
Simulation time 26438989650 ps
CPU time 14.62 seconds
Started Aug 03 04:55:26 PM PDT 24
Finished Aug 03 04:55:41 PM PDT 24
Peak memory 200028 kb
Host smart-6e2386f1-6b0d-473a-b737-eeed8a086df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503524106 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.uart_fifo_reset.2503524106
Directory /workspace/61.uart_fifo_reset/latest

Test location /workspace/coverage/default/61.uart_stress_all_with_rand_reset.1751414050
Short name T1132
Test name
Test status
Simulation time 40027415538 ps
CPU time 480.36 seconds
Started Aug 03 04:55:28 PM PDT 24
Finished Aug 03 05:03:28 PM PDT 24
Peak memory 224708 kb
Host smart-ca9c3435-55cc-497a-89b6-a2e28fb3b76b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751414050 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 61.uart_stress_all_with_rand_reset.1751414050
Directory /workspace/61.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/62.uart_fifo_reset.3231642883
Short name T864
Test name
Test status
Simulation time 35498572201 ps
CPU time 30.51 seconds
Started Aug 03 04:55:25 PM PDT 24
Finished Aug 03 04:55:56 PM PDT 24
Peak memory 199508 kb
Host smart-dc2691bd-17c3-414c-beb0-8a47a58221af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231642883 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.uart_fifo_reset.3231642883
Directory /workspace/62.uart_fifo_reset/latest

Test location /workspace/coverage/default/62.uart_stress_all_with_rand_reset.2625984319
Short name T871
Test name
Test status
Simulation time 7705337582 ps
CPU time 106.16 seconds
Started Aug 03 04:55:27 PM PDT 24
Finished Aug 03 04:57:13 PM PDT 24
Peak memory 209020 kb
Host smart-2a12676b-c1b4-4049-9e0c-8564f2df51ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625984319 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 62.uart_stress_all_with_rand_reset.2625984319
Directory /workspace/62.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/63.uart_fifo_reset.2098371387
Short name T938
Test name
Test status
Simulation time 39785014015 ps
CPU time 14.15 seconds
Started Aug 03 04:55:27 PM PDT 24
Finished Aug 03 04:55:41 PM PDT 24
Peak memory 199904 kb
Host smart-19041e3c-d406-4c5c-9d6a-d8c66b4f6d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098371387 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.uart_fifo_reset.2098371387
Directory /workspace/63.uart_fifo_reset/latest

Test location /workspace/coverage/default/63.uart_stress_all_with_rand_reset.1961193801
Short name T60
Test name
Test status
Simulation time 120897367322 ps
CPU time 1049.66 seconds
Started Aug 03 04:55:28 PM PDT 24
Finished Aug 03 05:12:58 PM PDT 24
Peak memory 216456 kb
Host smart-906a8176-7e76-48ee-af65-ee2c373fb760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961193801 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 63.uart_stress_all_with_rand_reset.1961193801
Directory /workspace/63.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/64.uart_fifo_reset.4292058682
Short name T181
Test name
Test status
Simulation time 137199109147 ps
CPU time 61.61 seconds
Started Aug 03 04:55:29 PM PDT 24
Finished Aug 03 04:56:30 PM PDT 24
Peak memory 199900 kb
Host smart-c929505e-4b04-4c59-b96a-84b17316723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292058682 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.uart_fifo_reset.4292058682
Directory /workspace/64.uart_fifo_reset/latest

Test location /workspace/coverage/default/64.uart_stress_all_with_rand_reset.625289005
Short name T739
Test name
Test status
Simulation time 52707844537 ps
CPU time 567.61 seconds
Started Aug 03 04:55:39 PM PDT 24
Finished Aug 03 05:05:07 PM PDT 24
Peak memory 216432 kb
Host smart-cb811701-67f5-49ee-9f3b-7f2f8f8a2536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625289005 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 64.uart_stress_all_with_rand_reset.625289005
Directory /workspace/64.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/65.uart_fifo_reset.2012487750
Short name T144
Test name
Test status
Simulation time 56124114223 ps
CPU time 79.81 seconds
Started Aug 03 04:55:32 PM PDT 24
Finished Aug 03 04:56:52 PM PDT 24
Peak memory 199852 kb
Host smart-281b8f89-4d06-4a55-b005-70b7a9ad9784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012487750 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.uart_fifo_reset.2012487750
Directory /workspace/65.uart_fifo_reset/latest

Test location /workspace/coverage/default/65.uart_stress_all_with_rand_reset.577026148
Short name T52
Test name
Test status
Simulation time 307062162531 ps
CPU time 642.99 seconds
Started Aug 03 04:55:36 PM PDT 24
Finished Aug 03 05:06:20 PM PDT 24
Peak memory 214656 kb
Host smart-3f2b5cd5-e08d-42a0-aba5-6982d4b220c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577026148 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 65.uart_stress_all_with_rand_reset.577026148
Directory /workspace/65.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/66.uart_fifo_reset.54324449
Short name T475
Test name
Test status
Simulation time 41893606466 ps
CPU time 68.94 seconds
Started Aug 03 04:55:40 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 199860 kb
Host smart-7cf92915-f10e-4cfb-ae66-010ef0000fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54324449 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.uart_fifo_reset.54324449
Directory /workspace/66.uart_fifo_reset/latest

Test location /workspace/coverage/default/66.uart_stress_all_with_rand_reset.1112991215
Short name T798
Test name
Test status
Simulation time 244418951542 ps
CPU time 432.17 seconds
Started Aug 03 04:55:33 PM PDT 24
Finished Aug 03 05:02:45 PM PDT 24
Peak memory 224688 kb
Host smart-4d65fccd-c9f8-4c11-99ca-e7db5c812842
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112991215 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 66.uart_stress_all_with_rand_reset.1112991215
Directory /workspace/66.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/67.uart_fifo_reset.3936158852
Short name T308
Test name
Test status
Simulation time 106205819681 ps
CPU time 27.69 seconds
Started Aug 03 04:55:32 PM PDT 24
Finished Aug 03 04:56:00 PM PDT 24
Peak memory 199344 kb
Host smart-475d4962-e703-488f-b2a6-5ffd3760d145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936158852 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.uart_fifo_reset.3936158852
Directory /workspace/67.uart_fifo_reset/latest

Test location /workspace/coverage/default/67.uart_stress_all_with_rand_reset.1256980049
Short name T97
Test name
Test status
Simulation time 52104128448 ps
CPU time 109.03 seconds
Started Aug 03 04:55:33 PM PDT 24
Finished Aug 03 04:57:22 PM PDT 24
Peak memory 212568 kb
Host smart-ed470339-eb27-4066-a894-27952c4cdb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256980049 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 67.uart_stress_all_with_rand_reset.1256980049
Directory /workspace/67.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/68.uart_fifo_reset.2699732000
Short name T1165
Test name
Test status
Simulation time 197900712568 ps
CPU time 38.52 seconds
Started Aug 03 04:55:37 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 199892 kb
Host smart-b72ae272-db4b-4483-9fd4-0a67bf0f08b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699732000 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.uart_fifo_reset.2699732000
Directory /workspace/68.uart_fifo_reset/latest

Test location /workspace/coverage/default/68.uart_stress_all_with_rand_reset.432078893
Short name T524
Test name
Test status
Simulation time 39102036567 ps
CPU time 1206.89 seconds
Started Aug 03 04:55:32 PM PDT 24
Finished Aug 03 05:15:40 PM PDT 24
Peak memory 210504 kb
Host smart-ed0c9269-1e0d-47c6-9c3d-5e5910402d90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432078893 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 68.uart_stress_all_with_rand_reset.432078893
Directory /workspace/68.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/69.uart_fifo_reset.3529967249
Short name T1113
Test name
Test status
Simulation time 51047302074 ps
CPU time 19.12 seconds
Started Aug 03 04:55:41 PM PDT 24
Finished Aug 03 04:56:01 PM PDT 24
Peak memory 199848 kb
Host smart-105b73e8-0fb8-4fb4-975e-8e541198e2a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529967249 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.uart_fifo_reset.3529967249
Directory /workspace/69.uart_fifo_reset/latest

Test location /workspace/coverage/default/69.uart_stress_all_with_rand_reset.640366403
Short name T1039
Test name
Test status
Simulation time 42816962635 ps
CPU time 750.99 seconds
Started Aug 03 04:55:41 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 216592 kb
Host smart-5713936b-999b-44f6-8760-d14cced03c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640366403 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 69.uart_stress_all_with_rand_reset.640366403
Directory /workspace/69.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_alert_test.2757007243
Short name T937
Test name
Test status
Simulation time 23689222 ps
CPU time 0.59 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:52:00 PM PDT 24
Peak memory 195296 kb
Host smart-1ed00cdf-263c-4c90-8983-5c631459bc8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757007243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_alert_test.2757007243
Directory /workspace/7.uart_alert_test/latest

Test location /workspace/coverage/default/7.uart_fifo_full.286426854
Short name T700
Test name
Test status
Simulation time 27911778813 ps
CPU time 42.41 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:52:37 PM PDT 24
Peak memory 199704 kb
Host smart-6bc809b7-bd87-4ff9-a07b-99080deb63c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286426854 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_full.286426854
Directory /workspace/7.uart_fifo_full/latest

Test location /workspace/coverage/default/7.uart_fifo_overflow.582328410
Short name T137
Test name
Test status
Simulation time 77747649906 ps
CPU time 124.52 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:54:08 PM PDT 24
Peak memory 199880 kb
Host smart-3cfc3760-5927-43ad-9fb3-b5602d543cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582328410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_overflow.582328410
Directory /workspace/7.uart_fifo_overflow/latest

Test location /workspace/coverage/default/7.uart_fifo_reset.2666755891
Short name T432
Test name
Test status
Simulation time 12737832463 ps
CPU time 14.17 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:16 PM PDT 24
Peak memory 199832 kb
Host smart-a978c59f-c142-4a07-bb9b-01c1ec0d4c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666755891 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_fifo_reset.2666755891
Directory /workspace/7.uart_fifo_reset/latest

Test location /workspace/coverage/default/7.uart_intr.3295587548
Short name T498
Test name
Test status
Simulation time 28510368739 ps
CPU time 36.93 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:38 PM PDT 24
Peak memory 199756 kb
Host smart-c8cf0021-d44b-4718-8cf1-efaab6a1a735
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295587548 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_intr.3295587548
Directory /workspace/7.uart_intr/latest

Test location /workspace/coverage/default/7.uart_long_xfer_wo_dly.2569202692
Short name T436
Test name
Test status
Simulation time 131356106289 ps
CPU time 605.77 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 05:02:14 PM PDT 24
Peak memory 199860 kb
Host smart-5cee595d-25c3-4cb1-b3bd-c36ba99631c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2569202692 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_long_xfer_wo_dly.2569202692
Directory /workspace/7.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/7.uart_loopback.2715918239
Short name T644
Test name
Test status
Simulation time 1632067294 ps
CPU time 2.38 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:03 PM PDT 24
Peak memory 197652 kb
Host smart-1b60f3da-e647-48ee-b19e-c573dfef46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715918239 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_loopback.2715918239
Directory /workspace/7.uart_loopback/latest

Test location /workspace/coverage/default/7.uart_noise_filter.772885992
Short name T250
Test name
Test status
Simulation time 378958795257 ps
CPU time 37.96 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:46 PM PDT 24
Peak memory 208248 kb
Host smart-c0fa0718-cb65-4c77-8b54-962b07ce58af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772885992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_noise_filter.772885992
Directory /workspace/7.uart_noise_filter/latest

Test location /workspace/coverage/default/7.uart_perf.543179910
Short name T489
Test name
Test status
Simulation time 23608889609 ps
CPU time 235.95 seconds
Started Aug 03 04:52:04 PM PDT 24
Finished Aug 03 04:56:00 PM PDT 24
Peak memory 199908 kb
Host smart-79305aed-f9b8-49ec-970e-9ed579e130c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=543179910 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_perf.543179910
Directory /workspace/7.uart_perf/latest

Test location /workspace/coverage/default/7.uart_rx_oversample.1550620163
Short name T956
Test name
Test status
Simulation time 2498743013 ps
CPU time 1.68 seconds
Started Aug 03 04:51:59 PM PDT 24
Finished Aug 03 04:52:00 PM PDT 24
Peak memory 198220 kb
Host smart-27f29e4d-ad98-4fbf-b775-4a526b0f2c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1550620163 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_oversample.1550620163
Directory /workspace/7.uart_rx_oversample/latest

Test location /workspace/coverage/default/7.uart_rx_parity_err.3286324213
Short name T1118
Test name
Test status
Simulation time 10619847873 ps
CPU time 16.26 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:24 PM PDT 24
Peak memory 199832 kb
Host smart-dc82c7a4-56ac-48e4-ac7c-c354eb67cdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286324213 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_parity_err.3286324213
Directory /workspace/7.uart_rx_parity_err/latest

Test location /workspace/coverage/default/7.uart_rx_start_bit_filter.2986129469
Short name T860
Test name
Test status
Simulation time 35983629511 ps
CPU time 56.08 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:52:56 PM PDT 24
Peak memory 196048 kb
Host smart-585db9b0-3452-47eb-8f74-10dd6cc5cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986129469 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_rx_start_bit_filter.2986129469
Directory /workspace/7.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/7.uart_smoke.482128486
Short name T667
Test name
Test status
Simulation time 11098153968 ps
CPU time 11.62 seconds
Started Aug 03 04:51:52 PM PDT 24
Finished Aug 03 04:52:04 PM PDT 24
Peak memory 199460 kb
Host smart-51e4ea51-c824-442b-94a4-4d2b084abeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482128486 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_smoke.482128486
Directory /workspace/7.uart_smoke/latest

Test location /workspace/coverage/default/7.uart_stress_all.1331623224
Short name T963
Test name
Test status
Simulation time 15168856424 ps
CPU time 8.48 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:15 PM PDT 24
Peak memory 199892 kb
Host smart-0552b19e-cdf8-4b7a-8051-8551cff1ce37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331623224 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_stress_all.1331623224
Directory /workspace/7.uart_stress_all/latest

Test location /workspace/coverage/default/7.uart_stress_all_with_rand_reset.2022285710
Short name T40
Test name
Test status
Simulation time 82667987723 ps
CPU time 117.83 seconds
Started Aug 03 04:51:59 PM PDT 24
Finished Aug 03 04:53:57 PM PDT 24
Peak memory 216428 kb
Host smart-af472e8d-e20e-4afa-bf69-79a17ce45977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022285710 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 7.uart_stress_all_with_rand_reset.2022285710
Directory /workspace/7.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.uart_tx_ovrd.540079165
Short name T287
Test name
Test status
Simulation time 1588049034 ps
CPU time 3.35 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:52:04 PM PDT 24
Peak memory 199564 kb
Host smart-72ad96ae-52f6-4aa6-b430-2f61db046812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540079165 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_ovrd.540079165
Directory /workspace/7.uart_tx_ovrd/latest

Test location /workspace/coverage/default/7.uart_tx_rx.3443343611
Short name T43
Test name
Test status
Simulation time 47951462286 ps
CPU time 22.1 seconds
Started Aug 03 04:51:55 PM PDT 24
Finished Aug 03 04:52:17 PM PDT 24
Peak memory 199916 kb
Host smart-ee6bce27-0be0-4017-9350-5e4c97730b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443343611 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.uart_tx_rx.3443343611
Directory /workspace/7.uart_tx_rx/latest

Test location /workspace/coverage/default/70.uart_fifo_reset.2466773445
Short name T599
Test name
Test status
Simulation time 57620985666 ps
CPU time 17.91 seconds
Started Aug 03 04:55:40 PM PDT 24
Finished Aug 03 04:55:58 PM PDT 24
Peak memory 199860 kb
Host smart-48479071-4356-4c92-8584-16560587824f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466773445 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.uart_fifo_reset.2466773445
Directory /workspace/70.uart_fifo_reset/latest

Test location /workspace/coverage/default/70.uart_stress_all_with_rand_reset.1285090188
Short name T673
Test name
Test status
Simulation time 65716202438 ps
CPU time 257.51 seconds
Started Aug 03 04:55:40 PM PDT 24
Finished Aug 03 04:59:58 PM PDT 24
Peak memory 214860 kb
Host smart-e417f3d9-0608-468d-a66f-2638da0e102f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285090188 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 70.uart_stress_all_with_rand_reset.1285090188
Directory /workspace/70.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/71.uart_fifo_reset.1968864250
Short name T614
Test name
Test status
Simulation time 143184304193 ps
CPU time 54.6 seconds
Started Aug 03 04:55:39 PM PDT 24
Finished Aug 03 04:56:34 PM PDT 24
Peak memory 199916 kb
Host smart-f8bd5cb2-88f9-471f-a53e-c1bb89d138cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968864250 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.uart_fifo_reset.1968864250
Directory /workspace/71.uart_fifo_reset/latest

Test location /workspace/coverage/default/71.uart_stress_all_with_rand_reset.3056534261
Short name T1069
Test name
Test status
Simulation time 24124937992 ps
CPU time 487.78 seconds
Started Aug 03 04:55:45 PM PDT 24
Finished Aug 03 05:03:53 PM PDT 24
Peak memory 216416 kb
Host smart-c94365b5-906f-4307-9d41-9c9c78043d7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056534261 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 71.uart_stress_all_with_rand_reset.3056534261
Directory /workspace/71.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/72.uart_fifo_reset.1961814359
Short name T1156
Test name
Test status
Simulation time 24394935545 ps
CPU time 18.87 seconds
Started Aug 03 04:55:46 PM PDT 24
Finished Aug 03 04:56:05 PM PDT 24
Peak memory 197088 kb
Host smart-ac2c6085-1265-4a71-8fde-675dc0dae87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961814359 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.uart_fifo_reset.1961814359
Directory /workspace/72.uart_fifo_reset/latest

Test location /workspace/coverage/default/72.uart_stress_all_with_rand_reset.3026243125
Short name T1129
Test name
Test status
Simulation time 77455271781 ps
CPU time 870.86 seconds
Started Aug 03 04:55:45 PM PDT 24
Finished Aug 03 05:10:16 PM PDT 24
Peak memory 224692 kb
Host smart-bf0d2c8f-056b-43d9-9857-3927a4e5fb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026243125 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 72.uart_stress_all_with_rand_reset.3026243125
Directory /workspace/72.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/73.uart_fifo_reset.721910092
Short name T1023
Test name
Test status
Simulation time 88053019650 ps
CPU time 118.71 seconds
Started Aug 03 04:55:47 PM PDT 24
Finished Aug 03 04:57:45 PM PDT 24
Peak memory 199844 kb
Host smart-cc30213c-abcf-4f41-99b2-c42ac74b2622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721910092 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.uart_fifo_reset.721910092
Directory /workspace/73.uart_fifo_reset/latest

Test location /workspace/coverage/default/73.uart_stress_all_with_rand_reset.654540049
Short name T1044
Test name
Test status
Simulation time 173132110042 ps
CPU time 611.92 seconds
Started Aug 03 04:55:46 PM PDT 24
Finished Aug 03 05:05:58 PM PDT 24
Peak memory 216568 kb
Host smart-0eb98455-805e-400f-889f-5e35adae1039
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654540049 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 73.uart_stress_all_with_rand_reset.654540049
Directory /workspace/73.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/74.uart_fifo_reset.4700410
Short name T491
Test name
Test status
Simulation time 64628616265 ps
CPU time 27.84 seconds
Started Aug 03 04:55:47 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 199816 kb
Host smart-3bb25b95-38d5-4f55-b661-cc94d28202df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4700410 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.uart_fifo_reset.4700410
Directory /workspace/74.uart_fifo_reset/latest

Test location /workspace/coverage/default/74.uart_stress_all_with_rand_reset.4072893959
Short name T534
Test name
Test status
Simulation time 81328539073 ps
CPU time 1381.96 seconds
Started Aug 03 04:55:45 PM PDT 24
Finished Aug 03 05:18:48 PM PDT 24
Peak memory 224764 kb
Host smart-dd321b55-5b24-4184-af52-a732b9576a11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072893959 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 74.uart_stress_all_with_rand_reset.4072893959
Directory /workspace/74.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/75.uart_fifo_reset.2256989914
Short name T979
Test name
Test status
Simulation time 28141100072 ps
CPU time 21.47 seconds
Started Aug 03 04:55:54 PM PDT 24
Finished Aug 03 04:56:15 PM PDT 24
Peak memory 199904 kb
Host smart-4f31f802-3b34-4dda-971b-059ccc149267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256989914 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.uart_fifo_reset.2256989914
Directory /workspace/75.uart_fifo_reset/latest

Test location /workspace/coverage/default/75.uart_stress_all_with_rand_reset.4253794592
Short name T91
Test name
Test status
Simulation time 104933353700 ps
CPU time 269.17 seconds
Started Aug 03 04:55:53 PM PDT 24
Finished Aug 03 05:00:22 PM PDT 24
Peak memory 216504 kb
Host smart-29dcb97c-2f63-4e3b-8c99-0ed1c6171318
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253794592 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 75.uart_stress_all_with_rand_reset.4253794592
Directory /workspace/75.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/76.uart_fifo_reset.994298897
Short name T754
Test name
Test status
Simulation time 129793261559 ps
CPU time 94.57 seconds
Started Aug 03 04:55:56 PM PDT 24
Finished Aug 03 04:57:31 PM PDT 24
Peak memory 199844 kb
Host smart-35aad6a6-30eb-49c5-a9c1-ff02c7cbf01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994298897 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.uart_fifo_reset.994298897
Directory /workspace/76.uart_fifo_reset/latest

Test location /workspace/coverage/default/76.uart_stress_all_with_rand_reset.3732011433
Short name T27
Test name
Test status
Simulation time 122216709902 ps
CPU time 360.71 seconds
Started Aug 03 04:55:53 PM PDT 24
Finished Aug 03 05:01:54 PM PDT 24
Peak memory 216440 kb
Host smart-7446411b-87cd-423d-bf69-e48a523fcf15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732011433 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 76.uart_stress_all_with_rand_reset.3732011433
Directory /workspace/76.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/77.uart_fifo_reset.4267316177
Short name T22
Test name
Test status
Simulation time 112313325388 ps
CPU time 40.58 seconds
Started Aug 03 04:55:53 PM PDT 24
Finished Aug 03 04:56:33 PM PDT 24
Peak memory 199900 kb
Host smart-df6642ff-cafc-4f06-bd5c-af19ed7dbea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267316177 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.uart_fifo_reset.4267316177
Directory /workspace/77.uart_fifo_reset/latest

Test location /workspace/coverage/default/77.uart_stress_all_with_rand_reset.1784610054
Short name T801
Test name
Test status
Simulation time 905755951533 ps
CPU time 1690.23 seconds
Started Aug 03 04:55:53 PM PDT 24
Finished Aug 03 05:24:03 PM PDT 24
Peak memory 241168 kb
Host smart-fba23dd5-742a-401f-bb8d-d9108d1c81a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784610054 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 77.uart_stress_all_with_rand_reset.1784610054
Directory /workspace/77.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/78.uart_fifo_reset.3626303695
Short name T740
Test name
Test status
Simulation time 51874906551 ps
CPU time 16.76 seconds
Started Aug 03 04:55:52 PM PDT 24
Finished Aug 03 04:56:09 PM PDT 24
Peak memory 199832 kb
Host smart-b5add910-0d85-4857-aefe-dd0605186208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626303695 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.uart_fifo_reset.3626303695
Directory /workspace/78.uart_fifo_reset/latest

Test location /workspace/coverage/default/78.uart_stress_all_with_rand_reset.463745118
Short name T1079
Test name
Test status
Simulation time 17723579377 ps
CPU time 223.85 seconds
Started Aug 03 04:55:53 PM PDT 24
Finished Aug 03 04:59:36 PM PDT 24
Peak memory 208224 kb
Host smart-75c54fe7-ea6b-4a23-b780-34d03387043f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463745118 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 78.uart_stress_all_with_rand_reset.463745118
Directory /workspace/78.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/79.uart_fifo_reset.3763045821
Short name T601
Test name
Test status
Simulation time 20690579309 ps
CPU time 17.29 seconds
Started Aug 03 04:56:00 PM PDT 24
Finished Aug 03 04:56:18 PM PDT 24
Peak memory 199784 kb
Host smart-291f98b7-fb67-4de9-8892-30fe57d620ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763045821 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.uart_fifo_reset.3763045821
Directory /workspace/79.uart_fifo_reset/latest

Test location /workspace/coverage/default/79.uart_stress_all_with_rand_reset.2441846018
Short name T1116
Test name
Test status
Simulation time 83781383236 ps
CPU time 209.94 seconds
Started Aug 03 04:55:57 PM PDT 24
Finished Aug 03 04:59:27 PM PDT 24
Peak memory 215600 kb
Host smart-a3501116-39fa-41ae-836a-02f37480e354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441846018 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 79.uart_stress_all_with_rand_reset.2441846018
Directory /workspace/79.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_alert_test.170748934
Short name T1109
Test name
Test status
Simulation time 22156122 ps
CPU time 0.64 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:52:01 PM PDT 24
Peak memory 195204 kb
Host smart-09033874-2ee3-4400-afbe-b0e86dba0f61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170748934 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_alert_test.170748934
Directory /workspace/8.uart_alert_test/latest

Test location /workspace/coverage/default/8.uart_fifo_full.3700231888
Short name T908
Test name
Test status
Simulation time 340022770370 ps
CPU time 250.64 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:56:11 PM PDT 24
Peak memory 199864 kb
Host smart-056f5456-7164-4a7d-a26e-68cd77fe964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700231888 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_full.3700231888
Directory /workspace/8.uart_fifo_full/latest

Test location /workspace/coverage/default/8.uart_fifo_overflow.4002062221
Short name T295
Test name
Test status
Simulation time 215982836713 ps
CPU time 31.93 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:40 PM PDT 24
Peak memory 199940 kb
Host smart-68941e8c-1cd8-4eb9-945b-c5a2488c1478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002062221 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_overflow.4002062221
Directory /workspace/8.uart_fifo_overflow/latest

Test location /workspace/coverage/default/8.uart_fifo_reset.3019273174
Short name T888
Test name
Test status
Simulation time 60088814648 ps
CPU time 48.93 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:57 PM PDT 24
Peak memory 199912 kb
Host smart-512c7184-cf0d-4a50-9802-f08e7e651c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019273174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_fifo_reset.3019273174
Directory /workspace/8.uart_fifo_reset/latest

Test location /workspace/coverage/default/8.uart_intr.4152012116
Short name T4
Test name
Test status
Simulation time 5774245174 ps
CPU time 2.45 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:52:06 PM PDT 24
Peak memory 196828 kb
Host smart-f9bc8293-9a89-4270-bfc2-e4edb330ab05
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152012116 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_intr.4152012116
Directory /workspace/8.uart_intr/latest

Test location /workspace/coverage/default/8.uart_long_xfer_wo_dly.2422176196
Short name T710
Test name
Test status
Simulation time 59935120727 ps
CPU time 342.28 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:57:49 PM PDT 24
Peak memory 199800 kb
Host smart-1fdf75f0-49f3-44c8-ad1a-d7d31446561b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2422176196 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_long_xfer_wo_dly.2422176196
Directory /workspace/8.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/8.uart_loopback.2225376383
Short name T881
Test name
Test status
Simulation time 2755959087 ps
CPU time 2.26 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 197540 kb
Host smart-de0d8854-0802-47e8-9ef2-2b0790d8132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225376383 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_loopback.2225376383
Directory /workspace/8.uart_loopback/latest

Test location /workspace/coverage/default/8.uart_noise_filter.2538596093
Short name T776
Test name
Test status
Simulation time 19394480581 ps
CPU time 27.39 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:52:35 PM PDT 24
Peak memory 197756 kb
Host smart-6e3230a8-b80d-4906-ac69-91d4cefcafcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538596093 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_noise_filter.2538596093
Directory /workspace/8.uart_noise_filter/latest

Test location /workspace/coverage/default/8.uart_perf.674463420
Short name T341
Test name
Test status
Simulation time 7167166955 ps
CPU time 210.21 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:55:37 PM PDT 24
Peak memory 199672 kb
Host smart-650e748c-bce7-4f61-9865-25312f4aece9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=674463420 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_perf.674463420
Directory /workspace/8.uart_perf/latest

Test location /workspace/coverage/default/8.uart_rx_oversample.2459280837
Short name T334
Test name
Test status
Simulation time 2836431735 ps
CPU time 22.11 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:30 PM PDT 24
Peak memory 199040 kb
Host smart-2fc3b5a8-6865-4da3-8b7d-3dac84e5fd17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2459280837 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_oversample.2459280837
Directory /workspace/8.uart_rx_oversample/latest

Test location /workspace/coverage/default/8.uart_rx_parity_err.2763595490
Short name T582
Test name
Test status
Simulation time 12592010908 ps
CPU time 11.08 seconds
Started Aug 03 04:52:02 PM PDT 24
Finished Aug 03 04:52:14 PM PDT 24
Peak memory 199812 kb
Host smart-cd20b9e4-3f83-44fc-af17-b02c61540886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763595490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_parity_err.2763595490
Directory /workspace/8.uart_rx_parity_err/latest

Test location /workspace/coverage/default/8.uart_rx_start_bit_filter.1946013174
Short name T1095
Test name
Test status
Simulation time 4566818418 ps
CPU time 7.93 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:52:13 PM PDT 24
Peak memory 196424 kb
Host smart-2a6e8b19-e6a8-459d-83fe-1950d1456368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946013174 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_rx_start_bit_filter.1946013174
Directory /workspace/8.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/8.uart_smoke.340148992
Short name T890
Test name
Test status
Simulation time 283378178 ps
CPU time 1 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:09 PM PDT 24
Peak memory 198252 kb
Host smart-24725b04-d19a-4dad-ad29-3c2f5ae7df6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340148992 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_smoke.340148992
Directory /workspace/8.uart_smoke/latest

Test location /workspace/coverage/default/8.uart_stress_all.3121421851
Short name T910
Test name
Test status
Simulation time 278173350555 ps
CPU time 475.24 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:59:56 PM PDT 24
Peak memory 199904 kb
Host smart-1158f670-d93e-4aa7-8ba6-1523e9222561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121421851 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_stress_all.3121421851
Directory /workspace/8.uart_stress_all/latest

Test location /workspace/coverage/default/8.uart_stress_all_with_rand_reset.336898017
Short name T49
Test name
Test status
Simulation time 110504576195 ps
CPU time 237.36 seconds
Started Aug 03 04:52:07 PM PDT 24
Finished Aug 03 04:56:04 PM PDT 24
Peak memory 216372 kb
Host smart-0d182fcd-9d64-4154-9e3b-c6020d127c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336898017 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 8.uart_stress_all_with_rand_reset.336898017
Directory /workspace/8.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.uart_tx_ovrd.3927985087
Short name T23
Test name
Test status
Simulation time 978195867 ps
CPU time 2.42 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 198692 kb
Host smart-fe890583-0b00-4626-a76c-1bab4f95262e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927985087 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_ovrd.3927985087
Directory /workspace/8.uart_tx_ovrd/latest

Test location /workspace/coverage/default/8.uart_tx_rx.3160840490
Short name T449
Test name
Test status
Simulation time 167539313185 ps
CPU time 44.74 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:46 PM PDT 24
Peak memory 199836 kb
Host smart-dc9d6d92-0f04-4d52-a3d8-e0015cb01f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160840490 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.uart_tx_rx.3160840490
Directory /workspace/8.uart_tx_rx/latest

Test location /workspace/coverage/default/80.uart_fifo_reset.2147530333
Short name T237
Test name
Test status
Simulation time 50140711078 ps
CPU time 22.12 seconds
Started Aug 03 04:55:59 PM PDT 24
Finished Aug 03 04:56:21 PM PDT 24
Peak memory 199880 kb
Host smart-3ca7d3fc-355d-4d8f-89c6-ae2740fc429a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147530333 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.uart_fifo_reset.2147530333
Directory /workspace/80.uart_fifo_reset/latest

Test location /workspace/coverage/default/80.uart_stress_all_with_rand_reset.2821213603
Short name T746
Test name
Test status
Simulation time 71419741638 ps
CPU time 774.17 seconds
Started Aug 03 04:55:59 PM PDT 24
Finished Aug 03 05:08:53 PM PDT 24
Peak memory 216392 kb
Host smart-ae993473-c57f-47d7-a577-225a3981a3ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821213603 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 80.uart_stress_all_with_rand_reset.2821213603
Directory /workspace/80.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/81.uart_fifo_reset.4267249395
Short name T800
Test name
Test status
Simulation time 37617519776 ps
CPU time 22.52 seconds
Started Aug 03 04:55:58 PM PDT 24
Finished Aug 03 04:56:21 PM PDT 24
Peak memory 199892 kb
Host smart-ce195d11-cd75-4317-a318-b83d0b4f121b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267249395 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.uart_fifo_reset.4267249395
Directory /workspace/81.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_fifo_reset.2857451263
Short name T762
Test name
Test status
Simulation time 47482120184 ps
CPU time 19.4 seconds
Started Aug 03 04:55:58 PM PDT 24
Finished Aug 03 04:56:17 PM PDT 24
Peak memory 199908 kb
Host smart-42cbe958-cc8d-4135-b68a-40967701f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857451263 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.uart_fifo_reset.2857451263
Directory /workspace/82.uart_fifo_reset/latest

Test location /workspace/coverage/default/82.uart_stress_all_with_rand_reset.1541608135
Short name T59
Test name
Test status
Simulation time 68961996419 ps
CPU time 482.16 seconds
Started Aug 03 04:55:58 PM PDT 24
Finished Aug 03 05:04:00 PM PDT 24
Peak memory 225820 kb
Host smart-f79ec731-95f2-4cf2-a63d-d88f4df44633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541608135 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 82.uart_stress_all_with_rand_reset.1541608135
Directory /workspace/82.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/83.uart_fifo_reset.3823992678
Short name T220
Test name
Test status
Simulation time 104673657158 ps
CPU time 106.77 seconds
Started Aug 03 04:55:59 PM PDT 24
Finished Aug 03 04:57:46 PM PDT 24
Peak memory 199932 kb
Host smart-05891786-93fe-4b1a-922f-124f6fae6603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823992678 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.uart_fifo_reset.3823992678
Directory /workspace/83.uart_fifo_reset/latest

Test location /workspace/coverage/default/83.uart_stress_all_with_rand_reset.2654388268
Short name T51
Test name
Test status
Simulation time 240195455010 ps
CPU time 657.06 seconds
Started Aug 03 04:56:01 PM PDT 24
Finished Aug 03 05:06:58 PM PDT 24
Peak memory 216552 kb
Host smart-ed5db3db-0b8d-4cd1-b5ed-2c9cfef5d992
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654388268 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 83.uart_stress_all_with_rand_reset.2654388268
Directory /workspace/83.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/84.uart_fifo_reset.2178985275
Short name T874
Test name
Test status
Simulation time 48158621806 ps
CPU time 70.28 seconds
Started Aug 03 04:55:57 PM PDT 24
Finished Aug 03 04:57:07 PM PDT 24
Peak memory 199592 kb
Host smart-90835d56-dc7a-446c-8627-0bd472c69ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178985275 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.uart_fifo_reset.2178985275
Directory /workspace/84.uart_fifo_reset/latest

Test location /workspace/coverage/default/84.uart_stress_all_with_rand_reset.4147972576
Short name T1136
Test name
Test status
Simulation time 152974857878 ps
CPU time 803.81 seconds
Started Aug 03 04:55:59 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 224724 kb
Host smart-05a62606-9cc7-4860-ac8b-7846172b954d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147972576 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 84.uart_stress_all_with_rand_reset.4147972576
Directory /workspace/84.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/85.uart_fifo_reset.3399732939
Short name T591
Test name
Test status
Simulation time 30879018923 ps
CPU time 12.52 seconds
Started Aug 03 04:55:59 PM PDT 24
Finished Aug 03 04:56:11 PM PDT 24
Peak memory 199816 kb
Host smart-49ef1725-f371-4dd2-afd8-72e26cc60979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399732939 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.uart_fifo_reset.3399732939
Directory /workspace/85.uart_fifo_reset/latest

Test location /workspace/coverage/default/85.uart_stress_all_with_rand_reset.3654293585
Short name T666
Test name
Test status
Simulation time 113330775160 ps
CPU time 231.42 seconds
Started Aug 03 04:55:58 PM PDT 24
Finished Aug 03 04:59:49 PM PDT 24
Peak memory 216280 kb
Host smart-4a3a5dda-942c-4e47-8031-81f667eae927
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654293585 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 85.uart_stress_all_with_rand_reset.3654293585
Directory /workspace/85.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/86.uart_fifo_reset.785458807
Short name T483
Test name
Test status
Simulation time 11894886926 ps
CPU time 35.38 seconds
Started Aug 03 04:55:58 PM PDT 24
Finished Aug 03 04:56:34 PM PDT 24
Peak memory 199896 kb
Host smart-d7bd14a4-8515-4534-8789-30e4d69f058a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785458807 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.uart_fifo_reset.785458807
Directory /workspace/86.uart_fifo_reset/latest

Test location /workspace/coverage/default/86.uart_stress_all_with_rand_reset.2834322180
Short name T1083
Test name
Test status
Simulation time 138508452857 ps
CPU time 1377.84 seconds
Started Aug 03 04:56:05 PM PDT 24
Finished Aug 03 05:19:03 PM PDT 24
Peak memory 229956 kb
Host smart-57ec4ed1-5885-4cfd-9b57-223ea82e5b62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834322180 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 86.uart_stress_all_with_rand_reset.2834322180
Directory /workspace/86.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.uart_fifo_reset.2971581792
Short name T124
Test name
Test status
Simulation time 35439154438 ps
CPU time 15.51 seconds
Started Aug 03 04:56:04 PM PDT 24
Finished Aug 03 04:56:20 PM PDT 24
Peak memory 199936 kb
Host smart-0d87b9e5-81db-4565-9129-37f559773795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971581792 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.uart_fifo_reset.2971581792
Directory /workspace/87.uart_fifo_reset/latest

Test location /workspace/coverage/default/87.uart_stress_all_with_rand_reset.1741943295
Short name T1007
Test name
Test status
Simulation time 40109650463 ps
CPU time 323.78 seconds
Started Aug 03 04:56:04 PM PDT 24
Finished Aug 03 05:01:28 PM PDT 24
Peak memory 216400 kb
Host smart-96ce0ea9-1276-4f3c-9794-284aff509c51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741943295 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 87.uart_stress_all_with_rand_reset.1741943295
Directory /workspace/87.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/88.uart_fifo_reset.2901919942
Short name T163
Test name
Test status
Simulation time 141163616148 ps
CPU time 52.76 seconds
Started Aug 03 04:56:04 PM PDT 24
Finished Aug 03 04:56:56 PM PDT 24
Peak memory 199784 kb
Host smart-ea7e797c-0244-489f-8849-473b5475a0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901919942 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.uart_fifo_reset.2901919942
Directory /workspace/88.uart_fifo_reset/latest

Test location /workspace/coverage/default/88.uart_stress_all_with_rand_reset.160702460
Short name T93
Test name
Test status
Simulation time 115706586375 ps
CPU time 716.17 seconds
Started Aug 03 04:56:05 PM PDT 24
Finished Aug 03 05:08:01 PM PDT 24
Peak memory 216356 kb
Host smart-3eeb66f4-2293-4694-8d16-5af80631935b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160702460 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 88.uart_stress_all_with_rand_reset.160702460
Directory /workspace/88.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/89.uart_fifo_reset.1365836508
Short name T1005
Test name
Test status
Simulation time 196220898496 ps
CPU time 30.79 seconds
Started Aug 03 04:56:04 PM PDT 24
Finished Aug 03 04:56:35 PM PDT 24
Peak memory 199860 kb
Host smart-0b2f9b93-9fe6-4ff3-9472-9a0101415f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365836508 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.uart_fifo_reset.1365836508
Directory /workspace/89.uart_fifo_reset/latest

Test location /workspace/coverage/default/89.uart_stress_all_with_rand_reset.1158637819
Short name T1173
Test name
Test status
Simulation time 55595273706 ps
CPU time 767.82 seconds
Started Aug 03 04:56:05 PM PDT 24
Finished Aug 03 05:08:53 PM PDT 24
Peak memory 216436 kb
Host smart-cfb0df6e-778f-4269-a3c2-b9d3d6ff6826
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158637819 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 89.uart_stress_all_with_rand_reset.1158637819
Directory /workspace/89.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_alert_test.2794077292
Short name T729
Test name
Test status
Simulation time 47666113 ps
CPU time 0.56 seconds
Started Aug 03 04:52:10 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 195252 kb
Host smart-13e07536-e83f-4030-81c9-fed75fd3d2d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794077292 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_alert_test.2794077292
Directory /workspace/9.uart_alert_test/latest

Test location /workspace/coverage/default/9.uart_fifo_full.880220639
Short name T1028
Test name
Test status
Simulation time 82936666109 ps
CPU time 152.3 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:54:33 PM PDT 24
Peak memory 199824 kb
Host smart-38f9cbaf-3d8a-4cad-b022-087e51e38358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880220639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_full.880220639
Directory /workspace/9.uart_fifo_full/latest

Test location /workspace/coverage/default/9.uart_fifo_overflow.3920548639
Short name T1035
Test name
Test status
Simulation time 20540315633 ps
CPU time 15.84 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:52:16 PM PDT 24
Peak memory 199636 kb
Host smart-641d8b56-634b-436f-ba13-4cec53c7a769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920548639 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_overflow.3920548639
Directory /workspace/9.uart_fifo_overflow/latest

Test location /workspace/coverage/default/9.uart_fifo_reset.1296297614
Short name T1134
Test name
Test status
Simulation time 189084962906 ps
CPU time 294.79 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:56:58 PM PDT 24
Peak memory 199888 kb
Host smart-6e645e9e-2d1d-4466-915a-54ac0cbf1929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296297614 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_fifo_reset.1296297614
Directory /workspace/9.uart_fifo_reset/latest

Test location /workspace/coverage/default/9.uart_intr.2943359175
Short name T404
Test name
Test status
Simulation time 26331187810 ps
CPU time 20.3 seconds
Started Aug 03 04:52:05 PM PDT 24
Finished Aug 03 04:52:26 PM PDT 24
Peak memory 199740 kb
Host smart-7aed76b1-f678-43d1-ab11-856f69d10254
User root
Command /workspace/default/simv +test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943359175 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_intr.2943359175
Directory /workspace/9.uart_intr/latest

Test location /workspace/coverage/default/9.uart_long_xfer_wo_dly.2471036578
Short name T911
Test name
Test status
Simulation time 118310446775 ps
CPU time 259.51 seconds
Started Aug 03 04:52:02 PM PDT 24
Finished Aug 03 04:56:21 PM PDT 24
Peak memory 199812 kb
Host smart-1594b46a-2ec1-46e5-bf64-e2e127a56f5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2471036578 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_long_xfer_wo_dly.2471036578
Directory /workspace/9.uart_long_xfer_wo_dly/latest

Test location /workspace/coverage/default/9.uart_loopback.852982169
Short name T335
Test name
Test status
Simulation time 5647578958 ps
CPU time 3.42 seconds
Started Aug 03 04:52:03 PM PDT 24
Finished Aug 03 04:52:07 PM PDT 24
Peak memory 198560 kb
Host smart-d2f84cc9-acb1-409c-b03f-3255167adfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852982169 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_loopback.852982169
Directory /workspace/9.uart_loopback/latest

Test location /workspace/coverage/default/9.uart_noise_filter.1243631623
Short name T987
Test name
Test status
Simulation time 47499063251 ps
CPU time 21.45 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:29 PM PDT 24
Peak memory 199840 kb
Host smart-e319c48e-24bf-4f1d-a4b1-e50d5c5a1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243631623 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_noise_filter.1243631623
Directory /workspace/9.uart_noise_filter/latest

Test location /workspace/coverage/default/9.uart_perf.1626501780
Short name T506
Test name
Test status
Simulation time 13727375090 ps
CPU time 692.07 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 05:03:40 PM PDT 24
Peak memory 199888 kb
Host smart-03f3f0cd-c461-488b-bc90-8e568a566e50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626501780 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_perf.1626501780
Directory /workspace/9.uart_perf/latest

Test location /workspace/coverage/default/9.uart_rx_oversample.74005972
Short name T1016
Test name
Test status
Simulation time 4583126624 ps
CPU time 2.99 seconds
Started Aug 03 04:52:02 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 198636 kb
Host smart-40fb5790-d0f8-4845-b0a1-73d0bab761bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74005972 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_oversample.74005972
Directory /workspace/9.uart_rx_oversample/latest

Test location /workspace/coverage/default/9.uart_rx_parity_err.1781306538
Short name T465
Test name
Test status
Simulation time 385948121650 ps
CPU time 91.59 seconds
Started Aug 03 04:52:04 PM PDT 24
Finished Aug 03 04:53:35 PM PDT 24
Peak memory 199916 kb
Host smart-6b64dca0-0265-4e71-a9c1-bef6fe825b0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781306538 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_parity_err.1781306538
Directory /workspace/9.uart_rx_parity_err/latest

Test location /workspace/coverage/default/9.uart_rx_start_bit_filter.3464278718
Short name T555
Test name
Test status
Simulation time 4566710861 ps
CPU time 2.4 seconds
Started Aug 03 04:52:08 PM PDT 24
Finished Aug 03 04:52:10 PM PDT 24
Peak memory 196432 kb
Host smart-a3ea541b-1c52-44ef-b3cc-68fafb32ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464278718 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_rx_start_bit_filter.3464278718
Directory /workspace/9.uart_rx_start_bit_filter/latest

Test location /workspace/coverage/default/9.uart_smoke.4285949655
Short name T1050
Test name
Test status
Simulation time 1006471758 ps
CPU time 1.62 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:02 PM PDT 24
Peak memory 199844 kb
Host smart-6884a84c-6caf-45cb-867f-6ae5f434ded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285949655 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_smoke.4285949655
Directory /workspace/9.uart_smoke/latest

Test location /workspace/coverage/default/9.uart_stress_all.3729830327
Short name T654
Test name
Test status
Simulation time 277053628258 ps
CPU time 900.76 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 05:07:01 PM PDT 24
Peak memory 208256 kb
Host smart-a645faed-ee60-4853-a18f-6deca257b9a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729830327 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_stress_all.3729830327
Directory /workspace/9.uart_stress_all/latest

Test location /workspace/coverage/default/9.uart_stress_all_with_rand_reset.2171365452
Short name T1102
Test name
Test status
Simulation time 32090362376 ps
CPU time 326.22 seconds
Started Aug 03 04:52:00 PM PDT 24
Finished Aug 03 04:57:27 PM PDT 24
Peak memory 216468 kb
Host smart-ac062e58-40e1-41e9-b88f-7ef21f2f54a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171365452 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 9.uart_stress_all_with_rand_reset.2171365452
Directory /workspace/9.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.uart_tx_ovrd.2102329890
Short name T585
Test name
Test status
Simulation time 902148186 ps
CPU time 4.18 seconds
Started Aug 03 04:52:01 PM PDT 24
Finished Aug 03 04:52:05 PM PDT 24
Peak memory 199596 kb
Host smart-d0875d41-f804-4dff-9b92-5c604f2c4a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102329890 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_ovrd.2102329890
Directory /workspace/9.uart_tx_ovrd/latest

Test location /workspace/coverage/default/9.uart_tx_rx.3352225522
Short name T752
Test name
Test status
Simulation time 35370974541 ps
CPU time 32.39 seconds
Started Aug 03 04:52:02 PM PDT 24
Finished Aug 03 04:52:34 PM PDT 24
Peak memory 199920 kb
Host smart-1df1b8eb-f775-421b-b9e8-4c007b921706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352225522 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.uart_tx_rx.3352225522
Directory /workspace/9.uart_tx_rx/latest

Test location /workspace/coverage/default/90.uart_fifo_reset.4045909743
Short name T206
Test name
Test status
Simulation time 20205204319 ps
CPU time 31.61 seconds
Started Aug 03 04:56:08 PM PDT 24
Finished Aug 03 04:56:39 PM PDT 24
Peak memory 199812 kb
Host smart-2a060cf2-a3f9-4e2a-8f63-3cfbb8cc73b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045909743 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.uart_fifo_reset.4045909743
Directory /workspace/90.uart_fifo_reset/latest

Test location /workspace/coverage/default/90.uart_stress_all_with_rand_reset.166307240
Short name T831
Test name
Test status
Simulation time 53273540951 ps
CPU time 573.29 seconds
Started Aug 03 04:56:03 PM PDT 24
Finished Aug 03 05:05:37 PM PDT 24
Peak memory 216428 kb
Host smart-f8a9ffef-1cb3-4584-b639-ed56dce7abfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166307240 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 90.uart_stress_all_with_rand_reset.166307240
Directory /workspace/90.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/91.uart_fifo_reset.1971009078
Short name T226
Test name
Test status
Simulation time 74430827805 ps
CPU time 50.21 seconds
Started Aug 03 04:56:12 PM PDT 24
Finished Aug 03 04:57:02 PM PDT 24
Peak memory 199880 kb
Host smart-93666f0f-db70-41ec-8789-10fbb2b77fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971009078 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.uart_fifo_reset.1971009078
Directory /workspace/91.uart_fifo_reset/latest

Test location /workspace/coverage/default/91.uart_stress_all_with_rand_reset.1755164601
Short name T36
Test name
Test status
Simulation time 40158857756 ps
CPU time 156.94 seconds
Started Aug 03 04:56:12 PM PDT 24
Finished Aug 03 04:58:49 PM PDT 24
Peak memory 216392 kb
Host smart-c2d7e3e0-f262-426e-a933-95664d59c9cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755164601 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 91.uart_stress_all_with_rand_reset.1755164601
Directory /workspace/91.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/92.uart_fifo_reset.4283152067
Short name T837
Test name
Test status
Simulation time 50031515206 ps
CPU time 40.91 seconds
Started Aug 03 04:56:10 PM PDT 24
Finished Aug 03 04:56:51 PM PDT 24
Peak memory 199888 kb
Host smart-0b0c15ae-6ee3-4bea-980e-bdbf031d895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283152067 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.uart_fifo_reset.4283152067
Directory /workspace/92.uart_fifo_reset/latest

Test location /workspace/coverage/default/92.uart_stress_all_with_rand_reset.1217505556
Short name T1040
Test name
Test status
Simulation time 368877742059 ps
CPU time 470.28 seconds
Started Aug 03 04:56:13 PM PDT 24
Finished Aug 03 05:04:03 PM PDT 24
Peak memory 224708 kb
Host smart-13d3b39a-c6d2-4855-a67f-d043f6fc4584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217505556 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 92.uart_stress_all_with_rand_reset.1217505556
Directory /workspace/92.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/93.uart_fifo_reset.3150265313
Short name T194
Test name
Test status
Simulation time 50240306530 ps
CPU time 133.59 seconds
Started Aug 03 04:56:10 PM PDT 24
Finished Aug 03 04:58:23 PM PDT 24
Peak memory 199880 kb
Host smart-1ecea028-5812-4eb7-b9d1-959509a68e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150265313 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.uart_fifo_reset.3150265313
Directory /workspace/93.uart_fifo_reset/latest

Test location /workspace/coverage/default/93.uart_stress_all_with_rand_reset.1056742818
Short name T50
Test name
Test status
Simulation time 55917278496 ps
CPU time 675.36 seconds
Started Aug 03 04:56:10 PM PDT 24
Finished Aug 03 05:07:26 PM PDT 24
Peak memory 216416 kb
Host smart-4d6a5c9f-c3a0-427e-9488-d7d06dfd0655
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056742818 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 93.uart_stress_all_with_rand_reset.1056742818
Directory /workspace/93.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/94.uart_fifo_reset.2300691568
Short name T195
Test name
Test status
Simulation time 117646927843 ps
CPU time 37.38 seconds
Started Aug 03 04:56:11 PM PDT 24
Finished Aug 03 04:56:49 PM PDT 24
Peak memory 199788 kb
Host smart-1cdc01f9-04ae-4388-b509-6a3d1c184fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300691568 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.uart_fifo_reset.2300691568
Directory /workspace/94.uart_fifo_reset/latest

Test location /workspace/coverage/default/94.uart_stress_all_with_rand_reset.3215228041
Short name T35
Test name
Test status
Simulation time 47526339217 ps
CPU time 752.44 seconds
Started Aug 03 04:56:11 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 216488 kb
Host smart-fabb09c2-62ab-4393-8e60-f076e76ecc93
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215228041 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 94.uart_stress_all_with_rand_reset.3215228041
Directory /workspace/94.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/95.uart_fifo_reset.3419160392
Short name T104
Test name
Test status
Simulation time 154613808649 ps
CPU time 339.69 seconds
Started Aug 03 04:56:12 PM PDT 24
Finished Aug 03 05:01:52 PM PDT 24
Peak memory 199872 kb
Host smart-2765d6f3-c8d2-427c-8a08-2e167f0d3f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419160392 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.uart_fifo_reset.3419160392
Directory /workspace/95.uart_fifo_reset/latest

Test location /workspace/coverage/default/95.uart_stress_all_with_rand_reset.3884525115
Short name T694
Test name
Test status
Simulation time 55880657762 ps
CPU time 646.51 seconds
Started Aug 03 04:56:13 PM PDT 24
Finished Aug 03 05:07:00 PM PDT 24
Peak memory 216452 kb
Host smart-cfe73543-9942-4638-be72-41e7a852a9c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884525115 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 95.uart_stress_all_with_rand_reset.3884525115
Directory /workspace/95.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/96.uart_fifo_reset.3158185583
Short name T830
Test name
Test status
Simulation time 136010596694 ps
CPU time 279.79 seconds
Started Aug 03 04:56:10 PM PDT 24
Finished Aug 03 05:00:50 PM PDT 24
Peak memory 199920 kb
Host smart-9011e8e0-1f24-4b1c-bed0-5ea68f3e695d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158185583 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.uart_fifo_reset.3158185583
Directory /workspace/96.uart_fifo_reset/latest

Test location /workspace/coverage/default/96.uart_stress_all_with_rand_reset.3134460642
Short name T403
Test name
Test status
Simulation time 55167093056 ps
CPU time 272.68 seconds
Started Aug 03 04:56:18 PM PDT 24
Finished Aug 03 05:00:50 PM PDT 24
Peak memory 216500 kb
Host smart-9cd9408c-c09a-4e0b-997b-719f14a970d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134460642 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 96.uart_stress_all_with_rand_reset.3134460642
Directory /workspace/96.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/97.uart_fifo_reset.984601464
Short name T999
Test name
Test status
Simulation time 155366956116 ps
CPU time 328.15 seconds
Started Aug 03 04:56:17 PM PDT 24
Finished Aug 03 05:01:46 PM PDT 24
Peak memory 199824 kb
Host smart-40971a50-9f75-47dd-bc8b-47bda7415d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984601464 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.uart_fifo_reset.984601464
Directory /workspace/97.uart_fifo_reset/latest

Test location /workspace/coverage/default/97.uart_stress_all_with_rand_reset.229821498
Short name T980
Test name
Test status
Simulation time 58069821110 ps
CPU time 137.22 seconds
Started Aug 03 04:56:18 PM PDT 24
Finished Aug 03 04:58:35 PM PDT 24
Peak memory 211212 kb
Host smart-fe4ab770-b268-4bd4-b838-44034e2fddaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229821498 -assert nopostpr
oc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v
db -cm_log /dev/null -cm_name 97.uart_stress_all_with_rand_reset.229821498
Directory /workspace/97.uart_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/98.uart_fifo_reset.1149645243
Short name T119
Test name
Test status
Simulation time 23769628657 ps
CPU time 38.78 seconds
Started Aug 03 04:56:19 PM PDT 24
Finished Aug 03 04:56:58 PM PDT 24
Peak memory 199824 kb
Host smart-a5891236-a63f-49be-ad68-748815ad7246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149645243 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.uart_fifo_reset.1149645243
Directory /workspace/98.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_fifo_reset.1578902599
Short name T522
Test name
Test status
Simulation time 154714206395 ps
CPU time 15.61 seconds
Started Aug 03 04:56:16 PM PDT 24
Finished Aug 03 04:56:32 PM PDT 24
Peak memory 199668 kb
Host smart-9becb158-7bf4-4913-a90a-21381eea7124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578902599 -assert nopostproc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.uart_fifo_reset.1578902599
Directory /workspace/99.uart_fifo_reset/latest

Test location /workspace/coverage/default/99.uart_stress_all_with_rand_reset.2638666528
Short name T320
Test name
Test status
Simulation time 14615108968 ps
CPU time 196.4 seconds
Started Aug 03 04:56:17 PM PDT 24
Finished Aug 03 04:59:33 PM PDT 24
Peak memory 215644 kb
Host smart-b32d83ed-e781-4495-af79-b9809f493962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638666528 -assert nopostp
roc +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.
vdb -cm_log /dev/null -cm_name 99.uart_stress_all_with_rand_reset.2638666528
Directory /workspace/99.uart_stress_all_with_rand_reset/latest
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