Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	36	0	36	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	9	0	9	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=8}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	36	0	36	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	106185	1			T1	5		T2	18		T3	113
all_values[1]	106185	1			T1	5		T2	18		T3	113
all_values[2]	106185	1			T1	5		T2	18		T3	113
all_values[3]	106185	1			T1	5		T2	18		T3	113
all_values[4]	106185	1			T1	5		T2	18		T3	113
all_values[5]	106185	1			T1	5		T2	18		T3	113
all_values[6]	106185	1			T1	5		T2	18		T3	113
all_values[7]	106185	1			T1	5		T2	18		T3	113
all_values[8]	106185	1			T1	5		T2	18		T3	113

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

486083

1

T1

20

T2

92

T3

645

auto[1]

469582

1

T1

25

T2

70

T3

372

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

859704

1

T1

35

T2

118

T3

823

auto[1]

95961

1

T1

10

T2

44

T3

194

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	0	36	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	29248	1			T3	13		T4	90		T6	1
all_values[0]	auto[0]	auto[1]	23688	1			T2	9		T3	92		T4	95
all_values[0]	auto[1]	auto[0]	29709	1			T1	1		T3	5		T4	46
all_values[0]	auto[1]	auto[1]	23540	1			T1	4		T2	9		T3	3
all_values[1]	auto[0]	auto[0]	50834	1			T1	2		T2	15		T3	92
all_values[1]	auto[0]	auto[1]	1719	1			T4	19		T9	10		T43	3
all_values[1]	auto[1]	auto[0]	52109	1			T1	3		T2	3		T3	21
all_values[1]	auto[1]	auto[1]	1523	1			T4	5		T6	5		T41	2
all_values[2]	auto[0]	auto[0]	51030	1			T2	7		T4	65		T5	4
all_values[2]	auto[0]	auto[1]	2746	1			T2	6		T4	8		T5	3
all_values[2]	auto[1]	auto[0]	49937	1			T1	3		T2	3		T3	109
all_values[2]	auto[1]	auto[1]	2472	1			T1	2		T2	2		T3	4
all_values[3]	auto[0]	auto[0]	56591	1			T2	5		T3	113		T4	118
all_values[3]	auto[0]	auto[1]	288	1			T4	5		T12	1		T38	2
all_values[3]	auto[1]	auto[0]	49003	1			T1	5		T2	13		T4	148
all_values[3]	auto[1]	auto[1]	303	1			T4	5		T6	1		T11	2
all_values[4]	auto[0]	auto[0]	52433	1			T1	3		T2	14		T3	8
all_values[4]	auto[0]	auto[1]	421	1			T4	14		T12	6		T29	4
all_values[4]	auto[1]	auto[0]	52916	1			T1	2		T2	4		T3	105
all_values[4]	auto[1]	auto[1]	415	1			T4	9		T13	6		T29	1
all_values[5]	auto[0]	auto[0]	56656	1			T1	5		T2	1		T3	107
all_values[5]	auto[0]	auto[1]	161	1			T4	1		T29	1		T30	5
all_values[5]	auto[1]	auto[0]	49175	1			T2	17		T3	6		T4	265
all_values[5]	auto[1]	auto[1]	193	1			T4	2		T30	3		T84	4
all_values[6]	auto[0]	auto[0]	52298	1			T1	3		T2	17		T3	15
all_values[6]	auto[0]	auto[1]	169	1			T29	1		T30	2		T84	1
all_values[6]	auto[1]	auto[0]	53539	1			T1	2		T2	1		T3	98
all_values[6]	auto[1]	auto[1]	179	1			T4	2		T29	1		T30	11
all_values[7]	auto[0]	auto[0]	55124	1			T1	2		T2	12		T3	92
all_values[7]	auto[0]	auto[1]	332	1			T4	3		T14	2		T85	1
all_values[7]	auto[1]	auto[0]	50411	1			T1	3		T2	6		T3	21
all_values[7]	auto[1]	auto[1]	318	1			T4	2		T15	1		T85	1
all_values[8]	auto[0]	auto[0]	32908	1			T1	1		T3	18		T4	110
all_values[8]	auto[0]	auto[1]	19437	1			T1	4		T2	6		T3	95
all_values[8]	auto[1]	auto[0]	35783	1			T4	39		T7	1		T9	179
all_values[8]	auto[1]	auto[1]	18057	1			T2	12		T4	102		T5	4