Unified Coverage Report :: Group :: uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

Group : uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_uart_env_0.1/uart_env_cov.sv

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Summary for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	34	0	34	100.00

Variables for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_baud_rate	7	0	7	100.00	100	1	1	0
cp_clk_freq	5	0	5	100.00	100	1	1	0

Crosses for Group uart_env_pkg::uart_env_cov::baud_rate_w_core_clk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
baud_rate_w_core_clk_cg_cc	34	0	34	100.00	100	1	1	0

Summary for Variable cp_baud_rate

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_baud_rate

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	2217	1			T2	1		T3	1		T4	10
auto[BaudRate115200]	1902	1			T1	3		T3	1		T4	12
auto[BaudRate230400]	1988	1			T1	3		T2	3		T3	2
auto[BaudRate128Kbps]	2033	1			T1	3		T2	2		T4	24
auto[BaudRate256Kbps]	2263	1			T2	2		T3	1		T4	19
auto[BaudRate1Mbps]	1787	1			T2	2		T4	23		T5	2
auto[BaudRate1p5Mbps]	1322	1			T3	1		T4	4		T6	1

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Summary for Variable cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_clk_freq

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
freqs[24]	1234	1			T4	102		T39	8		T20	2
freqs[25]	1296	1			T2	10		T258	6		T245	9
freqs[48]	360	1			T42	7		T36	7		T46	9
freqs[50]	516	1			T9	5		T41	5		T12	77
freqs[100]	1011	1			T99	10		T100	5		T324	2

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Summary for Cross baud_rate_w_core_clk_cg_cc

Samples crossed: cp_baud_rate cp_clk_freq

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	34	0	34	100.00
Automatically Generated Cross Bins	34	0	34	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for baud_rate_w_core_clk_cg_cc

Bins

cp_baud_rate	cp_clk_freq	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[BaudRate9600]	freqs[24]	224	1			T4	10		T39	2		T325	9
auto[BaudRate9600]	freqs[25]	223	1			T2	1		T258	1		T50	1
auto[BaudRate9600]	freqs[48]	47	1			T42	1		T46	2		T51	1
auto[BaudRate9600]	freqs[50]	80	1			T41	1		T12	3		T279	1
auto[BaudRate9600]	freqs[100]	162	1			T324	2		T70	1		T72	1
auto[BaudRate115200]	freqs[24]	171	1			T4	12		T39	1		T326	3
auto[BaudRate115200]	freqs[25]	175	1			T258	1		T245	1		T50	1
auto[BaudRate115200]	freqs[48]	45	1			T51	2		T263	2		T327	3
auto[BaudRate115200]	freqs[50]	58	1			T12	8		T109	2		T279	2
auto[BaudRate115200]	freqs[100]	120	1			T99	1		T100	1		T70	2
auto[BaudRate230400]	freqs[24]	175	1			T4	10		T39	2		T261	3
auto[BaudRate230400]	freqs[25]	190	1			T2	3		T245	2		T108	1
auto[BaudRate230400]	freqs[48]	54	1			T42	2		T51	1		T268	2
auto[BaudRate230400]	freqs[50]	70	1			T9	3		T12	20		T279	2
auto[BaudRate230400]	freqs[100]	138	1			T99	2		T100	1		T328	1
auto[BaudRate128Kbps]	freqs[24]	185	1			T4	24		T20	1		T261	3
auto[BaudRate128Kbps]	freqs[25]	187	1			T2	2		T258	2		T245	1
auto[BaudRate128Kbps]	freqs[48]	47	1			T42	1		T46	1		T51	1
auto[BaudRate128Kbps]	freqs[50]	83	1			T41	1		T12	15		T109	1
auto[BaudRate128Kbps]	freqs[100]	143	1			T100	2		T72	1		T110	1
auto[BaudRate256Kbps]	freqs[24]	203	1			T4	19		T20	1		T261	3
auto[BaudRate256Kbps]	freqs[25]	201	1			T2	2		T245	2		T108	1
auto[BaudRate256Kbps]	freqs[48]	59	1			T42	1		T36	1		T46	1
auto[BaudRate256Kbps]	freqs[50]	76	1			T9	1		T41	1		T12	19
auto[BaudRate256Kbps]	freqs[100]	145	1			T99	1		T70	2		T121	1
auto[BaudRate1Mbps]	freqs[24]	187	1			T4	23		T39	2		T261	1
auto[BaudRate1Mbps]	freqs[25]	212	1			T2	2		T258	1		T245	2
auto[BaudRate1Mbps]	freqs[48]	60	1			T42	1		T36	4		T46	3
auto[BaudRate1Mbps]	freqs[50]	89	1			T9	1		T41	2		T12	9
auto[BaudRate1Mbps]	freqs[100]	137	1			T99	4		T100	1		T70	2
auto[BaudRate1p5Mbps]	freqs[25]	108	1			T258	1		T245	1		T50	1
auto[BaudRate1p5Mbps]	freqs[48]	48	1			T42	1		T36	2		T46	2
auto[BaudRate1p5Mbps]	freqs[50]	60	1			T12	3		T109	2		T53	11
auto[BaudRate1p5Mbps]	freqs[100]	166	1			T99	2		T121	1		T110	1

User Defined Cross Bins for baud_rate_w_core_clk_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
unsupported	0	Excluded